1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 43 #include <sys/param.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/systm.h> 54 #include <sys/taskqueue.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_arp.h> 61 #include <net/ethernet.h> 62 #include <net/if_llc.h> 63 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 #include <net80211/ieee80211_regdomain.h> 67 #include <net80211/ieee80211_amrr.h> 68 #include <net80211/ieee80211_phy.h> 69 70 #include <net/bpf.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_ether.h> 75 #endif 76 77 #include <machine/bus.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 82 #include <dev/bwi/bitops.h> 83 #include <dev/bwi/if_bwireg.h> 84 #include <dev/bwi/if_bwivar.h> 85 #include <dev/bwi/bwimac.h> 86 #include <dev/bwi/bwirf.h> 87 88 struct bwi_clock_freq { 89 u_int clkfreq_min; 90 u_int clkfreq_max; 91 }; 92 93 struct bwi_myaddr_bssid { 94 uint8_t myaddr[IEEE80211_ADDR_LEN]; 95 uint8_t bssid[IEEE80211_ADDR_LEN]; 96 } __packed; 97 98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 99 const char [IFNAMSIZ], int, int, int, 100 const uint8_t [IEEE80211_ADDR_LEN], 101 const uint8_t [IEEE80211_ADDR_LEN]); 102 static void bwi_vap_delete(struct ieee80211vap *); 103 static void bwi_init(void *); 104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 105 static void bwi_start(struct ifnet *); 106 static void bwi_start_locked(struct ifnet *); 107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 108 const struct ieee80211_bpf_params *); 109 static void bwi_watchdog(struct ifnet *); 110 static void bwi_scan_start(struct ieee80211com *); 111 static void bwi_set_channel(struct ieee80211com *); 112 static void bwi_scan_end(struct ieee80211com *); 113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 114 static void bwi_updateslot(struct ifnet *); 115 static struct ieee80211_node *bwi_node_alloc(struct ieee80211vap *, 116 const uint8_t [IEEE80211_ADDR_LEN]); 117 static void bwi_newassoc(struct ieee80211_node *, int); 118 static int bwi_media_change(struct ifnet *); 119 120 static void bwi_calibrate(void *); 121 122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 123 static int bwi_calc_noise(struct bwi_softc *); 124 static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *); 125 static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *); 126 static void bwi_rx_radiotap(struct ifnet *, struct mbuf *, 127 struct bwi_rxbuf_hdr *, const void *, int, int, int); 128 129 static void bwi_restart(void *, int); 130 static void bwi_init_statechg(struct bwi_softc *, int); 131 static void bwi_stop(struct bwi_softc *, int); 132 static void bwi_stop_locked(struct bwi_softc *, int); 133 static int bwi_newbuf(struct bwi_softc *, int, int); 134 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *); 136 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *, 138 const struct ieee80211_bpf_params *); 139 140 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 141 bus_addr_t, int, int); 142 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 143 144 static int bwi_init_tx_ring32(struct bwi_softc *, int); 145 static int bwi_init_rx_ring32(struct bwi_softc *); 146 static int bwi_init_txstats32(struct bwi_softc *); 147 static void bwi_free_tx_ring32(struct bwi_softc *, int); 148 static void bwi_free_rx_ring32(struct bwi_softc *); 149 static void bwi_free_txstats32(struct bwi_softc *); 150 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 151 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 152 int, bus_addr_t, int); 153 static int bwi_rxeof32(struct bwi_softc *); 154 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 155 static void bwi_txeof_status32(struct bwi_softc *); 156 157 static int bwi_init_tx_ring64(struct bwi_softc *, int); 158 static int bwi_init_rx_ring64(struct bwi_softc *); 159 static int bwi_init_txstats64(struct bwi_softc *); 160 static void bwi_free_tx_ring64(struct bwi_softc *, int); 161 static void bwi_free_rx_ring64(struct bwi_softc *); 162 static void bwi_free_txstats64(struct bwi_softc *); 163 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 164 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 165 int, bus_addr_t, int); 166 static int bwi_rxeof64(struct bwi_softc *); 167 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 168 static void bwi_txeof_status64(struct bwi_softc *); 169 170 static int bwi_rxeof(struct bwi_softc *, int); 171 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 172 static void bwi_txeof(struct bwi_softc *); 173 static void bwi_txeof_status(struct bwi_softc *, int); 174 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 175 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 176 177 static int bwi_dma_alloc(struct bwi_softc *); 178 static void bwi_dma_free(struct bwi_softc *); 179 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 180 struct bwi_ring_data *, bus_size_t, 181 uint32_t); 182 static int bwi_dma_mbuf_create(struct bwi_softc *); 183 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 184 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 185 static void bwi_dma_txstats_free(struct bwi_softc *); 186 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 187 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 188 bus_size_t, int); 189 190 static void bwi_power_on(struct bwi_softc *, int); 191 static int bwi_power_off(struct bwi_softc *, int); 192 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 193 static int bwi_set_clock_delay(struct bwi_softc *); 194 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 195 static int bwi_get_pwron_delay(struct bwi_softc *sc); 196 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 197 const uint8_t *); 198 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 199 200 static void bwi_get_card_flags(struct bwi_softc *); 201 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 202 203 static int bwi_bus_attach(struct bwi_softc *); 204 static int bwi_bbp_attach(struct bwi_softc *); 205 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 206 static void bwi_bbp_power_off(struct bwi_softc *); 207 208 static const char *bwi_regwin_name(const struct bwi_regwin *); 209 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 210 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 211 static int bwi_regwin_select(struct bwi_softc *, int); 212 213 static void bwi_led_attach(struct bwi_softc *); 214 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 215 static void bwi_led_event(struct bwi_softc *, int); 216 static void bwi_led_blink_start(struct bwi_softc *, int, int); 217 static void bwi_led_blink_next(void *); 218 static void bwi_led_blink_end(void *); 219 220 static const struct { 221 uint16_t did_min; 222 uint16_t did_max; 223 uint16_t bbp_id; 224 } bwi_bbpid_map[] = { 225 { 0x4301, 0x4301, 0x4301 }, 226 { 0x4305, 0x4307, 0x4307 }, 227 { 0x4403, 0x4403, 0x4402 }, 228 { 0x4610, 0x4615, 0x4610 }, 229 { 0x4710, 0x4715, 0x4710 }, 230 { 0x4720, 0x4725, 0x4309 } 231 }; 232 233 static const struct { 234 uint16_t bbp_id; 235 int nregwin; 236 } bwi_regwin_count[] = { 237 { 0x4301, 5 }, 238 { 0x4306, 6 }, 239 { 0x4307, 5 }, 240 { 0x4310, 8 }, 241 { 0x4401, 3 }, 242 { 0x4402, 3 }, 243 { 0x4610, 9 }, 244 { 0x4704, 9 }, 245 { 0x4710, 9 }, 246 { 0x5365, 7 } 247 }; 248 249 #define CLKSRC(src) \ 250 [BWI_CLKSRC_ ## src] = { \ 251 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 252 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 253 } 254 255 static const struct { 256 u_int freq_min; 257 u_int freq_max; 258 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 259 CLKSRC(LP_OSC), 260 CLKSRC(CS_OSC), 261 CLKSRC(PCI) 262 }; 263 264 #undef CLKSRC 265 266 #define VENDOR_LED_ACT(vendor) \ 267 { \ 268 .vid = PCI_VENDOR_##vendor, \ 269 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 270 } 271 272 static const struct { 273 #define PCI_VENDOR_COMPAQ 0x0e11 274 #define PCI_VENDOR_LINKSYS 0x1737 275 uint16_t vid; 276 uint8_t led_act[BWI_LED_MAX]; 277 } bwi_vendor_led_act[] = { 278 VENDOR_LED_ACT(COMPAQ), 279 VENDOR_LED_ACT(LINKSYS) 280 #undef PCI_VENDOR_LINKSYS 281 #undef PCI_VENDOR_COMPAQ 282 }; 283 284 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 285 { BWI_VENDOR_LED_ACT_DEFAULT }; 286 287 #undef VENDOR_LED_ACT 288 289 static const struct { 290 int on_dur; 291 int off_dur; 292 } bwi_led_duration[109] = { 293 [0] = { 400, 100 }, 294 [2] = { 150, 75 }, 295 [4] = { 90, 45 }, 296 [11] = { 66, 34 }, 297 [12] = { 53, 26 }, 298 [18] = { 42, 21 }, 299 [22] = { 35, 17 }, 300 [24] = { 32, 16 }, 301 [36] = { 21, 10 }, 302 [48] = { 16, 8 }, 303 [72] = { 11, 5 }, 304 [96] = { 9, 4 }, 305 [108] = { 7, 3 } 306 }; 307 308 #ifdef BWI_DEBUG 309 #ifdef BWI_DEBUG_VERBOSE 310 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 311 #else 312 static uint32_t bwi_debug; 313 #endif 314 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 315 #endif /* BWI_DEBUG */ 316 317 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 318 319 uint16_t 320 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 321 { 322 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 323 } 324 325 static __inline void 326 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 327 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 328 int tx) 329 { 330 struct bwi_desc32 *desc = &desc_array[desc_idx]; 331 uint32_t ctrl, addr, addr_hi, addr_lo; 332 333 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 334 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 335 336 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 337 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 338 339 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 340 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 341 if (desc_idx == ndesc - 1) 342 ctrl |= BWI_DESC32_C_EOR; 343 if (tx) { 344 /* XXX */ 345 ctrl |= BWI_DESC32_C_FRAME_START | 346 BWI_DESC32_C_FRAME_END | 347 BWI_DESC32_C_INTR; 348 } 349 350 desc->addr = htole32(addr); 351 desc->ctrl = htole32(ctrl); 352 } 353 354 int 355 bwi_attach(struct bwi_softc *sc) 356 { 357 struct ieee80211com *ic; 358 device_t dev = sc->sc_dev; 359 struct ifnet *ifp; 360 struct bwi_mac *mac; 361 struct bwi_phy *phy; 362 int i, error; 363 uint8_t bands; 364 uint8_t macaddr[IEEE80211_ADDR_LEN]; 365 366 BWI_LOCK_INIT(sc); 367 368 /* 369 * Initialize taskq and various tasks 370 */ 371 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 372 taskqueue_thread_enqueue, &sc->sc_tq); 373 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 374 device_get_nameunit(dev)); 375 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 376 377 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 378 379 /* 380 * Initialize sysctl variables 381 */ 382 sc->sc_fw_version = BWI_FW_VERSION3; 383 sc->sc_led_idle = (2350 * hz) / 1000; 384 sc->sc_led_blink = 1; 385 sc->sc_txpwr_calib = 1; 386 #ifdef BWI_DEBUG 387 sc->sc_debug = bwi_debug; 388 #endif 389 bwi_power_on(sc, 1); 390 391 error = bwi_bbp_attach(sc); 392 if (error) 393 goto fail; 394 395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 396 if (error) 397 goto fail; 398 399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 400 error = bwi_set_clock_delay(sc); 401 if (error) 402 goto fail; 403 404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 405 if (error) 406 goto fail; 407 408 error = bwi_get_pwron_delay(sc); 409 if (error) 410 goto fail; 411 } 412 413 error = bwi_bus_attach(sc); 414 if (error) 415 goto fail; 416 417 bwi_get_card_flags(sc); 418 419 bwi_led_attach(sc); 420 421 for (i = 0; i < sc->sc_nmac; ++i) { 422 struct bwi_regwin *old; 423 424 mac = &sc->sc_mac[i]; 425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 426 if (error) 427 goto fail; 428 429 error = bwi_mac_lateattach(mac); 430 if (error) 431 goto fail; 432 433 error = bwi_regwin_switch(sc, old, NULL); 434 if (error) 435 goto fail; 436 } 437 438 /* 439 * XXX First MAC is known to exist 440 * TODO2 441 */ 442 mac = &sc->sc_mac[0]; 443 phy = &mac->mac_phy; 444 445 bwi_bbp_power_off(sc); 446 447 error = bwi_dma_alloc(sc); 448 if (error) 449 goto fail; 450 451 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 452 if (ifp == NULL) { 453 device_printf(dev, "can not if_alloc()\n"); 454 error = ENOSPC; 455 goto fail; 456 } 457 ic = ifp->if_l2com; 458 459 /* set these up early for if_printf use */ 460 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 461 462 ifp->if_softc = sc; 463 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 464 ifp->if_init = bwi_init; 465 ifp->if_ioctl = bwi_ioctl; 466 ifp->if_start = bwi_start; 467 ifp->if_watchdog = bwi_watchdog; 468 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 469 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 470 IFQ_SET_READY(&ifp->if_snd); 471 472 /* 473 * Setup ratesets, phytype, channels and get MAC address 474 */ 475 bands = 0; 476 if (phy->phy_mode == IEEE80211_MODE_11B || 477 phy->phy_mode == IEEE80211_MODE_11G) { 478 setbit(&bands, IEEE80211_MODE_11B); 479 if (phy->phy_mode == IEEE80211_MODE_11B) { 480 ic->ic_phytype = IEEE80211_T_DS; 481 } else { 482 ic->ic_phytype = IEEE80211_T_OFDM; 483 setbit(&bands, IEEE80211_MODE_11G); 484 } 485 486 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 487 if (IEEE80211_IS_MULTICAST(macaddr)) { 488 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 489 if (IEEE80211_IS_MULTICAST(macaddr)) { 490 device_printf(dev, 491 "invalid MAC address: %6D\n", 492 macaddr, ":"); 493 } 494 } 495 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 496 /* TODO:11A */ 497 setbit(&bands, IEEE80211_MODE_11A); 498 error = ENXIO; 499 goto fail; 500 } else { 501 panic("unknown phymode %d\n", phy->phy_mode); 502 } 503 504 /* Get locale */ 505 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 506 BWI_SPROM_CARD_INFO_LOCALE); 507 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 508 /* XXX use locale */ 509 ieee80211_init_channels(ic, NULL, &bands); 510 511 ic->ic_ifp = ifp; 512 ic->ic_caps = IEEE80211_C_STA | 513 IEEE80211_C_SHSLOT | 514 IEEE80211_C_SHPREAMBLE | 515 IEEE80211_C_WPA | 516 IEEE80211_C_BGSCAN | 517 IEEE80211_C_MONITOR; 518 ic->ic_opmode = IEEE80211_M_STA; 519 ieee80211_ifattach(ic, macaddr); 520 521 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 522 523 /* override default methods */ 524 ic->ic_vap_create = bwi_vap_create; 525 ic->ic_vap_delete = bwi_vap_delete; 526 ic->ic_raw_xmit = bwi_raw_xmit; 527 ic->ic_updateslot = bwi_updateslot; 528 ic->ic_node_alloc = bwi_node_alloc; 529 ic->ic_scan_start = bwi_scan_start; 530 ic->ic_scan_end = bwi_scan_end; 531 ic->ic_set_channel = bwi_set_channel; 532 533 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 534 535 /* 536 * Attach bpf. 537 */ 538 bpfattach(ifp, DLT_IEEE802_11_RADIO, 539 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th)); 540 541 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t)); 542 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len); 543 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT); 544 545 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t)); 546 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len); 547 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT); 548 549 /* 550 * Add sysctl nodes 551 */ 552 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 554 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 555 "Firmware version"); 556 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 558 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 559 "# ticks before LED enters idle state"); 560 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 561 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 562 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 563 "Allow LED to blink"); 564 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 565 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 566 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 567 "Enable software TX power calibration"); 568 #ifdef BWI_DEBUG 569 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 570 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 571 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 572 #endif 573 if (bootverbose) 574 ieee80211_announce(ic); 575 576 return (0); 577 fail: 578 BWI_LOCK_DESTROY(sc); 579 return (error); 580 } 581 582 int 583 bwi_detach(struct bwi_softc *sc) 584 { 585 struct ifnet *ifp = sc->sc_ifp; 586 struct ieee80211com *ic = ifp->if_l2com; 587 int i; 588 589 bwi_stop(sc, 1); 590 callout_drain(&sc->sc_calib_ch); 591 ieee80211_ifdetach(ic); 592 593 for (i = 0; i < sc->sc_nmac; ++i) 594 bwi_mac_detach(&sc->sc_mac[i]); 595 bwi_dma_free(sc); 596 if_free(ifp); 597 taskqueue_free(sc->sc_tq); 598 599 BWI_LOCK_DESTROY(sc); 600 601 return (0); 602 } 603 604 static struct ieee80211vap * 605 bwi_vap_create(struct ieee80211com *ic, 606 const char name[IFNAMSIZ], int unit, int opmode, int flags, 607 const uint8_t bssid[IEEE80211_ADDR_LEN], 608 const uint8_t mac[IEEE80211_ADDR_LEN]) 609 { 610 struct bwi_vap *bvp; 611 struct ieee80211vap *vap; 612 613 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 614 return NULL; 615 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 616 M_80211_VAP, M_WAITOK | M_ZERO); 617 if (bvp == NULL) 618 return NULL; 619 vap = &bvp->bv_vap; 620 /* enable s/w bmiss handling for sta mode */ 621 ieee80211_vap_setup(ic, vap, name, unit, opmode, 622 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 623 624 /* override default methods */ 625 bvp->bv_newstate = vap->iv_newstate; 626 vap->iv_newstate = bwi_newstate; 627 #if 0 628 vap->iv_update_beacon = bwi_beacon_update; 629 #endif 630 ieee80211_amrr_init(&bvp->bv_amrr, vap, 631 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 632 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 633 500 /*ms*/); 634 635 /* complete setup */ 636 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 637 ic->ic_opmode = opmode; 638 return vap; 639 } 640 641 static void 642 bwi_vap_delete(struct ieee80211vap *vap) 643 { 644 struct bwi_vap *bvp = BWI_VAP(vap); 645 646 ieee80211_amrr_cleanup(&bvp->bv_amrr); 647 ieee80211_vap_detach(vap); 648 free(bvp, M_80211_VAP); 649 } 650 651 void 652 bwi_suspend(struct bwi_softc *sc) 653 { 654 bwi_stop(sc, 1); 655 } 656 657 void 658 bwi_resume(struct bwi_softc *sc) 659 { 660 struct ifnet *ifp = sc->sc_ifp; 661 662 if (ifp->if_flags & IFF_UP) 663 bwi_init(sc); 664 } 665 666 int 667 bwi_shutdown(struct bwi_softc *sc) 668 { 669 bwi_stop(sc, 1); 670 return 0; 671 } 672 673 static void 674 bwi_power_on(struct bwi_softc *sc, int with_pll) 675 { 676 uint32_t gpio_in, gpio_out, gpio_en; 677 uint16_t status; 678 679 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 680 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 681 goto back; 682 683 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 684 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 685 686 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 687 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 688 if (with_pll) { 689 /* Turn off PLL first */ 690 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 691 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 692 } 693 694 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 695 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 696 DELAY(1000); 697 698 if (with_pll) { 699 /* Turn on PLL */ 700 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 701 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 702 DELAY(5000); 703 } 704 705 back: 706 /* Clear "Signaled Target Abort" */ 707 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 708 status &= ~PCIM_STATUS_STABORT; 709 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 710 } 711 712 static int 713 bwi_power_off(struct bwi_softc *sc, int with_pll) 714 { 715 uint32_t gpio_out, gpio_en; 716 717 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 718 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 719 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 720 721 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 722 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 723 if (with_pll) { 724 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 725 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 726 } 727 728 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 729 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 730 return 0; 731 } 732 733 int 734 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 735 struct bwi_regwin **old_rw) 736 { 737 int error; 738 739 if (old_rw != NULL) 740 *old_rw = NULL; 741 742 if (!BWI_REGWIN_EXIST(rw)) 743 return EINVAL; 744 745 if (sc->sc_cur_regwin != rw) { 746 error = bwi_regwin_select(sc, rw->rw_id); 747 if (error) { 748 device_printf(sc->sc_dev, "can't select regwin %d\n", 749 rw->rw_id); 750 return error; 751 } 752 } 753 754 if (old_rw != NULL) 755 *old_rw = sc->sc_cur_regwin; 756 sc->sc_cur_regwin = rw; 757 return 0; 758 } 759 760 static int 761 bwi_regwin_select(struct bwi_softc *sc, int id) 762 { 763 uint32_t win = BWI_PCIM_REGWIN(id); 764 int i; 765 766 #define RETRY_MAX 50 767 for (i = 0; i < RETRY_MAX; ++i) { 768 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 769 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 770 return 0; 771 DELAY(10); 772 } 773 #undef RETRY_MAX 774 775 return ENXIO; 776 } 777 778 static void 779 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 780 { 781 uint32_t val; 782 783 val = CSR_READ_4(sc, BWI_ID_HI); 784 *type = BWI_ID_HI_REGWIN_TYPE(val); 785 *rev = BWI_ID_HI_REGWIN_REV(val); 786 787 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 788 "vendor 0x%04x\n", *type, *rev, 789 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 790 } 791 792 static int 793 bwi_bbp_attach(struct bwi_softc *sc) 794 { 795 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 796 uint16_t bbp_id, rw_type; 797 uint8_t rw_rev; 798 uint32_t info; 799 int error, nregwin, i; 800 801 /* 802 * Get 0th regwin information 803 * NOTE: 0th regwin should exist 804 */ 805 error = bwi_regwin_select(sc, 0); 806 if (error) { 807 device_printf(sc->sc_dev, "can't select regwin 0\n"); 808 return error; 809 } 810 bwi_regwin_info(sc, &rw_type, &rw_rev); 811 812 /* 813 * Find out BBP id 814 */ 815 bbp_id = 0; 816 info = 0; 817 if (rw_type == BWI_REGWIN_T_COM) { 818 info = CSR_READ_4(sc, BWI_INFO); 819 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 820 821 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 822 823 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 824 } else { 825 for (i = 0; i < N(bwi_bbpid_map); ++i) { 826 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 827 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 828 bbp_id = bwi_bbpid_map[i].bbp_id; 829 break; 830 } 831 } 832 if (bbp_id == 0) { 833 device_printf(sc->sc_dev, "no BBP id for device id " 834 "0x%04x\n", sc->sc_pci_did); 835 return ENXIO; 836 } 837 838 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 839 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 840 } 841 842 /* 843 * Find out number of regwins 844 */ 845 nregwin = 0; 846 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 847 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 848 } else { 849 for (i = 0; i < N(bwi_regwin_count); ++i) { 850 if (bwi_regwin_count[i].bbp_id == bbp_id) { 851 nregwin = bwi_regwin_count[i].nregwin; 852 break; 853 } 854 } 855 if (nregwin == 0) { 856 device_printf(sc->sc_dev, "no number of win for " 857 "BBP id 0x%04x\n", bbp_id); 858 return ENXIO; 859 } 860 } 861 862 /* Record BBP id/rev for later using */ 863 sc->sc_bbp_id = bbp_id; 864 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 865 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 866 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 867 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 868 869 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 870 nregwin, sc->sc_cap); 871 872 /* 873 * Create rest of the regwins 874 */ 875 876 /* Don't re-create common regwin, if it is already created */ 877 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 878 879 for (; i < nregwin; ++i) { 880 /* 881 * Get regwin information 882 */ 883 error = bwi_regwin_select(sc, i); 884 if (error) { 885 device_printf(sc->sc_dev, 886 "can't select regwin %d\n", i); 887 return error; 888 } 889 bwi_regwin_info(sc, &rw_type, &rw_rev); 890 891 /* 892 * Try attach: 893 * 1) Bus (PCI/PCIE) regwin 894 * 2) MAC regwin 895 * Ignore rest types of regwin 896 */ 897 if (rw_type == BWI_REGWIN_T_BUSPCI || 898 rw_type == BWI_REGWIN_T_BUSPCIE) { 899 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 900 device_printf(sc->sc_dev, 901 "bus regwin already exists\n"); 902 } else { 903 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 904 rw_type, rw_rev); 905 } 906 } else if (rw_type == BWI_REGWIN_T_MAC) { 907 /* XXX ignore return value */ 908 bwi_mac_attach(sc, i, rw_rev); 909 } 910 } 911 912 /* At least one MAC shold exist */ 913 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 914 device_printf(sc->sc_dev, "no MAC was found\n"); 915 return ENXIO; 916 } 917 KASSERT(sc->sc_nmac > 0, ("no mac's")); 918 919 /* Bus regwin must exist */ 920 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 921 device_printf(sc->sc_dev, "no bus regwin was found\n"); 922 return ENXIO; 923 } 924 925 /* Start with first MAC */ 926 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 927 if (error) 928 return error; 929 930 return 0; 931 #undef N 932 } 933 934 int 935 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 936 { 937 struct bwi_regwin *old, *bus; 938 uint32_t val; 939 int error; 940 941 bus = &sc->sc_bus_regwin; 942 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 943 944 /* 945 * Tell bus to generate requested interrupts 946 */ 947 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 948 /* 949 * NOTE: Read BWI_FLAGS from MAC regwin 950 */ 951 val = CSR_READ_4(sc, BWI_FLAGS); 952 953 error = bwi_regwin_switch(sc, bus, &old); 954 if (error) 955 return error; 956 957 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 958 } else { 959 uint32_t mac_mask; 960 961 mac_mask = 1 << mac->mac_id; 962 963 error = bwi_regwin_switch(sc, bus, &old); 964 if (error) 965 return error; 966 967 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 968 val |= mac_mask << 8; 969 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 970 } 971 972 if (sc->sc_flags & BWI_F_BUS_INITED) 973 goto back; 974 975 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 976 /* 977 * Enable prefetch and burst 978 */ 979 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 980 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 981 982 if (bus->rw_rev < 5) { 983 struct bwi_regwin *com = &sc->sc_com_regwin; 984 985 /* 986 * Configure timeouts for bus operation 987 */ 988 989 /* 990 * Set service timeout and request timeout 991 */ 992 CSR_SETBITS_4(sc, BWI_CONF_LO, 993 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 994 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 995 996 /* 997 * If there is common regwin, we switch to that regwin 998 * and switch back to bus regwin once we have done. 999 */ 1000 if (BWI_REGWIN_EXIST(com)) { 1001 error = bwi_regwin_switch(sc, com, NULL); 1002 if (error) 1003 return error; 1004 } 1005 1006 /* Let bus know what we have changed */ 1007 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 1008 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 1009 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 1010 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 1011 1012 if (BWI_REGWIN_EXIST(com)) { 1013 error = bwi_regwin_switch(sc, bus, NULL); 1014 if (error) 1015 return error; 1016 } 1017 } else if (bus->rw_rev >= 11) { 1018 /* 1019 * Enable memory read multiple 1020 */ 1021 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1022 } 1023 } else { 1024 /* TODO:PCIE */ 1025 } 1026 1027 sc->sc_flags |= BWI_F_BUS_INITED; 1028 back: 1029 return bwi_regwin_switch(sc, old, NULL); 1030 } 1031 1032 static void 1033 bwi_get_card_flags(struct bwi_softc *sc) 1034 { 1035 #define PCI_VENDOR_APPLE 0x106b 1036 #define PCI_VENDOR_DELL 0x1028 1037 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1038 if (sc->sc_card_flags == 0xffff) 1039 sc->sc_card_flags = 0; 1040 1041 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1042 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1043 sc->sc_pci_revid == 0x74) 1044 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1045 1046 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1047 sc->sc_pci_subdid == 0x4e && /* XXX */ 1048 sc->sc_pci_revid > 0x40) 1049 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1050 1051 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1052 #undef PCI_VENDOR_DELL 1053 #undef PCI_VENDOR_APPLE 1054 } 1055 1056 static void 1057 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1058 { 1059 int i; 1060 1061 for (i = 0; i < 3; ++i) { 1062 *((uint16_t *)eaddr + i) = 1063 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1064 } 1065 } 1066 1067 static void 1068 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1069 { 1070 struct bwi_regwin *com; 1071 uint32_t val; 1072 u_int div; 1073 int src; 1074 1075 bzero(freq, sizeof(*freq)); 1076 com = &sc->sc_com_regwin; 1077 1078 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1079 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1080 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1081 1082 /* 1083 * Calculate clock frequency 1084 */ 1085 src = -1; 1086 div = 0; 1087 if (com->rw_rev < 6) { 1088 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1089 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1090 src = BWI_CLKSRC_PCI; 1091 div = 64; 1092 } else { 1093 src = BWI_CLKSRC_CS_OSC; 1094 div = 32; 1095 } 1096 } else if (com->rw_rev < 10) { 1097 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1098 1099 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1100 if (src == BWI_CLKSRC_LP_OSC) { 1101 div = 1; 1102 } else { 1103 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1104 1105 /* Unknown source */ 1106 if (src >= BWI_CLKSRC_MAX) 1107 src = BWI_CLKSRC_CS_OSC; 1108 } 1109 } else { 1110 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1111 1112 src = BWI_CLKSRC_CS_OSC; 1113 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1114 } 1115 1116 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1117 KASSERT(div != 0, ("div zero")); 1118 1119 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1120 src == BWI_CLKSRC_PCI ? "PCI" : 1121 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1122 1123 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1124 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1125 1126 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1127 freq->clkfreq_min, freq->clkfreq_max); 1128 } 1129 1130 static int 1131 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1132 { 1133 struct bwi_regwin *old, *com; 1134 uint32_t clk_ctrl, clk_src; 1135 int error, pwr_off = 0; 1136 1137 com = &sc->sc_com_regwin; 1138 if (!BWI_REGWIN_EXIST(com)) 1139 return 0; 1140 1141 if (com->rw_rev >= 10 || com->rw_rev < 6) 1142 return 0; 1143 1144 /* 1145 * For common regwin whose rev is [6, 10), the chip 1146 * must be capable to change clock mode. 1147 */ 1148 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1149 return 0; 1150 1151 error = bwi_regwin_switch(sc, com, &old); 1152 if (error) 1153 return error; 1154 1155 if (clk_mode == BWI_CLOCK_MODE_FAST) 1156 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1157 1158 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1159 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1160 1161 switch (clk_mode) { 1162 case BWI_CLOCK_MODE_FAST: 1163 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1164 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1165 break; 1166 case BWI_CLOCK_MODE_SLOW: 1167 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1168 break; 1169 case BWI_CLOCK_MODE_DYN: 1170 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1171 BWI_CLOCK_CTRL_IGNPLL | 1172 BWI_CLOCK_CTRL_NODYN); 1173 if (clk_src != BWI_CLKSRC_CS_OSC) { 1174 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1175 pwr_off = 1; 1176 } 1177 break; 1178 } 1179 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1180 1181 if (pwr_off) 1182 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1183 1184 return bwi_regwin_switch(sc, old, NULL); 1185 } 1186 1187 static int 1188 bwi_set_clock_delay(struct bwi_softc *sc) 1189 { 1190 struct bwi_regwin *old, *com; 1191 int error; 1192 1193 com = &sc->sc_com_regwin; 1194 if (!BWI_REGWIN_EXIST(com)) 1195 return 0; 1196 1197 error = bwi_regwin_switch(sc, com, &old); 1198 if (error) 1199 return error; 1200 1201 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1202 if (sc->sc_bbp_rev == 0) 1203 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1204 else if (sc->sc_bbp_rev == 1) 1205 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1206 } 1207 1208 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1209 if (com->rw_rev >= 10) { 1210 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1211 } else { 1212 struct bwi_clock_freq freq; 1213 1214 bwi_get_clock_freq(sc, &freq); 1215 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1216 howmany(freq.clkfreq_max * 150, 1000000)); 1217 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1218 howmany(freq.clkfreq_max * 15, 1000000)); 1219 } 1220 } 1221 1222 return bwi_regwin_switch(sc, old, NULL); 1223 } 1224 1225 static void 1226 bwi_init(void *xsc) 1227 { 1228 struct bwi_softc *sc = xsc; 1229 struct ifnet *ifp = sc->sc_ifp; 1230 struct ieee80211com *ic = ifp->if_l2com; 1231 1232 BWI_LOCK(sc); 1233 bwi_init_statechg(sc, 1); 1234 BWI_UNLOCK(sc); 1235 1236 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1237 ieee80211_start_all(ic); /* start all vap's */ 1238 } 1239 1240 static void 1241 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1242 { 1243 struct ifnet *ifp = sc->sc_ifp; 1244 struct bwi_mac *mac; 1245 int error; 1246 1247 bwi_stop_locked(sc, statechg); 1248 1249 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1250 1251 /* TODO: 2 MAC */ 1252 1253 mac = &sc->sc_mac[0]; 1254 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1255 if (error) { 1256 if_printf(ifp, "%s: error %d on regwin switch\n", 1257 __func__, error); 1258 goto bad; 1259 } 1260 error = bwi_mac_init(mac); 1261 if (error) { 1262 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1263 goto bad; 1264 } 1265 1266 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1267 1268 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1269 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1270 1271 bwi_mac_reset_hwkeys(mac); 1272 1273 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1274 int i; 1275 1276 #define NRETRY 1000 1277 /* 1278 * Drain any possible pending TX status 1279 */ 1280 for (i = 0; i < NRETRY; ++i) { 1281 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1282 BWI_TXSTATUS0_VALID) == 0) 1283 break; 1284 CSR_READ_4(sc, BWI_TXSTATUS1); 1285 } 1286 if (i == NRETRY) 1287 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1288 #undef NRETRY 1289 } 1290 1291 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1292 bwi_mac_updateslot(mac, 1); 1293 1294 /* Start MAC */ 1295 error = bwi_mac_start(mac); 1296 if (error) { 1297 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1298 goto bad; 1299 } 1300 1301 /* Clear stop flag before enabling interrupt */ 1302 sc->sc_flags &= ~BWI_F_STOP; 1303 1304 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1305 1306 /* Enable intrs */ 1307 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1308 return; 1309 bad: 1310 bwi_stop_locked(sc, 1); 1311 } 1312 1313 static int 1314 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1315 { 1316 #define IS_RUNNING(ifp) \ 1317 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1318 struct bwi_softc *sc = ifp->if_softc; 1319 struct ieee80211com *ic = ifp->if_l2com; 1320 struct ifreq *ifr = (struct ifreq *) data; 1321 int error = 0, startall = 0; 1322 1323 switch (cmd) { 1324 case SIOCSIFFLAGS: 1325 BWI_LOCK(sc); 1326 if (IS_RUNNING(ifp)) { 1327 struct bwi_mac *mac; 1328 int promisc = -1; 1329 1330 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1331 ("current regwin type %d", 1332 sc->sc_cur_regwin->rw_type)); 1333 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1334 1335 if ((ifp->if_flags & IFF_PROMISC) && 1336 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1337 promisc = 1; 1338 sc->sc_flags |= BWI_F_PROMISC; 1339 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1340 (sc->sc_flags & BWI_F_PROMISC)) { 1341 promisc = 0; 1342 sc->sc_flags &= ~BWI_F_PROMISC; 1343 } 1344 1345 if (promisc >= 0) 1346 bwi_mac_set_promisc(mac, promisc); 1347 } 1348 1349 if (ifp->if_flags & IFF_UP) { 1350 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1351 bwi_init_statechg(sc, 1); 1352 startall = 1; 1353 } 1354 } else { 1355 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1356 bwi_stop_locked(sc, 1); 1357 } 1358 BWI_UNLOCK(sc); 1359 if (startall) 1360 ieee80211_start_all(ic); 1361 break; 1362 case SIOCGIFMEDIA: 1363 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1364 break; 1365 case SIOCGIFADDR: 1366 error = ether_ioctl(ifp, cmd, data); 1367 break; 1368 default: 1369 error = EINVAL; 1370 break; 1371 } 1372 return error; 1373 #undef IS_RUNNING 1374 } 1375 1376 static void 1377 bwi_start(struct ifnet *ifp) 1378 { 1379 struct bwi_softc *sc = ifp->if_softc; 1380 1381 BWI_LOCK(sc); 1382 bwi_start_locked(ifp); 1383 BWI_UNLOCK(sc); 1384 } 1385 1386 static void 1387 bwi_start_locked(struct ifnet *ifp) 1388 { 1389 struct bwi_softc *sc = ifp->if_softc; 1390 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1391 struct ieee80211_frame *wh; 1392 struct ieee80211_node *ni; 1393 struct ieee80211_key *k; 1394 struct mbuf *m; 1395 int trans, idx; 1396 1397 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1398 return; 1399 1400 trans = 0; 1401 idx = tbd->tbd_idx; 1402 1403 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1404 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1405 if (m == NULL) 1406 break; 1407 1408 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1409 wh = mtod(m, struct ieee80211_frame *); 1410 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1411 k = ieee80211_crypto_encap(ni, m); 1412 if (k == NULL) { 1413 ieee80211_free_node(ni); 1414 m_freem(m); 1415 ifp->if_oerrors++; 1416 continue; 1417 } 1418 } 1419 wh = NULL; /* Catch any invalid use */ 1420 1421 if (bwi_encap(sc, idx, m, ni) != 0) { 1422 /* 'm' is freed in bwi_encap() if we reach here */ 1423 if (ni != NULL) 1424 ieee80211_free_node(ni); 1425 ifp->if_oerrors++; 1426 continue; 1427 } 1428 1429 trans = 1; 1430 tbd->tbd_used++; 1431 idx = (idx + 1) % BWI_TX_NDESC; 1432 1433 ifp->if_opackets++; 1434 1435 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1436 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1437 break; 1438 } 1439 } 1440 tbd->tbd_idx = idx; 1441 1442 if (trans) 1443 ifp->if_timer = 5; 1444 } 1445 1446 static int 1447 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1448 const struct ieee80211_bpf_params *params) 1449 { 1450 struct ieee80211com *ic = ni->ni_ic; 1451 struct ifnet *ifp = ic->ic_ifp; 1452 struct bwi_softc *sc = ifp->if_softc; 1453 /* XXX wme? */ 1454 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1455 int idx, error; 1456 1457 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1458 ieee80211_free_node(ni); 1459 m_freem(m); 1460 return ENETDOWN; 1461 } 1462 1463 BWI_LOCK(sc); 1464 idx = tbd->tbd_idx; 1465 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1466 if (params == NULL) { 1467 /* 1468 * Legacy path; interpret frame contents to decide 1469 * precisely how to send the frame. 1470 */ 1471 error = bwi_encap(sc, idx, m, ni); 1472 } else { 1473 /* 1474 * Caller supplied explicit parameters to use in 1475 * sending the frame. 1476 */ 1477 error = bwi_encap_raw(sc, idx, m, ni, params); 1478 } 1479 if (error == 0) { 1480 ifp->if_opackets++; 1481 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1482 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1483 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1484 ifp->if_timer = 5; 1485 } else { 1486 /* NB: m is reclaimed on encap failure */ 1487 ieee80211_free_node(ni); 1488 ifp->if_oerrors++; 1489 } 1490 BWI_UNLOCK(sc); 1491 return error; 1492 } 1493 1494 static void 1495 bwi_watchdog(struct ifnet *ifp) 1496 { 1497 struct bwi_softc *sc = ifp->if_softc; 1498 1499 BWI_LOCK(sc); 1500 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1501 if_printf(ifp, "watchdog timeout\n"); 1502 ifp->if_oerrors++; 1503 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1504 } 1505 BWI_UNLOCK(sc); 1506 } 1507 1508 static void 1509 bwi_stop(struct bwi_softc *sc, int statechg) 1510 { 1511 BWI_LOCK(sc); 1512 bwi_stop_locked(sc, statechg); 1513 BWI_UNLOCK(sc); 1514 } 1515 1516 static void 1517 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1518 { 1519 struct ifnet *ifp = sc->sc_ifp; 1520 struct bwi_mac *mac; 1521 int i, error, pwr_off = 0; 1522 1523 BWI_ASSERT_LOCKED(sc); 1524 1525 callout_stop(&sc->sc_calib_ch); 1526 callout_stop(&sc->sc_led_blink_ch); 1527 sc->sc_led_blinking = 0; 1528 sc->sc_flags |= BWI_F_STOP; 1529 1530 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1531 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1532 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1533 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1534 1535 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1536 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1537 bwi_mac_stop(mac); 1538 } 1539 1540 for (i = 0; i < sc->sc_nmac; ++i) { 1541 struct bwi_regwin *old_rw; 1542 1543 mac = &sc->sc_mac[i]; 1544 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1545 continue; 1546 1547 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1548 if (error) 1549 continue; 1550 1551 bwi_mac_shutdown(mac); 1552 pwr_off = 1; 1553 1554 bwi_regwin_switch(sc, old_rw, NULL); 1555 } 1556 1557 if (pwr_off) 1558 bwi_bbp_power_off(sc); 1559 1560 sc->sc_tx_timer = 0; 1561 ifp->if_timer = 0; 1562 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1563 } 1564 1565 void 1566 bwi_intr(void *xsc) 1567 { 1568 struct bwi_softc *sc = xsc; 1569 struct ifnet *ifp = sc->sc_ifp; 1570 struct bwi_mac *mac; 1571 uint32_t intr_status; 1572 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1573 int i, txrx_error, tx = 0, rx_data = -1; 1574 1575 BWI_LOCK(sc); 1576 1577 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1578 (sc->sc_flags & BWI_F_STOP)) { 1579 BWI_UNLOCK(sc); 1580 return; 1581 } 1582 /* 1583 * Get interrupt status 1584 */ 1585 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1586 if (intr_status == 0xffffffff) { /* Not for us */ 1587 BWI_UNLOCK(sc); 1588 return; 1589 } 1590 1591 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1592 1593 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1594 if (intr_status == 0) { /* Nothing is interesting */ 1595 BWI_UNLOCK(sc); 1596 return; 1597 } 1598 1599 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1600 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1601 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1602 1603 txrx_error = 0; 1604 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1605 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1606 uint32_t mask; 1607 1608 if (BWI_TXRX_IS_RX(i)) 1609 mask = BWI_TXRX_RX_INTRS; 1610 else 1611 mask = BWI_TXRX_TX_INTRS; 1612 1613 txrx_intr_status[i] = 1614 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1615 1616 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1617 i, txrx_intr_status[i]); 1618 1619 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1620 if_printf(ifp, 1621 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1622 __func__, i, txrx_intr_status[i]); 1623 txrx_error = 1; 1624 } 1625 } 1626 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1627 1628 /* 1629 * Acknowledge interrupt 1630 */ 1631 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1632 1633 for (i = 0; i < BWI_TXRX_NRING; ++i) 1634 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1635 1636 /* Disable all interrupts */ 1637 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1638 1639 if (intr_status & BWI_INTR_PHY_TXERR) { 1640 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1641 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1642 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1643 BWI_UNLOCK(sc); 1644 return; 1645 } 1646 } 1647 1648 if (txrx_error) { 1649 /* TODO: reset device */ 1650 } 1651 1652 if (intr_status & BWI_INTR_TBTT) 1653 bwi_mac_config_ps(mac); 1654 1655 if (intr_status & BWI_INTR_EO_ATIM) 1656 if_printf(ifp, "EO_ATIM\n"); 1657 1658 if (intr_status & BWI_INTR_PMQ) { 1659 for (;;) { 1660 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1661 break; 1662 } 1663 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1664 } 1665 1666 if (intr_status & BWI_INTR_NOISE) 1667 if_printf(ifp, "intr noise\n"); 1668 1669 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1670 rx_data = sc->sc_rxeof(sc); 1671 if (sc->sc_flags & BWI_F_STOP) { 1672 BWI_UNLOCK(sc); 1673 return; 1674 } 1675 } 1676 1677 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1678 sc->sc_txeof_status(sc); 1679 tx = 1; 1680 } 1681 1682 if (intr_status & BWI_INTR_TX_DONE) { 1683 bwi_txeof(sc); 1684 tx = 1; 1685 } 1686 1687 /* Re-enable interrupts */ 1688 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1689 1690 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1691 int evt = BWI_LED_EVENT_NONE; 1692 1693 if (tx && rx_data > 0) { 1694 if (sc->sc_rx_rate > sc->sc_tx_rate) 1695 evt = BWI_LED_EVENT_RX; 1696 else 1697 evt = BWI_LED_EVENT_TX; 1698 } else if (tx) { 1699 evt = BWI_LED_EVENT_TX; 1700 } else if (rx_data > 0) { 1701 evt = BWI_LED_EVENT_RX; 1702 } else if (rx_data == 0) { 1703 evt = BWI_LED_EVENT_POLL; 1704 } 1705 1706 if (evt != BWI_LED_EVENT_NONE) 1707 bwi_led_event(sc, evt); 1708 } 1709 1710 BWI_UNLOCK(sc); 1711 } 1712 1713 static void 1714 bwi_scan_start(struct ieee80211com *ic) 1715 { 1716 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1717 1718 BWI_LOCK(sc); 1719 /* Enable MAC beacon promiscuity */ 1720 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1721 BWI_UNLOCK(sc); 1722 } 1723 1724 static void 1725 bwi_set_channel(struct ieee80211com *ic) 1726 { 1727 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1728 struct ieee80211_channel *c = ic->ic_curchan; 1729 struct bwi_mac *mac; 1730 1731 BWI_LOCK(sc); 1732 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1733 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1734 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1735 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1736 1737 sc->sc_rates = ieee80211_get_ratetable(c); 1738 1739 /* 1740 * Setup radio tap channel freq and flags 1741 */ 1742 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1743 htole16(c->ic_freq); 1744 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1745 htole16(c->ic_flags & 0xffff); 1746 1747 BWI_UNLOCK(sc); 1748 } 1749 1750 static void 1751 bwi_scan_end(struct ieee80211com *ic) 1752 { 1753 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1754 1755 BWI_LOCK(sc); 1756 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1757 BWI_UNLOCK(sc); 1758 } 1759 1760 static int 1761 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1762 { 1763 struct bwi_vap *bvp = BWI_VAP(vap); 1764 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1765 struct bwi_softc *sc = ifp->if_softc; 1766 struct bwi_mac *mac; 1767 struct ieee80211_node *ni; 1768 int error; 1769 1770 BWI_LOCK(sc); 1771 1772 callout_stop(&sc->sc_calib_ch); 1773 1774 if (nstate == IEEE80211_S_INIT) 1775 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1776 1777 bwi_led_newstate(sc, nstate); 1778 1779 error = bvp->bv_newstate(vap, nstate, arg); 1780 if (error != 0) 1781 goto back; 1782 1783 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1784 /* Nothing to do */ 1785 } else if (nstate == IEEE80211_S_RUN) { 1786 ni = vap->iv_bss; 1787 1788 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1789 1790 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1791 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1792 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1793 1794 /* Initial TX power calibration */ 1795 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1796 #ifdef notyet 1797 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1798 #else 1799 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1800 #endif 1801 if (vap->iv_opmode == IEEE80211_M_STA) { 1802 /* fake a join to init the tx rate */ 1803 bwi_newassoc(ni, 1); 1804 } 1805 1806 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1807 } else { 1808 bwi_set_bssid(sc, bwi_zero_addr); 1809 } 1810 back: 1811 BWI_UNLOCK(sc); 1812 1813 return error; 1814 } 1815 1816 /* ARGUSED */ 1817 static struct ieee80211_node * 1818 bwi_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1819 { 1820 struct bwi_node *bn; 1821 1822 bn = malloc(sizeof(struct bwi_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1823 return bn != NULL ? &bn->ni : NULL; 1824 } 1825 1826 static void 1827 bwi_newassoc(struct ieee80211_node *ni, int isnew) 1828 { 1829 struct ieee80211vap *vap = ni->ni_vap; 1830 1831 ieee80211_amrr_node_init(&BWI_VAP(vap)->bv_amrr, 1832 &BWI_NODE(ni)->amn, ni); 1833 } 1834 1835 static int 1836 bwi_media_change(struct ifnet *ifp) 1837 { 1838 int error = ieee80211_media_change(ifp); 1839 /* NB: only the fixed rate can change and that doesn't need a reset */ 1840 return (error == ENETRESET ? 0 : error); 1841 } 1842 1843 static int 1844 bwi_dma_alloc(struct bwi_softc *sc) 1845 { 1846 int error, i, has_txstats; 1847 bus_addr_t lowaddr = 0; 1848 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1849 uint32_t txrx_ctrl_step = 0; 1850 1851 has_txstats = 0; 1852 for (i = 0; i < sc->sc_nmac; ++i) { 1853 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1854 has_txstats = 1; 1855 break; 1856 } 1857 } 1858 1859 switch (sc->sc_bus_space) { 1860 case BWI_BUS_SPACE_30BIT: 1861 case BWI_BUS_SPACE_32BIT: 1862 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1863 lowaddr = BWI_BUS_SPACE_MAXADDR; 1864 else 1865 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1866 desc_sz = sizeof(struct bwi_desc32); 1867 txrx_ctrl_step = 0x20; 1868 1869 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1870 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1871 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1872 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1873 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1874 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1875 sc->sc_rxeof = bwi_rxeof32; 1876 sc->sc_start_tx = bwi_start_tx32; 1877 if (has_txstats) { 1878 sc->sc_init_txstats = bwi_init_txstats32; 1879 sc->sc_free_txstats = bwi_free_txstats32; 1880 sc->sc_txeof_status = bwi_txeof_status32; 1881 } 1882 break; 1883 1884 case BWI_BUS_SPACE_64BIT: 1885 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1886 desc_sz = sizeof(struct bwi_desc64); 1887 txrx_ctrl_step = 0x40; 1888 1889 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1890 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1891 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1892 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1893 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1894 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1895 sc->sc_rxeof = bwi_rxeof64; 1896 sc->sc_start_tx = bwi_start_tx64; 1897 if (has_txstats) { 1898 sc->sc_init_txstats = bwi_init_txstats64; 1899 sc->sc_free_txstats = bwi_free_txstats64; 1900 sc->sc_txeof_status = bwi_txeof_status64; 1901 } 1902 break; 1903 } 1904 1905 KASSERT(lowaddr != 0, ("lowaddr zero")); 1906 KASSERT(desc_sz != 0, ("desc_sz zero")); 1907 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1908 1909 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1910 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1911 1912 /* 1913 * Create top level DMA tag 1914 */ 1915 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1916 BWI_ALIGN, 0, /* alignment, bounds */ 1917 lowaddr, /* lowaddr */ 1918 BUS_SPACE_MAXADDR, /* highaddr */ 1919 NULL, NULL, /* filter, filterarg */ 1920 MAXBSIZE, /* maxsize */ 1921 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1922 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1923 BUS_DMA_ALLOCNOW, /* flags */ 1924 NULL, NULL, /* lockfunc, lockarg */ 1925 &sc->sc_parent_dtag); 1926 if (error) { 1927 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1928 return error; 1929 } 1930 1931 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1932 1933 /* 1934 * Create TX ring DMA stuffs 1935 */ 1936 error = bus_dma_tag_create(sc->sc_parent_dtag, 1937 BWI_RING_ALIGN, 0, 1938 BUS_SPACE_MAXADDR, 1939 BUS_SPACE_MAXADDR, 1940 NULL, NULL, 1941 tx_ring_sz, 1942 1, 1943 BUS_SPACE_MAXSIZE_32BIT, 1944 BUS_DMA_ALLOCNOW, 1945 NULL, NULL, 1946 &sc->sc_txring_dtag); 1947 if (error) { 1948 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1949 return error; 1950 } 1951 1952 for (i = 0; i < BWI_TX_NRING; ++i) { 1953 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1954 &sc->sc_tx_rdata[i], tx_ring_sz, 1955 TXRX_CTRL(i)); 1956 if (error) { 1957 device_printf(sc->sc_dev, "%dth TX ring " 1958 "DMA alloc failed\n", i); 1959 return error; 1960 } 1961 } 1962 1963 /* 1964 * Create RX ring DMA stuffs 1965 */ 1966 error = bus_dma_tag_create(sc->sc_parent_dtag, 1967 BWI_RING_ALIGN, 0, 1968 BUS_SPACE_MAXADDR, 1969 BUS_SPACE_MAXADDR, 1970 NULL, NULL, 1971 rx_ring_sz, 1972 1, 1973 BUS_SPACE_MAXSIZE_32BIT, 1974 BUS_DMA_ALLOCNOW, 1975 NULL, NULL, 1976 &sc->sc_rxring_dtag); 1977 if (error) { 1978 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1979 return error; 1980 } 1981 1982 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1983 rx_ring_sz, TXRX_CTRL(0)); 1984 if (error) { 1985 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1986 return error; 1987 } 1988 1989 if (has_txstats) { 1990 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1991 if (error) { 1992 device_printf(sc->sc_dev, 1993 "TX stats DMA alloc failed\n"); 1994 return error; 1995 } 1996 } 1997 1998 #undef TXRX_CTRL 1999 2000 return bwi_dma_mbuf_create(sc); 2001 } 2002 2003 static void 2004 bwi_dma_free(struct bwi_softc *sc) 2005 { 2006 if (sc->sc_txring_dtag != NULL) { 2007 int i; 2008 2009 for (i = 0; i < BWI_TX_NRING; ++i) { 2010 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2011 2012 if (rd->rdata_desc != NULL) { 2013 bus_dmamap_unload(sc->sc_txring_dtag, 2014 rd->rdata_dmap); 2015 bus_dmamem_free(sc->sc_txring_dtag, 2016 rd->rdata_desc, 2017 rd->rdata_dmap); 2018 } 2019 } 2020 bus_dma_tag_destroy(sc->sc_txring_dtag); 2021 } 2022 2023 if (sc->sc_rxring_dtag != NULL) { 2024 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2025 2026 if (rd->rdata_desc != NULL) { 2027 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2028 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2029 rd->rdata_dmap); 2030 } 2031 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2032 } 2033 2034 bwi_dma_txstats_free(sc); 2035 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2036 2037 if (sc->sc_parent_dtag != NULL) 2038 bus_dma_tag_destroy(sc->sc_parent_dtag); 2039 } 2040 2041 static int 2042 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2043 struct bwi_ring_data *rd, bus_size_t size, 2044 uint32_t txrx_ctrl) 2045 { 2046 int error; 2047 2048 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2049 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2050 &rd->rdata_dmap); 2051 if (error) { 2052 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2053 return error; 2054 } 2055 2056 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2057 bwi_dma_ring_addr, &rd->rdata_paddr, 2058 BUS_DMA_NOWAIT); 2059 if (error) { 2060 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2061 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2062 rd->rdata_desc = NULL; 2063 return error; 2064 } 2065 2066 rd->rdata_txrx_ctrl = txrx_ctrl; 2067 return 0; 2068 } 2069 2070 static int 2071 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2072 bus_size_t desc_sz) 2073 { 2074 struct bwi_txstats_data *st; 2075 bus_size_t dma_size; 2076 int error; 2077 2078 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2079 if (st == NULL) { 2080 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2081 return ENOMEM; 2082 } 2083 sc->sc_txstats = st; 2084 2085 /* 2086 * Create TX stats descriptor DMA stuffs 2087 */ 2088 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2089 2090 error = bus_dma_tag_create(sc->sc_parent_dtag, 2091 BWI_RING_ALIGN, 2092 0, 2093 BUS_SPACE_MAXADDR, 2094 BUS_SPACE_MAXADDR, 2095 NULL, NULL, 2096 dma_size, 2097 1, 2098 BUS_SPACE_MAXSIZE_32BIT, 2099 BUS_DMA_ALLOCNOW, 2100 NULL, NULL, 2101 &st->stats_ring_dtag); 2102 if (error) { 2103 device_printf(sc->sc_dev, "can't create txstats ring " 2104 "DMA tag\n"); 2105 return error; 2106 } 2107 2108 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2109 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2110 &st->stats_ring_dmap); 2111 if (error) { 2112 device_printf(sc->sc_dev, "can't allocate txstats ring " 2113 "DMA mem\n"); 2114 bus_dma_tag_destroy(st->stats_ring_dtag); 2115 st->stats_ring_dtag = NULL; 2116 return error; 2117 } 2118 2119 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2120 st->stats_ring, dma_size, 2121 bwi_dma_ring_addr, &st->stats_ring_paddr, 2122 BUS_DMA_NOWAIT); 2123 if (error) { 2124 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2125 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2126 st->stats_ring_dmap); 2127 bus_dma_tag_destroy(st->stats_ring_dtag); 2128 st->stats_ring_dtag = NULL; 2129 return error; 2130 } 2131 2132 /* 2133 * Create TX stats DMA stuffs 2134 */ 2135 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2136 BWI_ALIGN); 2137 2138 error = bus_dma_tag_create(sc->sc_parent_dtag, 2139 BWI_ALIGN, 2140 0, 2141 BUS_SPACE_MAXADDR, 2142 BUS_SPACE_MAXADDR, 2143 NULL, NULL, 2144 dma_size, 2145 1, 2146 BUS_SPACE_MAXSIZE_32BIT, 2147 BUS_DMA_ALLOCNOW, 2148 NULL, NULL, 2149 &st->stats_dtag); 2150 if (error) { 2151 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2152 return error; 2153 } 2154 2155 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2156 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2157 &st->stats_dmap); 2158 if (error) { 2159 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2160 bus_dma_tag_destroy(st->stats_dtag); 2161 st->stats_dtag = NULL; 2162 return error; 2163 } 2164 2165 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2166 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2167 BUS_DMA_NOWAIT); 2168 if (error) { 2169 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2170 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2171 bus_dma_tag_destroy(st->stats_dtag); 2172 st->stats_dtag = NULL; 2173 return error; 2174 } 2175 2176 st->stats_ctrl_base = ctrl_base; 2177 return 0; 2178 } 2179 2180 static void 2181 bwi_dma_txstats_free(struct bwi_softc *sc) 2182 { 2183 struct bwi_txstats_data *st; 2184 2185 if (sc->sc_txstats == NULL) 2186 return; 2187 st = sc->sc_txstats; 2188 2189 if (st->stats_ring_dtag != NULL) { 2190 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2191 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2192 st->stats_ring_dmap); 2193 bus_dma_tag_destroy(st->stats_ring_dtag); 2194 } 2195 2196 if (st->stats_dtag != NULL) { 2197 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2198 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2199 bus_dma_tag_destroy(st->stats_dtag); 2200 } 2201 2202 free(st, M_DEVBUF); 2203 } 2204 2205 static void 2206 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2207 { 2208 KASSERT(nseg == 1, ("too many segments\n")); 2209 *((bus_addr_t *)arg) = seg->ds_addr; 2210 } 2211 2212 static int 2213 bwi_dma_mbuf_create(struct bwi_softc *sc) 2214 { 2215 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2216 int i, j, k, ntx, error; 2217 2218 /* 2219 * Create TX/RX mbuf DMA tag 2220 */ 2221 error = bus_dma_tag_create(sc->sc_parent_dtag, 2222 1, 2223 0, 2224 BUS_SPACE_MAXADDR, 2225 BUS_SPACE_MAXADDR, 2226 NULL, NULL, 2227 MCLBYTES, 2228 1, 2229 BUS_SPACE_MAXSIZE_32BIT, 2230 BUS_DMA_ALLOCNOW, 2231 NULL, NULL, 2232 &sc->sc_buf_dtag); 2233 if (error) { 2234 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2235 return error; 2236 } 2237 2238 ntx = 0; 2239 2240 /* 2241 * Create TX mbuf DMA map 2242 */ 2243 for (i = 0; i < BWI_TX_NRING; ++i) { 2244 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2245 2246 for (j = 0; j < BWI_TX_NDESC; ++j) { 2247 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2248 &tbd->tbd_buf[j].tb_dmap); 2249 if (error) { 2250 device_printf(sc->sc_dev, "can't create " 2251 "%dth tbd, %dth DMA map\n", i, j); 2252 2253 ntx = i; 2254 for (k = 0; k < j; ++k) { 2255 bus_dmamap_destroy(sc->sc_buf_dtag, 2256 tbd->tbd_buf[k].tb_dmap); 2257 } 2258 goto fail; 2259 } 2260 } 2261 } 2262 ntx = BWI_TX_NRING; 2263 2264 /* 2265 * Create RX mbuf DMA map and a spare DMA map 2266 */ 2267 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2268 &rbd->rbd_tmp_dmap); 2269 if (error) { 2270 device_printf(sc->sc_dev, 2271 "can't create spare RX buf DMA map\n"); 2272 goto fail; 2273 } 2274 2275 for (j = 0; j < BWI_RX_NDESC; ++j) { 2276 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2277 &rbd->rbd_buf[j].rb_dmap); 2278 if (error) { 2279 device_printf(sc->sc_dev, "can't create %dth " 2280 "RX buf DMA map\n", j); 2281 2282 for (k = 0; k < j; ++k) { 2283 bus_dmamap_destroy(sc->sc_buf_dtag, 2284 rbd->rbd_buf[j].rb_dmap); 2285 } 2286 bus_dmamap_destroy(sc->sc_buf_dtag, 2287 rbd->rbd_tmp_dmap); 2288 goto fail; 2289 } 2290 } 2291 2292 return 0; 2293 fail: 2294 bwi_dma_mbuf_destroy(sc, ntx, 0); 2295 return error; 2296 } 2297 2298 static void 2299 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2300 { 2301 int i, j; 2302 2303 if (sc->sc_buf_dtag == NULL) 2304 return; 2305 2306 for (i = 0; i < ntx; ++i) { 2307 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2308 2309 for (j = 0; j < BWI_TX_NDESC; ++j) { 2310 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2311 2312 if (tb->tb_mbuf != NULL) { 2313 bus_dmamap_unload(sc->sc_buf_dtag, 2314 tb->tb_dmap); 2315 m_freem(tb->tb_mbuf); 2316 } 2317 if (tb->tb_ni != NULL) 2318 ieee80211_free_node(tb->tb_ni); 2319 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2320 } 2321 } 2322 2323 if (nrx) { 2324 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2325 2326 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2327 for (j = 0; j < BWI_RX_NDESC; ++j) { 2328 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2329 2330 if (rb->rb_mbuf != NULL) { 2331 bus_dmamap_unload(sc->sc_buf_dtag, 2332 rb->rb_dmap); 2333 m_freem(rb->rb_mbuf); 2334 } 2335 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2336 } 2337 } 2338 2339 bus_dma_tag_destroy(sc->sc_buf_dtag); 2340 sc->sc_buf_dtag = NULL; 2341 } 2342 2343 static void 2344 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2345 { 2346 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2347 } 2348 2349 static void 2350 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2351 { 2352 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2353 } 2354 2355 static int 2356 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2357 { 2358 struct bwi_ring_data *rd; 2359 struct bwi_txbuf_data *tbd; 2360 uint32_t val, addr_hi, addr_lo; 2361 2362 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2363 rd = &sc->sc_tx_rdata[ring_idx]; 2364 tbd = &sc->sc_tx_bdata[ring_idx]; 2365 2366 tbd->tbd_idx = 0; 2367 tbd->tbd_used = 0; 2368 2369 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2370 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2371 BUS_DMASYNC_PREWRITE); 2372 2373 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2374 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2375 2376 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2377 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2378 BWI_TXRX32_RINGINFO_FUNC_MASK); 2379 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2380 2381 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2382 BWI_TXRX32_CTRL_ENABLE; 2383 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2384 2385 return 0; 2386 } 2387 2388 static void 2389 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2390 bus_addr_t paddr, int hdr_size, int ndesc) 2391 { 2392 uint32_t val, addr_hi, addr_lo; 2393 2394 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2395 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2396 2397 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2398 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2399 BWI_TXRX32_RINGINFO_FUNC_MASK); 2400 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2401 2402 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2403 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2404 BWI_TXRX32_CTRL_ENABLE; 2405 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2406 2407 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2408 (ndesc - 1) * sizeof(struct bwi_desc32)); 2409 } 2410 2411 static int 2412 bwi_init_rx_ring32(struct bwi_softc *sc) 2413 { 2414 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2415 int i, error; 2416 2417 sc->sc_rx_bdata.rbd_idx = 0; 2418 2419 for (i = 0; i < BWI_RX_NDESC; ++i) { 2420 error = bwi_newbuf(sc, i, 1); 2421 if (error) { 2422 device_printf(sc->sc_dev, 2423 "can't allocate %dth RX buffer\n", i); 2424 return error; 2425 } 2426 } 2427 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2428 BUS_DMASYNC_PREWRITE); 2429 2430 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2431 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2432 return 0; 2433 } 2434 2435 static int 2436 bwi_init_txstats32(struct bwi_softc *sc) 2437 { 2438 struct bwi_txstats_data *st = sc->sc_txstats; 2439 bus_addr_t stats_paddr; 2440 int i; 2441 2442 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2443 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2444 2445 st->stats_idx = 0; 2446 2447 stats_paddr = st->stats_paddr; 2448 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2449 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2450 stats_paddr, sizeof(struct bwi_txstats), 0); 2451 stats_paddr += sizeof(struct bwi_txstats); 2452 } 2453 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2454 BUS_DMASYNC_PREWRITE); 2455 2456 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2457 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2458 return 0; 2459 } 2460 2461 static void 2462 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2463 int buf_len) 2464 { 2465 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2466 2467 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2468 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2469 paddr, buf_len, 0); 2470 } 2471 2472 static void 2473 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2474 int buf_idx, bus_addr_t paddr, int buf_len) 2475 { 2476 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2477 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2478 paddr, buf_len, 1); 2479 } 2480 2481 static int 2482 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2483 { 2484 /* TODO:64 */ 2485 return EOPNOTSUPP; 2486 } 2487 2488 static int 2489 bwi_init_rx_ring64(struct bwi_softc *sc) 2490 { 2491 /* TODO:64 */ 2492 return EOPNOTSUPP; 2493 } 2494 2495 static int 2496 bwi_init_txstats64(struct bwi_softc *sc) 2497 { 2498 /* TODO:64 */ 2499 return EOPNOTSUPP; 2500 } 2501 2502 static void 2503 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2504 int buf_len) 2505 { 2506 /* TODO:64 */ 2507 } 2508 2509 static void 2510 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2511 int buf_idx, bus_addr_t paddr, int buf_len) 2512 { 2513 /* TODO:64 */ 2514 } 2515 2516 static void 2517 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2518 bus_size_t mapsz __unused, int error) 2519 { 2520 if (!error) { 2521 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2522 *((bus_addr_t *)arg) = seg->ds_addr; 2523 } 2524 } 2525 2526 static int 2527 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2528 { 2529 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2530 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2531 struct bwi_rxbuf_hdr *hdr; 2532 bus_dmamap_t map; 2533 bus_addr_t paddr; 2534 struct mbuf *m; 2535 int error; 2536 2537 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2538 2539 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2540 if (m == NULL) { 2541 error = ENOBUFS; 2542 2543 /* 2544 * If the NIC is up and running, we need to: 2545 * - Clear RX buffer's header. 2546 * - Restore RX descriptor settings. 2547 */ 2548 if (init) 2549 return error; 2550 else 2551 goto back; 2552 } 2553 m->m_len = m->m_pkthdr.len = MCLBYTES; 2554 2555 /* 2556 * Try to load RX buf into temporary DMA map 2557 */ 2558 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2559 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2560 if (error) { 2561 m_freem(m); 2562 2563 /* 2564 * See the comment above 2565 */ 2566 if (init) 2567 return error; 2568 else 2569 goto back; 2570 } 2571 2572 if (!init) 2573 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2574 rxbuf->rb_mbuf = m; 2575 rxbuf->rb_paddr = paddr; 2576 2577 /* 2578 * Swap RX buf's DMA map with the loaded temporary one 2579 */ 2580 map = rxbuf->rb_dmap; 2581 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2582 rbd->rbd_tmp_dmap = map; 2583 2584 back: 2585 /* 2586 * Clear RX buf header 2587 */ 2588 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2589 bzero(hdr, sizeof(*hdr)); 2590 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2591 2592 /* 2593 * Setup RX buf descriptor 2594 */ 2595 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2596 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2597 return error; 2598 } 2599 2600 static void 2601 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2602 const uint8_t *addr) 2603 { 2604 int i; 2605 2606 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2607 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2608 2609 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2610 uint16_t addr_val; 2611 2612 addr_val = (uint16_t)addr[i * 2] | 2613 (((uint16_t)addr[(i * 2) + 1]) << 8); 2614 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2615 } 2616 } 2617 2618 static int 2619 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2620 { 2621 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2622 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2623 struct ifnet *ifp = sc->sc_ifp; 2624 struct ieee80211com *ic = ifp->if_l2com; 2625 int idx, rx_data = 0; 2626 2627 idx = rbd->rbd_idx; 2628 while (idx != end_idx) { 2629 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2630 struct bwi_rxbuf_hdr *hdr; 2631 struct ieee80211_frame_min *wh; 2632 struct ieee80211_node *ni; 2633 struct mbuf *m; 2634 const void *plcp; 2635 uint16_t flags2; 2636 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2637 2638 m = rb->rb_mbuf; 2639 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2640 BUS_DMASYNC_POSTREAD); 2641 2642 if (bwi_newbuf(sc, idx, 0)) { 2643 ifp->if_ierrors++; 2644 goto next; 2645 } 2646 2647 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2648 flags2 = le16toh(hdr->rxh_flags2); 2649 2650 hdr_extra = 0; 2651 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2652 hdr_extra = 2; 2653 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2654 2655 buflen = le16toh(hdr->rxh_buflen); 2656 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2657 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2658 __func__, hdr_extra); 2659 ifp->if_ierrors++; 2660 m_freem(m); 2661 goto next; 2662 } 2663 2664 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra); 2665 rssi = bwi_calc_rssi(sc, hdr); 2666 noise = bwi_calc_noise(sc); 2667 2668 m->m_pkthdr.rcvif = ifp; 2669 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2670 m_adj(m, sizeof(*hdr) + wh_ofs); 2671 2672 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2673 rate = bwi_ofdm_plcp2rate(plcp); 2674 else 2675 rate = bwi_ds_plcp2rate(plcp); 2676 2677 /* RX radio tap */ 2678 if (bpf_peers_present(ifp->if_bpf)) 2679 bwi_rx_radiotap(ifp, m, hdr, plcp, rate, rssi, noise); 2680 2681 m_adj(m, -IEEE80211_CRC_LEN); 2682 2683 BWI_UNLOCK(sc); 2684 2685 wh = mtod(m, struct ieee80211_frame_min *); 2686 ni = ieee80211_find_rxnode(ic, wh); 2687 if (ni != NULL) { 2688 type = ieee80211_input(ni, m, rssi - noise, noise, 0); 2689 ieee80211_free_node(ni); 2690 } else 2691 type = ieee80211_input_all(ic, m, rssi - noise, 2692 noise, 0); 2693 if (type == IEEE80211_FC0_TYPE_DATA) { 2694 rx_data = 1; 2695 sc->sc_rx_rate = rate; 2696 } 2697 2698 BWI_LOCK(sc); 2699 next: 2700 idx = (idx + 1) % BWI_RX_NDESC; 2701 2702 if (sc->sc_flags & BWI_F_STOP) { 2703 /* 2704 * Take the fast lane, don't do 2705 * any damage to softc 2706 */ 2707 return -1; 2708 } 2709 } 2710 2711 rbd->rbd_idx = idx; 2712 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2713 BUS_DMASYNC_PREWRITE); 2714 2715 return rx_data; 2716 } 2717 2718 static int 2719 bwi_rxeof32(struct bwi_softc *sc) 2720 { 2721 uint32_t val, rx_ctrl; 2722 int end_idx, rx_data; 2723 2724 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2725 2726 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2727 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2728 sizeof(struct bwi_desc32); 2729 2730 rx_data = bwi_rxeof(sc, end_idx); 2731 if (rx_data >= 0) { 2732 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2733 end_idx * sizeof(struct bwi_desc32)); 2734 } 2735 return rx_data; 2736 } 2737 2738 static int 2739 bwi_rxeof64(struct bwi_softc *sc) 2740 { 2741 /* TODO:64 */ 2742 return 0; 2743 } 2744 2745 static void 2746 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2747 { 2748 int i; 2749 2750 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2751 2752 #define NRETRY 10 2753 2754 for (i = 0; i < NRETRY; ++i) { 2755 uint32_t status; 2756 2757 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2758 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2759 BWI_RX32_STATUS_STATE_DISABLED) 2760 break; 2761 2762 DELAY(1000); 2763 } 2764 if (i == NRETRY) 2765 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2766 2767 #undef NRETRY 2768 2769 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2770 } 2771 2772 static void 2773 bwi_free_txstats32(struct bwi_softc *sc) 2774 { 2775 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2776 } 2777 2778 static void 2779 bwi_free_rx_ring32(struct bwi_softc *sc) 2780 { 2781 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2782 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2783 int i; 2784 2785 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2786 2787 for (i = 0; i < BWI_RX_NDESC; ++i) { 2788 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2789 2790 if (rb->rb_mbuf != NULL) { 2791 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2792 m_freem(rb->rb_mbuf); 2793 rb->rb_mbuf = NULL; 2794 } 2795 } 2796 } 2797 2798 static void 2799 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2800 { 2801 struct bwi_ring_data *rd; 2802 struct bwi_txbuf_data *tbd; 2803 struct ifnet *ifp = sc->sc_ifp; 2804 uint32_t state, val; 2805 int i; 2806 2807 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2808 rd = &sc->sc_tx_rdata[ring_idx]; 2809 tbd = &sc->sc_tx_bdata[ring_idx]; 2810 2811 #define NRETRY 10 2812 2813 for (i = 0; i < NRETRY; ++i) { 2814 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2815 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2816 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2817 state == BWI_TX32_STATUS_STATE_IDLE || 2818 state == BWI_TX32_STATUS_STATE_STOPPED) 2819 break; 2820 2821 DELAY(1000); 2822 } 2823 if (i == NRETRY) { 2824 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2825 __func__, ring_idx); 2826 } 2827 2828 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2829 for (i = 0; i < NRETRY; ++i) { 2830 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2831 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2832 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2833 break; 2834 2835 DELAY(1000); 2836 } 2837 if (i == NRETRY) 2838 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2839 __func__, ring_idx); 2840 2841 #undef NRETRY 2842 2843 DELAY(1000); 2844 2845 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2846 2847 for (i = 0; i < BWI_TX_NDESC; ++i) { 2848 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2849 2850 if (tb->tb_mbuf != NULL) { 2851 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2852 m_freem(tb->tb_mbuf); 2853 tb->tb_mbuf = NULL; 2854 } 2855 if (tb->tb_ni != NULL) { 2856 ieee80211_free_node(tb->tb_ni); 2857 tb->tb_ni = NULL; 2858 } 2859 } 2860 } 2861 2862 static void 2863 bwi_free_txstats64(struct bwi_softc *sc) 2864 { 2865 /* TODO:64 */ 2866 } 2867 2868 static void 2869 bwi_free_rx_ring64(struct bwi_softc *sc) 2870 { 2871 /* TODO:64 */ 2872 } 2873 2874 static void 2875 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2876 { 2877 /* TODO:64 */ 2878 } 2879 2880 /* XXX does not belong here */ 2881 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2882 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2883 2884 static __inline void 2885 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2886 { 2887 uint32_t plcp; 2888 2889 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2890 IEEE80211_OFDM_PLCP_RATE_MASK) | 2891 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2892 *plcp0 = htole32(plcp); 2893 } 2894 2895 static __inline void 2896 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2897 uint8_t rate) 2898 { 2899 int len, service, pkt_bitlen; 2900 2901 pkt_bitlen = pkt_len * NBBY; 2902 len = howmany(pkt_bitlen * 2, rate); 2903 2904 service = IEEE80211_PLCP_SERVICE_LOCKED; 2905 if (rate == (11 * 2)) { 2906 int pkt_bitlen1; 2907 2908 /* 2909 * PLCP service field needs to be adjusted, 2910 * if TX rate is 11Mbytes/s 2911 */ 2912 pkt_bitlen1 = len * 11; 2913 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2914 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2915 } 2916 2917 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2918 plcp->i_service = service; 2919 plcp->i_length = htole16(len); 2920 /* NOTE: do NOT touch i_crc */ 2921 } 2922 2923 static __inline void 2924 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2925 void *plcp, int pkt_len, uint8_t rate) 2926 { 2927 enum ieee80211_phytype modtype; 2928 2929 /* 2930 * Assume caller has zeroed 'plcp' 2931 */ 2932 modtype = ieee80211_rate2phytype(rt, rate); 2933 if (modtype == IEEE80211_T_OFDM) 2934 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2935 else if (modtype == IEEE80211_T_DS) 2936 bwi_ds_plcp_header(plcp, pkt_len, rate); 2937 else 2938 panic("unsupport modulation type %u\n", modtype); 2939 } 2940 2941 static int 2942 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2943 struct ieee80211_node *ni) 2944 { 2945 struct ieee80211vap *vap = ni->ni_vap; 2946 struct ifnet *ifp = sc->sc_ifp; 2947 struct ieee80211com *ic = ifp->if_l2com; 2948 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2949 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2950 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2951 struct bwi_mac *mac; 2952 struct bwi_txbuf_hdr *hdr; 2953 struct ieee80211_frame *wh; 2954 const struct ieee80211_txparam *tp; 2955 uint8_t rate, rate_fb; 2956 uint32_t mac_ctrl; 2957 uint16_t phy_ctrl; 2958 bus_addr_t paddr; 2959 int type, ismcast, pkt_len, error, rix; 2960 #if 0 2961 const uint8_t *p; 2962 int i; 2963 #endif 2964 2965 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2966 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2967 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2968 2969 wh = mtod(m, struct ieee80211_frame *); 2970 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2971 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2972 2973 /* Get 802.11 frame len before prepending TX header */ 2974 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2975 2976 /* 2977 * Find TX rate 2978 */ 2979 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2980 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2981 rate = rate_fb = tp->mgmtrate; 2982 } else if (ismcast) { 2983 rate = rate_fb = tp->mcastrate; 2984 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2985 rate = rate_fb = tp->ucastrate; 2986 } else { 2987 rix = ieee80211_amrr_choose(ni, &BWI_NODE(ni)->amn); 2988 rate = ni->ni_txrate; 2989 2990 if (rix > 0) { 2991 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2992 IEEE80211_RATE_VAL; 2993 } else { 2994 rate_fb = rate; 2995 } 2996 } 2997 tb->tb_rate[0] = rate; 2998 tb->tb_rate[1] = rate_fb; 2999 sc->sc_tx_rate = rate; 3000 3001 /* 3002 * TX radio tap 3003 */ 3004 if (bpf_peers_present(ifp->if_bpf)) { 3005 sc->sc_tx_th.wt_flags = 0; 3006 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3007 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3008 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3009 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3010 rate != (1 * 2)) { 3011 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3012 } 3013 sc->sc_tx_th.wt_rate = rate; 3014 3015 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m); 3016 } 3017 3018 /* 3019 * Setup the embedded TX header 3020 */ 3021 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3022 if (m == NULL) { 3023 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3024 return ENOBUFS; 3025 } 3026 hdr = mtod(m, struct bwi_txbuf_hdr *); 3027 3028 bzero(hdr, sizeof(*hdr)); 3029 3030 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3031 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3032 3033 if (!ismcast) { 3034 uint16_t dur; 3035 3036 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3037 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3038 3039 hdr->txh_fb_duration = htole16(dur); 3040 } 3041 3042 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3043 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3044 3045 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3046 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3047 3048 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3049 BWI_TXH_PHY_C_ANTMODE_MASK); 3050 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3051 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3052 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3053 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3054 3055 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3056 if (!ismcast) 3057 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3058 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3059 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3060 3061 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3062 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3063 3064 /* Catch any further usage */ 3065 hdr = NULL; 3066 wh = NULL; 3067 3068 /* DMA load */ 3069 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3070 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3071 if (error && error != EFBIG) { 3072 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3073 __func__, error); 3074 goto back; 3075 } 3076 3077 if (error) { /* error == EFBIG */ 3078 struct mbuf *m_new; 3079 3080 m_new = m_defrag(m, M_DONTWAIT); 3081 if (m_new == NULL) { 3082 if_printf(ifp, "%s: can't defrag TX buffer\n", 3083 __func__); 3084 error = ENOBUFS; 3085 goto back; 3086 } else { 3087 m = m_new; 3088 } 3089 3090 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3091 bwi_dma_buf_addr, &paddr, 3092 BUS_DMA_NOWAIT); 3093 if (error) { 3094 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3095 __func__, error); 3096 goto back; 3097 } 3098 } 3099 error = 0; 3100 3101 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3102 3103 tb->tb_mbuf = m; 3104 tb->tb_ni = ni; 3105 3106 #if 0 3107 p = mtod(m, const uint8_t *); 3108 for (i = 0; i < m->m_pkthdr.len; ++i) { 3109 if (i != 0 && i % 8 == 0) 3110 printf("\n"); 3111 printf("%02x ", p[i]); 3112 } 3113 printf("\n"); 3114 #endif 3115 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3116 idx, pkt_len, m->m_pkthdr.len); 3117 3118 /* Setup TX descriptor */ 3119 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3120 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3121 BUS_DMASYNC_PREWRITE); 3122 3123 /* Kick start */ 3124 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3125 3126 back: 3127 if (error) 3128 m_freem(m); 3129 return error; 3130 } 3131 3132 static int 3133 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3134 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3135 { 3136 struct ifnet *ifp = sc->sc_ifp; 3137 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3138 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3139 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3140 struct bwi_mac *mac; 3141 struct bwi_txbuf_hdr *hdr; 3142 struct ieee80211_frame *wh; 3143 uint8_t rate, rate_fb; 3144 uint32_t mac_ctrl; 3145 uint16_t phy_ctrl; 3146 bus_addr_t paddr; 3147 int ismcast, pkt_len, error; 3148 3149 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3150 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3151 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3152 3153 wh = mtod(m, struct ieee80211_frame *); 3154 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3155 3156 /* Get 802.11 frame len before prepending TX header */ 3157 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3158 3159 /* 3160 * Find TX rate 3161 */ 3162 rate = params->ibp_rate0; 3163 rate_fb = (params->ibp_try1 != 0) ? 3164 params->ibp_rate1 : params->ibp_rate0; 3165 tb->tb_rate[0] = rate; 3166 tb->tb_rate[1] = rate_fb; 3167 sc->sc_tx_rate = rate; 3168 3169 /* 3170 * TX radio tap 3171 */ 3172 if (bpf_peers_present(ifp->if_bpf)) { 3173 sc->sc_tx_th.wt_flags = 0; 3174 /* XXX IEEE80211_BPF_CRYPTO */ 3175 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3176 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3177 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3178 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3179 sc->sc_tx_th.wt_rate = rate; 3180 3181 bpf_mtap2(ifp->if_bpf, &sc->sc_tx_th, sc->sc_tx_th_len, m); 3182 } 3183 3184 /* 3185 * Setup the embedded TX header 3186 */ 3187 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3188 if (m == NULL) { 3189 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3190 return ENOBUFS; 3191 } 3192 hdr = mtod(m, struct bwi_txbuf_hdr *); 3193 3194 bzero(hdr, sizeof(*hdr)); 3195 3196 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3197 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3198 3199 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3200 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3201 uint16_t dur; 3202 3203 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3204 3205 hdr->txh_fb_duration = htole16(dur); 3206 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3207 } 3208 3209 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3210 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3211 3212 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3213 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3214 3215 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3216 BWI_TXH_PHY_C_ANTMODE_MASK); 3217 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3218 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3219 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3220 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3221 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3222 3223 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3224 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3225 3226 /* Catch any further usage */ 3227 hdr = NULL; 3228 wh = NULL; 3229 3230 /* DMA load */ 3231 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3232 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3233 if (error != 0) { 3234 struct mbuf *m_new; 3235 3236 if (error != EFBIG) { 3237 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3238 __func__, error); 3239 goto back; 3240 } 3241 m_new = m_defrag(m, M_DONTWAIT); 3242 if (m_new == NULL) { 3243 if_printf(ifp, "%s: can't defrag TX buffer\n", 3244 __func__); 3245 error = ENOBUFS; 3246 goto back; 3247 } 3248 m = m_new; 3249 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3250 bwi_dma_buf_addr, &paddr, 3251 BUS_DMA_NOWAIT); 3252 if (error) { 3253 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3254 __func__, error); 3255 goto back; 3256 } 3257 } 3258 3259 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3260 3261 tb->tb_mbuf = m; 3262 tb->tb_ni = ni; 3263 3264 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3265 idx, pkt_len, m->m_pkthdr.len); 3266 3267 /* Setup TX descriptor */ 3268 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3269 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3270 BUS_DMASYNC_PREWRITE); 3271 3272 /* Kick start */ 3273 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3274 back: 3275 if (error) 3276 m_freem(m); 3277 return error; 3278 } 3279 3280 static void 3281 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3282 { 3283 idx = (idx + 1) % BWI_TX_NDESC; 3284 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3285 idx * sizeof(struct bwi_desc32)); 3286 } 3287 3288 static void 3289 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3290 { 3291 /* TODO:64 */ 3292 } 3293 3294 static void 3295 bwi_txeof_status32(struct bwi_softc *sc) 3296 { 3297 struct ifnet *ifp = sc->sc_ifp; 3298 uint32_t val, ctrl_base; 3299 int end_idx; 3300 3301 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3302 3303 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3304 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3305 sizeof(struct bwi_desc32); 3306 3307 bwi_txeof_status(sc, end_idx); 3308 3309 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3310 end_idx * sizeof(struct bwi_desc32)); 3311 3312 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3313 ifp->if_start(ifp); 3314 } 3315 3316 static void 3317 bwi_txeof_status64(struct bwi_softc *sc) 3318 { 3319 /* TODO:64 */ 3320 } 3321 3322 static void 3323 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3324 { 3325 struct ifnet *ifp = sc->sc_ifp; 3326 struct bwi_txbuf_data *tbd; 3327 struct bwi_txbuf *tb; 3328 int ring_idx, buf_idx; 3329 struct ieee80211_node *ni; 3330 3331 if (tx_id == 0) { 3332 if_printf(ifp, "%s: zero tx id\n", __func__); 3333 return; 3334 } 3335 3336 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3337 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3338 3339 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3340 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3341 3342 tbd = &sc->sc_tx_bdata[ring_idx]; 3343 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3344 tbd->tbd_used--; 3345 3346 tb = &tbd->tbd_buf[buf_idx]; 3347 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3348 "acked %d, data_txcnt %d, ni %p\n", 3349 buf_idx, acked, data_txcnt, tb->tb_ni); 3350 3351 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3352 3353 ni = tb->tb_ni; 3354 if (tb->tb_ni != NULL) { 3355 struct bwi_node *bn = (struct bwi_node *) tb->tb_ni; 3356 const struct bwi_txbuf_hdr *hdr = 3357 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3358 3359 /* NB: update rate control only for unicast frames */ 3360 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3361 /* 3362 * Feed back 'acked and data_txcnt'. Note that the 3363 * generic AMRR code only understands one tx rate 3364 * and the estimator doesn't handle real retry counts 3365 * well so to avoid over-aggressive downshifting we 3366 * treat any number of retries as "1". 3367 */ 3368 ieee80211_amrr_tx_complete(&bn->amn, acked, 3369 data_txcnt > 1); 3370 } 3371 3372 /* 3373 * Do any tx complete callback. Note this must 3374 * be done before releasing the node reference. 3375 */ 3376 if (tb->tb_mbuf->m_flags & M_TXCB) 3377 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3378 3379 ieee80211_free_node(tb->tb_ni); 3380 tb->tb_ni = NULL; 3381 } 3382 m_freem(tb->tb_mbuf); 3383 tb->tb_mbuf = NULL; 3384 3385 if (tbd->tbd_used == 0) 3386 ifp->if_timer = 0; 3387 3388 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3389 } 3390 3391 static void 3392 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3393 { 3394 struct bwi_txstats_data *st = sc->sc_txstats; 3395 int idx; 3396 3397 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3398 3399 idx = st->stats_idx; 3400 while (idx != end_idx) { 3401 const struct bwi_txstats *stats = &st->stats[idx]; 3402 3403 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3404 int data_txcnt; 3405 3406 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3407 BWI_TXS_TXCNT_DATA); 3408 _bwi_txeof(sc, le16toh(stats->txs_id), 3409 stats->txs_flags & BWI_TXS_F_ACKED, 3410 data_txcnt); 3411 } 3412 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3413 } 3414 st->stats_idx = idx; 3415 } 3416 3417 static void 3418 bwi_txeof(struct bwi_softc *sc) 3419 { 3420 struct ifnet *ifp = sc->sc_ifp; 3421 3422 for (;;) { 3423 uint32_t tx_status0, tx_status1; 3424 uint16_t tx_id; 3425 int data_txcnt; 3426 3427 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3428 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3429 break; 3430 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3431 3432 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3433 data_txcnt = __SHIFTOUT(tx_status0, 3434 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3435 3436 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3437 continue; 3438 3439 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3440 data_txcnt); 3441 } 3442 3443 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3444 ifp->if_start(ifp); 3445 } 3446 3447 static int 3448 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3449 { 3450 bwi_power_on(sc, 1); 3451 return bwi_set_clock_mode(sc, clk_mode); 3452 } 3453 3454 static void 3455 bwi_bbp_power_off(struct bwi_softc *sc) 3456 { 3457 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3458 bwi_power_off(sc, 1); 3459 } 3460 3461 static int 3462 bwi_get_pwron_delay(struct bwi_softc *sc) 3463 { 3464 struct bwi_regwin *com, *old; 3465 struct bwi_clock_freq freq; 3466 uint32_t val; 3467 int error; 3468 3469 com = &sc->sc_com_regwin; 3470 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3471 3472 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3473 return 0; 3474 3475 error = bwi_regwin_switch(sc, com, &old); 3476 if (error) 3477 return error; 3478 3479 bwi_get_clock_freq(sc, &freq); 3480 3481 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3482 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3483 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3484 3485 return bwi_regwin_switch(sc, old, NULL); 3486 } 3487 3488 static int 3489 bwi_bus_attach(struct bwi_softc *sc) 3490 { 3491 struct bwi_regwin *bus, *old; 3492 int error; 3493 3494 bus = &sc->sc_bus_regwin; 3495 3496 error = bwi_regwin_switch(sc, bus, &old); 3497 if (error) 3498 return error; 3499 3500 if (!bwi_regwin_is_enabled(sc, bus)) 3501 bwi_regwin_enable(sc, bus, 0); 3502 3503 /* Disable interripts */ 3504 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3505 3506 return bwi_regwin_switch(sc, old, NULL); 3507 } 3508 3509 static const char * 3510 bwi_regwin_name(const struct bwi_regwin *rw) 3511 { 3512 switch (rw->rw_type) { 3513 case BWI_REGWIN_T_COM: 3514 return "COM"; 3515 case BWI_REGWIN_T_BUSPCI: 3516 return "PCI"; 3517 case BWI_REGWIN_T_MAC: 3518 return "MAC"; 3519 case BWI_REGWIN_T_BUSPCIE: 3520 return "PCIE"; 3521 } 3522 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3523 return NULL; 3524 } 3525 3526 static uint32_t 3527 bwi_regwin_disable_bits(struct bwi_softc *sc) 3528 { 3529 uint32_t busrev; 3530 3531 /* XXX cache this */ 3532 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3533 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3534 "bus rev %u\n", busrev); 3535 3536 if (busrev == BWI_BUSREV_0) 3537 return BWI_STATE_LO_DISABLE1; 3538 else if (busrev == BWI_BUSREV_1) 3539 return BWI_STATE_LO_DISABLE2; 3540 else 3541 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3542 } 3543 3544 int 3545 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3546 { 3547 uint32_t val, disable_bits; 3548 3549 disable_bits = bwi_regwin_disable_bits(sc); 3550 val = CSR_READ_4(sc, BWI_STATE_LO); 3551 3552 if ((val & (BWI_STATE_LO_CLOCK | 3553 BWI_STATE_LO_RESET | 3554 disable_bits)) == BWI_STATE_LO_CLOCK) { 3555 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3556 bwi_regwin_name(rw)); 3557 return 1; 3558 } else { 3559 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3560 bwi_regwin_name(rw)); 3561 return 0; 3562 } 3563 } 3564 3565 void 3566 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3567 { 3568 uint32_t state_lo, disable_bits; 3569 int i; 3570 3571 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3572 3573 /* 3574 * If current regwin is in 'reset' state, it was already disabled. 3575 */ 3576 if (state_lo & BWI_STATE_LO_RESET) { 3577 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3578 "%s was already disabled\n", bwi_regwin_name(rw)); 3579 return; 3580 } 3581 3582 disable_bits = bwi_regwin_disable_bits(sc); 3583 3584 /* 3585 * Disable normal clock 3586 */ 3587 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3588 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3589 3590 /* 3591 * Wait until normal clock is disabled 3592 */ 3593 #define NRETRY 1000 3594 for (i = 0; i < NRETRY; ++i) { 3595 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3596 if (state_lo & disable_bits) 3597 break; 3598 DELAY(10); 3599 } 3600 if (i == NRETRY) { 3601 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3602 bwi_regwin_name(rw)); 3603 } 3604 3605 for (i = 0; i < NRETRY; ++i) { 3606 uint32_t state_hi; 3607 3608 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3609 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3610 break; 3611 DELAY(10); 3612 } 3613 if (i == NRETRY) { 3614 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3615 bwi_regwin_name(rw)); 3616 } 3617 #undef NRETRY 3618 3619 /* 3620 * Reset and disable regwin with gated clock 3621 */ 3622 state_lo = BWI_STATE_LO_RESET | disable_bits | 3623 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3624 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3625 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3626 3627 /* Flush pending bus write */ 3628 CSR_READ_4(sc, BWI_STATE_LO); 3629 DELAY(1); 3630 3631 /* Reset and disable regwin */ 3632 state_lo = BWI_STATE_LO_RESET | disable_bits | 3633 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3634 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3635 3636 /* Flush pending bus write */ 3637 CSR_READ_4(sc, BWI_STATE_LO); 3638 DELAY(1); 3639 } 3640 3641 void 3642 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3643 { 3644 uint32_t state_lo, state_hi, imstate; 3645 3646 bwi_regwin_disable(sc, rw, flags); 3647 3648 /* Reset regwin with gated clock */ 3649 state_lo = BWI_STATE_LO_RESET | 3650 BWI_STATE_LO_CLOCK | 3651 BWI_STATE_LO_GATED_CLOCK | 3652 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3653 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3654 3655 /* Flush pending bus write */ 3656 CSR_READ_4(sc, BWI_STATE_LO); 3657 DELAY(1); 3658 3659 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3660 if (state_hi & BWI_STATE_HI_SERROR) 3661 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3662 3663 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3664 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3665 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3666 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3667 } 3668 3669 /* Enable regwin with gated clock */ 3670 state_lo = BWI_STATE_LO_CLOCK | 3671 BWI_STATE_LO_GATED_CLOCK | 3672 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3673 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3674 3675 /* Flush pending bus write */ 3676 CSR_READ_4(sc, BWI_STATE_LO); 3677 DELAY(1); 3678 3679 /* Enable regwin with normal clock */ 3680 state_lo = BWI_STATE_LO_CLOCK | 3681 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3682 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3683 3684 /* Flush pending bus write */ 3685 CSR_READ_4(sc, BWI_STATE_LO); 3686 DELAY(1); 3687 } 3688 3689 static void 3690 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3691 { 3692 struct ifnet *ifp = sc->sc_ifp; 3693 struct bwi_mac *mac; 3694 struct bwi_myaddr_bssid buf; 3695 const uint8_t *p; 3696 uint32_t val; 3697 int n, i; 3698 3699 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3700 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3701 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3702 3703 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3704 3705 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3706 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3707 3708 n = sizeof(buf) / sizeof(val); 3709 p = (const uint8_t *)&buf; 3710 for (i = 0; i < n; ++i) { 3711 int j; 3712 3713 val = 0; 3714 for (j = 0; j < sizeof(val); ++j) 3715 val |= ((uint32_t)(*p++)) << (j * 8); 3716 3717 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3718 } 3719 } 3720 3721 static void 3722 bwi_updateslot(struct ifnet *ifp) 3723 { 3724 struct bwi_softc *sc = ifp->if_softc; 3725 struct ieee80211com *ic = ifp->if_l2com; 3726 struct bwi_mac *mac; 3727 3728 BWI_LOCK(sc); 3729 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3730 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3731 3732 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3733 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3734 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3735 3736 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3737 } 3738 BWI_UNLOCK(sc); 3739 } 3740 3741 static void 3742 bwi_calibrate(void *xsc) 3743 { 3744 struct bwi_softc *sc = xsc; 3745 #ifdef INVARIANTS 3746 struct ifnet *ifp = sc->sc_ifp; 3747 struct ieee80211com *ic = ifp->if_l2com; 3748 #endif 3749 struct bwi_mac *mac; 3750 3751 BWI_ASSERT_LOCKED(sc); 3752 3753 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3754 ("opmode %d", ic->ic_opmode)); 3755 3756 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3757 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3758 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3759 3760 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3761 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3762 3763 /* XXX 15 seconds */ 3764 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3765 } 3766 3767 static int 3768 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3769 { 3770 struct bwi_mac *mac; 3771 3772 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3773 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3774 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3775 3776 return bwi_rf_calc_rssi(mac, hdr); 3777 } 3778 3779 static int 3780 bwi_calc_noise(struct bwi_softc *sc) 3781 { 3782 struct bwi_mac *mac; 3783 3784 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3785 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3786 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3787 3788 return bwi_rf_calc_noise(mac); 3789 } 3790 3791 static __inline uint8_t 3792 bwi_ofdm_plcp2rate(const uint32_t *plcp0) 3793 { 3794 uint32_t plcp; 3795 uint8_t plcp_rate; 3796 3797 plcp = le32toh(*plcp0); 3798 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK); 3799 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM); 3800 } 3801 3802 static __inline uint8_t 3803 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr) 3804 { 3805 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS); 3806 } 3807 3808 static void 3809 bwi_rx_radiotap(struct ifnet *ifp, struct mbuf *m, 3810 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3811 { 3812 struct bwi_softc *sc = ifp->if_softc; 3813 const struct ieee80211_frame_min *wh; 3814 3815 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3816 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3817 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3818 3819 wh = mtod(m, const struct ieee80211_frame_min *); 3820 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3821 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3822 3823 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3824 sc->sc_rx_th.wr_rate = rate; 3825 sc->sc_rx_th.wr_antsignal = rssi; 3826 sc->sc_rx_th.wr_antnoise = noise; 3827 3828 bpf_mtap2(ifp->if_bpf, &sc->sc_rx_th, sc->sc_rx_th_len, m); 3829 } 3830 3831 static void 3832 bwi_led_attach(struct bwi_softc *sc) 3833 { 3834 const uint8_t *led_act = NULL; 3835 uint16_t gpio, val[BWI_LED_MAX]; 3836 int i; 3837 3838 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3839 3840 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3841 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3842 led_act = bwi_vendor_led_act[i].led_act; 3843 break; 3844 } 3845 } 3846 if (led_act == NULL) 3847 led_act = bwi_default_led_act; 3848 3849 #undef N 3850 3851 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3852 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3853 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3854 3855 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3856 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3857 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3858 3859 for (i = 0; i < BWI_LED_MAX; ++i) { 3860 struct bwi_led *led = &sc->sc_leds[i]; 3861 3862 if (val[i] == 0xff) { 3863 led->l_act = led_act[i]; 3864 } else { 3865 if (val[i] & BWI_LED_ACT_LOW) 3866 led->l_flags |= BWI_LED_F_ACTLOW; 3867 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3868 } 3869 led->l_mask = (1 << i); 3870 3871 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3872 led->l_act == BWI_LED_ACT_BLINK_POLL || 3873 led->l_act == BWI_LED_ACT_BLINK) { 3874 led->l_flags |= BWI_LED_F_BLINK; 3875 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3876 led->l_flags |= BWI_LED_F_POLLABLE; 3877 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3878 led->l_flags |= BWI_LED_F_SLOW; 3879 3880 if (sc->sc_blink_led == NULL) { 3881 sc->sc_blink_led = led; 3882 if (led->l_flags & BWI_LED_F_SLOW) 3883 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3884 } 3885 } 3886 3887 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3888 "%dth led, act %d, lowact %d\n", i, 3889 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3890 } 3891 callout_init(&sc->sc_led_blink_ch, CALLOUT_MPSAFE); 3892 } 3893 3894 static __inline uint16_t 3895 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3896 { 3897 if (led->l_flags & BWI_LED_F_ACTLOW) 3898 on = !on; 3899 if (on) 3900 val |= led->l_mask; 3901 else 3902 val &= ~led->l_mask; 3903 return val; 3904 } 3905 3906 static void 3907 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3908 { 3909 struct ifnet *ifp = sc->sc_ifp; 3910 struct ieee80211com *ic = ifp->if_l2com; 3911 uint16_t val; 3912 int i; 3913 3914 if (nstate == IEEE80211_S_INIT) { 3915 callout_stop(&sc->sc_led_blink_ch); 3916 sc->sc_led_blinking = 0; 3917 } 3918 3919 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3920 return; 3921 3922 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3923 for (i = 0; i < BWI_LED_MAX; ++i) { 3924 struct bwi_led *led = &sc->sc_leds[i]; 3925 int on; 3926 3927 if (led->l_act == BWI_LED_ACT_UNKN || 3928 led->l_act == BWI_LED_ACT_NULL) 3929 continue; 3930 3931 if ((led->l_flags & BWI_LED_F_BLINK) && 3932 nstate != IEEE80211_S_INIT) 3933 continue; 3934 3935 switch (led->l_act) { 3936 case BWI_LED_ACT_ON: /* Always on */ 3937 on = 1; 3938 break; 3939 case BWI_LED_ACT_OFF: /* Always off */ 3940 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3941 on = 0; 3942 break; 3943 default: 3944 on = 1; 3945 switch (nstate) { 3946 case IEEE80211_S_INIT: 3947 on = 0; 3948 break; 3949 case IEEE80211_S_RUN: 3950 if (led->l_act == BWI_LED_ACT_11G && 3951 ic->ic_curmode != IEEE80211_MODE_11G) 3952 on = 0; 3953 break; 3954 default: 3955 if (led->l_act == BWI_LED_ACT_ASSOC) 3956 on = 0; 3957 break; 3958 } 3959 break; 3960 } 3961 3962 val = bwi_led_onoff(led, val, on); 3963 } 3964 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3965 } 3966 static void 3967 bwi_led_event(struct bwi_softc *sc, int event) 3968 { 3969 struct bwi_led *led = sc->sc_blink_led; 3970 int rate; 3971 3972 if (event == BWI_LED_EVENT_POLL) { 3973 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3974 return; 3975 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3976 return; 3977 } 3978 3979 sc->sc_led_ticks = ticks; 3980 if (sc->sc_led_blinking) 3981 return; 3982 3983 switch (event) { 3984 case BWI_LED_EVENT_RX: 3985 rate = sc->sc_rx_rate; 3986 break; 3987 case BWI_LED_EVENT_TX: 3988 rate = sc->sc_tx_rate; 3989 break; 3990 case BWI_LED_EVENT_POLL: 3991 rate = 0; 3992 break; 3993 default: 3994 panic("unknown LED event %d\n", event); 3995 break; 3996 } 3997 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3998 bwi_led_duration[rate].off_dur); 3999 } 4000 4001 static void 4002 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4003 { 4004 struct bwi_led *led = sc->sc_blink_led; 4005 uint16_t val; 4006 4007 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4008 val = bwi_led_onoff(led, val, 1); 4009 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4010 4011 if (led->l_flags & BWI_LED_F_SLOW) { 4012 BWI_LED_SLOWDOWN(on_dur); 4013 BWI_LED_SLOWDOWN(off_dur); 4014 } 4015 4016 sc->sc_led_blinking = 1; 4017 sc->sc_led_blink_offdur = off_dur; 4018 4019 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4020 } 4021 4022 static void 4023 bwi_led_blink_next(void *xsc) 4024 { 4025 struct bwi_softc *sc = xsc; 4026 uint16_t val; 4027 4028 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4029 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4030 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4031 4032 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4033 bwi_led_blink_end, sc); 4034 } 4035 4036 static void 4037 bwi_led_blink_end(void *xsc) 4038 { 4039 struct bwi_softc *sc = xsc; 4040 sc->sc_led_blinking = 0; 4041 } 4042 4043 static void 4044 bwi_restart(void *xsc, int pending) 4045 { 4046 struct bwi_softc *sc = xsc; 4047 struct ifnet *ifp = sc->sc_ifp; 4048 4049 if_printf(ifp, "%s begin, help!\n", __func__); 4050 BWI_LOCK(sc); 4051 bwi_init_statechg(xsc, 0); 4052 BWI_UNLOCK(sc); 4053 #if 0 4054 bwi_start_locked(ifp); 4055 #endif 4056 } 4057