1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/malloc.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 #include <sys/taskqueue.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_arp.h> 63 #include <net/ethernet.h> 64 #include <net/if_llc.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_phy.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <machine/bus.h> 80 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 84 #include <dev/bwi/bitops.h> 85 #include <dev/bwi/if_bwireg.h> 86 #include <dev/bwi/if_bwivar.h> 87 #include <dev/bwi/bwimac.h> 88 #include <dev/bwi/bwirf.h> 89 90 struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93 }; 94 95 struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98 } __packed; 99 100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104 static void bwi_vap_delete(struct ieee80211vap *); 105 static void bwi_init(struct bwi_softc *); 106 static void bwi_parent(struct ieee80211com *); 107 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 108 static void bwi_start_locked(struct bwi_softc *); 109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111 static void bwi_watchdog(void *); 112 static void bwi_scan_start(struct ieee80211com *); 113 static void bwi_getradiocaps(struct ieee80211com *, int, int *, 114 struct ieee80211_channel[]); 115 static void bwi_set_channel(struct ieee80211com *); 116 static void bwi_scan_end(struct ieee80211com *); 117 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 118 static void bwi_updateslot(struct ieee80211com *); 119 120 static void bwi_calibrate(void *); 121 122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 123 static int bwi_calc_noise(struct bwi_softc *); 124 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 125 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 126 struct bwi_rxbuf_hdr *, const void *, int, int, int); 127 128 static void bwi_restart(void *, int); 129 static void bwi_init_statechg(struct bwi_softc *, int); 130 static void bwi_stop(struct bwi_softc *, int); 131 static void bwi_stop_locked(struct bwi_softc *, int); 132 static int bwi_newbuf(struct bwi_softc *, int, int); 133 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 134 struct ieee80211_node *); 135 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 136 struct ieee80211_node *, 137 const struct ieee80211_bpf_params *); 138 139 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 140 bus_addr_t, int, int); 141 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 142 143 static int bwi_init_tx_ring32(struct bwi_softc *, int); 144 static int bwi_init_rx_ring32(struct bwi_softc *); 145 static int bwi_init_txstats32(struct bwi_softc *); 146 static void bwi_free_tx_ring32(struct bwi_softc *, int); 147 static void bwi_free_rx_ring32(struct bwi_softc *); 148 static void bwi_free_txstats32(struct bwi_softc *); 149 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 150 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 151 int, bus_addr_t, int); 152 static int bwi_rxeof32(struct bwi_softc *); 153 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 154 static void bwi_txeof_status32(struct bwi_softc *); 155 156 static int bwi_init_tx_ring64(struct bwi_softc *, int); 157 static int bwi_init_rx_ring64(struct bwi_softc *); 158 static int bwi_init_txstats64(struct bwi_softc *); 159 static void bwi_free_tx_ring64(struct bwi_softc *, int); 160 static void bwi_free_rx_ring64(struct bwi_softc *); 161 static void bwi_free_txstats64(struct bwi_softc *); 162 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 163 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 164 int, bus_addr_t, int); 165 static int bwi_rxeof64(struct bwi_softc *); 166 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 167 static void bwi_txeof_status64(struct bwi_softc *); 168 169 static int bwi_rxeof(struct bwi_softc *, int); 170 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 171 static void bwi_txeof(struct bwi_softc *); 172 static void bwi_txeof_status(struct bwi_softc *, int); 173 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 174 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 175 176 static int bwi_dma_alloc(struct bwi_softc *); 177 static void bwi_dma_free(struct bwi_softc *); 178 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 179 struct bwi_ring_data *, bus_size_t, 180 uint32_t); 181 static int bwi_dma_mbuf_create(struct bwi_softc *); 182 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 183 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 184 static void bwi_dma_txstats_free(struct bwi_softc *); 185 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 186 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 187 bus_size_t, int); 188 189 static void bwi_power_on(struct bwi_softc *, int); 190 static int bwi_power_off(struct bwi_softc *, int); 191 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 192 static int bwi_set_clock_delay(struct bwi_softc *); 193 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 194 static int bwi_get_pwron_delay(struct bwi_softc *sc); 195 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 196 const uint8_t *); 197 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 198 199 static void bwi_get_card_flags(struct bwi_softc *); 200 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 201 202 static int bwi_bus_attach(struct bwi_softc *); 203 static int bwi_bbp_attach(struct bwi_softc *); 204 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 205 static void bwi_bbp_power_off(struct bwi_softc *); 206 207 static const char *bwi_regwin_name(const struct bwi_regwin *); 208 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 209 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 210 static int bwi_regwin_select(struct bwi_softc *, int); 211 212 static void bwi_led_attach(struct bwi_softc *); 213 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 214 static void bwi_led_event(struct bwi_softc *, int); 215 static void bwi_led_blink_start(struct bwi_softc *, int, int); 216 static void bwi_led_blink_next(void *); 217 static void bwi_led_blink_end(void *); 218 219 static const struct { 220 uint16_t did_min; 221 uint16_t did_max; 222 uint16_t bbp_id; 223 } bwi_bbpid_map[] = { 224 { 0x4301, 0x4301, 0x4301 }, 225 { 0x4305, 0x4307, 0x4307 }, 226 { 0x4402, 0x4403, 0x4402 }, 227 { 0x4610, 0x4615, 0x4610 }, 228 { 0x4710, 0x4715, 0x4710 }, 229 { 0x4720, 0x4725, 0x4309 } 230 }; 231 232 static const struct { 233 uint16_t bbp_id; 234 int nregwin; 235 } bwi_regwin_count[] = { 236 { 0x4301, 5 }, 237 { 0x4306, 6 }, 238 { 0x4307, 5 }, 239 { 0x4310, 8 }, 240 { 0x4401, 3 }, 241 { 0x4402, 3 }, 242 { 0x4610, 9 }, 243 { 0x4704, 9 }, 244 { 0x4710, 9 }, 245 { 0x5365, 7 } 246 }; 247 248 #define CLKSRC(src) \ 249 [BWI_CLKSRC_ ## src] = { \ 250 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 251 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 252 } 253 254 static const struct { 255 u_int freq_min; 256 u_int freq_max; 257 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 258 CLKSRC(LP_OSC), 259 CLKSRC(CS_OSC), 260 CLKSRC(PCI) 261 }; 262 263 #undef CLKSRC 264 265 #define VENDOR_LED_ACT(vendor) \ 266 { \ 267 .vid = PCI_VENDOR_##vendor, \ 268 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 269 } 270 271 static const struct { 272 #define PCI_VENDOR_COMPAQ 0x0e11 273 #define PCI_VENDOR_LINKSYS 0x1737 274 uint16_t vid; 275 uint8_t led_act[BWI_LED_MAX]; 276 } bwi_vendor_led_act[] = { 277 VENDOR_LED_ACT(COMPAQ), 278 VENDOR_LED_ACT(LINKSYS) 279 #undef PCI_VENDOR_LINKSYS 280 #undef PCI_VENDOR_COMPAQ 281 }; 282 283 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 284 { BWI_VENDOR_LED_ACT_DEFAULT }; 285 286 #undef VENDOR_LED_ACT 287 288 static const struct { 289 int on_dur; 290 int off_dur; 291 } bwi_led_duration[109] = { 292 [0] = { 400, 100 }, 293 [2] = { 150, 75 }, 294 [4] = { 90, 45 }, 295 [11] = { 66, 34 }, 296 [12] = { 53, 26 }, 297 [18] = { 42, 21 }, 298 [22] = { 35, 17 }, 299 [24] = { 32, 16 }, 300 [36] = { 21, 10 }, 301 [48] = { 16, 8 }, 302 [72] = { 11, 5 }, 303 [96] = { 9, 4 }, 304 [108] = { 7, 3 } 305 }; 306 307 #ifdef BWI_DEBUG 308 #ifdef BWI_DEBUG_VERBOSE 309 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 310 #else 311 static uint32_t bwi_debug; 312 #endif 313 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 314 #endif /* BWI_DEBUG */ 315 316 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 317 318 uint16_t 319 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 320 { 321 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 322 } 323 324 static __inline void 325 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 326 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 327 int tx) 328 { 329 struct bwi_desc32 *desc = &desc_array[desc_idx]; 330 uint32_t ctrl, addr, addr_hi, addr_lo; 331 332 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 333 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 334 335 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 336 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 337 338 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 339 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 340 if (desc_idx == ndesc - 1) 341 ctrl |= BWI_DESC32_C_EOR; 342 if (tx) { 343 /* XXX */ 344 ctrl |= BWI_DESC32_C_FRAME_START | 345 BWI_DESC32_C_FRAME_END | 346 BWI_DESC32_C_INTR; 347 } 348 349 desc->addr = htole32(addr); 350 desc->ctrl = htole32(ctrl); 351 } 352 353 int 354 bwi_attach(struct bwi_softc *sc) 355 { 356 struct ieee80211com *ic = &sc->sc_ic; 357 device_t dev = sc->sc_dev; 358 struct bwi_mac *mac; 359 struct bwi_phy *phy; 360 int i, error; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 373 mbufq_init(&sc->sc_snd, ifqmaxlen); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_ticks = ticks - sc->sc_led_idle; 381 sc->sc_led_blink = 1; 382 sc->sc_txpwr_calib = 1; 383 #ifdef BWI_DEBUG 384 sc->sc_debug = bwi_debug; 385 #endif 386 bwi_power_on(sc, 1); 387 388 error = bwi_bbp_attach(sc); 389 if (error) 390 goto fail; 391 392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 393 if (error) 394 goto fail; 395 396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 397 error = bwi_set_clock_delay(sc); 398 if (error) 399 goto fail; 400 401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 402 if (error) 403 goto fail; 404 405 error = bwi_get_pwron_delay(sc); 406 if (error) 407 goto fail; 408 } 409 410 error = bwi_bus_attach(sc); 411 if (error) 412 goto fail; 413 414 bwi_get_card_flags(sc); 415 416 bwi_led_attach(sc); 417 418 for (i = 0; i < sc->sc_nmac; ++i) { 419 struct bwi_regwin *old; 420 421 mac = &sc->sc_mac[i]; 422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 423 if (error) 424 goto fail; 425 426 error = bwi_mac_lateattach(mac); 427 if (error) 428 goto fail; 429 430 error = bwi_regwin_switch(sc, old, NULL); 431 if (error) 432 goto fail; 433 } 434 435 /* 436 * XXX First MAC is known to exist 437 * TODO2 438 */ 439 mac = &sc->sc_mac[0]; 440 phy = &mac->mac_phy; 441 442 bwi_bbp_power_off(sc); 443 444 error = bwi_dma_alloc(sc); 445 if (error) 446 goto fail; 447 448 error = bwi_mac_fw_alloc(mac); 449 if (error) 450 goto fail; 451 452 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 453 454 /* 455 * Setup ratesets, phytype, channels and get MAC address 456 */ 457 if (phy->phy_mode == IEEE80211_MODE_11B || 458 phy->phy_mode == IEEE80211_MODE_11G) { 459 if (phy->phy_mode == IEEE80211_MODE_11B) { 460 ic->ic_phytype = IEEE80211_T_DS; 461 } else { 462 ic->ic_phytype = IEEE80211_T_OFDM; 463 } 464 465 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 466 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 467 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 469 device_printf(dev, 470 "invalid MAC address: %6D\n", 471 ic->ic_macaddr, ":"); 472 } 473 } 474 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 475 /* TODO:11A */ 476 error = ENXIO; 477 goto fail; 478 } else { 479 panic("unknown phymode %d\n", phy->phy_mode); 480 } 481 482 /* Get locale */ 483 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 484 BWI_SPROM_CARD_INFO_LOCALE); 485 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 486 /* XXX use locale */ 487 488 ic->ic_softc = sc; 489 490 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 491 ic->ic_channels); 492 493 ic->ic_name = device_get_nameunit(dev); 494 ic->ic_caps = IEEE80211_C_STA | 495 IEEE80211_C_SHSLOT | 496 IEEE80211_C_SHPREAMBLE | 497 IEEE80211_C_WPA | 498 IEEE80211_C_BGSCAN | 499 IEEE80211_C_MONITOR; 500 ic->ic_opmode = IEEE80211_M_STA; 501 ieee80211_ifattach(ic); 502 503 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 504 505 /* override default methods */ 506 ic->ic_vap_create = bwi_vap_create; 507 ic->ic_vap_delete = bwi_vap_delete; 508 ic->ic_raw_xmit = bwi_raw_xmit; 509 ic->ic_updateslot = bwi_updateslot; 510 ic->ic_scan_start = bwi_scan_start; 511 ic->ic_scan_end = bwi_scan_end; 512 ic->ic_getradiocaps = bwi_getradiocaps; 513 ic->ic_set_channel = bwi_set_channel; 514 ic->ic_transmit = bwi_transmit; 515 ic->ic_parent = bwi_parent; 516 517 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 518 519 ieee80211_radiotap_attach(ic, 520 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 521 BWI_TX_RADIOTAP_PRESENT, 522 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 523 BWI_RX_RADIOTAP_PRESENT); 524 525 /* 526 * Add sysctl nodes 527 */ 528 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 529 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 530 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 531 "Firmware version"); 532 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 534 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 535 "# ticks before LED enters idle state"); 536 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 538 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 539 "Allow LED to blink"); 540 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 542 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 543 "Enable software TX power calibration"); 544 #ifdef BWI_DEBUG 545 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 546 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 547 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 548 #endif 549 if (bootverbose) 550 ieee80211_announce(ic); 551 552 return (0); 553 fail: 554 BWI_LOCK_DESTROY(sc); 555 return (error); 556 } 557 558 int 559 bwi_detach(struct bwi_softc *sc) 560 { 561 struct ieee80211com *ic = &sc->sc_ic; 562 int i; 563 564 bwi_stop(sc, 1); 565 callout_drain(&sc->sc_led_blink_ch); 566 callout_drain(&sc->sc_calib_ch); 567 callout_drain(&sc->sc_watchdog_timer); 568 ieee80211_ifdetach(ic); 569 570 for (i = 0; i < sc->sc_nmac; ++i) 571 bwi_mac_detach(&sc->sc_mac[i]); 572 bwi_dma_free(sc); 573 taskqueue_free(sc->sc_tq); 574 mbufq_drain(&sc->sc_snd); 575 576 BWI_LOCK_DESTROY(sc); 577 578 return (0); 579 } 580 581 static struct ieee80211vap * 582 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 583 enum ieee80211_opmode opmode, int flags, 584 const uint8_t bssid[IEEE80211_ADDR_LEN], 585 const uint8_t mac[IEEE80211_ADDR_LEN]) 586 { 587 struct bwi_vap *bvp; 588 struct ieee80211vap *vap; 589 590 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 591 return NULL; 592 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 593 vap = &bvp->bv_vap; 594 /* enable s/w bmiss handling for sta mode */ 595 ieee80211_vap_setup(ic, vap, name, unit, opmode, 596 flags | IEEE80211_CLONE_NOBEACONS, bssid); 597 598 /* override default methods */ 599 bvp->bv_newstate = vap->iv_newstate; 600 vap->iv_newstate = bwi_newstate; 601 #if 0 602 vap->iv_update_beacon = bwi_beacon_update; 603 #endif 604 ieee80211_ratectl_init(vap); 605 606 /* complete setup */ 607 ieee80211_vap_attach(vap, ieee80211_media_change, 608 ieee80211_media_status, mac); 609 ic->ic_opmode = opmode; 610 return vap; 611 } 612 613 static void 614 bwi_vap_delete(struct ieee80211vap *vap) 615 { 616 struct bwi_vap *bvp = BWI_VAP(vap); 617 618 ieee80211_ratectl_deinit(vap); 619 ieee80211_vap_detach(vap); 620 free(bvp, M_80211_VAP); 621 } 622 623 void 624 bwi_suspend(struct bwi_softc *sc) 625 { 626 bwi_stop(sc, 1); 627 } 628 629 void 630 bwi_resume(struct bwi_softc *sc) 631 { 632 633 if (sc->sc_ic.ic_nrunning > 0) 634 bwi_init(sc); 635 } 636 637 int 638 bwi_shutdown(struct bwi_softc *sc) 639 { 640 bwi_stop(sc, 1); 641 return 0; 642 } 643 644 static void 645 bwi_power_on(struct bwi_softc *sc, int with_pll) 646 { 647 uint32_t gpio_in, gpio_out, gpio_en; 648 uint16_t status; 649 650 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 651 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 652 goto back; 653 654 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 655 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 656 657 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 658 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 659 if (with_pll) { 660 /* Turn off PLL first */ 661 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 662 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 663 } 664 665 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 666 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 667 DELAY(1000); 668 669 if (with_pll) { 670 /* Turn on PLL */ 671 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 672 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 673 DELAY(5000); 674 } 675 676 back: 677 /* Clear "Signaled Target Abort" */ 678 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 679 status &= ~PCIM_STATUS_STABORT; 680 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 681 } 682 683 static int 684 bwi_power_off(struct bwi_softc *sc, int with_pll) 685 { 686 uint32_t gpio_out, gpio_en; 687 688 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 689 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 690 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 691 692 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 693 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 694 if (with_pll) { 695 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 696 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 697 } 698 699 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 700 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 701 return 0; 702 } 703 704 int 705 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 706 struct bwi_regwin **old_rw) 707 { 708 int error; 709 710 if (old_rw != NULL) 711 *old_rw = NULL; 712 713 if (!BWI_REGWIN_EXIST(rw)) 714 return EINVAL; 715 716 if (sc->sc_cur_regwin != rw) { 717 error = bwi_regwin_select(sc, rw->rw_id); 718 if (error) { 719 device_printf(sc->sc_dev, "can't select regwin %d\n", 720 rw->rw_id); 721 return error; 722 } 723 } 724 725 if (old_rw != NULL) 726 *old_rw = sc->sc_cur_regwin; 727 sc->sc_cur_regwin = rw; 728 return 0; 729 } 730 731 static int 732 bwi_regwin_select(struct bwi_softc *sc, int id) 733 { 734 uint32_t win = BWI_PCIM_REGWIN(id); 735 int i; 736 737 #define RETRY_MAX 50 738 for (i = 0; i < RETRY_MAX; ++i) { 739 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 740 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 741 return 0; 742 DELAY(10); 743 } 744 #undef RETRY_MAX 745 746 return ENXIO; 747 } 748 749 static void 750 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 751 { 752 uint32_t val; 753 754 val = CSR_READ_4(sc, BWI_ID_HI); 755 *type = BWI_ID_HI_REGWIN_TYPE(val); 756 *rev = BWI_ID_HI_REGWIN_REV(val); 757 758 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 759 "vendor 0x%04x\n", *type, *rev, 760 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 761 } 762 763 static int 764 bwi_bbp_attach(struct bwi_softc *sc) 765 { 766 uint16_t bbp_id, rw_type; 767 uint8_t rw_rev; 768 uint32_t info; 769 int error, nregwin, i; 770 771 /* 772 * Get 0th regwin information 773 * NOTE: 0th regwin should exist 774 */ 775 error = bwi_regwin_select(sc, 0); 776 if (error) { 777 device_printf(sc->sc_dev, "can't select regwin 0\n"); 778 return error; 779 } 780 bwi_regwin_info(sc, &rw_type, &rw_rev); 781 782 /* 783 * Find out BBP id 784 */ 785 bbp_id = 0; 786 info = 0; 787 if (rw_type == BWI_REGWIN_T_COM) { 788 info = CSR_READ_4(sc, BWI_INFO); 789 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 790 791 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 792 793 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 794 } else { 795 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 796 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 797 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 798 bbp_id = bwi_bbpid_map[i].bbp_id; 799 break; 800 } 801 } 802 if (bbp_id == 0) { 803 device_printf(sc->sc_dev, "no BBP id for device id " 804 "0x%04x\n", sc->sc_pci_did); 805 return ENXIO; 806 } 807 808 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 809 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 810 } 811 812 /* 813 * Find out number of regwins 814 */ 815 nregwin = 0; 816 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 817 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 818 } else { 819 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 820 if (bwi_regwin_count[i].bbp_id == bbp_id) { 821 nregwin = bwi_regwin_count[i].nregwin; 822 break; 823 } 824 } 825 if (nregwin == 0) { 826 device_printf(sc->sc_dev, "no number of win for " 827 "BBP id 0x%04x\n", bbp_id); 828 return ENXIO; 829 } 830 } 831 832 /* Record BBP id/rev for later using */ 833 sc->sc_bbp_id = bbp_id; 834 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 835 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 836 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 837 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 838 839 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 840 nregwin, sc->sc_cap); 841 842 /* 843 * Create rest of the regwins 844 */ 845 846 /* Don't re-create common regwin, if it is already created */ 847 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 848 849 for (; i < nregwin; ++i) { 850 /* 851 * Get regwin information 852 */ 853 error = bwi_regwin_select(sc, i); 854 if (error) { 855 device_printf(sc->sc_dev, 856 "can't select regwin %d\n", i); 857 return error; 858 } 859 bwi_regwin_info(sc, &rw_type, &rw_rev); 860 861 /* 862 * Try attach: 863 * 1) Bus (PCI/PCIE) regwin 864 * 2) MAC regwin 865 * Ignore rest types of regwin 866 */ 867 if (rw_type == BWI_REGWIN_T_BUSPCI || 868 rw_type == BWI_REGWIN_T_BUSPCIE) { 869 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 870 device_printf(sc->sc_dev, 871 "bus regwin already exists\n"); 872 } else { 873 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 874 rw_type, rw_rev); 875 } 876 } else if (rw_type == BWI_REGWIN_T_MAC) { 877 /* XXX ignore return value */ 878 bwi_mac_attach(sc, i, rw_rev); 879 } 880 } 881 882 /* At least one MAC shold exist */ 883 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 884 device_printf(sc->sc_dev, "no MAC was found\n"); 885 return ENXIO; 886 } 887 KASSERT(sc->sc_nmac > 0, ("no mac's")); 888 889 /* Bus regwin must exist */ 890 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 891 device_printf(sc->sc_dev, "no bus regwin was found\n"); 892 return ENXIO; 893 } 894 895 /* Start with first MAC */ 896 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 897 if (error) 898 return error; 899 900 return 0; 901 } 902 903 int 904 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 905 { 906 struct bwi_regwin *old, *bus; 907 uint32_t val; 908 int error; 909 910 bus = &sc->sc_bus_regwin; 911 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 912 913 /* 914 * Tell bus to generate requested interrupts 915 */ 916 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 917 /* 918 * NOTE: Read BWI_FLAGS from MAC regwin 919 */ 920 val = CSR_READ_4(sc, BWI_FLAGS); 921 922 error = bwi_regwin_switch(sc, bus, &old); 923 if (error) 924 return error; 925 926 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 927 } else { 928 uint32_t mac_mask; 929 930 mac_mask = 1 << mac->mac_id; 931 932 error = bwi_regwin_switch(sc, bus, &old); 933 if (error) 934 return error; 935 936 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 937 val |= mac_mask << 8; 938 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 939 } 940 941 if (sc->sc_flags & BWI_F_BUS_INITED) 942 goto back; 943 944 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 945 /* 946 * Enable prefetch and burst 947 */ 948 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 949 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 950 951 if (bus->rw_rev < 5) { 952 struct bwi_regwin *com = &sc->sc_com_regwin; 953 954 /* 955 * Configure timeouts for bus operation 956 */ 957 958 /* 959 * Set service timeout and request timeout 960 */ 961 CSR_SETBITS_4(sc, BWI_CONF_LO, 962 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 963 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 964 965 /* 966 * If there is common regwin, we switch to that regwin 967 * and switch back to bus regwin once we have done. 968 */ 969 if (BWI_REGWIN_EXIST(com)) { 970 error = bwi_regwin_switch(sc, com, NULL); 971 if (error) 972 return error; 973 } 974 975 /* Let bus know what we have changed */ 976 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 977 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 978 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 979 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 980 981 if (BWI_REGWIN_EXIST(com)) { 982 error = bwi_regwin_switch(sc, bus, NULL); 983 if (error) 984 return error; 985 } 986 } else if (bus->rw_rev >= 11) { 987 /* 988 * Enable memory read multiple 989 */ 990 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 991 } 992 } else { 993 /* TODO:PCIE */ 994 } 995 996 sc->sc_flags |= BWI_F_BUS_INITED; 997 back: 998 return bwi_regwin_switch(sc, old, NULL); 999 } 1000 1001 static void 1002 bwi_get_card_flags(struct bwi_softc *sc) 1003 { 1004 #define PCI_VENDOR_APPLE 0x106b 1005 #define PCI_VENDOR_DELL 0x1028 1006 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1007 if (sc->sc_card_flags == 0xffff) 1008 sc->sc_card_flags = 0; 1009 1010 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1011 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1012 sc->sc_pci_revid == 0x74) 1013 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1014 1015 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1016 sc->sc_pci_subdid == 0x4e && /* XXX */ 1017 sc->sc_pci_revid > 0x40) 1018 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1019 1020 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1021 #undef PCI_VENDOR_DELL 1022 #undef PCI_VENDOR_APPLE 1023 } 1024 1025 static void 1026 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1027 { 1028 int i; 1029 1030 for (i = 0; i < 3; ++i) { 1031 *((uint16_t *)eaddr + i) = 1032 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1033 } 1034 } 1035 1036 static void 1037 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1038 { 1039 struct bwi_regwin *com; 1040 uint32_t val; 1041 u_int div; 1042 int src; 1043 1044 bzero(freq, sizeof(*freq)); 1045 com = &sc->sc_com_regwin; 1046 1047 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1048 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1049 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1050 1051 /* 1052 * Calculate clock frequency 1053 */ 1054 src = -1; 1055 div = 0; 1056 if (com->rw_rev < 6) { 1057 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1058 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1059 src = BWI_CLKSRC_PCI; 1060 div = 64; 1061 } else { 1062 src = BWI_CLKSRC_CS_OSC; 1063 div = 32; 1064 } 1065 } else if (com->rw_rev < 10) { 1066 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1067 1068 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1069 if (src == BWI_CLKSRC_LP_OSC) { 1070 div = 1; 1071 } else { 1072 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1073 1074 /* Unknown source */ 1075 if (src >= BWI_CLKSRC_MAX) 1076 src = BWI_CLKSRC_CS_OSC; 1077 } 1078 } else { 1079 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1080 1081 src = BWI_CLKSRC_CS_OSC; 1082 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1083 } 1084 1085 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1086 KASSERT(div != 0, ("div zero")); 1087 1088 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1089 src == BWI_CLKSRC_PCI ? "PCI" : 1090 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1091 1092 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1093 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1094 1095 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1096 freq->clkfreq_min, freq->clkfreq_max); 1097 } 1098 1099 static int 1100 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1101 { 1102 struct bwi_regwin *old, *com; 1103 uint32_t clk_ctrl, clk_src; 1104 int error, pwr_off = 0; 1105 1106 com = &sc->sc_com_regwin; 1107 if (!BWI_REGWIN_EXIST(com)) 1108 return 0; 1109 1110 if (com->rw_rev >= 10 || com->rw_rev < 6) 1111 return 0; 1112 1113 /* 1114 * For common regwin whose rev is [6, 10), the chip 1115 * must be capable to change clock mode. 1116 */ 1117 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1118 return 0; 1119 1120 error = bwi_regwin_switch(sc, com, &old); 1121 if (error) 1122 return error; 1123 1124 if (clk_mode == BWI_CLOCK_MODE_FAST) 1125 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1126 1127 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1128 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1129 1130 switch (clk_mode) { 1131 case BWI_CLOCK_MODE_FAST: 1132 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1133 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1134 break; 1135 case BWI_CLOCK_MODE_SLOW: 1136 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1137 break; 1138 case BWI_CLOCK_MODE_DYN: 1139 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1140 BWI_CLOCK_CTRL_IGNPLL | 1141 BWI_CLOCK_CTRL_NODYN); 1142 if (clk_src != BWI_CLKSRC_CS_OSC) { 1143 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1144 pwr_off = 1; 1145 } 1146 break; 1147 } 1148 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1149 1150 if (pwr_off) 1151 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1152 1153 return bwi_regwin_switch(sc, old, NULL); 1154 } 1155 1156 static int 1157 bwi_set_clock_delay(struct bwi_softc *sc) 1158 { 1159 struct bwi_regwin *old, *com; 1160 int error; 1161 1162 com = &sc->sc_com_regwin; 1163 if (!BWI_REGWIN_EXIST(com)) 1164 return 0; 1165 1166 error = bwi_regwin_switch(sc, com, &old); 1167 if (error) 1168 return error; 1169 1170 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1171 if (sc->sc_bbp_rev == 0) 1172 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1173 else if (sc->sc_bbp_rev == 1) 1174 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1175 } 1176 1177 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1178 if (com->rw_rev >= 10) { 1179 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1180 } else { 1181 struct bwi_clock_freq freq; 1182 1183 bwi_get_clock_freq(sc, &freq); 1184 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1185 howmany(freq.clkfreq_max * 150, 1000000)); 1186 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1187 howmany(freq.clkfreq_max * 15, 1000000)); 1188 } 1189 } 1190 1191 return bwi_regwin_switch(sc, old, NULL); 1192 } 1193 1194 static void 1195 bwi_init(struct bwi_softc *sc) 1196 { 1197 struct ieee80211com *ic = &sc->sc_ic; 1198 1199 BWI_LOCK(sc); 1200 bwi_init_statechg(sc, 1); 1201 BWI_UNLOCK(sc); 1202 1203 if (sc->sc_flags & BWI_F_RUNNING) 1204 ieee80211_start_all(ic); /* start all vap's */ 1205 } 1206 1207 static void 1208 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1209 { 1210 struct bwi_mac *mac; 1211 int error; 1212 1213 BWI_ASSERT_LOCKED(sc); 1214 1215 bwi_stop_locked(sc, statechg); 1216 1217 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1218 1219 /* TODO: 2 MAC */ 1220 1221 mac = &sc->sc_mac[0]; 1222 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1223 if (error) { 1224 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1225 __func__, error); 1226 goto bad; 1227 } 1228 error = bwi_mac_init(mac); 1229 if (error) { 1230 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1231 __func__, error); 1232 goto bad; 1233 } 1234 1235 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1236 1237 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1238 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1239 1240 bwi_mac_reset_hwkeys(mac); 1241 1242 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1243 int i; 1244 1245 #define NRETRY 1000 1246 /* 1247 * Drain any possible pending TX status 1248 */ 1249 for (i = 0; i < NRETRY; ++i) { 1250 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1251 BWI_TXSTATUS0_VALID) == 0) 1252 break; 1253 CSR_READ_4(sc, BWI_TXSTATUS1); 1254 } 1255 if (i == NRETRY) 1256 device_printf(sc->sc_dev, 1257 "%s: can't drain TX status\n", __func__); 1258 #undef NRETRY 1259 } 1260 1261 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1262 bwi_mac_updateslot(mac, 1); 1263 1264 /* Start MAC */ 1265 error = bwi_mac_start(mac); 1266 if (error) { 1267 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1268 __func__, error); 1269 goto bad; 1270 } 1271 1272 /* Clear stop flag before enabling interrupt */ 1273 sc->sc_flags &= ~BWI_F_STOP; 1274 sc->sc_flags |= BWI_F_RUNNING; 1275 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1276 1277 /* Enable intrs */ 1278 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1279 return; 1280 bad: 1281 bwi_stop_locked(sc, 1); 1282 } 1283 1284 static void 1285 bwi_parent(struct ieee80211com *ic) 1286 { 1287 struct bwi_softc *sc = ic->ic_softc; 1288 int startall = 0; 1289 1290 BWI_LOCK(sc); 1291 if (ic->ic_nrunning > 0) { 1292 struct bwi_mac *mac; 1293 int promisc = -1; 1294 1295 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1296 ("current regwin type %d", 1297 sc->sc_cur_regwin->rw_type)); 1298 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1299 1300 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1301 promisc = 1; 1302 sc->sc_flags |= BWI_F_PROMISC; 1303 } else if (ic->ic_promisc == 0 && 1304 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1305 promisc = 0; 1306 sc->sc_flags &= ~BWI_F_PROMISC; 1307 } 1308 1309 if (promisc >= 0) 1310 bwi_mac_set_promisc(mac, promisc); 1311 } 1312 if (ic->ic_nrunning > 0) { 1313 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1314 bwi_init_statechg(sc, 1); 1315 startall = 1; 1316 } 1317 } else if (sc->sc_flags & BWI_F_RUNNING) 1318 bwi_stop_locked(sc, 1); 1319 BWI_UNLOCK(sc); 1320 if (startall) 1321 ieee80211_start_all(ic); 1322 } 1323 1324 static int 1325 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1326 { 1327 struct bwi_softc *sc = ic->ic_softc; 1328 int error; 1329 1330 BWI_LOCK(sc); 1331 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1332 BWI_UNLOCK(sc); 1333 return (ENXIO); 1334 } 1335 error = mbufq_enqueue(&sc->sc_snd, m); 1336 if (error) { 1337 BWI_UNLOCK(sc); 1338 return (error); 1339 } 1340 bwi_start_locked(sc); 1341 BWI_UNLOCK(sc); 1342 return (0); 1343 } 1344 1345 static void 1346 bwi_start_locked(struct bwi_softc *sc) 1347 { 1348 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1349 struct ieee80211_frame *wh; 1350 struct ieee80211_node *ni; 1351 struct mbuf *m; 1352 int trans, idx; 1353 1354 BWI_ASSERT_LOCKED(sc); 1355 1356 trans = 0; 1357 idx = tbd->tbd_idx; 1358 1359 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1360 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1361 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1362 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1363 wh = mtod(m, struct ieee80211_frame *); 1364 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1365 ieee80211_crypto_encap(ni, m) == NULL) { 1366 if_inc_counter(ni->ni_vap->iv_ifp, 1367 IFCOUNTER_OERRORS, 1); 1368 ieee80211_free_node(ni); 1369 m_freem(m); 1370 continue; 1371 } 1372 if (bwi_encap(sc, idx, m, ni) != 0) { 1373 /* 'm' is freed in bwi_encap() if we reach here */ 1374 if (ni != NULL) { 1375 if_inc_counter(ni->ni_vap->iv_ifp, 1376 IFCOUNTER_OERRORS, 1); 1377 ieee80211_free_node(ni); 1378 } else 1379 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1380 continue; 1381 } 1382 trans = 1; 1383 tbd->tbd_used++; 1384 idx = (idx + 1) % BWI_TX_NDESC; 1385 } 1386 1387 tbd->tbd_idx = idx; 1388 if (trans) 1389 sc->sc_tx_timer = 5; 1390 } 1391 1392 static int 1393 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1394 const struct ieee80211_bpf_params *params) 1395 { 1396 struct ieee80211com *ic = ni->ni_ic; 1397 struct bwi_softc *sc = ic->ic_softc; 1398 /* XXX wme? */ 1399 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1400 int idx, error; 1401 1402 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1403 m_freem(m); 1404 return ENETDOWN; 1405 } 1406 1407 BWI_LOCK(sc); 1408 idx = tbd->tbd_idx; 1409 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1410 if (params == NULL) { 1411 /* 1412 * Legacy path; interpret frame contents to decide 1413 * precisely how to send the frame. 1414 */ 1415 error = bwi_encap(sc, idx, m, ni); 1416 } else { 1417 /* 1418 * Caller supplied explicit parameters to use in 1419 * sending the frame. 1420 */ 1421 error = bwi_encap_raw(sc, idx, m, ni, params); 1422 } 1423 if (error == 0) { 1424 tbd->tbd_used++; 1425 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1426 sc->sc_tx_timer = 5; 1427 } 1428 BWI_UNLOCK(sc); 1429 return error; 1430 } 1431 1432 static void 1433 bwi_watchdog(void *arg) 1434 { 1435 struct bwi_softc *sc; 1436 1437 sc = arg; 1438 BWI_ASSERT_LOCKED(sc); 1439 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1440 device_printf(sc->sc_dev, "watchdog timeout\n"); 1441 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1442 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1443 } 1444 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1445 } 1446 1447 static void 1448 bwi_stop(struct bwi_softc *sc, int statechg) 1449 { 1450 BWI_LOCK(sc); 1451 bwi_stop_locked(sc, statechg); 1452 BWI_UNLOCK(sc); 1453 } 1454 1455 static void 1456 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1457 { 1458 struct bwi_mac *mac; 1459 int i, error, pwr_off = 0; 1460 1461 BWI_ASSERT_LOCKED(sc); 1462 1463 callout_stop(&sc->sc_calib_ch); 1464 callout_stop(&sc->sc_led_blink_ch); 1465 sc->sc_led_blinking = 0; 1466 sc->sc_flags |= BWI_F_STOP; 1467 1468 if (sc->sc_flags & BWI_F_RUNNING) { 1469 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1470 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1471 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1472 1473 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1474 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1475 bwi_mac_stop(mac); 1476 } 1477 1478 for (i = 0; i < sc->sc_nmac; ++i) { 1479 struct bwi_regwin *old_rw; 1480 1481 mac = &sc->sc_mac[i]; 1482 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1483 continue; 1484 1485 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1486 if (error) 1487 continue; 1488 1489 bwi_mac_shutdown(mac); 1490 pwr_off = 1; 1491 1492 bwi_regwin_switch(sc, old_rw, NULL); 1493 } 1494 1495 if (pwr_off) 1496 bwi_bbp_power_off(sc); 1497 1498 sc->sc_tx_timer = 0; 1499 callout_stop(&sc->sc_watchdog_timer); 1500 sc->sc_flags &= ~BWI_F_RUNNING; 1501 } 1502 1503 void 1504 bwi_intr(void *xsc) 1505 { 1506 struct bwi_softc *sc = xsc; 1507 struct bwi_mac *mac; 1508 uint32_t intr_status; 1509 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1510 int i, txrx_error, tx = 0, rx_data = -1; 1511 1512 BWI_LOCK(sc); 1513 1514 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1515 (sc->sc_flags & BWI_F_STOP)) { 1516 BWI_UNLOCK(sc); 1517 return; 1518 } 1519 /* 1520 * Get interrupt status 1521 */ 1522 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1523 if (intr_status == 0xffffffff) { /* Not for us */ 1524 BWI_UNLOCK(sc); 1525 return; 1526 } 1527 1528 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1529 1530 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1531 if (intr_status == 0) { /* Nothing is interesting */ 1532 BWI_UNLOCK(sc); 1533 return; 1534 } 1535 1536 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1537 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1538 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1539 1540 txrx_error = 0; 1541 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1542 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1543 uint32_t mask; 1544 1545 if (BWI_TXRX_IS_RX(i)) 1546 mask = BWI_TXRX_RX_INTRS; 1547 else 1548 mask = BWI_TXRX_TX_INTRS; 1549 1550 txrx_intr_status[i] = 1551 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1552 1553 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1554 i, txrx_intr_status[i]); 1555 1556 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1557 device_printf(sc->sc_dev, 1558 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1559 __func__, i, txrx_intr_status[i]); 1560 txrx_error = 1; 1561 } 1562 } 1563 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1564 1565 /* 1566 * Acknowledge interrupt 1567 */ 1568 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1569 1570 for (i = 0; i < BWI_TXRX_NRING; ++i) 1571 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1572 1573 /* Disable all interrupts */ 1574 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1575 1576 /* 1577 * http://bcm-specs.sipsolutions.net/Interrupts 1578 * Says for this bit (0x800): 1579 * "Fatal Error 1580 * 1581 * We got this one while testing things when by accident the 1582 * template ram wasn't set to big endian when it should have 1583 * been after writing the initial values. It keeps on being 1584 * triggered, the only way to stop it seems to shut down the 1585 * chip." 1586 * 1587 * Suggesting that we should never get it and if we do we're not 1588 * feeding TX packets into the MAC correctly if we do... Apparently, 1589 * it is valid only on mac version 5 and higher, but I couldn't 1590 * find a reference for that... Since I see them from time to time 1591 * on my card, this suggests an error in the tx path still... 1592 */ 1593 if (intr_status & BWI_INTR_PHY_TXERR) { 1594 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1595 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1596 __func__); 1597 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1598 BWI_UNLOCK(sc); 1599 return; 1600 } 1601 } 1602 1603 if (txrx_error) { 1604 /* TODO: reset device */ 1605 } 1606 1607 if (intr_status & BWI_INTR_TBTT) 1608 bwi_mac_config_ps(mac); 1609 1610 if (intr_status & BWI_INTR_EO_ATIM) 1611 device_printf(sc->sc_dev, "EO_ATIM\n"); 1612 1613 if (intr_status & BWI_INTR_PMQ) { 1614 for (;;) { 1615 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1616 break; 1617 } 1618 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1619 } 1620 1621 if (intr_status & BWI_INTR_NOISE) 1622 device_printf(sc->sc_dev, "intr noise\n"); 1623 1624 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1625 rx_data = sc->sc_rxeof(sc); 1626 if (sc->sc_flags & BWI_F_STOP) { 1627 BWI_UNLOCK(sc); 1628 return; 1629 } 1630 } 1631 1632 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1633 sc->sc_txeof_status(sc); 1634 tx = 1; 1635 } 1636 1637 if (intr_status & BWI_INTR_TX_DONE) { 1638 bwi_txeof(sc); 1639 tx = 1; 1640 } 1641 1642 /* Re-enable interrupts */ 1643 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1644 1645 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1646 int evt = BWI_LED_EVENT_NONE; 1647 1648 if (tx && rx_data > 0) { 1649 if (sc->sc_rx_rate > sc->sc_tx_rate) 1650 evt = BWI_LED_EVENT_RX; 1651 else 1652 evt = BWI_LED_EVENT_TX; 1653 } else if (tx) { 1654 evt = BWI_LED_EVENT_TX; 1655 } else if (rx_data > 0) { 1656 evt = BWI_LED_EVENT_RX; 1657 } else if (rx_data == 0) { 1658 evt = BWI_LED_EVENT_POLL; 1659 } 1660 1661 if (evt != BWI_LED_EVENT_NONE) 1662 bwi_led_event(sc, evt); 1663 } 1664 1665 BWI_UNLOCK(sc); 1666 } 1667 1668 static void 1669 bwi_scan_start(struct ieee80211com *ic) 1670 { 1671 struct bwi_softc *sc = ic->ic_softc; 1672 1673 BWI_LOCK(sc); 1674 /* Enable MAC beacon promiscuity */ 1675 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1676 BWI_UNLOCK(sc); 1677 } 1678 1679 static void 1680 bwi_getradiocaps(struct ieee80211com *ic, 1681 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1682 { 1683 struct bwi_softc *sc = ic->ic_softc; 1684 struct bwi_mac *mac; 1685 struct bwi_phy *phy; 1686 uint8_t bands[IEEE80211_MODE_BYTES]; 1687 1688 /* 1689 * XXX First MAC is known to exist 1690 * TODO2 1691 */ 1692 mac = &sc->sc_mac[0]; 1693 phy = &mac->mac_phy; 1694 1695 memset(bands, 0, sizeof(bands)); 1696 switch (phy->phy_mode) { 1697 case IEEE80211_MODE_11G: 1698 setbit(bands, IEEE80211_MODE_11G); 1699 /* FALLTHROUGH */ 1700 case IEEE80211_MODE_11B: 1701 setbit(bands, IEEE80211_MODE_11B); 1702 break; 1703 case IEEE80211_MODE_11A: 1704 /* TODO:11A */ 1705 setbit(bands, IEEE80211_MODE_11A); 1706 device_printf(sc->sc_dev, "no 11a support\n"); 1707 return; 1708 default: 1709 panic("unknown phymode %d\n", phy->phy_mode); 1710 } 1711 1712 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1713 } 1714 1715 static void 1716 bwi_set_channel(struct ieee80211com *ic) 1717 { 1718 struct bwi_softc *sc = ic->ic_softc; 1719 struct ieee80211_channel *c = ic->ic_curchan; 1720 struct bwi_mac *mac; 1721 1722 BWI_LOCK(sc); 1723 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1724 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1725 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1726 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1727 1728 sc->sc_rates = ieee80211_get_ratetable(c); 1729 BWI_UNLOCK(sc); 1730 } 1731 1732 static void 1733 bwi_scan_end(struct ieee80211com *ic) 1734 { 1735 struct bwi_softc *sc = ic->ic_softc; 1736 1737 BWI_LOCK(sc); 1738 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1739 BWI_UNLOCK(sc); 1740 } 1741 1742 static int 1743 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1744 { 1745 struct bwi_vap *bvp = BWI_VAP(vap); 1746 struct ieee80211com *ic= vap->iv_ic; 1747 struct bwi_softc *sc = ic->ic_softc; 1748 enum ieee80211_state ostate = vap->iv_state; 1749 struct bwi_mac *mac; 1750 int error; 1751 1752 BWI_LOCK(sc); 1753 1754 callout_stop(&sc->sc_calib_ch); 1755 1756 if (nstate == IEEE80211_S_INIT) 1757 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1758 1759 bwi_led_newstate(sc, nstate); 1760 1761 error = bvp->bv_newstate(vap, nstate, arg); 1762 if (error != 0) 1763 goto back; 1764 1765 /* 1766 * Clear the BSSID when we stop a STA 1767 */ 1768 if (vap->iv_opmode == IEEE80211_M_STA) { 1769 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1770 /* 1771 * Clear out the BSSID. If we reassociate to 1772 * the same AP, this will reinialize things 1773 * correctly... 1774 */ 1775 if (ic->ic_opmode == IEEE80211_M_STA && 1776 !(sc->sc_flags & BWI_F_STOP)) 1777 bwi_set_bssid(sc, bwi_zero_addr); 1778 } 1779 } 1780 1781 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1782 /* Nothing to do */ 1783 } else if (nstate == IEEE80211_S_RUN) { 1784 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1785 1786 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1787 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1788 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1789 1790 /* Initial TX power calibration */ 1791 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1792 #ifdef notyet 1793 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1794 #else 1795 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1796 #endif 1797 1798 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1799 } 1800 back: 1801 BWI_UNLOCK(sc); 1802 1803 return error; 1804 } 1805 1806 static int 1807 bwi_dma_alloc(struct bwi_softc *sc) 1808 { 1809 int error, i, has_txstats; 1810 bus_addr_t lowaddr = 0; 1811 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1812 uint32_t txrx_ctrl_step = 0; 1813 1814 has_txstats = 0; 1815 for (i = 0; i < sc->sc_nmac; ++i) { 1816 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1817 has_txstats = 1; 1818 break; 1819 } 1820 } 1821 1822 switch (sc->sc_bus_space) { 1823 case BWI_BUS_SPACE_30BIT: 1824 case BWI_BUS_SPACE_32BIT: 1825 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1826 lowaddr = BWI_BUS_SPACE_MAXADDR; 1827 else 1828 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1829 desc_sz = sizeof(struct bwi_desc32); 1830 txrx_ctrl_step = 0x20; 1831 1832 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1833 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1834 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1835 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1836 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1837 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1838 sc->sc_rxeof = bwi_rxeof32; 1839 sc->sc_start_tx = bwi_start_tx32; 1840 if (has_txstats) { 1841 sc->sc_init_txstats = bwi_init_txstats32; 1842 sc->sc_free_txstats = bwi_free_txstats32; 1843 sc->sc_txeof_status = bwi_txeof_status32; 1844 } 1845 break; 1846 1847 case BWI_BUS_SPACE_64BIT: 1848 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1849 desc_sz = sizeof(struct bwi_desc64); 1850 txrx_ctrl_step = 0x40; 1851 1852 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1853 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1854 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1855 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1856 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1857 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1858 sc->sc_rxeof = bwi_rxeof64; 1859 sc->sc_start_tx = bwi_start_tx64; 1860 if (has_txstats) { 1861 sc->sc_init_txstats = bwi_init_txstats64; 1862 sc->sc_free_txstats = bwi_free_txstats64; 1863 sc->sc_txeof_status = bwi_txeof_status64; 1864 } 1865 break; 1866 } 1867 1868 KASSERT(lowaddr != 0, ("lowaddr zero")); 1869 KASSERT(desc_sz != 0, ("desc_sz zero")); 1870 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1871 1872 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1873 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1874 1875 /* 1876 * Create top level DMA tag 1877 */ 1878 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1879 BWI_ALIGN, 0, /* alignment, bounds */ 1880 lowaddr, /* lowaddr */ 1881 BUS_SPACE_MAXADDR, /* highaddr */ 1882 NULL, NULL, /* filter, filterarg */ 1883 BUS_SPACE_MAXSIZE, /* maxsize */ 1884 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1885 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1886 0, /* flags */ 1887 NULL, NULL, /* lockfunc, lockarg */ 1888 &sc->sc_parent_dtag); 1889 if (error) { 1890 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1891 return error; 1892 } 1893 1894 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1895 1896 /* 1897 * Create TX ring DMA stuffs 1898 */ 1899 error = bus_dma_tag_create(sc->sc_parent_dtag, 1900 BWI_RING_ALIGN, 0, 1901 BUS_SPACE_MAXADDR, 1902 BUS_SPACE_MAXADDR, 1903 NULL, NULL, 1904 tx_ring_sz, 1905 1, 1906 tx_ring_sz, 1907 0, 1908 NULL, NULL, 1909 &sc->sc_txring_dtag); 1910 if (error) { 1911 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1912 return error; 1913 } 1914 1915 for (i = 0; i < BWI_TX_NRING; ++i) { 1916 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1917 &sc->sc_tx_rdata[i], tx_ring_sz, 1918 TXRX_CTRL(i)); 1919 if (error) { 1920 device_printf(sc->sc_dev, "%dth TX ring " 1921 "DMA alloc failed\n", i); 1922 return error; 1923 } 1924 } 1925 1926 /* 1927 * Create RX ring DMA stuffs 1928 */ 1929 error = bus_dma_tag_create(sc->sc_parent_dtag, 1930 BWI_RING_ALIGN, 0, 1931 BUS_SPACE_MAXADDR, 1932 BUS_SPACE_MAXADDR, 1933 NULL, NULL, 1934 rx_ring_sz, 1935 1, 1936 rx_ring_sz, 1937 0, 1938 NULL, NULL, 1939 &sc->sc_rxring_dtag); 1940 if (error) { 1941 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1942 return error; 1943 } 1944 1945 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1946 rx_ring_sz, TXRX_CTRL(0)); 1947 if (error) { 1948 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1949 return error; 1950 } 1951 1952 if (has_txstats) { 1953 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1954 if (error) { 1955 device_printf(sc->sc_dev, 1956 "TX stats DMA alloc failed\n"); 1957 return error; 1958 } 1959 } 1960 1961 #undef TXRX_CTRL 1962 1963 return bwi_dma_mbuf_create(sc); 1964 } 1965 1966 static void 1967 bwi_dma_free(struct bwi_softc *sc) 1968 { 1969 if (sc->sc_txring_dtag != NULL) { 1970 int i; 1971 1972 for (i = 0; i < BWI_TX_NRING; ++i) { 1973 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1974 1975 if (rd->rdata_desc != NULL) { 1976 bus_dmamap_unload(sc->sc_txring_dtag, 1977 rd->rdata_dmap); 1978 bus_dmamem_free(sc->sc_txring_dtag, 1979 rd->rdata_desc, 1980 rd->rdata_dmap); 1981 } 1982 } 1983 bus_dma_tag_destroy(sc->sc_txring_dtag); 1984 } 1985 1986 if (sc->sc_rxring_dtag != NULL) { 1987 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 1988 1989 if (rd->rdata_desc != NULL) { 1990 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 1991 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 1992 rd->rdata_dmap); 1993 } 1994 bus_dma_tag_destroy(sc->sc_rxring_dtag); 1995 } 1996 1997 bwi_dma_txstats_free(sc); 1998 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 1999 2000 if (sc->sc_parent_dtag != NULL) 2001 bus_dma_tag_destroy(sc->sc_parent_dtag); 2002 } 2003 2004 static int 2005 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2006 struct bwi_ring_data *rd, bus_size_t size, 2007 uint32_t txrx_ctrl) 2008 { 2009 int error; 2010 2011 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2012 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2013 &rd->rdata_dmap); 2014 if (error) { 2015 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2016 return error; 2017 } 2018 2019 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2020 bwi_dma_ring_addr, &rd->rdata_paddr, 2021 BUS_DMA_NOWAIT); 2022 if (error) { 2023 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2024 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2025 rd->rdata_desc = NULL; 2026 return error; 2027 } 2028 2029 rd->rdata_txrx_ctrl = txrx_ctrl; 2030 return 0; 2031 } 2032 2033 static int 2034 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2035 bus_size_t desc_sz) 2036 { 2037 struct bwi_txstats_data *st; 2038 bus_size_t dma_size; 2039 int error; 2040 2041 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2042 if (st == NULL) { 2043 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2044 return ENOMEM; 2045 } 2046 sc->sc_txstats = st; 2047 2048 /* 2049 * Create TX stats descriptor DMA stuffs 2050 */ 2051 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2052 2053 error = bus_dma_tag_create(sc->sc_parent_dtag, 2054 BWI_RING_ALIGN, 2055 0, 2056 BUS_SPACE_MAXADDR, 2057 BUS_SPACE_MAXADDR, 2058 NULL, NULL, 2059 dma_size, 2060 1, 2061 dma_size, 2062 0, 2063 NULL, NULL, 2064 &st->stats_ring_dtag); 2065 if (error) { 2066 device_printf(sc->sc_dev, "can't create txstats ring " 2067 "DMA tag\n"); 2068 return error; 2069 } 2070 2071 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2072 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2073 &st->stats_ring_dmap); 2074 if (error) { 2075 device_printf(sc->sc_dev, "can't allocate txstats ring " 2076 "DMA mem\n"); 2077 bus_dma_tag_destroy(st->stats_ring_dtag); 2078 st->stats_ring_dtag = NULL; 2079 return error; 2080 } 2081 2082 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2083 st->stats_ring, dma_size, 2084 bwi_dma_ring_addr, &st->stats_ring_paddr, 2085 BUS_DMA_NOWAIT); 2086 if (error) { 2087 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2088 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2089 st->stats_ring_dmap); 2090 bus_dma_tag_destroy(st->stats_ring_dtag); 2091 st->stats_ring_dtag = NULL; 2092 return error; 2093 } 2094 2095 /* 2096 * Create TX stats DMA stuffs 2097 */ 2098 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2099 BWI_ALIGN); 2100 2101 error = bus_dma_tag_create(sc->sc_parent_dtag, 2102 BWI_ALIGN, 2103 0, 2104 BUS_SPACE_MAXADDR, 2105 BUS_SPACE_MAXADDR, 2106 NULL, NULL, 2107 dma_size, 2108 1, 2109 dma_size, 2110 0, 2111 NULL, NULL, 2112 &st->stats_dtag); 2113 if (error) { 2114 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2115 return error; 2116 } 2117 2118 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2119 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2120 &st->stats_dmap); 2121 if (error) { 2122 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2123 bus_dma_tag_destroy(st->stats_dtag); 2124 st->stats_dtag = NULL; 2125 return error; 2126 } 2127 2128 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2129 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2130 BUS_DMA_NOWAIT); 2131 if (error) { 2132 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2133 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2134 bus_dma_tag_destroy(st->stats_dtag); 2135 st->stats_dtag = NULL; 2136 return error; 2137 } 2138 2139 st->stats_ctrl_base = ctrl_base; 2140 return 0; 2141 } 2142 2143 static void 2144 bwi_dma_txstats_free(struct bwi_softc *sc) 2145 { 2146 struct bwi_txstats_data *st; 2147 2148 if (sc->sc_txstats == NULL) 2149 return; 2150 st = sc->sc_txstats; 2151 2152 if (st->stats_ring_dtag != NULL) { 2153 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2154 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2155 st->stats_ring_dmap); 2156 bus_dma_tag_destroy(st->stats_ring_dtag); 2157 } 2158 2159 if (st->stats_dtag != NULL) { 2160 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2161 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2162 bus_dma_tag_destroy(st->stats_dtag); 2163 } 2164 2165 free(st, M_DEVBUF); 2166 } 2167 2168 static void 2169 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2170 { 2171 KASSERT(nseg == 1, ("too many segments\n")); 2172 *((bus_addr_t *)arg) = seg->ds_addr; 2173 } 2174 2175 static int 2176 bwi_dma_mbuf_create(struct bwi_softc *sc) 2177 { 2178 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2179 int i, j, k, ntx, error; 2180 2181 /* 2182 * Create TX/RX mbuf DMA tag 2183 */ 2184 error = bus_dma_tag_create(sc->sc_parent_dtag, 2185 1, 2186 0, 2187 BUS_SPACE_MAXADDR, 2188 BUS_SPACE_MAXADDR, 2189 NULL, NULL, 2190 MCLBYTES, 2191 1, 2192 MCLBYTES, 2193 BUS_DMA_ALLOCNOW, 2194 NULL, NULL, 2195 &sc->sc_buf_dtag); 2196 if (error) { 2197 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2198 return error; 2199 } 2200 2201 ntx = 0; 2202 2203 /* 2204 * Create TX mbuf DMA map 2205 */ 2206 for (i = 0; i < BWI_TX_NRING; ++i) { 2207 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2208 2209 for (j = 0; j < BWI_TX_NDESC; ++j) { 2210 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2211 &tbd->tbd_buf[j].tb_dmap); 2212 if (error) { 2213 device_printf(sc->sc_dev, "can't create " 2214 "%dth tbd, %dth DMA map\n", i, j); 2215 2216 ntx = i; 2217 for (k = 0; k < j; ++k) { 2218 bus_dmamap_destroy(sc->sc_buf_dtag, 2219 tbd->tbd_buf[k].tb_dmap); 2220 } 2221 goto fail; 2222 } 2223 } 2224 } 2225 ntx = BWI_TX_NRING; 2226 2227 /* 2228 * Create RX mbuf DMA map and a spare DMA map 2229 */ 2230 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2231 &rbd->rbd_tmp_dmap); 2232 if (error) { 2233 device_printf(sc->sc_dev, 2234 "can't create spare RX buf DMA map\n"); 2235 goto fail; 2236 } 2237 2238 for (j = 0; j < BWI_RX_NDESC; ++j) { 2239 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2240 &rbd->rbd_buf[j].rb_dmap); 2241 if (error) { 2242 device_printf(sc->sc_dev, "can't create %dth " 2243 "RX buf DMA map\n", j); 2244 2245 for (k = 0; k < j; ++k) { 2246 bus_dmamap_destroy(sc->sc_buf_dtag, 2247 rbd->rbd_buf[j].rb_dmap); 2248 } 2249 bus_dmamap_destroy(sc->sc_buf_dtag, 2250 rbd->rbd_tmp_dmap); 2251 goto fail; 2252 } 2253 } 2254 2255 return 0; 2256 fail: 2257 bwi_dma_mbuf_destroy(sc, ntx, 0); 2258 return error; 2259 } 2260 2261 static void 2262 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2263 { 2264 int i, j; 2265 2266 if (sc->sc_buf_dtag == NULL) 2267 return; 2268 2269 for (i = 0; i < ntx; ++i) { 2270 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2271 2272 for (j = 0; j < BWI_TX_NDESC; ++j) { 2273 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2274 2275 if (tb->tb_mbuf != NULL) { 2276 bus_dmamap_unload(sc->sc_buf_dtag, 2277 tb->tb_dmap); 2278 m_freem(tb->tb_mbuf); 2279 } 2280 if (tb->tb_ni != NULL) 2281 ieee80211_free_node(tb->tb_ni); 2282 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2283 } 2284 } 2285 2286 if (nrx) { 2287 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2288 2289 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2290 for (j = 0; j < BWI_RX_NDESC; ++j) { 2291 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2292 2293 if (rb->rb_mbuf != NULL) { 2294 bus_dmamap_unload(sc->sc_buf_dtag, 2295 rb->rb_dmap); 2296 m_freem(rb->rb_mbuf); 2297 } 2298 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2299 } 2300 } 2301 2302 bus_dma_tag_destroy(sc->sc_buf_dtag); 2303 sc->sc_buf_dtag = NULL; 2304 } 2305 2306 static void 2307 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2308 { 2309 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2310 } 2311 2312 static void 2313 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2314 { 2315 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2316 } 2317 2318 static int 2319 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2320 { 2321 struct bwi_ring_data *rd; 2322 struct bwi_txbuf_data *tbd; 2323 uint32_t val, addr_hi, addr_lo; 2324 2325 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2326 rd = &sc->sc_tx_rdata[ring_idx]; 2327 tbd = &sc->sc_tx_bdata[ring_idx]; 2328 2329 tbd->tbd_idx = 0; 2330 tbd->tbd_used = 0; 2331 2332 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2333 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2334 BUS_DMASYNC_PREWRITE); 2335 2336 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2337 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2338 2339 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2340 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2341 BWI_TXRX32_RINGINFO_FUNC_MASK); 2342 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2343 2344 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2345 BWI_TXRX32_CTRL_ENABLE; 2346 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2347 2348 return 0; 2349 } 2350 2351 static void 2352 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2353 bus_addr_t paddr, int hdr_size, int ndesc) 2354 { 2355 uint32_t val, addr_hi, addr_lo; 2356 2357 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2358 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2359 2360 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2361 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2362 BWI_TXRX32_RINGINFO_FUNC_MASK); 2363 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2364 2365 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2366 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2367 BWI_TXRX32_CTRL_ENABLE; 2368 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2369 2370 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2371 (ndesc - 1) * sizeof(struct bwi_desc32)); 2372 } 2373 2374 static int 2375 bwi_init_rx_ring32(struct bwi_softc *sc) 2376 { 2377 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2378 int i, error; 2379 2380 sc->sc_rx_bdata.rbd_idx = 0; 2381 2382 for (i = 0; i < BWI_RX_NDESC; ++i) { 2383 error = bwi_newbuf(sc, i, 1); 2384 if (error) { 2385 device_printf(sc->sc_dev, 2386 "can't allocate %dth RX buffer\n", i); 2387 return error; 2388 } 2389 } 2390 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2391 BUS_DMASYNC_PREWRITE); 2392 2393 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2394 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2395 return 0; 2396 } 2397 2398 static int 2399 bwi_init_txstats32(struct bwi_softc *sc) 2400 { 2401 struct bwi_txstats_data *st = sc->sc_txstats; 2402 bus_addr_t stats_paddr; 2403 int i; 2404 2405 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2406 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2407 2408 st->stats_idx = 0; 2409 2410 stats_paddr = st->stats_paddr; 2411 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2412 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2413 stats_paddr, sizeof(struct bwi_txstats), 0); 2414 stats_paddr += sizeof(struct bwi_txstats); 2415 } 2416 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2417 BUS_DMASYNC_PREWRITE); 2418 2419 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2420 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2421 return 0; 2422 } 2423 2424 static void 2425 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2426 int buf_len) 2427 { 2428 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2429 2430 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2431 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2432 paddr, buf_len, 0); 2433 } 2434 2435 static void 2436 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2437 int buf_idx, bus_addr_t paddr, int buf_len) 2438 { 2439 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2440 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2441 paddr, buf_len, 1); 2442 } 2443 2444 static int 2445 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2446 { 2447 /* TODO:64 */ 2448 return EOPNOTSUPP; 2449 } 2450 2451 static int 2452 bwi_init_rx_ring64(struct bwi_softc *sc) 2453 { 2454 /* TODO:64 */ 2455 return EOPNOTSUPP; 2456 } 2457 2458 static int 2459 bwi_init_txstats64(struct bwi_softc *sc) 2460 { 2461 /* TODO:64 */ 2462 return EOPNOTSUPP; 2463 } 2464 2465 static void 2466 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2467 int buf_len) 2468 { 2469 /* TODO:64 */ 2470 } 2471 2472 static void 2473 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2474 int buf_idx, bus_addr_t paddr, int buf_len) 2475 { 2476 /* TODO:64 */ 2477 } 2478 2479 static void 2480 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2481 bus_size_t mapsz __unused, int error) 2482 { 2483 if (!error) { 2484 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2485 *((bus_addr_t *)arg) = seg->ds_addr; 2486 } 2487 } 2488 2489 static int 2490 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2491 { 2492 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2493 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2494 struct bwi_rxbuf_hdr *hdr; 2495 bus_dmamap_t map; 2496 bus_addr_t paddr; 2497 struct mbuf *m; 2498 int error; 2499 2500 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2501 2502 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2503 if (m == NULL) { 2504 error = ENOBUFS; 2505 2506 /* 2507 * If the NIC is up and running, we need to: 2508 * - Clear RX buffer's header. 2509 * - Restore RX descriptor settings. 2510 */ 2511 if (init) 2512 return error; 2513 else 2514 goto back; 2515 } 2516 m->m_len = m->m_pkthdr.len = MCLBYTES; 2517 2518 /* 2519 * Try to load RX buf into temporary DMA map 2520 */ 2521 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2522 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2523 if (error) { 2524 m_freem(m); 2525 2526 /* 2527 * See the comment above 2528 */ 2529 if (init) 2530 return error; 2531 else 2532 goto back; 2533 } 2534 2535 if (!init) 2536 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2537 rxbuf->rb_mbuf = m; 2538 rxbuf->rb_paddr = paddr; 2539 2540 /* 2541 * Swap RX buf's DMA map with the loaded temporary one 2542 */ 2543 map = rxbuf->rb_dmap; 2544 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2545 rbd->rbd_tmp_dmap = map; 2546 2547 back: 2548 /* 2549 * Clear RX buf header 2550 */ 2551 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2552 bzero(hdr, sizeof(*hdr)); 2553 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2554 2555 /* 2556 * Setup RX buf descriptor 2557 */ 2558 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2559 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2560 return error; 2561 } 2562 2563 static void 2564 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2565 const uint8_t *addr) 2566 { 2567 int i; 2568 2569 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2570 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2571 2572 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2573 uint16_t addr_val; 2574 2575 addr_val = (uint16_t)addr[i * 2] | 2576 (((uint16_t)addr[(i * 2) + 1]) << 8); 2577 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2578 } 2579 } 2580 2581 static int 2582 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2583 { 2584 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2585 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2586 struct ieee80211com *ic = &sc->sc_ic; 2587 int idx, rx_data = 0; 2588 2589 idx = rbd->rbd_idx; 2590 while (idx != end_idx) { 2591 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2592 struct bwi_rxbuf_hdr *hdr; 2593 struct ieee80211_frame_min *wh; 2594 struct ieee80211_node *ni; 2595 struct mbuf *m; 2596 uint32_t plcp; 2597 uint16_t flags2; 2598 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2599 2600 m = rb->rb_mbuf; 2601 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2602 BUS_DMASYNC_POSTREAD); 2603 2604 if (bwi_newbuf(sc, idx, 0)) { 2605 counter_u64_add(ic->ic_ierrors, 1); 2606 goto next; 2607 } 2608 2609 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2610 flags2 = le16toh(hdr->rxh_flags2); 2611 2612 hdr_extra = 0; 2613 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2614 hdr_extra = 2; 2615 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2616 2617 buflen = le16toh(hdr->rxh_buflen); 2618 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2619 device_printf(sc->sc_dev, 2620 "%s: zero length data, hdr_extra %d\n", 2621 __func__, hdr_extra); 2622 counter_u64_add(ic->ic_ierrors, 1); 2623 m_freem(m); 2624 goto next; 2625 } 2626 2627 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2628 rssi = bwi_calc_rssi(sc, hdr); 2629 noise = bwi_calc_noise(sc); 2630 2631 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2632 m_adj(m, sizeof(*hdr) + wh_ofs); 2633 2634 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2635 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2636 else 2637 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2638 2639 /* RX radio tap */ 2640 if (ieee80211_radiotap_active(ic)) 2641 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2642 2643 m_adj(m, -IEEE80211_CRC_LEN); 2644 2645 BWI_UNLOCK(sc); 2646 2647 wh = mtod(m, struct ieee80211_frame_min *); 2648 ni = ieee80211_find_rxnode(ic, wh); 2649 if (ni != NULL) { 2650 type = ieee80211_input(ni, m, rssi - noise, noise); 2651 ieee80211_free_node(ni); 2652 } else 2653 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2654 if (type == IEEE80211_FC0_TYPE_DATA) { 2655 rx_data = 1; 2656 sc->sc_rx_rate = rate; 2657 } 2658 2659 BWI_LOCK(sc); 2660 next: 2661 idx = (idx + 1) % BWI_RX_NDESC; 2662 2663 if (sc->sc_flags & BWI_F_STOP) { 2664 /* 2665 * Take the fast lane, don't do 2666 * any damage to softc 2667 */ 2668 return -1; 2669 } 2670 } 2671 2672 rbd->rbd_idx = idx; 2673 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2674 BUS_DMASYNC_PREWRITE); 2675 2676 return rx_data; 2677 } 2678 2679 static int 2680 bwi_rxeof32(struct bwi_softc *sc) 2681 { 2682 uint32_t val, rx_ctrl; 2683 int end_idx, rx_data; 2684 2685 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2686 2687 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2688 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2689 sizeof(struct bwi_desc32); 2690 2691 rx_data = bwi_rxeof(sc, end_idx); 2692 if (rx_data >= 0) { 2693 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2694 end_idx * sizeof(struct bwi_desc32)); 2695 } 2696 return rx_data; 2697 } 2698 2699 static int 2700 bwi_rxeof64(struct bwi_softc *sc) 2701 { 2702 /* TODO:64 */ 2703 return 0; 2704 } 2705 2706 static void 2707 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2708 { 2709 int i; 2710 2711 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2712 2713 #define NRETRY 10 2714 2715 for (i = 0; i < NRETRY; ++i) { 2716 uint32_t status; 2717 2718 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2719 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2720 BWI_RX32_STATUS_STATE_DISABLED) 2721 break; 2722 2723 DELAY(1000); 2724 } 2725 if (i == NRETRY) 2726 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2727 2728 #undef NRETRY 2729 2730 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2731 } 2732 2733 static void 2734 bwi_free_txstats32(struct bwi_softc *sc) 2735 { 2736 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2737 } 2738 2739 static void 2740 bwi_free_rx_ring32(struct bwi_softc *sc) 2741 { 2742 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2743 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2744 int i; 2745 2746 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2747 2748 for (i = 0; i < BWI_RX_NDESC; ++i) { 2749 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2750 2751 if (rb->rb_mbuf != NULL) { 2752 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2753 m_freem(rb->rb_mbuf); 2754 rb->rb_mbuf = NULL; 2755 } 2756 } 2757 } 2758 2759 static void 2760 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2761 { 2762 struct bwi_ring_data *rd; 2763 struct bwi_txbuf_data *tbd; 2764 uint32_t state, val; 2765 int i; 2766 2767 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2768 rd = &sc->sc_tx_rdata[ring_idx]; 2769 tbd = &sc->sc_tx_bdata[ring_idx]; 2770 2771 #define NRETRY 10 2772 2773 for (i = 0; i < NRETRY; ++i) { 2774 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2775 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2776 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2777 state == BWI_TX32_STATUS_STATE_IDLE || 2778 state == BWI_TX32_STATUS_STATE_STOPPED) 2779 break; 2780 2781 DELAY(1000); 2782 } 2783 if (i == NRETRY) { 2784 device_printf(sc->sc_dev, 2785 "%s: wait for TX ring(%d) stable timed out\n", 2786 __func__, ring_idx); 2787 } 2788 2789 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2790 for (i = 0; i < NRETRY; ++i) { 2791 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2792 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2793 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2794 break; 2795 2796 DELAY(1000); 2797 } 2798 if (i == NRETRY) 2799 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2800 __func__, ring_idx); 2801 2802 #undef NRETRY 2803 2804 DELAY(1000); 2805 2806 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2807 2808 for (i = 0; i < BWI_TX_NDESC; ++i) { 2809 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2810 2811 if (tb->tb_mbuf != NULL) { 2812 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2813 m_freem(tb->tb_mbuf); 2814 tb->tb_mbuf = NULL; 2815 } 2816 if (tb->tb_ni != NULL) { 2817 ieee80211_free_node(tb->tb_ni); 2818 tb->tb_ni = NULL; 2819 } 2820 } 2821 } 2822 2823 static void 2824 bwi_free_txstats64(struct bwi_softc *sc) 2825 { 2826 /* TODO:64 */ 2827 } 2828 2829 static void 2830 bwi_free_rx_ring64(struct bwi_softc *sc) 2831 { 2832 /* TODO:64 */ 2833 } 2834 2835 static void 2836 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2837 { 2838 /* TODO:64 */ 2839 } 2840 2841 /* XXX does not belong here */ 2842 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2843 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2844 2845 static __inline void 2846 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2847 { 2848 uint32_t plcp; 2849 2850 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2851 IEEE80211_OFDM_PLCP_RATE_MASK) | 2852 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2853 *plcp0 = htole32(plcp); 2854 } 2855 2856 static __inline void 2857 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2858 uint8_t rate) 2859 { 2860 int len, service, pkt_bitlen; 2861 2862 pkt_bitlen = pkt_len * NBBY; 2863 len = howmany(pkt_bitlen * 2, rate); 2864 2865 service = IEEE80211_PLCP_SERVICE_LOCKED; 2866 if (rate == (11 * 2)) { 2867 int pkt_bitlen1; 2868 2869 /* 2870 * PLCP service field needs to be adjusted, 2871 * if TX rate is 11Mbytes/s 2872 */ 2873 pkt_bitlen1 = len * 11; 2874 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2875 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2876 } 2877 2878 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2879 plcp->i_service = service; 2880 plcp->i_length = htole16(len); 2881 /* NOTE: do NOT touch i_crc */ 2882 } 2883 2884 static __inline void 2885 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2886 void *plcp, int pkt_len, uint8_t rate) 2887 { 2888 enum ieee80211_phytype modtype; 2889 2890 /* 2891 * Assume caller has zeroed 'plcp' 2892 */ 2893 modtype = ieee80211_rate2phytype(rt, rate); 2894 if (modtype == IEEE80211_T_OFDM) 2895 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2896 else if (modtype == IEEE80211_T_DS) 2897 bwi_ds_plcp_header(plcp, pkt_len, rate); 2898 else 2899 panic("unsupport modulation type %u\n", modtype); 2900 } 2901 2902 static int 2903 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2904 struct ieee80211_node *ni) 2905 { 2906 struct ieee80211vap *vap = ni->ni_vap; 2907 struct ieee80211com *ic = &sc->sc_ic; 2908 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2909 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2910 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2911 struct bwi_mac *mac; 2912 struct bwi_txbuf_hdr *hdr; 2913 struct ieee80211_frame *wh; 2914 const struct ieee80211_txparam *tp = ni->ni_txparms; 2915 uint8_t rate, rate_fb; 2916 uint32_t mac_ctrl; 2917 uint16_t phy_ctrl; 2918 bus_addr_t paddr; 2919 int type, ismcast, pkt_len, error, rix; 2920 #if 0 2921 const uint8_t *p; 2922 int i; 2923 #endif 2924 2925 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2926 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2927 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2928 2929 wh = mtod(m, struct ieee80211_frame *); 2930 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2931 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2932 2933 /* Get 802.11 frame len before prepending TX header */ 2934 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2935 2936 /* 2937 * Find TX rate 2938 */ 2939 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2940 rate = rate_fb = tp->mgmtrate; 2941 } else if (ismcast) { 2942 rate = rate_fb = tp->mcastrate; 2943 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2944 rate = rate_fb = tp->ucastrate; 2945 } else { 2946 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2947 rate = ni->ni_txrate; 2948 2949 if (rix > 0) { 2950 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2951 IEEE80211_RATE_VAL; 2952 } else { 2953 rate_fb = rate; 2954 } 2955 } 2956 tb->tb_rate[0] = rate; 2957 tb->tb_rate[1] = rate_fb; 2958 sc->sc_tx_rate = rate; 2959 2960 /* 2961 * TX radio tap 2962 */ 2963 if (ieee80211_radiotap_active_vap(vap)) { 2964 sc->sc_tx_th.wt_flags = 0; 2965 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2966 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2967 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2968 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2969 rate != (1 * 2)) { 2970 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2971 } 2972 sc->sc_tx_th.wt_rate = rate; 2973 2974 ieee80211_radiotap_tx(vap, m); 2975 } 2976 2977 /* 2978 * Setup the embedded TX header 2979 */ 2980 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2981 if (m == NULL) { 2982 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2983 __func__); 2984 return ENOBUFS; 2985 } 2986 hdr = mtod(m, struct bwi_txbuf_hdr *); 2987 2988 bzero(hdr, sizeof(*hdr)); 2989 2990 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 2991 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 2992 2993 if (!ismcast) { 2994 uint16_t dur; 2995 2996 dur = ieee80211_ack_duration(sc->sc_rates, rate, 2997 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 2998 2999 hdr->txh_fb_duration = htole16(dur); 3000 } 3001 3002 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3003 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3004 3005 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3006 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3007 3008 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3009 BWI_TXH_PHY_C_ANTMODE_MASK); 3010 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3011 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3012 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3013 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3014 3015 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3016 if (!ismcast) 3017 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3018 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3019 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3020 3021 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3022 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3023 3024 /* Catch any further usage */ 3025 hdr = NULL; 3026 wh = NULL; 3027 3028 /* DMA load */ 3029 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3030 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3031 if (error && error != EFBIG) { 3032 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3033 __func__, error); 3034 goto back; 3035 } 3036 3037 if (error) { /* error == EFBIG */ 3038 struct mbuf *m_new; 3039 3040 m_new = m_defrag(m, M_NOWAIT); 3041 if (m_new == NULL) { 3042 device_printf(sc->sc_dev, 3043 "%s: can't defrag TX buffer\n", __func__); 3044 error = ENOBUFS; 3045 goto back; 3046 } else { 3047 m = m_new; 3048 } 3049 3050 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3051 bwi_dma_buf_addr, &paddr, 3052 BUS_DMA_NOWAIT); 3053 if (error) { 3054 device_printf(sc->sc_dev, 3055 "%s: can't load TX buffer (2) %d\n", 3056 __func__, error); 3057 goto back; 3058 } 3059 } 3060 error = 0; 3061 3062 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3063 3064 tb->tb_mbuf = m; 3065 tb->tb_ni = ni; 3066 3067 #if 0 3068 p = mtod(m, const uint8_t *); 3069 for (i = 0; i < m->m_pkthdr.len; ++i) { 3070 if (i != 0 && i % 8 == 0) 3071 printf("\n"); 3072 printf("%02x ", p[i]); 3073 } 3074 printf("\n"); 3075 #endif 3076 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3077 idx, pkt_len, m->m_pkthdr.len); 3078 3079 /* Setup TX descriptor */ 3080 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3081 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3082 BUS_DMASYNC_PREWRITE); 3083 3084 /* Kick start */ 3085 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3086 3087 back: 3088 if (error) 3089 m_freem(m); 3090 return error; 3091 } 3092 3093 static int 3094 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3095 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3096 { 3097 struct ieee80211vap *vap = ni->ni_vap; 3098 struct ieee80211com *ic = ni->ni_ic; 3099 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3100 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3101 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3102 struct bwi_mac *mac; 3103 struct bwi_txbuf_hdr *hdr; 3104 struct ieee80211_frame *wh; 3105 uint8_t rate, rate_fb; 3106 uint32_t mac_ctrl; 3107 uint16_t phy_ctrl; 3108 bus_addr_t paddr; 3109 int ismcast, pkt_len, error; 3110 3111 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3112 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3113 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3114 3115 wh = mtod(m, struct ieee80211_frame *); 3116 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3117 3118 /* Get 802.11 frame len before prepending TX header */ 3119 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3120 3121 /* 3122 * Find TX rate 3123 */ 3124 rate = params->ibp_rate0; 3125 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3126 /* XXX fall back to mcast/mgmt rate? */ 3127 m_freem(m); 3128 return EINVAL; 3129 } 3130 if (params->ibp_try1 != 0) { 3131 rate_fb = params->ibp_rate1; 3132 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3133 /* XXX fall back to rate0? */ 3134 m_freem(m); 3135 return EINVAL; 3136 } 3137 } else 3138 rate_fb = rate; 3139 tb->tb_rate[0] = rate; 3140 tb->tb_rate[1] = rate_fb; 3141 sc->sc_tx_rate = rate; 3142 3143 /* 3144 * TX radio tap 3145 */ 3146 if (ieee80211_radiotap_active_vap(vap)) { 3147 sc->sc_tx_th.wt_flags = 0; 3148 /* XXX IEEE80211_BPF_CRYPTO */ 3149 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3150 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3151 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3152 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3153 sc->sc_tx_th.wt_rate = rate; 3154 3155 ieee80211_radiotap_tx(vap, m); 3156 } 3157 3158 /* 3159 * Setup the embedded TX header 3160 */ 3161 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3162 if (m == NULL) { 3163 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3164 __func__); 3165 return ENOBUFS; 3166 } 3167 hdr = mtod(m, struct bwi_txbuf_hdr *); 3168 3169 bzero(hdr, sizeof(*hdr)); 3170 3171 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3172 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3173 3174 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3175 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3176 uint16_t dur; 3177 3178 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3179 3180 hdr->txh_fb_duration = htole16(dur); 3181 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3182 } 3183 3184 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3185 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3186 3187 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3188 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3189 3190 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3191 BWI_TXH_PHY_C_ANTMODE_MASK); 3192 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3193 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3194 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3195 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3196 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3197 3198 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3199 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3200 3201 /* Catch any further usage */ 3202 hdr = NULL; 3203 wh = NULL; 3204 3205 /* DMA load */ 3206 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3207 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3208 if (error != 0) { 3209 struct mbuf *m_new; 3210 3211 if (error != EFBIG) { 3212 device_printf(sc->sc_dev, 3213 "%s: can't load TX buffer (1) %d\n", 3214 __func__, error); 3215 goto back; 3216 } 3217 m_new = m_defrag(m, M_NOWAIT); 3218 if (m_new == NULL) { 3219 device_printf(sc->sc_dev, 3220 "%s: can't defrag TX buffer\n", __func__); 3221 error = ENOBUFS; 3222 goto back; 3223 } 3224 m = m_new; 3225 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3226 bwi_dma_buf_addr, &paddr, 3227 BUS_DMA_NOWAIT); 3228 if (error) { 3229 device_printf(sc->sc_dev, 3230 "%s: can't load TX buffer (2) %d\n", 3231 __func__, error); 3232 goto back; 3233 } 3234 } 3235 3236 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3237 3238 tb->tb_mbuf = m; 3239 tb->tb_ni = ni; 3240 3241 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3242 idx, pkt_len, m->m_pkthdr.len); 3243 3244 /* Setup TX descriptor */ 3245 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3246 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3247 BUS_DMASYNC_PREWRITE); 3248 3249 /* Kick start */ 3250 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3251 back: 3252 if (error) 3253 m_freem(m); 3254 return error; 3255 } 3256 3257 static void 3258 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3259 { 3260 idx = (idx + 1) % BWI_TX_NDESC; 3261 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3262 idx * sizeof(struct bwi_desc32)); 3263 } 3264 3265 static void 3266 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3267 { 3268 /* TODO:64 */ 3269 } 3270 3271 static void 3272 bwi_txeof_status32(struct bwi_softc *sc) 3273 { 3274 uint32_t val, ctrl_base; 3275 int end_idx; 3276 3277 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3278 3279 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3280 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3281 sizeof(struct bwi_desc32); 3282 3283 bwi_txeof_status(sc, end_idx); 3284 3285 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3286 end_idx * sizeof(struct bwi_desc32)); 3287 3288 bwi_start_locked(sc); 3289 } 3290 3291 static void 3292 bwi_txeof_status64(struct bwi_softc *sc) 3293 { 3294 /* TODO:64 */ 3295 } 3296 3297 static void 3298 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3299 { 3300 struct bwi_txbuf_data *tbd; 3301 struct bwi_txbuf *tb; 3302 int ring_idx, buf_idx; 3303 struct ieee80211_node *ni; 3304 3305 if (tx_id == 0) { 3306 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3307 return; 3308 } 3309 3310 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3311 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3312 3313 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3314 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3315 3316 tbd = &sc->sc_tx_bdata[ring_idx]; 3317 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3318 tbd->tbd_used--; 3319 3320 tb = &tbd->tbd_buf[buf_idx]; 3321 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3322 "acked %d, data_txcnt %d, ni %p\n", 3323 buf_idx, acked, data_txcnt, tb->tb_ni); 3324 3325 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3326 3327 if ((ni = tb->tb_ni) != NULL) { 3328 const struct bwi_txbuf_hdr *hdr = 3329 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3330 struct ieee80211_ratectl_tx_status txs; 3331 3332 /* NB: update rate control only for unicast frames */ 3333 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3334 /* 3335 * Feed back 'acked and data_txcnt'. Note that the 3336 * generic AMRR code only understands one tx rate 3337 * and the estimator doesn't handle real retry counts 3338 * well so to avoid over-aggressive downshifting we 3339 * treat any number of retries as "1". 3340 */ 3341 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 3342 txs.long_retries = acked; 3343 if (data_txcnt > 1) 3344 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 3345 else { 3346 txs.status = 3347 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3348 } 3349 ieee80211_ratectl_tx_complete(ni, &txs); 3350 } 3351 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3352 tb->tb_ni = NULL; 3353 } else 3354 m_freem(tb->tb_mbuf); 3355 tb->tb_mbuf = NULL; 3356 3357 if (tbd->tbd_used == 0) 3358 sc->sc_tx_timer = 0; 3359 } 3360 3361 static void 3362 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3363 { 3364 struct bwi_txstats_data *st = sc->sc_txstats; 3365 int idx; 3366 3367 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3368 3369 idx = st->stats_idx; 3370 while (idx != end_idx) { 3371 const struct bwi_txstats *stats = &st->stats[idx]; 3372 3373 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3374 int data_txcnt; 3375 3376 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3377 BWI_TXS_TXCNT_DATA); 3378 _bwi_txeof(sc, le16toh(stats->txs_id), 3379 stats->txs_flags & BWI_TXS_F_ACKED, 3380 data_txcnt); 3381 } 3382 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3383 } 3384 st->stats_idx = idx; 3385 } 3386 3387 static void 3388 bwi_txeof(struct bwi_softc *sc) 3389 { 3390 3391 for (;;) { 3392 uint32_t tx_status0, tx_status1 __unused; 3393 uint16_t tx_id; 3394 int data_txcnt; 3395 3396 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3397 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3398 break; 3399 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3400 3401 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3402 data_txcnt = __SHIFTOUT(tx_status0, 3403 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3404 3405 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3406 continue; 3407 3408 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3409 data_txcnt); 3410 } 3411 3412 bwi_start_locked(sc); 3413 } 3414 3415 static int 3416 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3417 { 3418 bwi_power_on(sc, 1); 3419 return bwi_set_clock_mode(sc, clk_mode); 3420 } 3421 3422 static void 3423 bwi_bbp_power_off(struct bwi_softc *sc) 3424 { 3425 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3426 bwi_power_off(sc, 1); 3427 } 3428 3429 static int 3430 bwi_get_pwron_delay(struct bwi_softc *sc) 3431 { 3432 struct bwi_regwin *com, *old; 3433 struct bwi_clock_freq freq; 3434 uint32_t val; 3435 int error; 3436 3437 com = &sc->sc_com_regwin; 3438 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3439 3440 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3441 return 0; 3442 3443 error = bwi_regwin_switch(sc, com, &old); 3444 if (error) 3445 return error; 3446 3447 bwi_get_clock_freq(sc, &freq); 3448 3449 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3450 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3451 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3452 3453 return bwi_regwin_switch(sc, old, NULL); 3454 } 3455 3456 static int 3457 bwi_bus_attach(struct bwi_softc *sc) 3458 { 3459 struct bwi_regwin *bus, *old; 3460 int error; 3461 3462 bus = &sc->sc_bus_regwin; 3463 3464 error = bwi_regwin_switch(sc, bus, &old); 3465 if (error) 3466 return error; 3467 3468 if (!bwi_regwin_is_enabled(sc, bus)) 3469 bwi_regwin_enable(sc, bus, 0); 3470 3471 /* Disable interripts */ 3472 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3473 3474 return bwi_regwin_switch(sc, old, NULL); 3475 } 3476 3477 static const char * 3478 bwi_regwin_name(const struct bwi_regwin *rw) 3479 { 3480 switch (rw->rw_type) { 3481 case BWI_REGWIN_T_COM: 3482 return "COM"; 3483 case BWI_REGWIN_T_BUSPCI: 3484 return "PCI"; 3485 case BWI_REGWIN_T_MAC: 3486 return "MAC"; 3487 case BWI_REGWIN_T_BUSPCIE: 3488 return "PCIE"; 3489 } 3490 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3491 return NULL; 3492 } 3493 3494 static uint32_t 3495 bwi_regwin_disable_bits(struct bwi_softc *sc) 3496 { 3497 uint32_t busrev; 3498 3499 /* XXX cache this */ 3500 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3501 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3502 "bus rev %u\n", busrev); 3503 3504 if (busrev == BWI_BUSREV_0) 3505 return BWI_STATE_LO_DISABLE1; 3506 else if (busrev == BWI_BUSREV_1) 3507 return BWI_STATE_LO_DISABLE2; 3508 else 3509 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3510 } 3511 3512 int 3513 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3514 { 3515 uint32_t val, disable_bits; 3516 3517 disable_bits = bwi_regwin_disable_bits(sc); 3518 val = CSR_READ_4(sc, BWI_STATE_LO); 3519 3520 if ((val & (BWI_STATE_LO_CLOCK | 3521 BWI_STATE_LO_RESET | 3522 disable_bits)) == BWI_STATE_LO_CLOCK) { 3523 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3524 bwi_regwin_name(rw)); 3525 return 1; 3526 } else { 3527 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3528 bwi_regwin_name(rw)); 3529 return 0; 3530 } 3531 } 3532 3533 void 3534 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3535 { 3536 uint32_t state_lo, disable_bits; 3537 int i; 3538 3539 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3540 3541 /* 3542 * If current regwin is in 'reset' state, it was already disabled. 3543 */ 3544 if (state_lo & BWI_STATE_LO_RESET) { 3545 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3546 "%s was already disabled\n", bwi_regwin_name(rw)); 3547 return; 3548 } 3549 3550 disable_bits = bwi_regwin_disable_bits(sc); 3551 3552 /* 3553 * Disable normal clock 3554 */ 3555 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3556 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3557 3558 /* 3559 * Wait until normal clock is disabled 3560 */ 3561 #define NRETRY 1000 3562 for (i = 0; i < NRETRY; ++i) { 3563 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3564 if (state_lo & disable_bits) 3565 break; 3566 DELAY(10); 3567 } 3568 if (i == NRETRY) { 3569 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3570 bwi_regwin_name(rw)); 3571 } 3572 3573 for (i = 0; i < NRETRY; ++i) { 3574 uint32_t state_hi; 3575 3576 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3577 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3578 break; 3579 DELAY(10); 3580 } 3581 if (i == NRETRY) { 3582 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3583 bwi_regwin_name(rw)); 3584 } 3585 #undef NRETRY 3586 3587 /* 3588 * Reset and disable regwin with gated clock 3589 */ 3590 state_lo = BWI_STATE_LO_RESET | disable_bits | 3591 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3592 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3593 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3594 3595 /* Flush pending bus write */ 3596 CSR_READ_4(sc, BWI_STATE_LO); 3597 DELAY(1); 3598 3599 /* Reset and disable regwin */ 3600 state_lo = BWI_STATE_LO_RESET | disable_bits | 3601 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3602 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3603 3604 /* Flush pending bus write */ 3605 CSR_READ_4(sc, BWI_STATE_LO); 3606 DELAY(1); 3607 } 3608 3609 void 3610 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3611 { 3612 uint32_t state_lo, state_hi, imstate; 3613 3614 bwi_regwin_disable(sc, rw, flags); 3615 3616 /* Reset regwin with gated clock */ 3617 state_lo = BWI_STATE_LO_RESET | 3618 BWI_STATE_LO_CLOCK | 3619 BWI_STATE_LO_GATED_CLOCK | 3620 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3621 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3622 3623 /* Flush pending bus write */ 3624 CSR_READ_4(sc, BWI_STATE_LO); 3625 DELAY(1); 3626 3627 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3628 if (state_hi & BWI_STATE_HI_SERROR) 3629 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3630 3631 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3632 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3633 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3634 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3635 } 3636 3637 /* Enable regwin with gated clock */ 3638 state_lo = BWI_STATE_LO_CLOCK | 3639 BWI_STATE_LO_GATED_CLOCK | 3640 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3641 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3642 3643 /* Flush pending bus write */ 3644 CSR_READ_4(sc, BWI_STATE_LO); 3645 DELAY(1); 3646 3647 /* Enable regwin with normal clock */ 3648 state_lo = BWI_STATE_LO_CLOCK | 3649 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3650 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3651 3652 /* Flush pending bus write */ 3653 CSR_READ_4(sc, BWI_STATE_LO); 3654 DELAY(1); 3655 } 3656 3657 static void 3658 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3659 { 3660 struct bwi_mac *mac; 3661 struct bwi_myaddr_bssid buf; 3662 const uint8_t *p; 3663 uint32_t val; 3664 int n, i; 3665 3666 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3667 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3668 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3669 3670 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3671 3672 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3673 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3674 3675 n = sizeof(buf) / sizeof(val); 3676 p = (const uint8_t *)&buf; 3677 for (i = 0; i < n; ++i) { 3678 int j; 3679 3680 val = 0; 3681 for (j = 0; j < sizeof(val); ++j) 3682 val |= ((uint32_t)(*p++)) << (j * 8); 3683 3684 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3685 } 3686 } 3687 3688 static void 3689 bwi_updateslot(struct ieee80211com *ic) 3690 { 3691 struct bwi_softc *sc = ic->ic_softc; 3692 struct bwi_mac *mac; 3693 3694 BWI_LOCK(sc); 3695 if (sc->sc_flags & BWI_F_RUNNING) { 3696 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3697 3698 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3699 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3700 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3701 3702 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3703 } 3704 BWI_UNLOCK(sc); 3705 } 3706 3707 static void 3708 bwi_calibrate(void *xsc) 3709 { 3710 struct bwi_softc *sc = xsc; 3711 struct bwi_mac *mac; 3712 3713 BWI_ASSERT_LOCKED(sc); 3714 3715 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3716 ("opmode %d", sc->sc_ic.ic_opmode)); 3717 3718 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3719 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3720 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3721 3722 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3723 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3724 3725 /* XXX 15 seconds */ 3726 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3727 } 3728 3729 static int 3730 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3731 { 3732 struct bwi_mac *mac; 3733 3734 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3735 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3736 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3737 3738 return bwi_rf_calc_rssi(mac, hdr); 3739 } 3740 3741 static int 3742 bwi_calc_noise(struct bwi_softc *sc) 3743 { 3744 struct bwi_mac *mac; 3745 3746 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3747 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3748 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3749 3750 return bwi_rf_calc_noise(mac); 3751 } 3752 3753 static __inline uint8_t 3754 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3755 { 3756 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3757 return (ieee80211_plcp2rate(plcp, type)); 3758 } 3759 3760 static void 3761 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3762 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3763 { 3764 const struct ieee80211_frame_min *wh; 3765 3766 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3767 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3768 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3769 3770 wh = mtod(m, const struct ieee80211_frame_min *); 3771 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3772 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3773 3774 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */ 3775 sc->sc_rx_th.wr_rate = rate; 3776 sc->sc_rx_th.wr_antsignal = rssi; 3777 sc->sc_rx_th.wr_antnoise = noise; 3778 } 3779 3780 static void 3781 bwi_led_attach(struct bwi_softc *sc) 3782 { 3783 const uint8_t *led_act = NULL; 3784 uint16_t gpio, val[BWI_LED_MAX]; 3785 int i; 3786 3787 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3788 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3789 led_act = bwi_vendor_led_act[i].led_act; 3790 break; 3791 } 3792 } 3793 if (led_act == NULL) 3794 led_act = bwi_default_led_act; 3795 3796 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3797 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3798 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3799 3800 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3801 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3802 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3803 3804 for (i = 0; i < BWI_LED_MAX; ++i) { 3805 struct bwi_led *led = &sc->sc_leds[i]; 3806 3807 if (val[i] == 0xff) { 3808 led->l_act = led_act[i]; 3809 } else { 3810 if (val[i] & BWI_LED_ACT_LOW) 3811 led->l_flags |= BWI_LED_F_ACTLOW; 3812 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3813 } 3814 led->l_mask = (1 << i); 3815 3816 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3817 led->l_act == BWI_LED_ACT_BLINK_POLL || 3818 led->l_act == BWI_LED_ACT_BLINK) { 3819 led->l_flags |= BWI_LED_F_BLINK; 3820 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3821 led->l_flags |= BWI_LED_F_POLLABLE; 3822 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3823 led->l_flags |= BWI_LED_F_SLOW; 3824 3825 if (sc->sc_blink_led == NULL) { 3826 sc->sc_blink_led = led; 3827 if (led->l_flags & BWI_LED_F_SLOW) 3828 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3829 } 3830 } 3831 3832 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3833 "%dth led, act %d, lowact %d\n", i, 3834 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3835 } 3836 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3837 } 3838 3839 static __inline uint16_t 3840 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3841 { 3842 if (led->l_flags & BWI_LED_F_ACTLOW) 3843 on = !on; 3844 if (on) 3845 val |= led->l_mask; 3846 else 3847 val &= ~led->l_mask; 3848 return val; 3849 } 3850 3851 static void 3852 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3853 { 3854 struct ieee80211com *ic = &sc->sc_ic; 3855 uint16_t val; 3856 int i; 3857 3858 if (nstate == IEEE80211_S_INIT) { 3859 callout_stop(&sc->sc_led_blink_ch); 3860 sc->sc_led_blinking = 0; 3861 } 3862 3863 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3864 return; 3865 3866 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3867 for (i = 0; i < BWI_LED_MAX; ++i) { 3868 struct bwi_led *led = &sc->sc_leds[i]; 3869 int on; 3870 3871 if (led->l_act == BWI_LED_ACT_UNKN || 3872 led->l_act == BWI_LED_ACT_NULL) 3873 continue; 3874 3875 if ((led->l_flags & BWI_LED_F_BLINK) && 3876 nstate != IEEE80211_S_INIT) 3877 continue; 3878 3879 switch (led->l_act) { 3880 case BWI_LED_ACT_ON: /* Always on */ 3881 on = 1; 3882 break; 3883 case BWI_LED_ACT_OFF: /* Always off */ 3884 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3885 on = 0; 3886 break; 3887 default: 3888 on = 1; 3889 switch (nstate) { 3890 case IEEE80211_S_INIT: 3891 on = 0; 3892 break; 3893 case IEEE80211_S_RUN: 3894 if (led->l_act == BWI_LED_ACT_11G && 3895 ic->ic_curmode != IEEE80211_MODE_11G) 3896 on = 0; 3897 break; 3898 default: 3899 if (led->l_act == BWI_LED_ACT_ASSOC) 3900 on = 0; 3901 break; 3902 } 3903 break; 3904 } 3905 3906 val = bwi_led_onoff(led, val, on); 3907 } 3908 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3909 } 3910 static void 3911 bwi_led_event(struct bwi_softc *sc, int event) 3912 { 3913 struct bwi_led *led = sc->sc_blink_led; 3914 int rate; 3915 3916 if (event == BWI_LED_EVENT_POLL) { 3917 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3918 return; 3919 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3920 return; 3921 } 3922 3923 sc->sc_led_ticks = ticks; 3924 if (sc->sc_led_blinking) 3925 return; 3926 3927 switch (event) { 3928 case BWI_LED_EVENT_RX: 3929 rate = sc->sc_rx_rate; 3930 break; 3931 case BWI_LED_EVENT_TX: 3932 rate = sc->sc_tx_rate; 3933 break; 3934 case BWI_LED_EVENT_POLL: 3935 rate = 0; 3936 break; 3937 default: 3938 panic("unknown LED event %d\n", event); 3939 break; 3940 } 3941 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3942 bwi_led_duration[rate].off_dur); 3943 } 3944 3945 static void 3946 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3947 { 3948 struct bwi_led *led = sc->sc_blink_led; 3949 uint16_t val; 3950 3951 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3952 val = bwi_led_onoff(led, val, 1); 3953 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3954 3955 if (led->l_flags & BWI_LED_F_SLOW) { 3956 BWI_LED_SLOWDOWN(on_dur); 3957 BWI_LED_SLOWDOWN(off_dur); 3958 } 3959 3960 sc->sc_led_blinking = 1; 3961 sc->sc_led_blink_offdur = off_dur; 3962 3963 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3964 } 3965 3966 static void 3967 bwi_led_blink_next(void *xsc) 3968 { 3969 struct bwi_softc *sc = xsc; 3970 uint16_t val; 3971 3972 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3973 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3974 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3975 3976 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3977 bwi_led_blink_end, sc); 3978 } 3979 3980 static void 3981 bwi_led_blink_end(void *xsc) 3982 { 3983 struct bwi_softc *sc = xsc; 3984 sc->sc_led_blinking = 0; 3985 } 3986 3987 static void 3988 bwi_restart(void *xsc, int pending) 3989 { 3990 struct bwi_softc *sc = xsc; 3991 3992 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 3993 BWI_LOCK(sc); 3994 bwi_init_statechg(sc, 0); 3995 #if 0 3996 bwi_start_locked(sc); 3997 #endif 3998 BWI_UNLOCK(sc); 3999 } 4000