1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/malloc.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 #include <sys/taskqueue.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_arp.h> 63 #include <net/ethernet.h> 64 #include <net/if_llc.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_phy.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <machine/bus.h> 80 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 84 #include <dev/bwi/bitops.h> 85 #include <dev/bwi/if_bwireg.h> 86 #include <dev/bwi/if_bwivar.h> 87 #include <dev/bwi/bwimac.h> 88 #include <dev/bwi/bwirf.h> 89 90 struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93 }; 94 95 struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98 } __packed; 99 100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104 static void bwi_vap_delete(struct ieee80211vap *); 105 static void bwi_init(struct bwi_softc *); 106 static void bwi_parent(struct ieee80211com *); 107 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 108 static void bwi_start_locked(struct bwi_softc *); 109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111 static void bwi_watchdog(void *); 112 static void bwi_scan_start(struct ieee80211com *); 113 static void bwi_getradiocaps(struct ieee80211com *, int, int *, 114 struct ieee80211_channel[]); 115 static void bwi_set_channel(struct ieee80211com *); 116 static void bwi_scan_end(struct ieee80211com *); 117 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 118 static void bwi_updateslot(struct ieee80211com *); 119 120 static void bwi_calibrate(void *); 121 122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 123 static int bwi_calc_noise(struct bwi_softc *); 124 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 125 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 126 struct bwi_rxbuf_hdr *, const void *, int, int, int); 127 128 static void bwi_restart(void *, int); 129 static void bwi_init_statechg(struct bwi_softc *, int); 130 static void bwi_stop(struct bwi_softc *, int); 131 static void bwi_stop_locked(struct bwi_softc *, int); 132 static int bwi_newbuf(struct bwi_softc *, int, int); 133 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 134 struct ieee80211_node *); 135 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 136 struct ieee80211_node *, 137 const struct ieee80211_bpf_params *); 138 139 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 140 bus_addr_t, int, int); 141 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 142 143 static int bwi_init_tx_ring32(struct bwi_softc *, int); 144 static int bwi_init_rx_ring32(struct bwi_softc *); 145 static int bwi_init_txstats32(struct bwi_softc *); 146 static void bwi_free_tx_ring32(struct bwi_softc *, int); 147 static void bwi_free_rx_ring32(struct bwi_softc *); 148 static void bwi_free_txstats32(struct bwi_softc *); 149 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 150 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 151 int, bus_addr_t, int); 152 static int bwi_rxeof32(struct bwi_softc *); 153 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 154 static void bwi_txeof_status32(struct bwi_softc *); 155 156 static int bwi_init_tx_ring64(struct bwi_softc *, int); 157 static int bwi_init_rx_ring64(struct bwi_softc *); 158 static int bwi_init_txstats64(struct bwi_softc *); 159 static void bwi_free_tx_ring64(struct bwi_softc *, int); 160 static void bwi_free_rx_ring64(struct bwi_softc *); 161 static void bwi_free_txstats64(struct bwi_softc *); 162 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 163 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 164 int, bus_addr_t, int); 165 static int bwi_rxeof64(struct bwi_softc *); 166 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 167 static void bwi_txeof_status64(struct bwi_softc *); 168 169 static int bwi_rxeof(struct bwi_softc *, int); 170 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 171 static void bwi_txeof(struct bwi_softc *); 172 static void bwi_txeof_status(struct bwi_softc *, int); 173 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 174 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 175 176 static int bwi_dma_alloc(struct bwi_softc *); 177 static void bwi_dma_free(struct bwi_softc *); 178 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 179 struct bwi_ring_data *, bus_size_t, 180 uint32_t); 181 static int bwi_dma_mbuf_create(struct bwi_softc *); 182 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 183 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 184 static void bwi_dma_txstats_free(struct bwi_softc *); 185 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 186 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 187 bus_size_t, int); 188 189 static void bwi_power_on(struct bwi_softc *, int); 190 static int bwi_power_off(struct bwi_softc *, int); 191 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 192 static int bwi_set_clock_delay(struct bwi_softc *); 193 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 194 static int bwi_get_pwron_delay(struct bwi_softc *sc); 195 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 196 const uint8_t *); 197 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 198 199 static void bwi_get_card_flags(struct bwi_softc *); 200 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 201 202 static int bwi_bus_attach(struct bwi_softc *); 203 static int bwi_bbp_attach(struct bwi_softc *); 204 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 205 static void bwi_bbp_power_off(struct bwi_softc *); 206 207 static const char *bwi_regwin_name(const struct bwi_regwin *); 208 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 209 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 210 static int bwi_regwin_select(struct bwi_softc *, int); 211 212 static void bwi_led_attach(struct bwi_softc *); 213 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 214 static void bwi_led_event(struct bwi_softc *, int); 215 static void bwi_led_blink_start(struct bwi_softc *, int, int); 216 static void bwi_led_blink_next(void *); 217 static void bwi_led_blink_end(void *); 218 219 static const struct { 220 uint16_t did_min; 221 uint16_t did_max; 222 uint16_t bbp_id; 223 } bwi_bbpid_map[] = { 224 { 0x4301, 0x4301, 0x4301 }, 225 { 0x4305, 0x4307, 0x4307 }, 226 { 0x4402, 0x4403, 0x4402 }, 227 { 0x4610, 0x4615, 0x4610 }, 228 { 0x4710, 0x4715, 0x4710 }, 229 { 0x4720, 0x4725, 0x4309 } 230 }; 231 232 static const struct { 233 uint16_t bbp_id; 234 int nregwin; 235 } bwi_regwin_count[] = { 236 { 0x4301, 5 }, 237 { 0x4306, 6 }, 238 { 0x4307, 5 }, 239 { 0x4310, 8 }, 240 { 0x4401, 3 }, 241 { 0x4402, 3 }, 242 { 0x4610, 9 }, 243 { 0x4704, 9 }, 244 { 0x4710, 9 }, 245 { 0x5365, 7 } 246 }; 247 248 #define CLKSRC(src) \ 249 [BWI_CLKSRC_ ## src] = { \ 250 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 251 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 252 } 253 254 static const struct { 255 u_int freq_min; 256 u_int freq_max; 257 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 258 CLKSRC(LP_OSC), 259 CLKSRC(CS_OSC), 260 CLKSRC(PCI) 261 }; 262 263 #undef CLKSRC 264 265 #define VENDOR_LED_ACT(vendor) \ 266 { \ 267 .vid = PCI_VENDOR_##vendor, \ 268 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 269 } 270 271 static const struct { 272 #define PCI_VENDOR_COMPAQ 0x0e11 273 #define PCI_VENDOR_LINKSYS 0x1737 274 uint16_t vid; 275 uint8_t led_act[BWI_LED_MAX]; 276 } bwi_vendor_led_act[] = { 277 VENDOR_LED_ACT(COMPAQ), 278 VENDOR_LED_ACT(LINKSYS) 279 #undef PCI_VENDOR_LINKSYS 280 #undef PCI_VENDOR_COMPAQ 281 }; 282 283 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 284 { BWI_VENDOR_LED_ACT_DEFAULT }; 285 286 #undef VENDOR_LED_ACT 287 288 static const struct { 289 int on_dur; 290 int off_dur; 291 } bwi_led_duration[109] = { 292 [0] = { 400, 100 }, 293 [2] = { 150, 75 }, 294 [4] = { 90, 45 }, 295 [11] = { 66, 34 }, 296 [12] = { 53, 26 }, 297 [18] = { 42, 21 }, 298 [22] = { 35, 17 }, 299 [24] = { 32, 16 }, 300 [36] = { 21, 10 }, 301 [48] = { 16, 8 }, 302 [72] = { 11, 5 }, 303 [96] = { 9, 4 }, 304 [108] = { 7, 3 } 305 }; 306 307 #ifdef BWI_DEBUG 308 #ifdef BWI_DEBUG_VERBOSE 309 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 310 #else 311 static uint32_t bwi_debug; 312 #endif 313 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 314 #endif /* BWI_DEBUG */ 315 316 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 317 318 uint16_t 319 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 320 { 321 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 322 } 323 324 static __inline void 325 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 326 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 327 int tx) 328 { 329 struct bwi_desc32 *desc = &desc_array[desc_idx]; 330 uint32_t ctrl, addr, addr_hi, addr_lo; 331 332 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 333 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 334 335 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 336 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 337 338 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 339 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 340 if (desc_idx == ndesc - 1) 341 ctrl |= BWI_DESC32_C_EOR; 342 if (tx) { 343 /* XXX */ 344 ctrl |= BWI_DESC32_C_FRAME_START | 345 BWI_DESC32_C_FRAME_END | 346 BWI_DESC32_C_INTR; 347 } 348 349 desc->addr = htole32(addr); 350 desc->ctrl = htole32(ctrl); 351 } 352 353 int 354 bwi_attach(struct bwi_softc *sc) 355 { 356 struct ieee80211com *ic = &sc->sc_ic; 357 device_t dev = sc->sc_dev; 358 struct bwi_mac *mac; 359 struct bwi_phy *phy; 360 int i, error; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 373 mbufq_init(&sc->sc_snd, ifqmaxlen); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_ticks = ticks - sc->sc_led_idle; 381 sc->sc_led_blink = 1; 382 sc->sc_txpwr_calib = 1; 383 #ifdef BWI_DEBUG 384 sc->sc_debug = bwi_debug; 385 #endif 386 bwi_power_on(sc, 1); 387 388 error = bwi_bbp_attach(sc); 389 if (error) 390 goto fail; 391 392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 393 if (error) 394 goto fail; 395 396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 397 error = bwi_set_clock_delay(sc); 398 if (error) 399 goto fail; 400 401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 402 if (error) 403 goto fail; 404 405 error = bwi_get_pwron_delay(sc); 406 if (error) 407 goto fail; 408 } 409 410 error = bwi_bus_attach(sc); 411 if (error) 412 goto fail; 413 414 bwi_get_card_flags(sc); 415 416 bwi_led_attach(sc); 417 418 for (i = 0; i < sc->sc_nmac; ++i) { 419 struct bwi_regwin *old; 420 421 mac = &sc->sc_mac[i]; 422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 423 if (error) 424 goto fail; 425 426 error = bwi_mac_lateattach(mac); 427 if (error) 428 goto fail; 429 430 error = bwi_regwin_switch(sc, old, NULL); 431 if (error) 432 goto fail; 433 } 434 435 /* 436 * XXX First MAC is known to exist 437 * TODO2 438 */ 439 mac = &sc->sc_mac[0]; 440 phy = &mac->mac_phy; 441 442 bwi_bbp_power_off(sc); 443 444 error = bwi_dma_alloc(sc); 445 if (error) 446 goto fail; 447 448 error = bwi_mac_fw_alloc(mac); 449 if (error) 450 goto fail; 451 452 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 453 454 /* 455 * Setup ratesets, phytype, channels and get MAC address 456 */ 457 if (phy->phy_mode == IEEE80211_MODE_11B || 458 phy->phy_mode == IEEE80211_MODE_11G) { 459 if (phy->phy_mode == IEEE80211_MODE_11B) { 460 ic->ic_phytype = IEEE80211_T_DS; 461 } else { 462 ic->ic_phytype = IEEE80211_T_OFDM; 463 } 464 465 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 466 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 467 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 469 device_printf(dev, 470 "invalid MAC address: %6D\n", 471 ic->ic_macaddr, ":"); 472 } 473 } 474 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 475 /* TODO:11A */ 476 error = ENXIO; 477 goto fail; 478 } else { 479 panic("unknown phymode %d\n", phy->phy_mode); 480 } 481 482 /* Get locale */ 483 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 484 BWI_SPROM_CARD_INFO_LOCALE); 485 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 486 /* XXX use locale */ 487 488 ic->ic_softc = sc; 489 490 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 491 ic->ic_channels); 492 493 ic->ic_name = device_get_nameunit(dev); 494 ic->ic_caps = IEEE80211_C_STA | 495 IEEE80211_C_SHSLOT | 496 IEEE80211_C_SHPREAMBLE | 497 IEEE80211_C_WPA | 498 IEEE80211_C_BGSCAN | 499 IEEE80211_C_MONITOR; 500 ic->ic_opmode = IEEE80211_M_STA; 501 ieee80211_ifattach(ic); 502 503 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 504 505 /* override default methods */ 506 ic->ic_vap_create = bwi_vap_create; 507 ic->ic_vap_delete = bwi_vap_delete; 508 ic->ic_raw_xmit = bwi_raw_xmit; 509 ic->ic_updateslot = bwi_updateslot; 510 ic->ic_scan_start = bwi_scan_start; 511 ic->ic_scan_end = bwi_scan_end; 512 ic->ic_getradiocaps = bwi_getradiocaps; 513 ic->ic_set_channel = bwi_set_channel; 514 ic->ic_transmit = bwi_transmit; 515 ic->ic_parent = bwi_parent; 516 517 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 518 519 ieee80211_radiotap_attach(ic, 520 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 521 BWI_TX_RADIOTAP_PRESENT, 522 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 523 BWI_RX_RADIOTAP_PRESENT); 524 525 /* 526 * Add sysctl nodes 527 */ 528 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 529 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 530 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 531 "Firmware version"); 532 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 534 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 535 "# ticks before LED enters idle state"); 536 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 538 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 539 "Allow LED to blink"); 540 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 542 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 543 "Enable software TX power calibration"); 544 #ifdef BWI_DEBUG 545 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 546 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 547 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 548 #endif 549 if (bootverbose) 550 ieee80211_announce(ic); 551 552 return (0); 553 fail: 554 BWI_LOCK_DESTROY(sc); 555 return (error); 556 } 557 558 int 559 bwi_detach(struct bwi_softc *sc) 560 { 561 struct ieee80211com *ic = &sc->sc_ic; 562 int i; 563 564 bwi_stop(sc, 1); 565 callout_drain(&sc->sc_led_blink_ch); 566 callout_drain(&sc->sc_calib_ch); 567 callout_drain(&sc->sc_watchdog_timer); 568 ieee80211_ifdetach(ic); 569 570 for (i = 0; i < sc->sc_nmac; ++i) 571 bwi_mac_detach(&sc->sc_mac[i]); 572 bwi_dma_free(sc); 573 taskqueue_free(sc->sc_tq); 574 mbufq_drain(&sc->sc_snd); 575 576 BWI_LOCK_DESTROY(sc); 577 578 return (0); 579 } 580 581 static struct ieee80211vap * 582 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 583 enum ieee80211_opmode opmode, int flags, 584 const uint8_t bssid[IEEE80211_ADDR_LEN], 585 const uint8_t mac[IEEE80211_ADDR_LEN]) 586 { 587 struct bwi_vap *bvp; 588 struct ieee80211vap *vap; 589 590 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 591 return NULL; 592 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 593 vap = &bvp->bv_vap; 594 /* enable s/w bmiss handling for sta mode */ 595 ieee80211_vap_setup(ic, vap, name, unit, opmode, 596 flags | IEEE80211_CLONE_NOBEACONS, bssid); 597 598 /* override default methods */ 599 bvp->bv_newstate = vap->iv_newstate; 600 vap->iv_newstate = bwi_newstate; 601 #if 0 602 vap->iv_update_beacon = bwi_beacon_update; 603 #endif 604 ieee80211_ratectl_init(vap); 605 606 /* complete setup */ 607 ieee80211_vap_attach(vap, ieee80211_media_change, 608 ieee80211_media_status, mac); 609 ic->ic_opmode = opmode; 610 return vap; 611 } 612 613 static void 614 bwi_vap_delete(struct ieee80211vap *vap) 615 { 616 struct bwi_vap *bvp = BWI_VAP(vap); 617 618 ieee80211_ratectl_deinit(vap); 619 ieee80211_vap_detach(vap); 620 free(bvp, M_80211_VAP); 621 } 622 623 void 624 bwi_suspend(struct bwi_softc *sc) 625 { 626 bwi_stop(sc, 1); 627 } 628 629 void 630 bwi_resume(struct bwi_softc *sc) 631 { 632 633 if (sc->sc_ic.ic_nrunning > 0) 634 bwi_init(sc); 635 } 636 637 int 638 bwi_shutdown(struct bwi_softc *sc) 639 { 640 bwi_stop(sc, 1); 641 return 0; 642 } 643 644 static void 645 bwi_power_on(struct bwi_softc *sc, int with_pll) 646 { 647 uint32_t gpio_in, gpio_out, gpio_en; 648 uint16_t status; 649 650 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 651 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 652 goto back; 653 654 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 655 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 656 657 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 658 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 659 if (with_pll) { 660 /* Turn off PLL first */ 661 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 662 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 663 } 664 665 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 666 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 667 DELAY(1000); 668 669 if (with_pll) { 670 /* Turn on PLL */ 671 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 672 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 673 DELAY(5000); 674 } 675 676 back: 677 /* Clear "Signaled Target Abort" */ 678 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 679 status &= ~PCIM_STATUS_STABORT; 680 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 681 } 682 683 static int 684 bwi_power_off(struct bwi_softc *sc, int with_pll) 685 { 686 uint32_t gpio_out, gpio_en; 687 688 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 689 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 690 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 691 692 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 693 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 694 if (with_pll) { 695 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 696 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 697 } 698 699 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 700 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 701 return 0; 702 } 703 704 int 705 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 706 struct bwi_regwin **old_rw) 707 { 708 int error; 709 710 if (old_rw != NULL) 711 *old_rw = NULL; 712 713 if (!BWI_REGWIN_EXIST(rw)) 714 return EINVAL; 715 716 if (sc->sc_cur_regwin != rw) { 717 error = bwi_regwin_select(sc, rw->rw_id); 718 if (error) { 719 device_printf(sc->sc_dev, "can't select regwin %d\n", 720 rw->rw_id); 721 return error; 722 } 723 } 724 725 if (old_rw != NULL) 726 *old_rw = sc->sc_cur_regwin; 727 sc->sc_cur_regwin = rw; 728 return 0; 729 } 730 731 static int 732 bwi_regwin_select(struct bwi_softc *sc, int id) 733 { 734 uint32_t win = BWI_PCIM_REGWIN(id); 735 int i; 736 737 #define RETRY_MAX 50 738 for (i = 0; i < RETRY_MAX; ++i) { 739 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 740 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 741 return 0; 742 DELAY(10); 743 } 744 #undef RETRY_MAX 745 746 return ENXIO; 747 } 748 749 static void 750 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 751 { 752 uint32_t val; 753 754 val = CSR_READ_4(sc, BWI_ID_HI); 755 *type = BWI_ID_HI_REGWIN_TYPE(val); 756 *rev = BWI_ID_HI_REGWIN_REV(val); 757 758 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 759 "vendor 0x%04x\n", *type, *rev, 760 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 761 } 762 763 static int 764 bwi_bbp_attach(struct bwi_softc *sc) 765 { 766 uint16_t bbp_id, rw_type; 767 uint8_t rw_rev; 768 uint32_t info; 769 int error, nregwin, i; 770 771 /* 772 * Get 0th regwin information 773 * NOTE: 0th regwin should exist 774 */ 775 error = bwi_regwin_select(sc, 0); 776 if (error) { 777 device_printf(sc->sc_dev, "can't select regwin 0\n"); 778 return error; 779 } 780 bwi_regwin_info(sc, &rw_type, &rw_rev); 781 782 /* 783 * Find out BBP id 784 */ 785 bbp_id = 0; 786 info = 0; 787 if (rw_type == BWI_REGWIN_T_COM) { 788 info = CSR_READ_4(sc, BWI_INFO); 789 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 790 791 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 792 793 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 794 } else { 795 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 796 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 797 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 798 bbp_id = bwi_bbpid_map[i].bbp_id; 799 break; 800 } 801 } 802 if (bbp_id == 0) { 803 device_printf(sc->sc_dev, "no BBP id for device id " 804 "0x%04x\n", sc->sc_pci_did); 805 return ENXIO; 806 } 807 808 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 809 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 810 } 811 812 /* 813 * Find out number of regwins 814 */ 815 nregwin = 0; 816 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 817 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 818 } else { 819 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 820 if (bwi_regwin_count[i].bbp_id == bbp_id) { 821 nregwin = bwi_regwin_count[i].nregwin; 822 break; 823 } 824 } 825 if (nregwin == 0) { 826 device_printf(sc->sc_dev, "no number of win for " 827 "BBP id 0x%04x\n", bbp_id); 828 return ENXIO; 829 } 830 } 831 832 /* Record BBP id/rev for later using */ 833 sc->sc_bbp_id = bbp_id; 834 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 835 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 836 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 837 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 838 839 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 840 nregwin, sc->sc_cap); 841 842 /* 843 * Create rest of the regwins 844 */ 845 846 /* Don't re-create common regwin, if it is already created */ 847 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 848 849 for (; i < nregwin; ++i) { 850 /* 851 * Get regwin information 852 */ 853 error = bwi_regwin_select(sc, i); 854 if (error) { 855 device_printf(sc->sc_dev, 856 "can't select regwin %d\n", i); 857 return error; 858 } 859 bwi_regwin_info(sc, &rw_type, &rw_rev); 860 861 /* 862 * Try attach: 863 * 1) Bus (PCI/PCIE) regwin 864 * 2) MAC regwin 865 * Ignore rest types of regwin 866 */ 867 if (rw_type == BWI_REGWIN_T_BUSPCI || 868 rw_type == BWI_REGWIN_T_BUSPCIE) { 869 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 870 device_printf(sc->sc_dev, 871 "bus regwin already exists\n"); 872 } else { 873 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 874 rw_type, rw_rev); 875 } 876 } else if (rw_type == BWI_REGWIN_T_MAC) { 877 /* XXX ignore return value */ 878 bwi_mac_attach(sc, i, rw_rev); 879 } 880 } 881 882 /* At least one MAC shold exist */ 883 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 884 device_printf(sc->sc_dev, "no MAC was found\n"); 885 return ENXIO; 886 } 887 KASSERT(sc->sc_nmac > 0, ("no mac's")); 888 889 /* Bus regwin must exist */ 890 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 891 device_printf(sc->sc_dev, "no bus regwin was found\n"); 892 return ENXIO; 893 } 894 895 /* Start with first MAC */ 896 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 897 if (error) 898 return error; 899 900 return 0; 901 } 902 903 int 904 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 905 { 906 struct bwi_regwin *old, *bus; 907 uint32_t val; 908 int error; 909 910 bus = &sc->sc_bus_regwin; 911 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 912 913 /* 914 * Tell bus to generate requested interrupts 915 */ 916 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 917 /* 918 * NOTE: Read BWI_FLAGS from MAC regwin 919 */ 920 val = CSR_READ_4(sc, BWI_FLAGS); 921 922 error = bwi_regwin_switch(sc, bus, &old); 923 if (error) 924 return error; 925 926 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 927 } else { 928 uint32_t mac_mask; 929 930 mac_mask = 1 << mac->mac_id; 931 932 error = bwi_regwin_switch(sc, bus, &old); 933 if (error) 934 return error; 935 936 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 937 val |= mac_mask << 8; 938 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 939 } 940 941 if (sc->sc_flags & BWI_F_BUS_INITED) 942 goto back; 943 944 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 945 /* 946 * Enable prefetch and burst 947 */ 948 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 949 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 950 951 if (bus->rw_rev < 5) { 952 struct bwi_regwin *com = &sc->sc_com_regwin; 953 954 /* 955 * Configure timeouts for bus operation 956 */ 957 958 /* 959 * Set service timeout and request timeout 960 */ 961 CSR_SETBITS_4(sc, BWI_CONF_LO, 962 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 963 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 964 965 /* 966 * If there is common regwin, we switch to that regwin 967 * and switch back to bus regwin once we have done. 968 */ 969 if (BWI_REGWIN_EXIST(com)) { 970 error = bwi_regwin_switch(sc, com, NULL); 971 if (error) 972 return error; 973 } 974 975 /* Let bus know what we have changed */ 976 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 977 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 978 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 979 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 980 981 if (BWI_REGWIN_EXIST(com)) { 982 error = bwi_regwin_switch(sc, bus, NULL); 983 if (error) 984 return error; 985 } 986 } else if (bus->rw_rev >= 11) { 987 /* 988 * Enable memory read multiple 989 */ 990 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 991 } 992 } else { 993 /* TODO:PCIE */ 994 } 995 996 sc->sc_flags |= BWI_F_BUS_INITED; 997 back: 998 return bwi_regwin_switch(sc, old, NULL); 999 } 1000 1001 static void 1002 bwi_get_card_flags(struct bwi_softc *sc) 1003 { 1004 #define PCI_VENDOR_APPLE 0x106b 1005 #define PCI_VENDOR_DELL 0x1028 1006 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1007 if (sc->sc_card_flags == 0xffff) 1008 sc->sc_card_flags = 0; 1009 1010 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1011 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1012 sc->sc_pci_revid == 0x74) 1013 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1014 1015 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1016 sc->sc_pci_subdid == 0x4e && /* XXX */ 1017 sc->sc_pci_revid > 0x40) 1018 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1019 1020 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1021 #undef PCI_VENDOR_DELL 1022 #undef PCI_VENDOR_APPLE 1023 } 1024 1025 static void 1026 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1027 { 1028 int i; 1029 1030 for (i = 0; i < 3; ++i) { 1031 *((uint16_t *)eaddr + i) = 1032 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1033 } 1034 } 1035 1036 static void 1037 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1038 { 1039 struct bwi_regwin *com; 1040 uint32_t val; 1041 u_int div; 1042 int src; 1043 1044 bzero(freq, sizeof(*freq)); 1045 com = &sc->sc_com_regwin; 1046 1047 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1048 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1049 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1050 1051 /* 1052 * Calculate clock frequency 1053 */ 1054 src = -1; 1055 div = 0; 1056 if (com->rw_rev < 6) { 1057 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1058 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1059 src = BWI_CLKSRC_PCI; 1060 div = 64; 1061 } else { 1062 src = BWI_CLKSRC_CS_OSC; 1063 div = 32; 1064 } 1065 } else if (com->rw_rev < 10) { 1066 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1067 1068 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1069 if (src == BWI_CLKSRC_LP_OSC) { 1070 div = 1; 1071 } else { 1072 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1073 1074 /* Unknown source */ 1075 if (src >= BWI_CLKSRC_MAX) 1076 src = BWI_CLKSRC_CS_OSC; 1077 } 1078 } else { 1079 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1080 1081 src = BWI_CLKSRC_CS_OSC; 1082 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1083 } 1084 1085 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1086 KASSERT(div != 0, ("div zero")); 1087 1088 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1089 src == BWI_CLKSRC_PCI ? "PCI" : 1090 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1091 1092 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1093 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1094 1095 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1096 freq->clkfreq_min, freq->clkfreq_max); 1097 } 1098 1099 static int 1100 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1101 { 1102 struct bwi_regwin *old, *com; 1103 uint32_t clk_ctrl, clk_src; 1104 int error, pwr_off = 0; 1105 1106 com = &sc->sc_com_regwin; 1107 if (!BWI_REGWIN_EXIST(com)) 1108 return 0; 1109 1110 if (com->rw_rev >= 10 || com->rw_rev < 6) 1111 return 0; 1112 1113 /* 1114 * For common regwin whose rev is [6, 10), the chip 1115 * must be capable to change clock mode. 1116 */ 1117 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1118 return 0; 1119 1120 error = bwi_regwin_switch(sc, com, &old); 1121 if (error) 1122 return error; 1123 1124 if (clk_mode == BWI_CLOCK_MODE_FAST) 1125 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1126 1127 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1128 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1129 1130 switch (clk_mode) { 1131 case BWI_CLOCK_MODE_FAST: 1132 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1133 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1134 break; 1135 case BWI_CLOCK_MODE_SLOW: 1136 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1137 break; 1138 case BWI_CLOCK_MODE_DYN: 1139 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1140 BWI_CLOCK_CTRL_IGNPLL | 1141 BWI_CLOCK_CTRL_NODYN); 1142 if (clk_src != BWI_CLKSRC_CS_OSC) { 1143 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1144 pwr_off = 1; 1145 } 1146 break; 1147 } 1148 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1149 1150 if (pwr_off) 1151 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1152 1153 return bwi_regwin_switch(sc, old, NULL); 1154 } 1155 1156 static int 1157 bwi_set_clock_delay(struct bwi_softc *sc) 1158 { 1159 struct bwi_regwin *old, *com; 1160 int error; 1161 1162 com = &sc->sc_com_regwin; 1163 if (!BWI_REGWIN_EXIST(com)) 1164 return 0; 1165 1166 error = bwi_regwin_switch(sc, com, &old); 1167 if (error) 1168 return error; 1169 1170 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1171 if (sc->sc_bbp_rev == 0) 1172 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1173 else if (sc->sc_bbp_rev == 1) 1174 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1175 } 1176 1177 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1178 if (com->rw_rev >= 10) { 1179 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1180 } else { 1181 struct bwi_clock_freq freq; 1182 1183 bwi_get_clock_freq(sc, &freq); 1184 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1185 howmany(freq.clkfreq_max * 150, 1000000)); 1186 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1187 howmany(freq.clkfreq_max * 15, 1000000)); 1188 } 1189 } 1190 1191 return bwi_regwin_switch(sc, old, NULL); 1192 } 1193 1194 static void 1195 bwi_init(struct bwi_softc *sc) 1196 { 1197 struct ieee80211com *ic = &sc->sc_ic; 1198 1199 BWI_LOCK(sc); 1200 bwi_init_statechg(sc, 1); 1201 BWI_UNLOCK(sc); 1202 1203 if (sc->sc_flags & BWI_F_RUNNING) 1204 ieee80211_start_all(ic); /* start all vap's */ 1205 } 1206 1207 static void 1208 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1209 { 1210 struct bwi_mac *mac; 1211 int error; 1212 1213 BWI_ASSERT_LOCKED(sc); 1214 1215 bwi_stop_locked(sc, statechg); 1216 1217 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1218 1219 /* TODO: 2 MAC */ 1220 1221 mac = &sc->sc_mac[0]; 1222 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1223 if (error) { 1224 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1225 __func__, error); 1226 goto bad; 1227 } 1228 error = bwi_mac_init(mac); 1229 if (error) { 1230 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1231 __func__, error); 1232 goto bad; 1233 } 1234 1235 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1236 1237 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1238 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1239 1240 bwi_mac_reset_hwkeys(mac); 1241 1242 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1243 int i; 1244 1245 #define NRETRY 1000 1246 /* 1247 * Drain any possible pending TX status 1248 */ 1249 for (i = 0; i < NRETRY; ++i) { 1250 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1251 BWI_TXSTATUS0_VALID) == 0) 1252 break; 1253 CSR_READ_4(sc, BWI_TXSTATUS1); 1254 } 1255 if (i == NRETRY) 1256 device_printf(sc->sc_dev, 1257 "%s: can't drain TX status\n", __func__); 1258 #undef NRETRY 1259 } 1260 1261 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1262 bwi_mac_updateslot(mac, 1); 1263 1264 /* Start MAC */ 1265 error = bwi_mac_start(mac); 1266 if (error) { 1267 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1268 __func__, error); 1269 goto bad; 1270 } 1271 1272 /* Clear stop flag before enabling interrupt */ 1273 sc->sc_flags &= ~BWI_F_STOP; 1274 sc->sc_flags |= BWI_F_RUNNING; 1275 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1276 1277 /* Enable intrs */ 1278 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1279 return; 1280 bad: 1281 bwi_stop_locked(sc, 1); 1282 } 1283 1284 static void 1285 bwi_parent(struct ieee80211com *ic) 1286 { 1287 struct bwi_softc *sc = ic->ic_softc; 1288 int startall = 0; 1289 1290 BWI_LOCK(sc); 1291 if (ic->ic_nrunning > 0) { 1292 struct bwi_mac *mac; 1293 int promisc = -1; 1294 1295 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1296 ("current regwin type %d", 1297 sc->sc_cur_regwin->rw_type)); 1298 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1299 1300 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1301 promisc = 1; 1302 sc->sc_flags |= BWI_F_PROMISC; 1303 } else if (ic->ic_promisc == 0 && 1304 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1305 promisc = 0; 1306 sc->sc_flags &= ~BWI_F_PROMISC; 1307 } 1308 1309 if (promisc >= 0) 1310 bwi_mac_set_promisc(mac, promisc); 1311 } 1312 if (ic->ic_nrunning > 0) { 1313 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1314 bwi_init_statechg(sc, 1); 1315 startall = 1; 1316 } 1317 } else if (sc->sc_flags & BWI_F_RUNNING) 1318 bwi_stop_locked(sc, 1); 1319 BWI_UNLOCK(sc); 1320 if (startall) 1321 ieee80211_start_all(ic); 1322 } 1323 1324 static int 1325 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1326 { 1327 struct bwi_softc *sc = ic->ic_softc; 1328 int error; 1329 1330 BWI_LOCK(sc); 1331 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1332 BWI_UNLOCK(sc); 1333 return (ENXIO); 1334 } 1335 error = mbufq_enqueue(&sc->sc_snd, m); 1336 if (error) { 1337 BWI_UNLOCK(sc); 1338 return (error); 1339 } 1340 bwi_start_locked(sc); 1341 BWI_UNLOCK(sc); 1342 return (0); 1343 } 1344 1345 static void 1346 bwi_start_locked(struct bwi_softc *sc) 1347 { 1348 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1349 struct ieee80211_frame *wh; 1350 struct ieee80211_node *ni; 1351 struct mbuf *m; 1352 int trans, idx; 1353 1354 BWI_ASSERT_LOCKED(sc); 1355 1356 trans = 0; 1357 idx = tbd->tbd_idx; 1358 1359 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1360 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1361 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1362 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1363 wh = mtod(m, struct ieee80211_frame *); 1364 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1365 ieee80211_crypto_encap(ni, m) == NULL) { 1366 if_inc_counter(ni->ni_vap->iv_ifp, 1367 IFCOUNTER_OERRORS, 1); 1368 ieee80211_free_node(ni); 1369 m_freem(m); 1370 continue; 1371 } 1372 if (bwi_encap(sc, idx, m, ni) != 0) { 1373 /* 'm' is freed in bwi_encap() if we reach here */ 1374 if (ni != NULL) { 1375 if_inc_counter(ni->ni_vap->iv_ifp, 1376 IFCOUNTER_OERRORS, 1); 1377 ieee80211_free_node(ni); 1378 } else 1379 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1380 continue; 1381 } 1382 trans = 1; 1383 tbd->tbd_used++; 1384 idx = (idx + 1) % BWI_TX_NDESC; 1385 } 1386 1387 tbd->tbd_idx = idx; 1388 if (trans) 1389 sc->sc_tx_timer = 5; 1390 } 1391 1392 static int 1393 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1394 const struct ieee80211_bpf_params *params) 1395 { 1396 struct ieee80211com *ic = ni->ni_ic; 1397 struct bwi_softc *sc = ic->ic_softc; 1398 /* XXX wme? */ 1399 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1400 int idx, error; 1401 1402 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1403 m_freem(m); 1404 return ENETDOWN; 1405 } 1406 1407 BWI_LOCK(sc); 1408 idx = tbd->tbd_idx; 1409 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1410 if (params == NULL) { 1411 /* 1412 * Legacy path; interpret frame contents to decide 1413 * precisely how to send the frame. 1414 */ 1415 error = bwi_encap(sc, idx, m, ni); 1416 } else { 1417 /* 1418 * Caller supplied explicit parameters to use in 1419 * sending the frame. 1420 */ 1421 error = bwi_encap_raw(sc, idx, m, ni, params); 1422 } 1423 if (error == 0) { 1424 tbd->tbd_used++; 1425 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1426 sc->sc_tx_timer = 5; 1427 } 1428 BWI_UNLOCK(sc); 1429 return error; 1430 } 1431 1432 static void 1433 bwi_watchdog(void *arg) 1434 { 1435 struct bwi_softc *sc; 1436 1437 sc = arg; 1438 BWI_ASSERT_LOCKED(sc); 1439 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1440 device_printf(sc->sc_dev, "watchdog timeout\n"); 1441 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1442 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1443 } 1444 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1445 } 1446 1447 static void 1448 bwi_stop(struct bwi_softc *sc, int statechg) 1449 { 1450 BWI_LOCK(sc); 1451 bwi_stop_locked(sc, statechg); 1452 BWI_UNLOCK(sc); 1453 } 1454 1455 static void 1456 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1457 { 1458 struct bwi_mac *mac; 1459 int i, error, pwr_off = 0; 1460 1461 BWI_ASSERT_LOCKED(sc); 1462 1463 callout_stop(&sc->sc_calib_ch); 1464 callout_stop(&sc->sc_led_blink_ch); 1465 sc->sc_led_blinking = 0; 1466 sc->sc_flags |= BWI_F_STOP; 1467 1468 if (sc->sc_flags & BWI_F_RUNNING) { 1469 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1470 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1471 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1472 1473 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1474 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1475 bwi_mac_stop(mac); 1476 } 1477 1478 for (i = 0; i < sc->sc_nmac; ++i) { 1479 struct bwi_regwin *old_rw; 1480 1481 mac = &sc->sc_mac[i]; 1482 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1483 continue; 1484 1485 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1486 if (error) 1487 continue; 1488 1489 bwi_mac_shutdown(mac); 1490 pwr_off = 1; 1491 1492 bwi_regwin_switch(sc, old_rw, NULL); 1493 } 1494 1495 if (pwr_off) 1496 bwi_bbp_power_off(sc); 1497 1498 sc->sc_tx_timer = 0; 1499 callout_stop(&sc->sc_watchdog_timer); 1500 sc->sc_flags &= ~BWI_F_RUNNING; 1501 } 1502 1503 void 1504 bwi_intr(void *xsc) 1505 { 1506 struct epoch_tracker et; 1507 struct bwi_softc *sc = xsc; 1508 struct bwi_mac *mac; 1509 uint32_t intr_status; 1510 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1511 int i, txrx_error, tx = 0, rx_data = -1; 1512 1513 BWI_LOCK(sc); 1514 1515 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1516 (sc->sc_flags & BWI_F_STOP)) { 1517 BWI_UNLOCK(sc); 1518 return; 1519 } 1520 /* 1521 * Get interrupt status 1522 */ 1523 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1524 if (intr_status == 0xffffffff) { /* Not for us */ 1525 BWI_UNLOCK(sc); 1526 return; 1527 } 1528 1529 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1530 1531 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1532 if (intr_status == 0) { /* Nothing is interesting */ 1533 BWI_UNLOCK(sc); 1534 return; 1535 } 1536 1537 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1538 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1539 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1540 1541 txrx_error = 0; 1542 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1543 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1544 uint32_t mask; 1545 1546 if (BWI_TXRX_IS_RX(i)) 1547 mask = BWI_TXRX_RX_INTRS; 1548 else 1549 mask = BWI_TXRX_TX_INTRS; 1550 1551 txrx_intr_status[i] = 1552 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1553 1554 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1555 i, txrx_intr_status[i]); 1556 1557 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1558 device_printf(sc->sc_dev, 1559 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1560 __func__, i, txrx_intr_status[i]); 1561 txrx_error = 1; 1562 } 1563 } 1564 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1565 1566 /* 1567 * Acknowledge interrupt 1568 */ 1569 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1570 1571 for (i = 0; i < BWI_TXRX_NRING; ++i) 1572 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1573 1574 /* Disable all interrupts */ 1575 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1576 1577 /* 1578 * http://bcm-specs.sipsolutions.net/Interrupts 1579 * Says for this bit (0x800): 1580 * "Fatal Error 1581 * 1582 * We got this one while testing things when by accident the 1583 * template ram wasn't set to big endian when it should have 1584 * been after writing the initial values. It keeps on being 1585 * triggered, the only way to stop it seems to shut down the 1586 * chip." 1587 * 1588 * Suggesting that we should never get it and if we do we're not 1589 * feeding TX packets into the MAC correctly if we do... Apparently, 1590 * it is valid only on mac version 5 and higher, but I couldn't 1591 * find a reference for that... Since I see them from time to time 1592 * on my card, this suggests an error in the tx path still... 1593 */ 1594 if (intr_status & BWI_INTR_PHY_TXERR) { 1595 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1596 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1597 __func__); 1598 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1599 BWI_UNLOCK(sc); 1600 return; 1601 } 1602 } 1603 1604 if (txrx_error) { 1605 /* TODO: reset device */ 1606 } 1607 1608 if (intr_status & BWI_INTR_TBTT) 1609 bwi_mac_config_ps(mac); 1610 1611 if (intr_status & BWI_INTR_EO_ATIM) 1612 device_printf(sc->sc_dev, "EO_ATIM\n"); 1613 1614 if (intr_status & BWI_INTR_PMQ) { 1615 for (;;) { 1616 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1617 break; 1618 } 1619 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1620 } 1621 1622 if (intr_status & BWI_INTR_NOISE) 1623 device_printf(sc->sc_dev, "intr noise\n"); 1624 1625 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1626 NET_EPOCH_ENTER(et); 1627 rx_data = sc->sc_rxeof(sc); 1628 NET_EPOCH_EXIT(et); 1629 if (sc->sc_flags & BWI_F_STOP) { 1630 BWI_UNLOCK(sc); 1631 return; 1632 } 1633 } 1634 1635 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1636 sc->sc_txeof_status(sc); 1637 tx = 1; 1638 } 1639 1640 if (intr_status & BWI_INTR_TX_DONE) { 1641 bwi_txeof(sc); 1642 tx = 1; 1643 } 1644 1645 /* Re-enable interrupts */ 1646 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1647 1648 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1649 int evt = BWI_LED_EVENT_NONE; 1650 1651 if (tx && rx_data > 0) { 1652 if (sc->sc_rx_rate > sc->sc_tx_rate) 1653 evt = BWI_LED_EVENT_RX; 1654 else 1655 evt = BWI_LED_EVENT_TX; 1656 } else if (tx) { 1657 evt = BWI_LED_EVENT_TX; 1658 } else if (rx_data > 0) { 1659 evt = BWI_LED_EVENT_RX; 1660 } else if (rx_data == 0) { 1661 evt = BWI_LED_EVENT_POLL; 1662 } 1663 1664 if (evt != BWI_LED_EVENT_NONE) 1665 bwi_led_event(sc, evt); 1666 } 1667 1668 BWI_UNLOCK(sc); 1669 } 1670 1671 static void 1672 bwi_scan_start(struct ieee80211com *ic) 1673 { 1674 struct bwi_softc *sc = ic->ic_softc; 1675 1676 BWI_LOCK(sc); 1677 /* Enable MAC beacon promiscuity */ 1678 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1679 BWI_UNLOCK(sc); 1680 } 1681 1682 static void 1683 bwi_getradiocaps(struct ieee80211com *ic, 1684 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1685 { 1686 struct bwi_softc *sc = ic->ic_softc; 1687 struct bwi_mac *mac; 1688 struct bwi_phy *phy; 1689 uint8_t bands[IEEE80211_MODE_BYTES]; 1690 1691 /* 1692 * XXX First MAC is known to exist 1693 * TODO2 1694 */ 1695 mac = &sc->sc_mac[0]; 1696 phy = &mac->mac_phy; 1697 1698 memset(bands, 0, sizeof(bands)); 1699 switch (phy->phy_mode) { 1700 case IEEE80211_MODE_11G: 1701 setbit(bands, IEEE80211_MODE_11G); 1702 /* FALLTHROUGH */ 1703 case IEEE80211_MODE_11B: 1704 setbit(bands, IEEE80211_MODE_11B); 1705 break; 1706 case IEEE80211_MODE_11A: 1707 /* TODO:11A */ 1708 setbit(bands, IEEE80211_MODE_11A); 1709 device_printf(sc->sc_dev, "no 11a support\n"); 1710 return; 1711 default: 1712 panic("unknown phymode %d\n", phy->phy_mode); 1713 } 1714 1715 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1716 } 1717 1718 static void 1719 bwi_set_channel(struct ieee80211com *ic) 1720 { 1721 struct bwi_softc *sc = ic->ic_softc; 1722 struct ieee80211_channel *c = ic->ic_curchan; 1723 struct bwi_mac *mac; 1724 1725 BWI_LOCK(sc); 1726 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1727 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1728 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1729 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1730 1731 sc->sc_rates = ieee80211_get_ratetable(c); 1732 BWI_UNLOCK(sc); 1733 } 1734 1735 static void 1736 bwi_scan_end(struct ieee80211com *ic) 1737 { 1738 struct bwi_softc *sc = ic->ic_softc; 1739 1740 BWI_LOCK(sc); 1741 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1742 BWI_UNLOCK(sc); 1743 } 1744 1745 static int 1746 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1747 { 1748 struct bwi_vap *bvp = BWI_VAP(vap); 1749 struct ieee80211com *ic= vap->iv_ic; 1750 struct bwi_softc *sc = ic->ic_softc; 1751 enum ieee80211_state ostate = vap->iv_state; 1752 struct bwi_mac *mac; 1753 int error; 1754 1755 BWI_LOCK(sc); 1756 1757 callout_stop(&sc->sc_calib_ch); 1758 1759 if (nstate == IEEE80211_S_INIT) 1760 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1761 1762 bwi_led_newstate(sc, nstate); 1763 1764 error = bvp->bv_newstate(vap, nstate, arg); 1765 if (error != 0) 1766 goto back; 1767 1768 /* 1769 * Clear the BSSID when we stop a STA 1770 */ 1771 if (vap->iv_opmode == IEEE80211_M_STA) { 1772 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1773 /* 1774 * Clear out the BSSID. If we reassociate to 1775 * the same AP, this will reinialize things 1776 * correctly... 1777 */ 1778 if (ic->ic_opmode == IEEE80211_M_STA && 1779 !(sc->sc_flags & BWI_F_STOP)) 1780 bwi_set_bssid(sc, bwi_zero_addr); 1781 } 1782 } 1783 1784 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1785 /* Nothing to do */ 1786 } else if (nstate == IEEE80211_S_RUN) { 1787 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1788 1789 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1790 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1791 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1792 1793 /* Initial TX power calibration */ 1794 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1795 #ifdef notyet 1796 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1797 #else 1798 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1799 #endif 1800 1801 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1802 } 1803 back: 1804 BWI_UNLOCK(sc); 1805 1806 return error; 1807 } 1808 1809 static int 1810 bwi_dma_alloc(struct bwi_softc *sc) 1811 { 1812 int error, i, has_txstats; 1813 bus_addr_t lowaddr = 0; 1814 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1815 uint32_t txrx_ctrl_step = 0; 1816 1817 has_txstats = 0; 1818 for (i = 0; i < sc->sc_nmac; ++i) { 1819 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1820 has_txstats = 1; 1821 break; 1822 } 1823 } 1824 1825 switch (sc->sc_bus_space) { 1826 case BWI_BUS_SPACE_30BIT: 1827 case BWI_BUS_SPACE_32BIT: 1828 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1829 lowaddr = BWI_BUS_SPACE_MAXADDR; 1830 else 1831 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1832 desc_sz = sizeof(struct bwi_desc32); 1833 txrx_ctrl_step = 0x20; 1834 1835 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1836 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1837 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1838 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1839 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1840 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1841 sc->sc_rxeof = bwi_rxeof32; 1842 sc->sc_start_tx = bwi_start_tx32; 1843 if (has_txstats) { 1844 sc->sc_init_txstats = bwi_init_txstats32; 1845 sc->sc_free_txstats = bwi_free_txstats32; 1846 sc->sc_txeof_status = bwi_txeof_status32; 1847 } 1848 break; 1849 1850 case BWI_BUS_SPACE_64BIT: 1851 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1852 desc_sz = sizeof(struct bwi_desc64); 1853 txrx_ctrl_step = 0x40; 1854 1855 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1856 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1857 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1858 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1859 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1860 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1861 sc->sc_rxeof = bwi_rxeof64; 1862 sc->sc_start_tx = bwi_start_tx64; 1863 if (has_txstats) { 1864 sc->sc_init_txstats = bwi_init_txstats64; 1865 sc->sc_free_txstats = bwi_free_txstats64; 1866 sc->sc_txeof_status = bwi_txeof_status64; 1867 } 1868 break; 1869 } 1870 1871 KASSERT(lowaddr != 0, ("lowaddr zero")); 1872 KASSERT(desc_sz != 0, ("desc_sz zero")); 1873 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1874 1875 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1876 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1877 1878 /* 1879 * Create top level DMA tag 1880 */ 1881 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1882 BWI_ALIGN, 0, /* alignment, bounds */ 1883 lowaddr, /* lowaddr */ 1884 BUS_SPACE_MAXADDR, /* highaddr */ 1885 NULL, NULL, /* filter, filterarg */ 1886 BUS_SPACE_MAXSIZE, /* maxsize */ 1887 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1888 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1889 0, /* flags */ 1890 NULL, NULL, /* lockfunc, lockarg */ 1891 &sc->sc_parent_dtag); 1892 if (error) { 1893 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1894 return error; 1895 } 1896 1897 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1898 1899 /* 1900 * Create TX ring DMA stuffs 1901 */ 1902 error = bus_dma_tag_create(sc->sc_parent_dtag, 1903 BWI_RING_ALIGN, 0, 1904 BUS_SPACE_MAXADDR, 1905 BUS_SPACE_MAXADDR, 1906 NULL, NULL, 1907 tx_ring_sz, 1908 1, 1909 tx_ring_sz, 1910 0, 1911 NULL, NULL, 1912 &sc->sc_txring_dtag); 1913 if (error) { 1914 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1915 return error; 1916 } 1917 1918 for (i = 0; i < BWI_TX_NRING; ++i) { 1919 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1920 &sc->sc_tx_rdata[i], tx_ring_sz, 1921 TXRX_CTRL(i)); 1922 if (error) { 1923 device_printf(sc->sc_dev, "%dth TX ring " 1924 "DMA alloc failed\n", i); 1925 return error; 1926 } 1927 } 1928 1929 /* 1930 * Create RX ring DMA stuffs 1931 */ 1932 error = bus_dma_tag_create(sc->sc_parent_dtag, 1933 BWI_RING_ALIGN, 0, 1934 BUS_SPACE_MAXADDR, 1935 BUS_SPACE_MAXADDR, 1936 NULL, NULL, 1937 rx_ring_sz, 1938 1, 1939 rx_ring_sz, 1940 0, 1941 NULL, NULL, 1942 &sc->sc_rxring_dtag); 1943 if (error) { 1944 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1945 return error; 1946 } 1947 1948 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1949 rx_ring_sz, TXRX_CTRL(0)); 1950 if (error) { 1951 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1952 return error; 1953 } 1954 1955 if (has_txstats) { 1956 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1957 if (error) { 1958 device_printf(sc->sc_dev, 1959 "TX stats DMA alloc failed\n"); 1960 return error; 1961 } 1962 } 1963 1964 #undef TXRX_CTRL 1965 1966 return bwi_dma_mbuf_create(sc); 1967 } 1968 1969 static void 1970 bwi_dma_free(struct bwi_softc *sc) 1971 { 1972 if (sc->sc_txring_dtag != NULL) { 1973 int i; 1974 1975 for (i = 0; i < BWI_TX_NRING; ++i) { 1976 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1977 1978 if (rd->rdata_desc != NULL) { 1979 bus_dmamap_unload(sc->sc_txring_dtag, 1980 rd->rdata_dmap); 1981 bus_dmamem_free(sc->sc_txring_dtag, 1982 rd->rdata_desc, 1983 rd->rdata_dmap); 1984 } 1985 } 1986 bus_dma_tag_destroy(sc->sc_txring_dtag); 1987 } 1988 1989 if (sc->sc_rxring_dtag != NULL) { 1990 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 1991 1992 if (rd->rdata_desc != NULL) { 1993 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 1994 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 1995 rd->rdata_dmap); 1996 } 1997 bus_dma_tag_destroy(sc->sc_rxring_dtag); 1998 } 1999 2000 bwi_dma_txstats_free(sc); 2001 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2002 2003 if (sc->sc_parent_dtag != NULL) 2004 bus_dma_tag_destroy(sc->sc_parent_dtag); 2005 } 2006 2007 static int 2008 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2009 struct bwi_ring_data *rd, bus_size_t size, 2010 uint32_t txrx_ctrl) 2011 { 2012 int error; 2013 2014 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2015 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2016 &rd->rdata_dmap); 2017 if (error) { 2018 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2019 return error; 2020 } 2021 2022 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2023 bwi_dma_ring_addr, &rd->rdata_paddr, 2024 BUS_DMA_NOWAIT); 2025 if (error) { 2026 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2027 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2028 rd->rdata_desc = NULL; 2029 return error; 2030 } 2031 2032 rd->rdata_txrx_ctrl = txrx_ctrl; 2033 return 0; 2034 } 2035 2036 static int 2037 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2038 bus_size_t desc_sz) 2039 { 2040 struct bwi_txstats_data *st; 2041 bus_size_t dma_size; 2042 int error; 2043 2044 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2045 if (st == NULL) { 2046 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2047 return ENOMEM; 2048 } 2049 sc->sc_txstats = st; 2050 2051 /* 2052 * Create TX stats descriptor DMA stuffs 2053 */ 2054 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2055 2056 error = bus_dma_tag_create(sc->sc_parent_dtag, 2057 BWI_RING_ALIGN, 2058 0, 2059 BUS_SPACE_MAXADDR, 2060 BUS_SPACE_MAXADDR, 2061 NULL, NULL, 2062 dma_size, 2063 1, 2064 dma_size, 2065 0, 2066 NULL, NULL, 2067 &st->stats_ring_dtag); 2068 if (error) { 2069 device_printf(sc->sc_dev, "can't create txstats ring " 2070 "DMA tag\n"); 2071 return error; 2072 } 2073 2074 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2075 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2076 &st->stats_ring_dmap); 2077 if (error) { 2078 device_printf(sc->sc_dev, "can't allocate txstats ring " 2079 "DMA mem\n"); 2080 bus_dma_tag_destroy(st->stats_ring_dtag); 2081 st->stats_ring_dtag = NULL; 2082 return error; 2083 } 2084 2085 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2086 st->stats_ring, dma_size, 2087 bwi_dma_ring_addr, &st->stats_ring_paddr, 2088 BUS_DMA_NOWAIT); 2089 if (error) { 2090 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2091 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2092 st->stats_ring_dmap); 2093 bus_dma_tag_destroy(st->stats_ring_dtag); 2094 st->stats_ring_dtag = NULL; 2095 return error; 2096 } 2097 2098 /* 2099 * Create TX stats DMA stuffs 2100 */ 2101 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2102 BWI_ALIGN); 2103 2104 error = bus_dma_tag_create(sc->sc_parent_dtag, 2105 BWI_ALIGN, 2106 0, 2107 BUS_SPACE_MAXADDR, 2108 BUS_SPACE_MAXADDR, 2109 NULL, NULL, 2110 dma_size, 2111 1, 2112 dma_size, 2113 0, 2114 NULL, NULL, 2115 &st->stats_dtag); 2116 if (error) { 2117 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2118 return error; 2119 } 2120 2121 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2122 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2123 &st->stats_dmap); 2124 if (error) { 2125 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2126 bus_dma_tag_destroy(st->stats_dtag); 2127 st->stats_dtag = NULL; 2128 return error; 2129 } 2130 2131 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2132 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2133 BUS_DMA_NOWAIT); 2134 if (error) { 2135 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2136 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2137 bus_dma_tag_destroy(st->stats_dtag); 2138 st->stats_dtag = NULL; 2139 return error; 2140 } 2141 2142 st->stats_ctrl_base = ctrl_base; 2143 return 0; 2144 } 2145 2146 static void 2147 bwi_dma_txstats_free(struct bwi_softc *sc) 2148 { 2149 struct bwi_txstats_data *st; 2150 2151 if (sc->sc_txstats == NULL) 2152 return; 2153 st = sc->sc_txstats; 2154 2155 if (st->stats_ring_dtag != NULL) { 2156 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2157 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2158 st->stats_ring_dmap); 2159 bus_dma_tag_destroy(st->stats_ring_dtag); 2160 } 2161 2162 if (st->stats_dtag != NULL) { 2163 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2164 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2165 bus_dma_tag_destroy(st->stats_dtag); 2166 } 2167 2168 free(st, M_DEVBUF); 2169 } 2170 2171 static void 2172 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2173 { 2174 KASSERT(nseg == 1, ("too many segments\n")); 2175 *((bus_addr_t *)arg) = seg->ds_addr; 2176 } 2177 2178 static int 2179 bwi_dma_mbuf_create(struct bwi_softc *sc) 2180 { 2181 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2182 int i, j, k, ntx, error; 2183 2184 /* 2185 * Create TX/RX mbuf DMA tag 2186 */ 2187 error = bus_dma_tag_create(sc->sc_parent_dtag, 2188 1, 2189 0, 2190 BUS_SPACE_MAXADDR, 2191 BUS_SPACE_MAXADDR, 2192 NULL, NULL, 2193 MCLBYTES, 2194 1, 2195 MCLBYTES, 2196 BUS_DMA_ALLOCNOW, 2197 NULL, NULL, 2198 &sc->sc_buf_dtag); 2199 if (error) { 2200 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2201 return error; 2202 } 2203 2204 ntx = 0; 2205 2206 /* 2207 * Create TX mbuf DMA map 2208 */ 2209 for (i = 0; i < BWI_TX_NRING; ++i) { 2210 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2211 2212 for (j = 0; j < BWI_TX_NDESC; ++j) { 2213 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2214 &tbd->tbd_buf[j].tb_dmap); 2215 if (error) { 2216 device_printf(sc->sc_dev, "can't create " 2217 "%dth tbd, %dth DMA map\n", i, j); 2218 2219 ntx = i; 2220 for (k = 0; k < j; ++k) { 2221 bus_dmamap_destroy(sc->sc_buf_dtag, 2222 tbd->tbd_buf[k].tb_dmap); 2223 } 2224 goto fail; 2225 } 2226 } 2227 } 2228 ntx = BWI_TX_NRING; 2229 2230 /* 2231 * Create RX mbuf DMA map and a spare DMA map 2232 */ 2233 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2234 &rbd->rbd_tmp_dmap); 2235 if (error) { 2236 device_printf(sc->sc_dev, 2237 "can't create spare RX buf DMA map\n"); 2238 goto fail; 2239 } 2240 2241 for (j = 0; j < BWI_RX_NDESC; ++j) { 2242 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2243 &rbd->rbd_buf[j].rb_dmap); 2244 if (error) { 2245 device_printf(sc->sc_dev, "can't create %dth " 2246 "RX buf DMA map\n", j); 2247 2248 for (k = 0; k < j; ++k) { 2249 bus_dmamap_destroy(sc->sc_buf_dtag, 2250 rbd->rbd_buf[j].rb_dmap); 2251 } 2252 bus_dmamap_destroy(sc->sc_buf_dtag, 2253 rbd->rbd_tmp_dmap); 2254 goto fail; 2255 } 2256 } 2257 2258 return 0; 2259 fail: 2260 bwi_dma_mbuf_destroy(sc, ntx, 0); 2261 return error; 2262 } 2263 2264 static void 2265 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2266 { 2267 int i, j; 2268 2269 if (sc->sc_buf_dtag == NULL) 2270 return; 2271 2272 for (i = 0; i < ntx; ++i) { 2273 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2274 2275 for (j = 0; j < BWI_TX_NDESC; ++j) { 2276 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2277 2278 if (tb->tb_mbuf != NULL) { 2279 bus_dmamap_unload(sc->sc_buf_dtag, 2280 tb->tb_dmap); 2281 m_freem(tb->tb_mbuf); 2282 } 2283 if (tb->tb_ni != NULL) 2284 ieee80211_free_node(tb->tb_ni); 2285 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2286 } 2287 } 2288 2289 if (nrx) { 2290 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2291 2292 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2293 for (j = 0; j < BWI_RX_NDESC; ++j) { 2294 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2295 2296 if (rb->rb_mbuf != NULL) { 2297 bus_dmamap_unload(sc->sc_buf_dtag, 2298 rb->rb_dmap); 2299 m_freem(rb->rb_mbuf); 2300 } 2301 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2302 } 2303 } 2304 2305 bus_dma_tag_destroy(sc->sc_buf_dtag); 2306 sc->sc_buf_dtag = NULL; 2307 } 2308 2309 static void 2310 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2311 { 2312 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2313 } 2314 2315 static void 2316 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2317 { 2318 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2319 } 2320 2321 static int 2322 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2323 { 2324 struct bwi_ring_data *rd; 2325 struct bwi_txbuf_data *tbd; 2326 uint32_t val, addr_hi, addr_lo; 2327 2328 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2329 rd = &sc->sc_tx_rdata[ring_idx]; 2330 tbd = &sc->sc_tx_bdata[ring_idx]; 2331 2332 tbd->tbd_idx = 0; 2333 tbd->tbd_used = 0; 2334 2335 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2336 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2337 BUS_DMASYNC_PREWRITE); 2338 2339 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2340 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2341 2342 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2343 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2344 BWI_TXRX32_RINGINFO_FUNC_MASK); 2345 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2346 2347 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2348 BWI_TXRX32_CTRL_ENABLE; 2349 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2350 2351 return 0; 2352 } 2353 2354 static void 2355 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2356 bus_addr_t paddr, int hdr_size, int ndesc) 2357 { 2358 uint32_t val, addr_hi, addr_lo; 2359 2360 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2361 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2362 2363 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2364 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2365 BWI_TXRX32_RINGINFO_FUNC_MASK); 2366 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2367 2368 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2369 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2370 BWI_TXRX32_CTRL_ENABLE; 2371 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2372 2373 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2374 (ndesc - 1) * sizeof(struct bwi_desc32)); 2375 } 2376 2377 static int 2378 bwi_init_rx_ring32(struct bwi_softc *sc) 2379 { 2380 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2381 int i, error; 2382 2383 sc->sc_rx_bdata.rbd_idx = 0; 2384 2385 for (i = 0; i < BWI_RX_NDESC; ++i) { 2386 error = bwi_newbuf(sc, i, 1); 2387 if (error) { 2388 device_printf(sc->sc_dev, 2389 "can't allocate %dth RX buffer\n", i); 2390 return error; 2391 } 2392 } 2393 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2394 BUS_DMASYNC_PREWRITE); 2395 2396 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2397 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2398 return 0; 2399 } 2400 2401 static int 2402 bwi_init_txstats32(struct bwi_softc *sc) 2403 { 2404 struct bwi_txstats_data *st = sc->sc_txstats; 2405 bus_addr_t stats_paddr; 2406 int i; 2407 2408 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2409 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2410 2411 st->stats_idx = 0; 2412 2413 stats_paddr = st->stats_paddr; 2414 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2415 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2416 stats_paddr, sizeof(struct bwi_txstats), 0); 2417 stats_paddr += sizeof(struct bwi_txstats); 2418 } 2419 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2420 BUS_DMASYNC_PREWRITE); 2421 2422 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2423 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2424 return 0; 2425 } 2426 2427 static void 2428 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2429 int buf_len) 2430 { 2431 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2432 2433 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2434 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2435 paddr, buf_len, 0); 2436 } 2437 2438 static void 2439 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2440 int buf_idx, bus_addr_t paddr, int buf_len) 2441 { 2442 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2443 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2444 paddr, buf_len, 1); 2445 } 2446 2447 static int 2448 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2449 { 2450 /* TODO:64 */ 2451 return EOPNOTSUPP; 2452 } 2453 2454 static int 2455 bwi_init_rx_ring64(struct bwi_softc *sc) 2456 { 2457 /* TODO:64 */ 2458 return EOPNOTSUPP; 2459 } 2460 2461 static int 2462 bwi_init_txstats64(struct bwi_softc *sc) 2463 { 2464 /* TODO:64 */ 2465 return EOPNOTSUPP; 2466 } 2467 2468 static void 2469 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2470 int buf_len) 2471 { 2472 /* TODO:64 */ 2473 } 2474 2475 static void 2476 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2477 int buf_idx, bus_addr_t paddr, int buf_len) 2478 { 2479 /* TODO:64 */ 2480 } 2481 2482 static void 2483 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2484 bus_size_t mapsz __unused, int error) 2485 { 2486 if (!error) { 2487 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2488 *((bus_addr_t *)arg) = seg->ds_addr; 2489 } 2490 } 2491 2492 static int 2493 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2494 { 2495 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2496 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2497 struct bwi_rxbuf_hdr *hdr; 2498 bus_dmamap_t map; 2499 bus_addr_t paddr; 2500 struct mbuf *m; 2501 int error; 2502 2503 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2504 2505 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2506 if (m == NULL) { 2507 error = ENOBUFS; 2508 2509 /* 2510 * If the NIC is up and running, we need to: 2511 * - Clear RX buffer's header. 2512 * - Restore RX descriptor settings. 2513 */ 2514 if (init) 2515 return error; 2516 else 2517 goto back; 2518 } 2519 m->m_len = m->m_pkthdr.len = MCLBYTES; 2520 2521 /* 2522 * Try to load RX buf into temporary DMA map 2523 */ 2524 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2525 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2526 if (error) { 2527 m_freem(m); 2528 2529 /* 2530 * See the comment above 2531 */ 2532 if (init) 2533 return error; 2534 else 2535 goto back; 2536 } 2537 2538 if (!init) 2539 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2540 rxbuf->rb_mbuf = m; 2541 rxbuf->rb_paddr = paddr; 2542 2543 /* 2544 * Swap RX buf's DMA map with the loaded temporary one 2545 */ 2546 map = rxbuf->rb_dmap; 2547 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2548 rbd->rbd_tmp_dmap = map; 2549 2550 back: 2551 /* 2552 * Clear RX buf header 2553 */ 2554 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2555 bzero(hdr, sizeof(*hdr)); 2556 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2557 2558 /* 2559 * Setup RX buf descriptor 2560 */ 2561 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2562 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2563 return error; 2564 } 2565 2566 static void 2567 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2568 const uint8_t *addr) 2569 { 2570 int i; 2571 2572 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2573 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2574 2575 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2576 uint16_t addr_val; 2577 2578 addr_val = (uint16_t)addr[i * 2] | 2579 (((uint16_t)addr[(i * 2) + 1]) << 8); 2580 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2581 } 2582 } 2583 2584 static int 2585 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2586 { 2587 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2588 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2589 struct ieee80211com *ic = &sc->sc_ic; 2590 int idx, rx_data = 0; 2591 2592 idx = rbd->rbd_idx; 2593 while (idx != end_idx) { 2594 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2595 struct bwi_rxbuf_hdr *hdr; 2596 struct ieee80211_frame_min *wh; 2597 struct ieee80211_node *ni; 2598 struct mbuf *m; 2599 uint32_t plcp; 2600 uint16_t flags2; 2601 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2602 2603 m = rb->rb_mbuf; 2604 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2605 BUS_DMASYNC_POSTREAD); 2606 2607 if (bwi_newbuf(sc, idx, 0)) { 2608 counter_u64_add(ic->ic_ierrors, 1); 2609 goto next; 2610 } 2611 2612 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2613 flags2 = le16toh(hdr->rxh_flags2); 2614 2615 hdr_extra = 0; 2616 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2617 hdr_extra = 2; 2618 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2619 2620 buflen = le16toh(hdr->rxh_buflen); 2621 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2622 device_printf(sc->sc_dev, 2623 "%s: zero length data, hdr_extra %d\n", 2624 __func__, hdr_extra); 2625 counter_u64_add(ic->ic_ierrors, 1); 2626 m_freem(m); 2627 goto next; 2628 } 2629 2630 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2631 rssi = bwi_calc_rssi(sc, hdr); 2632 noise = bwi_calc_noise(sc); 2633 2634 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2635 m_adj(m, sizeof(*hdr) + wh_ofs); 2636 2637 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2638 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2639 else 2640 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2641 2642 /* RX radio tap */ 2643 if (ieee80211_radiotap_active(ic)) 2644 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2645 2646 m_adj(m, -IEEE80211_CRC_LEN); 2647 2648 BWI_UNLOCK(sc); 2649 2650 wh = mtod(m, struct ieee80211_frame_min *); 2651 ni = ieee80211_find_rxnode(ic, wh); 2652 if (ni != NULL) { 2653 type = ieee80211_input(ni, m, rssi - noise, noise); 2654 ieee80211_free_node(ni); 2655 } else 2656 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2657 if (type == IEEE80211_FC0_TYPE_DATA) { 2658 rx_data = 1; 2659 sc->sc_rx_rate = rate; 2660 } 2661 2662 BWI_LOCK(sc); 2663 next: 2664 idx = (idx + 1) % BWI_RX_NDESC; 2665 2666 if (sc->sc_flags & BWI_F_STOP) { 2667 /* 2668 * Take the fast lane, don't do 2669 * any damage to softc 2670 */ 2671 return -1; 2672 } 2673 } 2674 2675 rbd->rbd_idx = idx; 2676 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2677 BUS_DMASYNC_PREWRITE); 2678 2679 return rx_data; 2680 } 2681 2682 static int 2683 bwi_rxeof32(struct bwi_softc *sc) 2684 { 2685 uint32_t val, rx_ctrl; 2686 int end_idx, rx_data; 2687 2688 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2689 2690 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2691 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2692 sizeof(struct bwi_desc32); 2693 2694 rx_data = bwi_rxeof(sc, end_idx); 2695 if (rx_data >= 0) { 2696 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2697 end_idx * sizeof(struct bwi_desc32)); 2698 } 2699 return rx_data; 2700 } 2701 2702 static int 2703 bwi_rxeof64(struct bwi_softc *sc) 2704 { 2705 /* TODO:64 */ 2706 return 0; 2707 } 2708 2709 static void 2710 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2711 { 2712 int i; 2713 2714 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2715 2716 #define NRETRY 10 2717 2718 for (i = 0; i < NRETRY; ++i) { 2719 uint32_t status; 2720 2721 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2722 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2723 BWI_RX32_STATUS_STATE_DISABLED) 2724 break; 2725 2726 DELAY(1000); 2727 } 2728 if (i == NRETRY) 2729 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2730 2731 #undef NRETRY 2732 2733 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2734 } 2735 2736 static void 2737 bwi_free_txstats32(struct bwi_softc *sc) 2738 { 2739 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2740 } 2741 2742 static void 2743 bwi_free_rx_ring32(struct bwi_softc *sc) 2744 { 2745 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2746 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2747 int i; 2748 2749 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2750 2751 for (i = 0; i < BWI_RX_NDESC; ++i) { 2752 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2753 2754 if (rb->rb_mbuf != NULL) { 2755 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2756 m_freem(rb->rb_mbuf); 2757 rb->rb_mbuf = NULL; 2758 } 2759 } 2760 } 2761 2762 static void 2763 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2764 { 2765 struct bwi_ring_data *rd; 2766 struct bwi_txbuf_data *tbd; 2767 uint32_t state, val; 2768 int i; 2769 2770 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2771 rd = &sc->sc_tx_rdata[ring_idx]; 2772 tbd = &sc->sc_tx_bdata[ring_idx]; 2773 2774 #define NRETRY 10 2775 2776 for (i = 0; i < NRETRY; ++i) { 2777 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2778 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2779 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2780 state == BWI_TX32_STATUS_STATE_IDLE || 2781 state == BWI_TX32_STATUS_STATE_STOPPED) 2782 break; 2783 2784 DELAY(1000); 2785 } 2786 if (i == NRETRY) { 2787 device_printf(sc->sc_dev, 2788 "%s: wait for TX ring(%d) stable timed out\n", 2789 __func__, ring_idx); 2790 } 2791 2792 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2793 for (i = 0; i < NRETRY; ++i) { 2794 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2795 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2796 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2797 break; 2798 2799 DELAY(1000); 2800 } 2801 if (i == NRETRY) 2802 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2803 __func__, ring_idx); 2804 2805 #undef NRETRY 2806 2807 DELAY(1000); 2808 2809 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2810 2811 for (i = 0; i < BWI_TX_NDESC; ++i) { 2812 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2813 2814 if (tb->tb_mbuf != NULL) { 2815 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2816 m_freem(tb->tb_mbuf); 2817 tb->tb_mbuf = NULL; 2818 } 2819 if (tb->tb_ni != NULL) { 2820 ieee80211_free_node(tb->tb_ni); 2821 tb->tb_ni = NULL; 2822 } 2823 } 2824 } 2825 2826 static void 2827 bwi_free_txstats64(struct bwi_softc *sc) 2828 { 2829 /* TODO:64 */ 2830 } 2831 2832 static void 2833 bwi_free_rx_ring64(struct bwi_softc *sc) 2834 { 2835 /* TODO:64 */ 2836 } 2837 2838 static void 2839 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2840 { 2841 /* TODO:64 */ 2842 } 2843 2844 /* XXX does not belong here */ 2845 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2846 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2847 2848 static __inline void 2849 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2850 { 2851 uint32_t plcp; 2852 2853 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2854 IEEE80211_OFDM_PLCP_RATE_MASK) | 2855 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2856 *plcp0 = htole32(plcp); 2857 } 2858 2859 static __inline void 2860 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2861 uint8_t rate) 2862 { 2863 int len, service, pkt_bitlen; 2864 2865 pkt_bitlen = pkt_len * NBBY; 2866 len = howmany(pkt_bitlen * 2, rate); 2867 2868 service = IEEE80211_PLCP_SERVICE_LOCKED; 2869 if (rate == (11 * 2)) { 2870 int pkt_bitlen1; 2871 2872 /* 2873 * PLCP service field needs to be adjusted, 2874 * if TX rate is 11Mbytes/s 2875 */ 2876 pkt_bitlen1 = len * 11; 2877 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2878 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2879 } 2880 2881 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2882 plcp->i_service = service; 2883 plcp->i_length = htole16(len); 2884 /* NOTE: do NOT touch i_crc */ 2885 } 2886 2887 static __inline void 2888 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2889 void *plcp, int pkt_len, uint8_t rate) 2890 { 2891 enum ieee80211_phytype modtype; 2892 2893 /* 2894 * Assume caller has zeroed 'plcp' 2895 */ 2896 modtype = ieee80211_rate2phytype(rt, rate); 2897 if (modtype == IEEE80211_T_OFDM) 2898 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2899 else if (modtype == IEEE80211_T_DS) 2900 bwi_ds_plcp_header(plcp, pkt_len, rate); 2901 else 2902 panic("unsupport modulation type %u\n", modtype); 2903 } 2904 2905 static int 2906 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2907 struct ieee80211_node *ni) 2908 { 2909 struct ieee80211vap *vap = ni->ni_vap; 2910 struct ieee80211com *ic = &sc->sc_ic; 2911 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2912 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2913 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2914 struct bwi_mac *mac; 2915 struct bwi_txbuf_hdr *hdr; 2916 struct ieee80211_frame *wh; 2917 const struct ieee80211_txparam *tp = ni->ni_txparms; 2918 uint8_t rate, rate_fb; 2919 uint32_t mac_ctrl; 2920 uint16_t phy_ctrl; 2921 bus_addr_t paddr; 2922 int type, ismcast, pkt_len, error, rix; 2923 #if 0 2924 const uint8_t *p; 2925 int i; 2926 #endif 2927 2928 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2929 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2930 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2931 2932 wh = mtod(m, struct ieee80211_frame *); 2933 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2934 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2935 2936 /* Get 802.11 frame len before prepending TX header */ 2937 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2938 2939 /* 2940 * Find TX rate 2941 */ 2942 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2943 rate = rate_fb = tp->mgmtrate; 2944 } else if (ismcast) { 2945 rate = rate_fb = tp->mcastrate; 2946 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2947 rate = rate_fb = tp->ucastrate; 2948 } else { 2949 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2950 rate = ni->ni_txrate; 2951 2952 if (rix > 0) { 2953 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2954 IEEE80211_RATE_VAL; 2955 } else { 2956 rate_fb = rate; 2957 } 2958 } 2959 tb->tb_rate[0] = rate; 2960 tb->tb_rate[1] = rate_fb; 2961 sc->sc_tx_rate = rate; 2962 2963 /* 2964 * TX radio tap 2965 */ 2966 if (ieee80211_radiotap_active_vap(vap)) { 2967 sc->sc_tx_th.wt_flags = 0; 2968 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2969 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2970 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2971 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2972 rate != (1 * 2)) { 2973 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2974 } 2975 sc->sc_tx_th.wt_rate = rate; 2976 2977 ieee80211_radiotap_tx(vap, m); 2978 } 2979 2980 /* 2981 * Setup the embedded TX header 2982 */ 2983 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2984 if (m == NULL) { 2985 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2986 __func__); 2987 return ENOBUFS; 2988 } 2989 hdr = mtod(m, struct bwi_txbuf_hdr *); 2990 2991 bzero(hdr, sizeof(*hdr)); 2992 2993 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 2994 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 2995 2996 if (!ismcast) { 2997 uint16_t dur; 2998 2999 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3000 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3001 3002 hdr->txh_fb_duration = htole16(dur); 3003 } 3004 3005 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3006 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3007 3008 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3009 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3010 3011 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3012 BWI_TXH_PHY_C_ANTMODE_MASK); 3013 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3014 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3015 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3016 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3017 3018 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3019 if (!ismcast) 3020 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3021 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3022 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3023 3024 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3025 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3026 3027 /* Catch any further usage */ 3028 hdr = NULL; 3029 wh = NULL; 3030 3031 /* DMA load */ 3032 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3033 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3034 if (error && error != EFBIG) { 3035 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3036 __func__, error); 3037 goto back; 3038 } 3039 3040 if (error) { /* error == EFBIG */ 3041 struct mbuf *m_new; 3042 3043 m_new = m_defrag(m, M_NOWAIT); 3044 if (m_new == NULL) { 3045 device_printf(sc->sc_dev, 3046 "%s: can't defrag TX buffer\n", __func__); 3047 error = ENOBUFS; 3048 goto back; 3049 } else { 3050 m = m_new; 3051 } 3052 3053 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3054 bwi_dma_buf_addr, &paddr, 3055 BUS_DMA_NOWAIT); 3056 if (error) { 3057 device_printf(sc->sc_dev, 3058 "%s: can't load TX buffer (2) %d\n", 3059 __func__, error); 3060 goto back; 3061 } 3062 } 3063 error = 0; 3064 3065 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3066 3067 tb->tb_mbuf = m; 3068 tb->tb_ni = ni; 3069 3070 #if 0 3071 p = mtod(m, const uint8_t *); 3072 for (i = 0; i < m->m_pkthdr.len; ++i) { 3073 if (i != 0 && i % 8 == 0) 3074 printf("\n"); 3075 printf("%02x ", p[i]); 3076 } 3077 printf("\n"); 3078 #endif 3079 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3080 idx, pkt_len, m->m_pkthdr.len); 3081 3082 /* Setup TX descriptor */ 3083 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3084 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3085 BUS_DMASYNC_PREWRITE); 3086 3087 /* Kick start */ 3088 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3089 3090 back: 3091 if (error) 3092 m_freem(m); 3093 return error; 3094 } 3095 3096 static int 3097 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3098 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3099 { 3100 struct ieee80211vap *vap = ni->ni_vap; 3101 struct ieee80211com *ic = ni->ni_ic; 3102 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3103 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3104 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3105 struct bwi_mac *mac; 3106 struct bwi_txbuf_hdr *hdr; 3107 struct ieee80211_frame *wh; 3108 uint8_t rate, rate_fb; 3109 uint32_t mac_ctrl; 3110 uint16_t phy_ctrl; 3111 bus_addr_t paddr; 3112 int ismcast, pkt_len, error; 3113 3114 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3115 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3116 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3117 3118 wh = mtod(m, struct ieee80211_frame *); 3119 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3120 3121 /* Get 802.11 frame len before prepending TX header */ 3122 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3123 3124 /* 3125 * Find TX rate 3126 */ 3127 rate = params->ibp_rate0; 3128 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3129 /* XXX fall back to mcast/mgmt rate? */ 3130 m_freem(m); 3131 return EINVAL; 3132 } 3133 if (params->ibp_try1 != 0) { 3134 rate_fb = params->ibp_rate1; 3135 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3136 /* XXX fall back to rate0? */ 3137 m_freem(m); 3138 return EINVAL; 3139 } 3140 } else 3141 rate_fb = rate; 3142 tb->tb_rate[0] = rate; 3143 tb->tb_rate[1] = rate_fb; 3144 sc->sc_tx_rate = rate; 3145 3146 /* 3147 * TX radio tap 3148 */ 3149 if (ieee80211_radiotap_active_vap(vap)) { 3150 sc->sc_tx_th.wt_flags = 0; 3151 /* XXX IEEE80211_BPF_CRYPTO */ 3152 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3153 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3154 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3155 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3156 sc->sc_tx_th.wt_rate = rate; 3157 3158 ieee80211_radiotap_tx(vap, m); 3159 } 3160 3161 /* 3162 * Setup the embedded TX header 3163 */ 3164 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3165 if (m == NULL) { 3166 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3167 __func__); 3168 return ENOBUFS; 3169 } 3170 hdr = mtod(m, struct bwi_txbuf_hdr *); 3171 3172 bzero(hdr, sizeof(*hdr)); 3173 3174 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3175 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3176 3177 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3178 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3179 uint16_t dur; 3180 3181 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3182 3183 hdr->txh_fb_duration = htole16(dur); 3184 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3185 } 3186 3187 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3188 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3189 3190 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3191 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3192 3193 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3194 BWI_TXH_PHY_C_ANTMODE_MASK); 3195 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3196 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3197 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3198 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3199 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3200 3201 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3202 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3203 3204 /* Catch any further usage */ 3205 hdr = NULL; 3206 wh = NULL; 3207 3208 /* DMA load */ 3209 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3210 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3211 if (error != 0) { 3212 struct mbuf *m_new; 3213 3214 if (error != EFBIG) { 3215 device_printf(sc->sc_dev, 3216 "%s: can't load TX buffer (1) %d\n", 3217 __func__, error); 3218 goto back; 3219 } 3220 m_new = m_defrag(m, M_NOWAIT); 3221 if (m_new == NULL) { 3222 device_printf(sc->sc_dev, 3223 "%s: can't defrag TX buffer\n", __func__); 3224 error = ENOBUFS; 3225 goto back; 3226 } 3227 m = m_new; 3228 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3229 bwi_dma_buf_addr, &paddr, 3230 BUS_DMA_NOWAIT); 3231 if (error) { 3232 device_printf(sc->sc_dev, 3233 "%s: can't load TX buffer (2) %d\n", 3234 __func__, error); 3235 goto back; 3236 } 3237 } 3238 3239 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3240 3241 tb->tb_mbuf = m; 3242 tb->tb_ni = ni; 3243 3244 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3245 idx, pkt_len, m->m_pkthdr.len); 3246 3247 /* Setup TX descriptor */ 3248 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3249 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3250 BUS_DMASYNC_PREWRITE); 3251 3252 /* Kick start */ 3253 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3254 back: 3255 if (error) 3256 m_freem(m); 3257 return error; 3258 } 3259 3260 static void 3261 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3262 { 3263 idx = (idx + 1) % BWI_TX_NDESC; 3264 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3265 idx * sizeof(struct bwi_desc32)); 3266 } 3267 3268 static void 3269 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3270 { 3271 /* TODO:64 */ 3272 } 3273 3274 static void 3275 bwi_txeof_status32(struct bwi_softc *sc) 3276 { 3277 uint32_t val, ctrl_base; 3278 int end_idx; 3279 3280 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3281 3282 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3283 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3284 sizeof(struct bwi_desc32); 3285 3286 bwi_txeof_status(sc, end_idx); 3287 3288 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3289 end_idx * sizeof(struct bwi_desc32)); 3290 3291 bwi_start_locked(sc); 3292 } 3293 3294 static void 3295 bwi_txeof_status64(struct bwi_softc *sc) 3296 { 3297 /* TODO:64 */ 3298 } 3299 3300 static void 3301 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3302 { 3303 struct bwi_txbuf_data *tbd; 3304 struct bwi_txbuf *tb; 3305 int ring_idx, buf_idx; 3306 struct ieee80211_node *ni; 3307 3308 if (tx_id == 0) { 3309 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3310 return; 3311 } 3312 3313 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3314 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3315 3316 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3317 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3318 3319 tbd = &sc->sc_tx_bdata[ring_idx]; 3320 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3321 tbd->tbd_used--; 3322 3323 tb = &tbd->tbd_buf[buf_idx]; 3324 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3325 "acked %d, data_txcnt %d, ni %p\n", 3326 buf_idx, acked, data_txcnt, tb->tb_ni); 3327 3328 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3329 3330 if ((ni = tb->tb_ni) != NULL) { 3331 const struct bwi_txbuf_hdr *hdr = 3332 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3333 struct ieee80211_ratectl_tx_status txs; 3334 3335 /* NB: update rate control only for unicast frames */ 3336 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3337 /* 3338 * Feed back 'acked and data_txcnt'. Note that the 3339 * generic AMRR code only understands one tx rate 3340 * and the estimator doesn't handle real retry counts 3341 * well so to avoid over-aggressive downshifting we 3342 * treat any number of retries as "1". 3343 */ 3344 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 3345 txs.long_retries = acked; 3346 if (data_txcnt > 1) 3347 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 3348 else { 3349 txs.status = 3350 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3351 } 3352 ieee80211_ratectl_tx_complete(ni, &txs); 3353 } 3354 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3355 tb->tb_ni = NULL; 3356 } else 3357 m_freem(tb->tb_mbuf); 3358 tb->tb_mbuf = NULL; 3359 3360 if (tbd->tbd_used == 0) 3361 sc->sc_tx_timer = 0; 3362 } 3363 3364 static void 3365 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3366 { 3367 struct bwi_txstats_data *st = sc->sc_txstats; 3368 int idx; 3369 3370 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3371 3372 idx = st->stats_idx; 3373 while (idx != end_idx) { 3374 const struct bwi_txstats *stats = &st->stats[idx]; 3375 3376 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3377 int data_txcnt; 3378 3379 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3380 BWI_TXS_TXCNT_DATA); 3381 _bwi_txeof(sc, le16toh(stats->txs_id), 3382 stats->txs_flags & BWI_TXS_F_ACKED, 3383 data_txcnt); 3384 } 3385 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3386 } 3387 st->stats_idx = idx; 3388 } 3389 3390 static void 3391 bwi_txeof(struct bwi_softc *sc) 3392 { 3393 3394 for (;;) { 3395 uint32_t tx_status0, tx_status1 __unused; 3396 uint16_t tx_id; 3397 int data_txcnt; 3398 3399 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3400 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3401 break; 3402 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3403 3404 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3405 data_txcnt = __SHIFTOUT(tx_status0, 3406 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3407 3408 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3409 continue; 3410 3411 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3412 data_txcnt); 3413 } 3414 3415 bwi_start_locked(sc); 3416 } 3417 3418 static int 3419 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3420 { 3421 bwi_power_on(sc, 1); 3422 return bwi_set_clock_mode(sc, clk_mode); 3423 } 3424 3425 static void 3426 bwi_bbp_power_off(struct bwi_softc *sc) 3427 { 3428 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3429 bwi_power_off(sc, 1); 3430 } 3431 3432 static int 3433 bwi_get_pwron_delay(struct bwi_softc *sc) 3434 { 3435 struct bwi_regwin *com, *old; 3436 struct bwi_clock_freq freq; 3437 uint32_t val; 3438 int error; 3439 3440 com = &sc->sc_com_regwin; 3441 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3442 3443 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3444 return 0; 3445 3446 error = bwi_regwin_switch(sc, com, &old); 3447 if (error) 3448 return error; 3449 3450 bwi_get_clock_freq(sc, &freq); 3451 3452 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3453 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3454 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3455 3456 return bwi_regwin_switch(sc, old, NULL); 3457 } 3458 3459 static int 3460 bwi_bus_attach(struct bwi_softc *sc) 3461 { 3462 struct bwi_regwin *bus, *old; 3463 int error; 3464 3465 bus = &sc->sc_bus_regwin; 3466 3467 error = bwi_regwin_switch(sc, bus, &old); 3468 if (error) 3469 return error; 3470 3471 if (!bwi_regwin_is_enabled(sc, bus)) 3472 bwi_regwin_enable(sc, bus, 0); 3473 3474 /* Disable interripts */ 3475 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3476 3477 return bwi_regwin_switch(sc, old, NULL); 3478 } 3479 3480 static const char * 3481 bwi_regwin_name(const struct bwi_regwin *rw) 3482 { 3483 switch (rw->rw_type) { 3484 case BWI_REGWIN_T_COM: 3485 return "COM"; 3486 case BWI_REGWIN_T_BUSPCI: 3487 return "PCI"; 3488 case BWI_REGWIN_T_MAC: 3489 return "MAC"; 3490 case BWI_REGWIN_T_BUSPCIE: 3491 return "PCIE"; 3492 } 3493 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3494 return NULL; 3495 } 3496 3497 static uint32_t 3498 bwi_regwin_disable_bits(struct bwi_softc *sc) 3499 { 3500 uint32_t busrev; 3501 3502 /* XXX cache this */ 3503 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3504 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3505 "bus rev %u\n", busrev); 3506 3507 if (busrev == BWI_BUSREV_0) 3508 return BWI_STATE_LO_DISABLE1; 3509 else if (busrev == BWI_BUSREV_1) 3510 return BWI_STATE_LO_DISABLE2; 3511 else 3512 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3513 } 3514 3515 int 3516 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3517 { 3518 uint32_t val, disable_bits; 3519 3520 disable_bits = bwi_regwin_disable_bits(sc); 3521 val = CSR_READ_4(sc, BWI_STATE_LO); 3522 3523 if ((val & (BWI_STATE_LO_CLOCK | 3524 BWI_STATE_LO_RESET | 3525 disable_bits)) == BWI_STATE_LO_CLOCK) { 3526 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3527 bwi_regwin_name(rw)); 3528 return 1; 3529 } else { 3530 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3531 bwi_regwin_name(rw)); 3532 return 0; 3533 } 3534 } 3535 3536 void 3537 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3538 { 3539 uint32_t state_lo, disable_bits; 3540 int i; 3541 3542 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3543 3544 /* 3545 * If current regwin is in 'reset' state, it was already disabled. 3546 */ 3547 if (state_lo & BWI_STATE_LO_RESET) { 3548 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3549 "%s was already disabled\n", bwi_regwin_name(rw)); 3550 return; 3551 } 3552 3553 disable_bits = bwi_regwin_disable_bits(sc); 3554 3555 /* 3556 * Disable normal clock 3557 */ 3558 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3559 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3560 3561 /* 3562 * Wait until normal clock is disabled 3563 */ 3564 #define NRETRY 1000 3565 for (i = 0; i < NRETRY; ++i) { 3566 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3567 if (state_lo & disable_bits) 3568 break; 3569 DELAY(10); 3570 } 3571 if (i == NRETRY) { 3572 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3573 bwi_regwin_name(rw)); 3574 } 3575 3576 for (i = 0; i < NRETRY; ++i) { 3577 uint32_t state_hi; 3578 3579 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3580 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3581 break; 3582 DELAY(10); 3583 } 3584 if (i == NRETRY) { 3585 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3586 bwi_regwin_name(rw)); 3587 } 3588 #undef NRETRY 3589 3590 /* 3591 * Reset and disable regwin with gated clock 3592 */ 3593 state_lo = BWI_STATE_LO_RESET | disable_bits | 3594 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3595 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3596 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3597 3598 /* Flush pending bus write */ 3599 CSR_READ_4(sc, BWI_STATE_LO); 3600 DELAY(1); 3601 3602 /* Reset and disable regwin */ 3603 state_lo = BWI_STATE_LO_RESET | disable_bits | 3604 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3605 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3606 3607 /* Flush pending bus write */ 3608 CSR_READ_4(sc, BWI_STATE_LO); 3609 DELAY(1); 3610 } 3611 3612 void 3613 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3614 { 3615 uint32_t state_lo, state_hi, imstate; 3616 3617 bwi_regwin_disable(sc, rw, flags); 3618 3619 /* Reset regwin with gated clock */ 3620 state_lo = BWI_STATE_LO_RESET | 3621 BWI_STATE_LO_CLOCK | 3622 BWI_STATE_LO_GATED_CLOCK | 3623 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3624 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3625 3626 /* Flush pending bus write */ 3627 CSR_READ_4(sc, BWI_STATE_LO); 3628 DELAY(1); 3629 3630 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3631 if (state_hi & BWI_STATE_HI_SERROR) 3632 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3633 3634 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3635 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3636 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3637 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3638 } 3639 3640 /* Enable regwin with gated clock */ 3641 state_lo = BWI_STATE_LO_CLOCK | 3642 BWI_STATE_LO_GATED_CLOCK | 3643 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3644 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3645 3646 /* Flush pending bus write */ 3647 CSR_READ_4(sc, BWI_STATE_LO); 3648 DELAY(1); 3649 3650 /* Enable regwin with normal clock */ 3651 state_lo = BWI_STATE_LO_CLOCK | 3652 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3653 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3654 3655 /* Flush pending bus write */ 3656 CSR_READ_4(sc, BWI_STATE_LO); 3657 DELAY(1); 3658 } 3659 3660 static void 3661 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3662 { 3663 struct bwi_mac *mac; 3664 struct bwi_myaddr_bssid buf; 3665 const uint8_t *p; 3666 uint32_t val; 3667 int n, i; 3668 3669 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3670 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3671 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3672 3673 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3674 3675 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3676 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3677 3678 n = sizeof(buf) / sizeof(val); 3679 p = (const uint8_t *)&buf; 3680 for (i = 0; i < n; ++i) { 3681 int j; 3682 3683 val = 0; 3684 for (j = 0; j < sizeof(val); ++j) 3685 val |= ((uint32_t)(*p++)) << (j * 8); 3686 3687 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3688 } 3689 } 3690 3691 static void 3692 bwi_updateslot(struct ieee80211com *ic) 3693 { 3694 struct bwi_softc *sc = ic->ic_softc; 3695 struct bwi_mac *mac; 3696 3697 BWI_LOCK(sc); 3698 if (sc->sc_flags & BWI_F_RUNNING) { 3699 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3700 3701 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3702 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3703 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3704 3705 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3706 } 3707 BWI_UNLOCK(sc); 3708 } 3709 3710 static void 3711 bwi_calibrate(void *xsc) 3712 { 3713 struct bwi_softc *sc = xsc; 3714 struct bwi_mac *mac; 3715 3716 BWI_ASSERT_LOCKED(sc); 3717 3718 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3719 ("opmode %d", sc->sc_ic.ic_opmode)); 3720 3721 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3722 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3723 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3724 3725 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3726 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3727 3728 /* XXX 15 seconds */ 3729 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3730 } 3731 3732 static int 3733 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3734 { 3735 struct bwi_mac *mac; 3736 3737 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3738 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3739 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3740 3741 return bwi_rf_calc_rssi(mac, hdr); 3742 } 3743 3744 static int 3745 bwi_calc_noise(struct bwi_softc *sc) 3746 { 3747 struct bwi_mac *mac; 3748 3749 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3750 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3751 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3752 3753 return bwi_rf_calc_noise(mac); 3754 } 3755 3756 static __inline uint8_t 3757 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3758 { 3759 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3760 return (ieee80211_plcp2rate(plcp, type)); 3761 } 3762 3763 static void 3764 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3765 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3766 { 3767 const struct ieee80211_frame_min *wh; 3768 3769 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3770 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3771 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3772 3773 wh = mtod(m, const struct ieee80211_frame_min *); 3774 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3775 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3776 3777 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */ 3778 sc->sc_rx_th.wr_rate = rate; 3779 sc->sc_rx_th.wr_antsignal = rssi; 3780 sc->sc_rx_th.wr_antnoise = noise; 3781 } 3782 3783 static void 3784 bwi_led_attach(struct bwi_softc *sc) 3785 { 3786 const uint8_t *led_act = NULL; 3787 uint16_t gpio, val[BWI_LED_MAX]; 3788 int i; 3789 3790 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3791 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3792 led_act = bwi_vendor_led_act[i].led_act; 3793 break; 3794 } 3795 } 3796 if (led_act == NULL) 3797 led_act = bwi_default_led_act; 3798 3799 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3800 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3801 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3802 3803 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3804 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3805 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3806 3807 for (i = 0; i < BWI_LED_MAX; ++i) { 3808 struct bwi_led *led = &sc->sc_leds[i]; 3809 3810 if (val[i] == 0xff) { 3811 led->l_act = led_act[i]; 3812 } else { 3813 if (val[i] & BWI_LED_ACT_LOW) 3814 led->l_flags |= BWI_LED_F_ACTLOW; 3815 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3816 } 3817 led->l_mask = (1 << i); 3818 3819 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3820 led->l_act == BWI_LED_ACT_BLINK_POLL || 3821 led->l_act == BWI_LED_ACT_BLINK) { 3822 led->l_flags |= BWI_LED_F_BLINK; 3823 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3824 led->l_flags |= BWI_LED_F_POLLABLE; 3825 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3826 led->l_flags |= BWI_LED_F_SLOW; 3827 3828 if (sc->sc_blink_led == NULL) { 3829 sc->sc_blink_led = led; 3830 if (led->l_flags & BWI_LED_F_SLOW) 3831 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3832 } 3833 } 3834 3835 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3836 "%dth led, act %d, lowact %d\n", i, 3837 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3838 } 3839 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3840 } 3841 3842 static __inline uint16_t 3843 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3844 { 3845 if (led->l_flags & BWI_LED_F_ACTLOW) 3846 on = !on; 3847 if (on) 3848 val |= led->l_mask; 3849 else 3850 val &= ~led->l_mask; 3851 return val; 3852 } 3853 3854 static void 3855 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3856 { 3857 struct ieee80211com *ic = &sc->sc_ic; 3858 uint16_t val; 3859 int i; 3860 3861 if (nstate == IEEE80211_S_INIT) { 3862 callout_stop(&sc->sc_led_blink_ch); 3863 sc->sc_led_blinking = 0; 3864 } 3865 3866 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3867 return; 3868 3869 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3870 for (i = 0; i < BWI_LED_MAX; ++i) { 3871 struct bwi_led *led = &sc->sc_leds[i]; 3872 int on; 3873 3874 if (led->l_act == BWI_LED_ACT_UNKN || 3875 led->l_act == BWI_LED_ACT_NULL) 3876 continue; 3877 3878 if ((led->l_flags & BWI_LED_F_BLINK) && 3879 nstate != IEEE80211_S_INIT) 3880 continue; 3881 3882 switch (led->l_act) { 3883 case BWI_LED_ACT_ON: /* Always on */ 3884 on = 1; 3885 break; 3886 case BWI_LED_ACT_OFF: /* Always off */ 3887 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3888 on = 0; 3889 break; 3890 default: 3891 on = 1; 3892 switch (nstate) { 3893 case IEEE80211_S_INIT: 3894 on = 0; 3895 break; 3896 case IEEE80211_S_RUN: 3897 if (led->l_act == BWI_LED_ACT_11G && 3898 ic->ic_curmode != IEEE80211_MODE_11G) 3899 on = 0; 3900 break; 3901 default: 3902 if (led->l_act == BWI_LED_ACT_ASSOC) 3903 on = 0; 3904 break; 3905 } 3906 break; 3907 } 3908 3909 val = bwi_led_onoff(led, val, on); 3910 } 3911 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3912 } 3913 static void 3914 bwi_led_event(struct bwi_softc *sc, int event) 3915 { 3916 struct bwi_led *led = sc->sc_blink_led; 3917 int rate; 3918 3919 if (event == BWI_LED_EVENT_POLL) { 3920 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3921 return; 3922 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3923 return; 3924 } 3925 3926 sc->sc_led_ticks = ticks; 3927 if (sc->sc_led_blinking) 3928 return; 3929 3930 switch (event) { 3931 case BWI_LED_EVENT_RX: 3932 rate = sc->sc_rx_rate; 3933 break; 3934 case BWI_LED_EVENT_TX: 3935 rate = sc->sc_tx_rate; 3936 break; 3937 case BWI_LED_EVENT_POLL: 3938 rate = 0; 3939 break; 3940 default: 3941 panic("unknown LED event %d\n", event); 3942 break; 3943 } 3944 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3945 bwi_led_duration[rate].off_dur); 3946 } 3947 3948 static void 3949 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3950 { 3951 struct bwi_led *led = sc->sc_blink_led; 3952 uint16_t val; 3953 3954 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3955 val = bwi_led_onoff(led, val, 1); 3956 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3957 3958 if (led->l_flags & BWI_LED_F_SLOW) { 3959 BWI_LED_SLOWDOWN(on_dur); 3960 BWI_LED_SLOWDOWN(off_dur); 3961 } 3962 3963 sc->sc_led_blinking = 1; 3964 sc->sc_led_blink_offdur = off_dur; 3965 3966 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3967 } 3968 3969 static void 3970 bwi_led_blink_next(void *xsc) 3971 { 3972 struct bwi_softc *sc = xsc; 3973 uint16_t val; 3974 3975 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3976 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3977 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3978 3979 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3980 bwi_led_blink_end, sc); 3981 } 3982 3983 static void 3984 bwi_led_blink_end(void *xsc) 3985 { 3986 struct bwi_softc *sc = xsc; 3987 sc->sc_led_blinking = 0; 3988 } 3989 3990 static void 3991 bwi_restart(void *xsc, int pending) 3992 { 3993 struct bwi_softc *sc = xsc; 3994 3995 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 3996 BWI_LOCK(sc); 3997 bwi_init_statechg(sc, 0); 3998 #if 0 3999 bwi_start_locked(sc); 4000 #endif 4001 BWI_UNLOCK(sc); 4002 } 4003