1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include "opt_inet.h" 43 #include "opt_bwi.h" 44 #include "opt_wlan.h" 45 46 #include <sys/param.h> 47 #include <sys/endian.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 #include <sys/systm.h> 57 #include <sys/taskqueue.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 #include <net/if_arp.h> 65 #include <net/ethernet.h> 66 #include <net/if_llc.h> 67 68 #include <net80211/ieee80211_var.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_regdomain.h> 71 #include <net80211/ieee80211_phy.h> 72 #include <net80211/ieee80211_ratectl.h> 73 74 #include <net/bpf.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/if_ether.h> 79 #endif 80 81 #include <machine/bus.h> 82 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcireg.h> 85 86 #include <dev/bwi/bitops.h> 87 #include <dev/bwi/if_bwireg.h> 88 #include <dev/bwi/if_bwivar.h> 89 #include <dev/bwi/bwimac.h> 90 #include <dev/bwi/bwirf.h> 91 92 struct bwi_clock_freq { 93 u_int clkfreq_min; 94 u_int clkfreq_max; 95 }; 96 97 struct bwi_myaddr_bssid { 98 uint8_t myaddr[IEEE80211_ADDR_LEN]; 99 uint8_t bssid[IEEE80211_ADDR_LEN]; 100 } __packed; 101 102 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 103 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 104 const uint8_t [IEEE80211_ADDR_LEN], 105 const uint8_t [IEEE80211_ADDR_LEN]); 106 static void bwi_vap_delete(struct ieee80211vap *); 107 static void bwi_init(struct bwi_softc *); 108 static void bwi_parent(struct ieee80211com *); 109 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 110 static void bwi_start_locked(struct bwi_softc *); 111 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 112 const struct ieee80211_bpf_params *); 113 static void bwi_watchdog(void *); 114 static void bwi_scan_start(struct ieee80211com *); 115 static void bwi_getradiocaps(struct ieee80211com *, int, int *, 116 struct ieee80211_channel[]); 117 static void bwi_set_channel(struct ieee80211com *); 118 static void bwi_scan_end(struct ieee80211com *); 119 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 120 static void bwi_updateslot(struct ieee80211com *); 121 static int bwi_media_change(struct ifnet *); 122 123 static void bwi_calibrate(void *); 124 125 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 126 static int bwi_calc_noise(struct bwi_softc *); 127 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 128 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 129 struct bwi_rxbuf_hdr *, const void *, int, int, int); 130 131 static void bwi_restart(void *, int); 132 static void bwi_init_statechg(struct bwi_softc *, int); 133 static void bwi_stop(struct bwi_softc *, int); 134 static void bwi_stop_locked(struct bwi_softc *, int); 135 static int bwi_newbuf(struct bwi_softc *, int, int); 136 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *); 138 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 139 struct ieee80211_node *, 140 const struct ieee80211_bpf_params *); 141 142 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 143 bus_addr_t, int, int); 144 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 145 146 static int bwi_init_tx_ring32(struct bwi_softc *, int); 147 static int bwi_init_rx_ring32(struct bwi_softc *); 148 static int bwi_init_txstats32(struct bwi_softc *); 149 static void bwi_free_tx_ring32(struct bwi_softc *, int); 150 static void bwi_free_rx_ring32(struct bwi_softc *); 151 static void bwi_free_txstats32(struct bwi_softc *); 152 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 153 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 154 int, bus_addr_t, int); 155 static int bwi_rxeof32(struct bwi_softc *); 156 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 157 static void bwi_txeof_status32(struct bwi_softc *); 158 159 static int bwi_init_tx_ring64(struct bwi_softc *, int); 160 static int bwi_init_rx_ring64(struct bwi_softc *); 161 static int bwi_init_txstats64(struct bwi_softc *); 162 static void bwi_free_tx_ring64(struct bwi_softc *, int); 163 static void bwi_free_rx_ring64(struct bwi_softc *); 164 static void bwi_free_txstats64(struct bwi_softc *); 165 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 166 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 167 int, bus_addr_t, int); 168 static int bwi_rxeof64(struct bwi_softc *); 169 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 170 static void bwi_txeof_status64(struct bwi_softc *); 171 172 static int bwi_rxeof(struct bwi_softc *, int); 173 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 174 static void bwi_txeof(struct bwi_softc *); 175 static void bwi_txeof_status(struct bwi_softc *, int); 176 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 177 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 178 179 static int bwi_dma_alloc(struct bwi_softc *); 180 static void bwi_dma_free(struct bwi_softc *); 181 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 182 struct bwi_ring_data *, bus_size_t, 183 uint32_t); 184 static int bwi_dma_mbuf_create(struct bwi_softc *); 185 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 186 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 187 static void bwi_dma_txstats_free(struct bwi_softc *); 188 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 189 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 190 bus_size_t, int); 191 192 static void bwi_power_on(struct bwi_softc *, int); 193 static int bwi_power_off(struct bwi_softc *, int); 194 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 195 static int bwi_set_clock_delay(struct bwi_softc *); 196 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 197 static int bwi_get_pwron_delay(struct bwi_softc *sc); 198 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 199 const uint8_t *); 200 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 201 202 static void bwi_get_card_flags(struct bwi_softc *); 203 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 204 205 static int bwi_bus_attach(struct bwi_softc *); 206 static int bwi_bbp_attach(struct bwi_softc *); 207 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 208 static void bwi_bbp_power_off(struct bwi_softc *); 209 210 static const char *bwi_regwin_name(const struct bwi_regwin *); 211 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 212 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 213 static int bwi_regwin_select(struct bwi_softc *, int); 214 215 static void bwi_led_attach(struct bwi_softc *); 216 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 217 static void bwi_led_event(struct bwi_softc *, int); 218 static void bwi_led_blink_start(struct bwi_softc *, int, int); 219 static void bwi_led_blink_next(void *); 220 static void bwi_led_blink_end(void *); 221 222 static const struct { 223 uint16_t did_min; 224 uint16_t did_max; 225 uint16_t bbp_id; 226 } bwi_bbpid_map[] = { 227 { 0x4301, 0x4301, 0x4301 }, 228 { 0x4305, 0x4307, 0x4307 }, 229 { 0x4402, 0x4403, 0x4402 }, 230 { 0x4610, 0x4615, 0x4610 }, 231 { 0x4710, 0x4715, 0x4710 }, 232 { 0x4720, 0x4725, 0x4309 } 233 }; 234 235 static const struct { 236 uint16_t bbp_id; 237 int nregwin; 238 } bwi_regwin_count[] = { 239 { 0x4301, 5 }, 240 { 0x4306, 6 }, 241 { 0x4307, 5 }, 242 { 0x4310, 8 }, 243 { 0x4401, 3 }, 244 { 0x4402, 3 }, 245 { 0x4610, 9 }, 246 { 0x4704, 9 }, 247 { 0x4710, 9 }, 248 { 0x5365, 7 } 249 }; 250 251 #define CLKSRC(src) \ 252 [BWI_CLKSRC_ ## src] = { \ 253 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 254 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 255 } 256 257 static const struct { 258 u_int freq_min; 259 u_int freq_max; 260 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 261 CLKSRC(LP_OSC), 262 CLKSRC(CS_OSC), 263 CLKSRC(PCI) 264 }; 265 266 #undef CLKSRC 267 268 #define VENDOR_LED_ACT(vendor) \ 269 { \ 270 .vid = PCI_VENDOR_##vendor, \ 271 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 272 } 273 274 static const struct { 275 #define PCI_VENDOR_COMPAQ 0x0e11 276 #define PCI_VENDOR_LINKSYS 0x1737 277 uint16_t vid; 278 uint8_t led_act[BWI_LED_MAX]; 279 } bwi_vendor_led_act[] = { 280 VENDOR_LED_ACT(COMPAQ), 281 VENDOR_LED_ACT(LINKSYS) 282 #undef PCI_VENDOR_LINKSYS 283 #undef PCI_VENDOR_COMPAQ 284 }; 285 286 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 287 { BWI_VENDOR_LED_ACT_DEFAULT }; 288 289 #undef VENDOR_LED_ACT 290 291 static const struct { 292 int on_dur; 293 int off_dur; 294 } bwi_led_duration[109] = { 295 [0] = { 400, 100 }, 296 [2] = { 150, 75 }, 297 [4] = { 90, 45 }, 298 [11] = { 66, 34 }, 299 [12] = { 53, 26 }, 300 [18] = { 42, 21 }, 301 [22] = { 35, 17 }, 302 [24] = { 32, 16 }, 303 [36] = { 21, 10 }, 304 [48] = { 16, 8 }, 305 [72] = { 11, 5 }, 306 [96] = { 9, 4 }, 307 [108] = { 7, 3 } 308 }; 309 310 static const uint8_t bwi_chan_2ghz[] = 311 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 312 313 #ifdef BWI_DEBUG 314 #ifdef BWI_DEBUG_VERBOSE 315 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 316 #else 317 static uint32_t bwi_debug; 318 #endif 319 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 320 #endif /* BWI_DEBUG */ 321 322 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 323 324 uint16_t 325 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 326 { 327 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 328 } 329 330 static __inline void 331 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 332 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 333 int tx) 334 { 335 struct bwi_desc32 *desc = &desc_array[desc_idx]; 336 uint32_t ctrl, addr, addr_hi, addr_lo; 337 338 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 339 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 340 341 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 342 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 343 344 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 345 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 346 if (desc_idx == ndesc - 1) 347 ctrl |= BWI_DESC32_C_EOR; 348 if (tx) { 349 /* XXX */ 350 ctrl |= BWI_DESC32_C_FRAME_START | 351 BWI_DESC32_C_FRAME_END | 352 BWI_DESC32_C_INTR; 353 } 354 355 desc->addr = htole32(addr); 356 desc->ctrl = htole32(ctrl); 357 } 358 359 int 360 bwi_attach(struct bwi_softc *sc) 361 { 362 struct ieee80211com *ic = &sc->sc_ic; 363 device_t dev = sc->sc_dev; 364 struct bwi_mac *mac; 365 struct bwi_phy *phy; 366 int i, error; 367 368 BWI_LOCK_INIT(sc); 369 370 /* 371 * Initialize taskq and various tasks 372 */ 373 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 374 taskqueue_thread_enqueue, &sc->sc_tq); 375 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 376 device_get_nameunit(dev)); 377 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 378 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 379 mbufq_init(&sc->sc_snd, ifqmaxlen); 380 381 /* 382 * Initialize sysctl variables 383 */ 384 sc->sc_fw_version = BWI_FW_VERSION3; 385 sc->sc_led_idle = (2350 * hz) / 1000; 386 sc->sc_led_ticks = ticks - sc->sc_led_idle; 387 sc->sc_led_blink = 1; 388 sc->sc_txpwr_calib = 1; 389 #ifdef BWI_DEBUG 390 sc->sc_debug = bwi_debug; 391 #endif 392 bwi_power_on(sc, 1); 393 394 error = bwi_bbp_attach(sc); 395 if (error) 396 goto fail; 397 398 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 399 if (error) 400 goto fail; 401 402 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 403 error = bwi_set_clock_delay(sc); 404 if (error) 405 goto fail; 406 407 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 408 if (error) 409 goto fail; 410 411 error = bwi_get_pwron_delay(sc); 412 if (error) 413 goto fail; 414 } 415 416 error = bwi_bus_attach(sc); 417 if (error) 418 goto fail; 419 420 bwi_get_card_flags(sc); 421 422 bwi_led_attach(sc); 423 424 for (i = 0; i < sc->sc_nmac; ++i) { 425 struct bwi_regwin *old; 426 427 mac = &sc->sc_mac[i]; 428 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 429 if (error) 430 goto fail; 431 432 error = bwi_mac_lateattach(mac); 433 if (error) 434 goto fail; 435 436 error = bwi_regwin_switch(sc, old, NULL); 437 if (error) 438 goto fail; 439 } 440 441 /* 442 * XXX First MAC is known to exist 443 * TODO2 444 */ 445 mac = &sc->sc_mac[0]; 446 phy = &mac->mac_phy; 447 448 bwi_bbp_power_off(sc); 449 450 error = bwi_dma_alloc(sc); 451 if (error) 452 goto fail; 453 454 error = bwi_mac_fw_alloc(mac); 455 if (error) 456 goto fail; 457 458 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 459 460 /* 461 * Setup ratesets, phytype, channels and get MAC address 462 */ 463 if (phy->phy_mode == IEEE80211_MODE_11B || 464 phy->phy_mode == IEEE80211_MODE_11G) { 465 if (phy->phy_mode == IEEE80211_MODE_11B) { 466 ic->ic_phytype = IEEE80211_T_DS; 467 } else { 468 ic->ic_phytype = IEEE80211_T_OFDM; 469 } 470 471 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 472 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 473 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 474 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 475 device_printf(dev, 476 "invalid MAC address: %6D\n", 477 ic->ic_macaddr, ":"); 478 } 479 } 480 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 481 /* TODO:11A */ 482 error = ENXIO; 483 goto fail; 484 } else { 485 panic("unknown phymode %d\n", phy->phy_mode); 486 } 487 488 /* Get locale */ 489 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 490 BWI_SPROM_CARD_INFO_LOCALE); 491 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 492 /* XXX use locale */ 493 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 494 ic->ic_channels); 495 496 ic->ic_softc = sc; 497 ic->ic_name = device_get_nameunit(dev); 498 ic->ic_caps = IEEE80211_C_STA | 499 IEEE80211_C_SHSLOT | 500 IEEE80211_C_SHPREAMBLE | 501 IEEE80211_C_WPA | 502 IEEE80211_C_BGSCAN | 503 IEEE80211_C_MONITOR; 504 ic->ic_opmode = IEEE80211_M_STA; 505 ieee80211_ifattach(ic); 506 507 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 508 509 /* override default methods */ 510 ic->ic_vap_create = bwi_vap_create; 511 ic->ic_vap_delete = bwi_vap_delete; 512 ic->ic_raw_xmit = bwi_raw_xmit; 513 ic->ic_updateslot = bwi_updateslot; 514 ic->ic_scan_start = bwi_scan_start; 515 ic->ic_scan_end = bwi_scan_end; 516 ic->ic_getradiocaps = bwi_getradiocaps; 517 ic->ic_set_channel = bwi_set_channel; 518 ic->ic_transmit = bwi_transmit; 519 ic->ic_parent = bwi_parent; 520 521 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 522 523 ieee80211_radiotap_attach(ic, 524 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 525 BWI_TX_RADIOTAP_PRESENT, 526 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 527 BWI_RX_RADIOTAP_PRESENT); 528 529 /* 530 * Add sysctl nodes 531 */ 532 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 533 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 534 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 535 "Firmware version"); 536 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 537 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 538 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 539 "# ticks before LED enters idle state"); 540 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 542 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 543 "Allow LED to blink"); 544 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 547 "Enable software TX power calibration"); 548 #ifdef BWI_DEBUG 549 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 550 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 551 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 552 #endif 553 if (bootverbose) 554 ieee80211_announce(ic); 555 556 return (0); 557 fail: 558 BWI_LOCK_DESTROY(sc); 559 return (error); 560 } 561 562 int 563 bwi_detach(struct bwi_softc *sc) 564 { 565 struct ieee80211com *ic = &sc->sc_ic; 566 int i; 567 568 bwi_stop(sc, 1); 569 callout_drain(&sc->sc_led_blink_ch); 570 callout_drain(&sc->sc_calib_ch); 571 callout_drain(&sc->sc_watchdog_timer); 572 ieee80211_ifdetach(ic); 573 574 for (i = 0; i < sc->sc_nmac; ++i) 575 bwi_mac_detach(&sc->sc_mac[i]); 576 bwi_dma_free(sc); 577 taskqueue_free(sc->sc_tq); 578 mbufq_drain(&sc->sc_snd); 579 580 BWI_LOCK_DESTROY(sc); 581 582 return (0); 583 } 584 585 static struct ieee80211vap * 586 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 587 enum ieee80211_opmode opmode, int flags, 588 const uint8_t bssid[IEEE80211_ADDR_LEN], 589 const uint8_t mac[IEEE80211_ADDR_LEN]) 590 { 591 struct bwi_vap *bvp; 592 struct ieee80211vap *vap; 593 594 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 595 return NULL; 596 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 597 vap = &bvp->bv_vap; 598 /* enable s/w bmiss handling for sta mode */ 599 ieee80211_vap_setup(ic, vap, name, unit, opmode, 600 flags | IEEE80211_CLONE_NOBEACONS, bssid); 601 602 /* override default methods */ 603 bvp->bv_newstate = vap->iv_newstate; 604 vap->iv_newstate = bwi_newstate; 605 #if 0 606 vap->iv_update_beacon = bwi_beacon_update; 607 #endif 608 ieee80211_ratectl_init(vap); 609 610 /* complete setup */ 611 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status, 612 mac); 613 ic->ic_opmode = opmode; 614 return vap; 615 } 616 617 static void 618 bwi_vap_delete(struct ieee80211vap *vap) 619 { 620 struct bwi_vap *bvp = BWI_VAP(vap); 621 622 ieee80211_ratectl_deinit(vap); 623 ieee80211_vap_detach(vap); 624 free(bvp, M_80211_VAP); 625 } 626 627 void 628 bwi_suspend(struct bwi_softc *sc) 629 { 630 bwi_stop(sc, 1); 631 } 632 633 void 634 bwi_resume(struct bwi_softc *sc) 635 { 636 637 if (sc->sc_ic.ic_nrunning > 0) 638 bwi_init(sc); 639 } 640 641 int 642 bwi_shutdown(struct bwi_softc *sc) 643 { 644 bwi_stop(sc, 1); 645 return 0; 646 } 647 648 static void 649 bwi_power_on(struct bwi_softc *sc, int with_pll) 650 { 651 uint32_t gpio_in, gpio_out, gpio_en; 652 uint16_t status; 653 654 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 655 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 656 goto back; 657 658 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 659 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 660 661 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 662 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 663 if (with_pll) { 664 /* Turn off PLL first */ 665 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 666 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 667 } 668 669 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 670 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 671 DELAY(1000); 672 673 if (with_pll) { 674 /* Turn on PLL */ 675 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 676 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 677 DELAY(5000); 678 } 679 680 back: 681 /* Clear "Signaled Target Abort" */ 682 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 683 status &= ~PCIM_STATUS_STABORT; 684 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 685 } 686 687 static int 688 bwi_power_off(struct bwi_softc *sc, int with_pll) 689 { 690 uint32_t gpio_out, gpio_en; 691 692 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 693 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 694 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 695 696 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 697 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 698 if (with_pll) { 699 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 700 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 701 } 702 703 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 704 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 705 return 0; 706 } 707 708 int 709 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 710 struct bwi_regwin **old_rw) 711 { 712 int error; 713 714 if (old_rw != NULL) 715 *old_rw = NULL; 716 717 if (!BWI_REGWIN_EXIST(rw)) 718 return EINVAL; 719 720 if (sc->sc_cur_regwin != rw) { 721 error = bwi_regwin_select(sc, rw->rw_id); 722 if (error) { 723 device_printf(sc->sc_dev, "can't select regwin %d\n", 724 rw->rw_id); 725 return error; 726 } 727 } 728 729 if (old_rw != NULL) 730 *old_rw = sc->sc_cur_regwin; 731 sc->sc_cur_regwin = rw; 732 return 0; 733 } 734 735 static int 736 bwi_regwin_select(struct bwi_softc *sc, int id) 737 { 738 uint32_t win = BWI_PCIM_REGWIN(id); 739 int i; 740 741 #define RETRY_MAX 50 742 for (i = 0; i < RETRY_MAX; ++i) { 743 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 744 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 745 return 0; 746 DELAY(10); 747 } 748 #undef RETRY_MAX 749 750 return ENXIO; 751 } 752 753 static void 754 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 755 { 756 uint32_t val; 757 758 val = CSR_READ_4(sc, BWI_ID_HI); 759 *type = BWI_ID_HI_REGWIN_TYPE(val); 760 *rev = BWI_ID_HI_REGWIN_REV(val); 761 762 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 763 "vendor 0x%04x\n", *type, *rev, 764 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 765 } 766 767 static int 768 bwi_bbp_attach(struct bwi_softc *sc) 769 { 770 uint16_t bbp_id, rw_type; 771 uint8_t rw_rev; 772 uint32_t info; 773 int error, nregwin, i; 774 775 /* 776 * Get 0th regwin information 777 * NOTE: 0th regwin should exist 778 */ 779 error = bwi_regwin_select(sc, 0); 780 if (error) { 781 device_printf(sc->sc_dev, "can't select regwin 0\n"); 782 return error; 783 } 784 bwi_regwin_info(sc, &rw_type, &rw_rev); 785 786 /* 787 * Find out BBP id 788 */ 789 bbp_id = 0; 790 info = 0; 791 if (rw_type == BWI_REGWIN_T_COM) { 792 info = CSR_READ_4(sc, BWI_INFO); 793 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 794 795 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 796 797 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 798 } else { 799 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 800 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 801 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 802 bbp_id = bwi_bbpid_map[i].bbp_id; 803 break; 804 } 805 } 806 if (bbp_id == 0) { 807 device_printf(sc->sc_dev, "no BBP id for device id " 808 "0x%04x\n", sc->sc_pci_did); 809 return ENXIO; 810 } 811 812 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 813 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 814 } 815 816 /* 817 * Find out number of regwins 818 */ 819 nregwin = 0; 820 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 821 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 822 } else { 823 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 824 if (bwi_regwin_count[i].bbp_id == bbp_id) { 825 nregwin = bwi_regwin_count[i].nregwin; 826 break; 827 } 828 } 829 if (nregwin == 0) { 830 device_printf(sc->sc_dev, "no number of win for " 831 "BBP id 0x%04x\n", bbp_id); 832 return ENXIO; 833 } 834 } 835 836 /* Record BBP id/rev for later using */ 837 sc->sc_bbp_id = bbp_id; 838 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 839 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 840 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 841 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 842 843 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 844 nregwin, sc->sc_cap); 845 846 /* 847 * Create rest of the regwins 848 */ 849 850 /* Don't re-create common regwin, if it is already created */ 851 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 852 853 for (; i < nregwin; ++i) { 854 /* 855 * Get regwin information 856 */ 857 error = bwi_regwin_select(sc, i); 858 if (error) { 859 device_printf(sc->sc_dev, 860 "can't select regwin %d\n", i); 861 return error; 862 } 863 bwi_regwin_info(sc, &rw_type, &rw_rev); 864 865 /* 866 * Try attach: 867 * 1) Bus (PCI/PCIE) regwin 868 * 2) MAC regwin 869 * Ignore rest types of regwin 870 */ 871 if (rw_type == BWI_REGWIN_T_BUSPCI || 872 rw_type == BWI_REGWIN_T_BUSPCIE) { 873 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 874 device_printf(sc->sc_dev, 875 "bus regwin already exists\n"); 876 } else { 877 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 878 rw_type, rw_rev); 879 } 880 } else if (rw_type == BWI_REGWIN_T_MAC) { 881 /* XXX ignore return value */ 882 bwi_mac_attach(sc, i, rw_rev); 883 } 884 } 885 886 /* At least one MAC shold exist */ 887 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 888 device_printf(sc->sc_dev, "no MAC was found\n"); 889 return ENXIO; 890 } 891 KASSERT(sc->sc_nmac > 0, ("no mac's")); 892 893 /* Bus regwin must exist */ 894 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 895 device_printf(sc->sc_dev, "no bus regwin was found\n"); 896 return ENXIO; 897 } 898 899 /* Start with first MAC */ 900 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 901 if (error) 902 return error; 903 904 return 0; 905 } 906 907 int 908 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 909 { 910 struct bwi_regwin *old, *bus; 911 uint32_t val; 912 int error; 913 914 bus = &sc->sc_bus_regwin; 915 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 916 917 /* 918 * Tell bus to generate requested interrupts 919 */ 920 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 921 /* 922 * NOTE: Read BWI_FLAGS from MAC regwin 923 */ 924 val = CSR_READ_4(sc, BWI_FLAGS); 925 926 error = bwi_regwin_switch(sc, bus, &old); 927 if (error) 928 return error; 929 930 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 931 } else { 932 uint32_t mac_mask; 933 934 mac_mask = 1 << mac->mac_id; 935 936 error = bwi_regwin_switch(sc, bus, &old); 937 if (error) 938 return error; 939 940 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 941 val |= mac_mask << 8; 942 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 943 } 944 945 if (sc->sc_flags & BWI_F_BUS_INITED) 946 goto back; 947 948 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 949 /* 950 * Enable prefetch and burst 951 */ 952 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 953 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 954 955 if (bus->rw_rev < 5) { 956 struct bwi_regwin *com = &sc->sc_com_regwin; 957 958 /* 959 * Configure timeouts for bus operation 960 */ 961 962 /* 963 * Set service timeout and request timeout 964 */ 965 CSR_SETBITS_4(sc, BWI_CONF_LO, 966 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 967 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 968 969 /* 970 * If there is common regwin, we switch to that regwin 971 * and switch back to bus regwin once we have done. 972 */ 973 if (BWI_REGWIN_EXIST(com)) { 974 error = bwi_regwin_switch(sc, com, NULL); 975 if (error) 976 return error; 977 } 978 979 /* Let bus know what we have changed */ 980 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 981 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 982 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 983 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 984 985 if (BWI_REGWIN_EXIST(com)) { 986 error = bwi_regwin_switch(sc, bus, NULL); 987 if (error) 988 return error; 989 } 990 } else if (bus->rw_rev >= 11) { 991 /* 992 * Enable memory read multiple 993 */ 994 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 995 } 996 } else { 997 /* TODO:PCIE */ 998 } 999 1000 sc->sc_flags |= BWI_F_BUS_INITED; 1001 back: 1002 return bwi_regwin_switch(sc, old, NULL); 1003 } 1004 1005 static void 1006 bwi_get_card_flags(struct bwi_softc *sc) 1007 { 1008 #define PCI_VENDOR_APPLE 0x106b 1009 #define PCI_VENDOR_DELL 0x1028 1010 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1011 if (sc->sc_card_flags == 0xffff) 1012 sc->sc_card_flags = 0; 1013 1014 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1015 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1016 sc->sc_pci_revid == 0x74) 1017 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1018 1019 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1020 sc->sc_pci_subdid == 0x4e && /* XXX */ 1021 sc->sc_pci_revid > 0x40) 1022 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1023 1024 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1025 #undef PCI_VENDOR_DELL 1026 #undef PCI_VENDOR_APPLE 1027 } 1028 1029 static void 1030 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1031 { 1032 int i; 1033 1034 for (i = 0; i < 3; ++i) { 1035 *((uint16_t *)eaddr + i) = 1036 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1037 } 1038 } 1039 1040 static void 1041 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1042 { 1043 struct bwi_regwin *com; 1044 uint32_t val; 1045 u_int div; 1046 int src; 1047 1048 bzero(freq, sizeof(*freq)); 1049 com = &sc->sc_com_regwin; 1050 1051 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1052 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1053 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1054 1055 /* 1056 * Calculate clock frequency 1057 */ 1058 src = -1; 1059 div = 0; 1060 if (com->rw_rev < 6) { 1061 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1062 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1063 src = BWI_CLKSRC_PCI; 1064 div = 64; 1065 } else { 1066 src = BWI_CLKSRC_CS_OSC; 1067 div = 32; 1068 } 1069 } else if (com->rw_rev < 10) { 1070 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1071 1072 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1073 if (src == BWI_CLKSRC_LP_OSC) { 1074 div = 1; 1075 } else { 1076 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1077 1078 /* Unknown source */ 1079 if (src >= BWI_CLKSRC_MAX) 1080 src = BWI_CLKSRC_CS_OSC; 1081 } 1082 } else { 1083 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1084 1085 src = BWI_CLKSRC_CS_OSC; 1086 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1087 } 1088 1089 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1090 KASSERT(div != 0, ("div zero")); 1091 1092 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1093 src == BWI_CLKSRC_PCI ? "PCI" : 1094 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1095 1096 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1097 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1098 1099 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1100 freq->clkfreq_min, freq->clkfreq_max); 1101 } 1102 1103 static int 1104 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1105 { 1106 struct bwi_regwin *old, *com; 1107 uint32_t clk_ctrl, clk_src; 1108 int error, pwr_off = 0; 1109 1110 com = &sc->sc_com_regwin; 1111 if (!BWI_REGWIN_EXIST(com)) 1112 return 0; 1113 1114 if (com->rw_rev >= 10 || com->rw_rev < 6) 1115 return 0; 1116 1117 /* 1118 * For common regwin whose rev is [6, 10), the chip 1119 * must be capable to change clock mode. 1120 */ 1121 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1122 return 0; 1123 1124 error = bwi_regwin_switch(sc, com, &old); 1125 if (error) 1126 return error; 1127 1128 if (clk_mode == BWI_CLOCK_MODE_FAST) 1129 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1130 1131 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1132 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1133 1134 switch (clk_mode) { 1135 case BWI_CLOCK_MODE_FAST: 1136 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1137 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1138 break; 1139 case BWI_CLOCK_MODE_SLOW: 1140 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1141 break; 1142 case BWI_CLOCK_MODE_DYN: 1143 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1144 BWI_CLOCK_CTRL_IGNPLL | 1145 BWI_CLOCK_CTRL_NODYN); 1146 if (clk_src != BWI_CLKSRC_CS_OSC) { 1147 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1148 pwr_off = 1; 1149 } 1150 break; 1151 } 1152 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1153 1154 if (pwr_off) 1155 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1156 1157 return bwi_regwin_switch(sc, old, NULL); 1158 } 1159 1160 static int 1161 bwi_set_clock_delay(struct bwi_softc *sc) 1162 { 1163 struct bwi_regwin *old, *com; 1164 int error; 1165 1166 com = &sc->sc_com_regwin; 1167 if (!BWI_REGWIN_EXIST(com)) 1168 return 0; 1169 1170 error = bwi_regwin_switch(sc, com, &old); 1171 if (error) 1172 return error; 1173 1174 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1175 if (sc->sc_bbp_rev == 0) 1176 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1177 else if (sc->sc_bbp_rev == 1) 1178 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1179 } 1180 1181 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1182 if (com->rw_rev >= 10) { 1183 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1184 } else { 1185 struct bwi_clock_freq freq; 1186 1187 bwi_get_clock_freq(sc, &freq); 1188 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1189 howmany(freq.clkfreq_max * 150, 1000000)); 1190 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1191 howmany(freq.clkfreq_max * 15, 1000000)); 1192 } 1193 } 1194 1195 return bwi_regwin_switch(sc, old, NULL); 1196 } 1197 1198 static void 1199 bwi_init(struct bwi_softc *sc) 1200 { 1201 struct ieee80211com *ic = &sc->sc_ic; 1202 1203 BWI_LOCK(sc); 1204 bwi_init_statechg(sc, 1); 1205 BWI_UNLOCK(sc); 1206 1207 if (sc->sc_flags & BWI_F_RUNNING) 1208 ieee80211_start_all(ic); /* start all vap's */ 1209 } 1210 1211 static void 1212 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1213 { 1214 struct bwi_mac *mac; 1215 int error; 1216 1217 BWI_ASSERT_LOCKED(sc); 1218 1219 bwi_stop_locked(sc, statechg); 1220 1221 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1222 1223 /* TODO: 2 MAC */ 1224 1225 mac = &sc->sc_mac[0]; 1226 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1227 if (error) { 1228 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1229 __func__, error); 1230 goto bad; 1231 } 1232 error = bwi_mac_init(mac); 1233 if (error) { 1234 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1235 __func__, error); 1236 goto bad; 1237 } 1238 1239 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1240 1241 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1242 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1243 1244 bwi_mac_reset_hwkeys(mac); 1245 1246 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1247 int i; 1248 1249 #define NRETRY 1000 1250 /* 1251 * Drain any possible pending TX status 1252 */ 1253 for (i = 0; i < NRETRY; ++i) { 1254 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1255 BWI_TXSTATUS0_VALID) == 0) 1256 break; 1257 CSR_READ_4(sc, BWI_TXSTATUS1); 1258 } 1259 if (i == NRETRY) 1260 device_printf(sc->sc_dev, 1261 "%s: can't drain TX status\n", __func__); 1262 #undef NRETRY 1263 } 1264 1265 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1266 bwi_mac_updateslot(mac, 1); 1267 1268 /* Start MAC */ 1269 error = bwi_mac_start(mac); 1270 if (error) { 1271 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1272 __func__, error); 1273 goto bad; 1274 } 1275 1276 /* Clear stop flag before enabling interrupt */ 1277 sc->sc_flags &= ~BWI_F_STOP; 1278 sc->sc_flags |= BWI_F_RUNNING; 1279 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1280 1281 /* Enable intrs */ 1282 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1283 return; 1284 bad: 1285 bwi_stop_locked(sc, 1); 1286 } 1287 1288 static void 1289 bwi_parent(struct ieee80211com *ic) 1290 { 1291 struct bwi_softc *sc = ic->ic_softc; 1292 int startall = 0; 1293 1294 BWI_LOCK(sc); 1295 if (ic->ic_nrunning > 0) { 1296 struct bwi_mac *mac; 1297 int promisc = -1; 1298 1299 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1300 ("current regwin type %d", 1301 sc->sc_cur_regwin->rw_type)); 1302 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1303 1304 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1305 promisc = 1; 1306 sc->sc_flags |= BWI_F_PROMISC; 1307 } else if (ic->ic_promisc == 0 && 1308 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1309 promisc = 0; 1310 sc->sc_flags &= ~BWI_F_PROMISC; 1311 } 1312 1313 if (promisc >= 0) 1314 bwi_mac_set_promisc(mac, promisc); 1315 } 1316 if (ic->ic_nrunning > 0) { 1317 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1318 bwi_init_statechg(sc, 1); 1319 startall = 1; 1320 } 1321 } else if (sc->sc_flags & BWI_F_RUNNING) 1322 bwi_stop_locked(sc, 1); 1323 BWI_UNLOCK(sc); 1324 if (startall) 1325 ieee80211_start_all(ic); 1326 } 1327 1328 static int 1329 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1330 { 1331 struct bwi_softc *sc = ic->ic_softc; 1332 int error; 1333 1334 BWI_LOCK(sc); 1335 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1336 BWI_UNLOCK(sc); 1337 return (ENXIO); 1338 } 1339 error = mbufq_enqueue(&sc->sc_snd, m); 1340 if (error) { 1341 BWI_UNLOCK(sc); 1342 return (error); 1343 } 1344 bwi_start_locked(sc); 1345 BWI_UNLOCK(sc); 1346 return (0); 1347 } 1348 1349 static void 1350 bwi_start_locked(struct bwi_softc *sc) 1351 { 1352 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1353 struct ieee80211_frame *wh; 1354 struct ieee80211_node *ni; 1355 struct mbuf *m; 1356 int trans, idx; 1357 1358 BWI_ASSERT_LOCKED(sc); 1359 1360 trans = 0; 1361 idx = tbd->tbd_idx; 1362 1363 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1364 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1365 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1366 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1367 wh = mtod(m, struct ieee80211_frame *); 1368 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1369 ieee80211_crypto_encap(ni, m) == NULL) { 1370 if_inc_counter(ni->ni_vap->iv_ifp, 1371 IFCOUNTER_OERRORS, 1); 1372 ieee80211_free_node(ni); 1373 m_freem(m); 1374 continue; 1375 } 1376 if (bwi_encap(sc, idx, m, ni) != 0) { 1377 /* 'm' is freed in bwi_encap() if we reach here */ 1378 if (ni != NULL) { 1379 if_inc_counter(ni->ni_vap->iv_ifp, 1380 IFCOUNTER_OERRORS, 1); 1381 ieee80211_free_node(ni); 1382 } else 1383 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1384 continue; 1385 } 1386 trans = 1; 1387 tbd->tbd_used++; 1388 idx = (idx + 1) % BWI_TX_NDESC; 1389 } 1390 1391 tbd->tbd_idx = idx; 1392 if (trans) 1393 sc->sc_tx_timer = 5; 1394 } 1395 1396 static int 1397 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1398 const struct ieee80211_bpf_params *params) 1399 { 1400 struct ieee80211com *ic = ni->ni_ic; 1401 struct bwi_softc *sc = ic->ic_softc; 1402 /* XXX wme? */ 1403 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1404 int idx, error; 1405 1406 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1407 m_freem(m); 1408 return ENETDOWN; 1409 } 1410 1411 BWI_LOCK(sc); 1412 idx = tbd->tbd_idx; 1413 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1414 if (params == NULL) { 1415 /* 1416 * Legacy path; interpret frame contents to decide 1417 * precisely how to send the frame. 1418 */ 1419 error = bwi_encap(sc, idx, m, ni); 1420 } else { 1421 /* 1422 * Caller supplied explicit parameters to use in 1423 * sending the frame. 1424 */ 1425 error = bwi_encap_raw(sc, idx, m, ni, params); 1426 } 1427 if (error == 0) { 1428 tbd->tbd_used++; 1429 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1430 sc->sc_tx_timer = 5; 1431 } 1432 BWI_UNLOCK(sc); 1433 return error; 1434 } 1435 1436 static void 1437 bwi_watchdog(void *arg) 1438 { 1439 struct bwi_softc *sc; 1440 1441 sc = arg; 1442 BWI_ASSERT_LOCKED(sc); 1443 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1444 device_printf(sc->sc_dev, "watchdog timeout\n"); 1445 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1446 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1447 } 1448 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1449 } 1450 1451 static void 1452 bwi_stop(struct bwi_softc *sc, int statechg) 1453 { 1454 BWI_LOCK(sc); 1455 bwi_stop_locked(sc, statechg); 1456 BWI_UNLOCK(sc); 1457 } 1458 1459 static void 1460 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1461 { 1462 struct bwi_mac *mac; 1463 int i, error, pwr_off = 0; 1464 1465 BWI_ASSERT_LOCKED(sc); 1466 1467 callout_stop(&sc->sc_calib_ch); 1468 callout_stop(&sc->sc_led_blink_ch); 1469 sc->sc_led_blinking = 0; 1470 sc->sc_flags |= BWI_F_STOP; 1471 1472 if (sc->sc_flags & BWI_F_RUNNING) { 1473 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1474 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1475 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1476 1477 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1478 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1479 bwi_mac_stop(mac); 1480 } 1481 1482 for (i = 0; i < sc->sc_nmac; ++i) { 1483 struct bwi_regwin *old_rw; 1484 1485 mac = &sc->sc_mac[i]; 1486 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1487 continue; 1488 1489 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1490 if (error) 1491 continue; 1492 1493 bwi_mac_shutdown(mac); 1494 pwr_off = 1; 1495 1496 bwi_regwin_switch(sc, old_rw, NULL); 1497 } 1498 1499 if (pwr_off) 1500 bwi_bbp_power_off(sc); 1501 1502 sc->sc_tx_timer = 0; 1503 callout_stop(&sc->sc_watchdog_timer); 1504 sc->sc_flags &= ~BWI_F_RUNNING; 1505 } 1506 1507 void 1508 bwi_intr(void *xsc) 1509 { 1510 struct bwi_softc *sc = xsc; 1511 struct bwi_mac *mac; 1512 uint32_t intr_status; 1513 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1514 int i, txrx_error, tx = 0, rx_data = -1; 1515 1516 BWI_LOCK(sc); 1517 1518 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1519 (sc->sc_flags & BWI_F_STOP)) { 1520 BWI_UNLOCK(sc); 1521 return; 1522 } 1523 /* 1524 * Get interrupt status 1525 */ 1526 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1527 if (intr_status == 0xffffffff) { /* Not for us */ 1528 BWI_UNLOCK(sc); 1529 return; 1530 } 1531 1532 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1533 1534 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1535 if (intr_status == 0) { /* Nothing is interesting */ 1536 BWI_UNLOCK(sc); 1537 return; 1538 } 1539 1540 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1541 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1542 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1543 1544 txrx_error = 0; 1545 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1546 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1547 uint32_t mask; 1548 1549 if (BWI_TXRX_IS_RX(i)) 1550 mask = BWI_TXRX_RX_INTRS; 1551 else 1552 mask = BWI_TXRX_TX_INTRS; 1553 1554 txrx_intr_status[i] = 1555 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1556 1557 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1558 i, txrx_intr_status[i]); 1559 1560 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1561 device_printf(sc->sc_dev, 1562 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1563 __func__, i, txrx_intr_status[i]); 1564 txrx_error = 1; 1565 } 1566 } 1567 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1568 1569 /* 1570 * Acknowledge interrupt 1571 */ 1572 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1573 1574 for (i = 0; i < BWI_TXRX_NRING; ++i) 1575 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1576 1577 /* Disable all interrupts */ 1578 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1579 1580 /* 1581 * http://bcm-specs.sipsolutions.net/Interrupts 1582 * Says for this bit (0x800): 1583 * "Fatal Error 1584 * 1585 * We got this one while testing things when by accident the 1586 * template ram wasn't set to big endian when it should have 1587 * been after writing the initial values. It keeps on being 1588 * triggered, the only way to stop it seems to shut down the 1589 * chip." 1590 * 1591 * Suggesting that we should never get it and if we do we're not 1592 * feeding TX packets into the MAC correctly if we do... Apparently, 1593 * it is valid only on mac version 5 and higher, but I couldn't 1594 * find a reference for that... Since I see them from time to time 1595 * on my card, this suggests an error in the tx path still... 1596 */ 1597 if (intr_status & BWI_INTR_PHY_TXERR) { 1598 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1599 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1600 __func__); 1601 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1602 BWI_UNLOCK(sc); 1603 return; 1604 } 1605 } 1606 1607 if (txrx_error) { 1608 /* TODO: reset device */ 1609 } 1610 1611 if (intr_status & BWI_INTR_TBTT) 1612 bwi_mac_config_ps(mac); 1613 1614 if (intr_status & BWI_INTR_EO_ATIM) 1615 device_printf(sc->sc_dev, "EO_ATIM\n"); 1616 1617 if (intr_status & BWI_INTR_PMQ) { 1618 for (;;) { 1619 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1620 break; 1621 } 1622 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1623 } 1624 1625 if (intr_status & BWI_INTR_NOISE) 1626 device_printf(sc->sc_dev, "intr noise\n"); 1627 1628 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1629 rx_data = sc->sc_rxeof(sc); 1630 if (sc->sc_flags & BWI_F_STOP) { 1631 BWI_UNLOCK(sc); 1632 return; 1633 } 1634 } 1635 1636 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1637 sc->sc_txeof_status(sc); 1638 tx = 1; 1639 } 1640 1641 if (intr_status & BWI_INTR_TX_DONE) { 1642 bwi_txeof(sc); 1643 tx = 1; 1644 } 1645 1646 /* Re-enable interrupts */ 1647 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1648 1649 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1650 int evt = BWI_LED_EVENT_NONE; 1651 1652 if (tx && rx_data > 0) { 1653 if (sc->sc_rx_rate > sc->sc_tx_rate) 1654 evt = BWI_LED_EVENT_RX; 1655 else 1656 evt = BWI_LED_EVENT_TX; 1657 } else if (tx) { 1658 evt = BWI_LED_EVENT_TX; 1659 } else if (rx_data > 0) { 1660 evt = BWI_LED_EVENT_RX; 1661 } else if (rx_data == 0) { 1662 evt = BWI_LED_EVENT_POLL; 1663 } 1664 1665 if (evt != BWI_LED_EVENT_NONE) 1666 bwi_led_event(sc, evt); 1667 } 1668 1669 BWI_UNLOCK(sc); 1670 } 1671 1672 static void 1673 bwi_scan_start(struct ieee80211com *ic) 1674 { 1675 struct bwi_softc *sc = ic->ic_softc; 1676 1677 BWI_LOCK(sc); 1678 /* Enable MAC beacon promiscuity */ 1679 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1680 BWI_UNLOCK(sc); 1681 } 1682 1683 static void 1684 bwi_getradiocaps(struct ieee80211com *ic, 1685 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1686 { 1687 struct bwi_softc *sc = ic->ic_softc; 1688 struct bwi_mac *mac; 1689 struct bwi_phy *phy; 1690 uint8_t bands[IEEE80211_MODE_BYTES]; 1691 1692 /* 1693 * XXX First MAC is known to exist 1694 * TODO2 1695 */ 1696 mac = &sc->sc_mac[0]; 1697 phy = &mac->mac_phy; 1698 1699 memset(bands, 0, sizeof(bands)); 1700 switch (phy->phy_mode) { 1701 case IEEE80211_MODE_11G: 1702 setbit(bands, IEEE80211_MODE_11G); 1703 /* FALLTHROUGH */ 1704 case IEEE80211_MODE_11B: 1705 setbit(bands, IEEE80211_MODE_11B); 1706 break; 1707 case IEEE80211_MODE_11A: 1708 /* TODO:11A */ 1709 setbit(bands, IEEE80211_MODE_11A); 1710 device_printf(sc->sc_dev, "no 11a support\n"); 1711 return; 1712 default: 1713 panic("unknown phymode %d\n", phy->phy_mode); 1714 } 1715 1716 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 1717 bwi_chan_2ghz, nitems(bwi_chan_2ghz), bands, 0); 1718 } 1719 1720 static void 1721 bwi_set_channel(struct ieee80211com *ic) 1722 { 1723 struct bwi_softc *sc = ic->ic_softc; 1724 struct ieee80211_channel *c = ic->ic_curchan; 1725 struct bwi_mac *mac; 1726 1727 BWI_LOCK(sc); 1728 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1729 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1730 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1731 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1732 1733 sc->sc_rates = ieee80211_get_ratetable(c); 1734 1735 /* 1736 * Setup radio tap channel freq and flags 1737 */ 1738 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1739 htole16(c->ic_freq); 1740 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1741 htole16(c->ic_flags & 0xffff); 1742 1743 BWI_UNLOCK(sc); 1744 } 1745 1746 static void 1747 bwi_scan_end(struct ieee80211com *ic) 1748 { 1749 struct bwi_softc *sc = ic->ic_softc; 1750 1751 BWI_LOCK(sc); 1752 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1753 BWI_UNLOCK(sc); 1754 } 1755 1756 static int 1757 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1758 { 1759 struct bwi_vap *bvp = BWI_VAP(vap); 1760 struct ieee80211com *ic= vap->iv_ic; 1761 struct bwi_softc *sc = ic->ic_softc; 1762 enum ieee80211_state ostate = vap->iv_state; 1763 struct bwi_mac *mac; 1764 int error; 1765 1766 BWI_LOCK(sc); 1767 1768 callout_stop(&sc->sc_calib_ch); 1769 1770 if (nstate == IEEE80211_S_INIT) 1771 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1772 1773 bwi_led_newstate(sc, nstate); 1774 1775 error = bvp->bv_newstate(vap, nstate, arg); 1776 if (error != 0) 1777 goto back; 1778 1779 /* 1780 * Clear the BSSID when we stop a STA 1781 */ 1782 if (vap->iv_opmode == IEEE80211_M_STA) { 1783 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1784 /* 1785 * Clear out the BSSID. If we reassociate to 1786 * the same AP, this will reinialize things 1787 * correctly... 1788 */ 1789 if (ic->ic_opmode == IEEE80211_M_STA && 1790 !(sc->sc_flags & BWI_F_STOP)) 1791 bwi_set_bssid(sc, bwi_zero_addr); 1792 } 1793 } 1794 1795 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1796 /* Nothing to do */ 1797 } else if (nstate == IEEE80211_S_RUN) { 1798 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1799 1800 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1801 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1802 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1803 1804 /* Initial TX power calibration */ 1805 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1806 #ifdef notyet 1807 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1808 #else 1809 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1810 #endif 1811 1812 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1813 } 1814 back: 1815 BWI_UNLOCK(sc); 1816 1817 return error; 1818 } 1819 1820 static int 1821 bwi_media_change(struct ifnet *ifp) 1822 { 1823 int error = ieee80211_media_change(ifp); 1824 /* NB: only the fixed rate can change and that doesn't need a reset */ 1825 return (error == ENETRESET ? 0 : error); 1826 } 1827 1828 static int 1829 bwi_dma_alloc(struct bwi_softc *sc) 1830 { 1831 int error, i, has_txstats; 1832 bus_addr_t lowaddr = 0; 1833 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1834 uint32_t txrx_ctrl_step = 0; 1835 1836 has_txstats = 0; 1837 for (i = 0; i < sc->sc_nmac; ++i) { 1838 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1839 has_txstats = 1; 1840 break; 1841 } 1842 } 1843 1844 switch (sc->sc_bus_space) { 1845 case BWI_BUS_SPACE_30BIT: 1846 case BWI_BUS_SPACE_32BIT: 1847 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1848 lowaddr = BWI_BUS_SPACE_MAXADDR; 1849 else 1850 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1851 desc_sz = sizeof(struct bwi_desc32); 1852 txrx_ctrl_step = 0x20; 1853 1854 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1855 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1856 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1857 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1858 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1859 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1860 sc->sc_rxeof = bwi_rxeof32; 1861 sc->sc_start_tx = bwi_start_tx32; 1862 if (has_txstats) { 1863 sc->sc_init_txstats = bwi_init_txstats32; 1864 sc->sc_free_txstats = bwi_free_txstats32; 1865 sc->sc_txeof_status = bwi_txeof_status32; 1866 } 1867 break; 1868 1869 case BWI_BUS_SPACE_64BIT: 1870 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1871 desc_sz = sizeof(struct bwi_desc64); 1872 txrx_ctrl_step = 0x40; 1873 1874 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1875 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1876 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1877 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1878 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1879 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1880 sc->sc_rxeof = bwi_rxeof64; 1881 sc->sc_start_tx = bwi_start_tx64; 1882 if (has_txstats) { 1883 sc->sc_init_txstats = bwi_init_txstats64; 1884 sc->sc_free_txstats = bwi_free_txstats64; 1885 sc->sc_txeof_status = bwi_txeof_status64; 1886 } 1887 break; 1888 } 1889 1890 KASSERT(lowaddr != 0, ("lowaddr zero")); 1891 KASSERT(desc_sz != 0, ("desc_sz zero")); 1892 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1893 1894 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1895 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1896 1897 /* 1898 * Create top level DMA tag 1899 */ 1900 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1901 BWI_ALIGN, 0, /* alignment, bounds */ 1902 lowaddr, /* lowaddr */ 1903 BUS_SPACE_MAXADDR, /* highaddr */ 1904 NULL, NULL, /* filter, filterarg */ 1905 BUS_SPACE_MAXSIZE, /* maxsize */ 1906 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1907 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1908 0, /* flags */ 1909 NULL, NULL, /* lockfunc, lockarg */ 1910 &sc->sc_parent_dtag); 1911 if (error) { 1912 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1913 return error; 1914 } 1915 1916 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1917 1918 /* 1919 * Create TX ring DMA stuffs 1920 */ 1921 error = bus_dma_tag_create(sc->sc_parent_dtag, 1922 BWI_RING_ALIGN, 0, 1923 BUS_SPACE_MAXADDR, 1924 BUS_SPACE_MAXADDR, 1925 NULL, NULL, 1926 tx_ring_sz, 1927 1, 1928 tx_ring_sz, 1929 0, 1930 NULL, NULL, 1931 &sc->sc_txring_dtag); 1932 if (error) { 1933 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1934 return error; 1935 } 1936 1937 for (i = 0; i < BWI_TX_NRING; ++i) { 1938 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1939 &sc->sc_tx_rdata[i], tx_ring_sz, 1940 TXRX_CTRL(i)); 1941 if (error) { 1942 device_printf(sc->sc_dev, "%dth TX ring " 1943 "DMA alloc failed\n", i); 1944 return error; 1945 } 1946 } 1947 1948 /* 1949 * Create RX ring DMA stuffs 1950 */ 1951 error = bus_dma_tag_create(sc->sc_parent_dtag, 1952 BWI_RING_ALIGN, 0, 1953 BUS_SPACE_MAXADDR, 1954 BUS_SPACE_MAXADDR, 1955 NULL, NULL, 1956 rx_ring_sz, 1957 1, 1958 rx_ring_sz, 1959 0, 1960 NULL, NULL, 1961 &sc->sc_rxring_dtag); 1962 if (error) { 1963 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1964 return error; 1965 } 1966 1967 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1968 rx_ring_sz, TXRX_CTRL(0)); 1969 if (error) { 1970 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1971 return error; 1972 } 1973 1974 if (has_txstats) { 1975 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1976 if (error) { 1977 device_printf(sc->sc_dev, 1978 "TX stats DMA alloc failed\n"); 1979 return error; 1980 } 1981 } 1982 1983 #undef TXRX_CTRL 1984 1985 return bwi_dma_mbuf_create(sc); 1986 } 1987 1988 static void 1989 bwi_dma_free(struct bwi_softc *sc) 1990 { 1991 if (sc->sc_txring_dtag != NULL) { 1992 int i; 1993 1994 for (i = 0; i < BWI_TX_NRING; ++i) { 1995 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1996 1997 if (rd->rdata_desc != NULL) { 1998 bus_dmamap_unload(sc->sc_txring_dtag, 1999 rd->rdata_dmap); 2000 bus_dmamem_free(sc->sc_txring_dtag, 2001 rd->rdata_desc, 2002 rd->rdata_dmap); 2003 } 2004 } 2005 bus_dma_tag_destroy(sc->sc_txring_dtag); 2006 } 2007 2008 if (sc->sc_rxring_dtag != NULL) { 2009 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2010 2011 if (rd->rdata_desc != NULL) { 2012 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2013 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2014 rd->rdata_dmap); 2015 } 2016 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2017 } 2018 2019 bwi_dma_txstats_free(sc); 2020 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2021 2022 if (sc->sc_parent_dtag != NULL) 2023 bus_dma_tag_destroy(sc->sc_parent_dtag); 2024 } 2025 2026 static int 2027 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2028 struct bwi_ring_data *rd, bus_size_t size, 2029 uint32_t txrx_ctrl) 2030 { 2031 int error; 2032 2033 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2034 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2035 &rd->rdata_dmap); 2036 if (error) { 2037 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2038 return error; 2039 } 2040 2041 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2042 bwi_dma_ring_addr, &rd->rdata_paddr, 2043 BUS_DMA_NOWAIT); 2044 if (error) { 2045 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2046 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2047 rd->rdata_desc = NULL; 2048 return error; 2049 } 2050 2051 rd->rdata_txrx_ctrl = txrx_ctrl; 2052 return 0; 2053 } 2054 2055 static int 2056 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2057 bus_size_t desc_sz) 2058 { 2059 struct bwi_txstats_data *st; 2060 bus_size_t dma_size; 2061 int error; 2062 2063 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2064 if (st == NULL) { 2065 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2066 return ENOMEM; 2067 } 2068 sc->sc_txstats = st; 2069 2070 /* 2071 * Create TX stats descriptor DMA stuffs 2072 */ 2073 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2074 2075 error = bus_dma_tag_create(sc->sc_parent_dtag, 2076 BWI_RING_ALIGN, 2077 0, 2078 BUS_SPACE_MAXADDR, 2079 BUS_SPACE_MAXADDR, 2080 NULL, NULL, 2081 dma_size, 2082 1, 2083 dma_size, 2084 0, 2085 NULL, NULL, 2086 &st->stats_ring_dtag); 2087 if (error) { 2088 device_printf(sc->sc_dev, "can't create txstats ring " 2089 "DMA tag\n"); 2090 return error; 2091 } 2092 2093 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2094 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2095 &st->stats_ring_dmap); 2096 if (error) { 2097 device_printf(sc->sc_dev, "can't allocate txstats ring " 2098 "DMA mem\n"); 2099 bus_dma_tag_destroy(st->stats_ring_dtag); 2100 st->stats_ring_dtag = NULL; 2101 return error; 2102 } 2103 2104 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2105 st->stats_ring, dma_size, 2106 bwi_dma_ring_addr, &st->stats_ring_paddr, 2107 BUS_DMA_NOWAIT); 2108 if (error) { 2109 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2110 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2111 st->stats_ring_dmap); 2112 bus_dma_tag_destroy(st->stats_ring_dtag); 2113 st->stats_ring_dtag = NULL; 2114 return error; 2115 } 2116 2117 /* 2118 * Create TX stats DMA stuffs 2119 */ 2120 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2121 BWI_ALIGN); 2122 2123 error = bus_dma_tag_create(sc->sc_parent_dtag, 2124 BWI_ALIGN, 2125 0, 2126 BUS_SPACE_MAXADDR, 2127 BUS_SPACE_MAXADDR, 2128 NULL, NULL, 2129 dma_size, 2130 1, 2131 dma_size, 2132 0, 2133 NULL, NULL, 2134 &st->stats_dtag); 2135 if (error) { 2136 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2137 return error; 2138 } 2139 2140 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2141 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2142 &st->stats_dmap); 2143 if (error) { 2144 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2145 bus_dma_tag_destroy(st->stats_dtag); 2146 st->stats_dtag = NULL; 2147 return error; 2148 } 2149 2150 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2151 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2152 BUS_DMA_NOWAIT); 2153 if (error) { 2154 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2155 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2156 bus_dma_tag_destroy(st->stats_dtag); 2157 st->stats_dtag = NULL; 2158 return error; 2159 } 2160 2161 st->stats_ctrl_base = ctrl_base; 2162 return 0; 2163 } 2164 2165 static void 2166 bwi_dma_txstats_free(struct bwi_softc *sc) 2167 { 2168 struct bwi_txstats_data *st; 2169 2170 if (sc->sc_txstats == NULL) 2171 return; 2172 st = sc->sc_txstats; 2173 2174 if (st->stats_ring_dtag != NULL) { 2175 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2176 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2177 st->stats_ring_dmap); 2178 bus_dma_tag_destroy(st->stats_ring_dtag); 2179 } 2180 2181 if (st->stats_dtag != NULL) { 2182 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2183 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2184 bus_dma_tag_destroy(st->stats_dtag); 2185 } 2186 2187 free(st, M_DEVBUF); 2188 } 2189 2190 static void 2191 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2192 { 2193 KASSERT(nseg == 1, ("too many segments\n")); 2194 *((bus_addr_t *)arg) = seg->ds_addr; 2195 } 2196 2197 static int 2198 bwi_dma_mbuf_create(struct bwi_softc *sc) 2199 { 2200 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2201 int i, j, k, ntx, error; 2202 2203 /* 2204 * Create TX/RX mbuf DMA tag 2205 */ 2206 error = bus_dma_tag_create(sc->sc_parent_dtag, 2207 1, 2208 0, 2209 BUS_SPACE_MAXADDR, 2210 BUS_SPACE_MAXADDR, 2211 NULL, NULL, 2212 MCLBYTES, 2213 1, 2214 MCLBYTES, 2215 BUS_DMA_ALLOCNOW, 2216 NULL, NULL, 2217 &sc->sc_buf_dtag); 2218 if (error) { 2219 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2220 return error; 2221 } 2222 2223 ntx = 0; 2224 2225 /* 2226 * Create TX mbuf DMA map 2227 */ 2228 for (i = 0; i < BWI_TX_NRING; ++i) { 2229 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2230 2231 for (j = 0; j < BWI_TX_NDESC; ++j) { 2232 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2233 &tbd->tbd_buf[j].tb_dmap); 2234 if (error) { 2235 device_printf(sc->sc_dev, "can't create " 2236 "%dth tbd, %dth DMA map\n", i, j); 2237 2238 ntx = i; 2239 for (k = 0; k < j; ++k) { 2240 bus_dmamap_destroy(sc->sc_buf_dtag, 2241 tbd->tbd_buf[k].tb_dmap); 2242 } 2243 goto fail; 2244 } 2245 } 2246 } 2247 ntx = BWI_TX_NRING; 2248 2249 /* 2250 * Create RX mbuf DMA map and a spare DMA map 2251 */ 2252 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2253 &rbd->rbd_tmp_dmap); 2254 if (error) { 2255 device_printf(sc->sc_dev, 2256 "can't create spare RX buf DMA map\n"); 2257 goto fail; 2258 } 2259 2260 for (j = 0; j < BWI_RX_NDESC; ++j) { 2261 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2262 &rbd->rbd_buf[j].rb_dmap); 2263 if (error) { 2264 device_printf(sc->sc_dev, "can't create %dth " 2265 "RX buf DMA map\n", j); 2266 2267 for (k = 0; k < j; ++k) { 2268 bus_dmamap_destroy(sc->sc_buf_dtag, 2269 rbd->rbd_buf[j].rb_dmap); 2270 } 2271 bus_dmamap_destroy(sc->sc_buf_dtag, 2272 rbd->rbd_tmp_dmap); 2273 goto fail; 2274 } 2275 } 2276 2277 return 0; 2278 fail: 2279 bwi_dma_mbuf_destroy(sc, ntx, 0); 2280 return error; 2281 } 2282 2283 static void 2284 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2285 { 2286 int i, j; 2287 2288 if (sc->sc_buf_dtag == NULL) 2289 return; 2290 2291 for (i = 0; i < ntx; ++i) { 2292 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2293 2294 for (j = 0; j < BWI_TX_NDESC; ++j) { 2295 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2296 2297 if (tb->tb_mbuf != NULL) { 2298 bus_dmamap_unload(sc->sc_buf_dtag, 2299 tb->tb_dmap); 2300 m_freem(tb->tb_mbuf); 2301 } 2302 if (tb->tb_ni != NULL) 2303 ieee80211_free_node(tb->tb_ni); 2304 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2305 } 2306 } 2307 2308 if (nrx) { 2309 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2310 2311 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2312 for (j = 0; j < BWI_RX_NDESC; ++j) { 2313 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2314 2315 if (rb->rb_mbuf != NULL) { 2316 bus_dmamap_unload(sc->sc_buf_dtag, 2317 rb->rb_dmap); 2318 m_freem(rb->rb_mbuf); 2319 } 2320 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2321 } 2322 } 2323 2324 bus_dma_tag_destroy(sc->sc_buf_dtag); 2325 sc->sc_buf_dtag = NULL; 2326 } 2327 2328 static void 2329 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2330 { 2331 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2332 } 2333 2334 static void 2335 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2336 { 2337 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2338 } 2339 2340 static int 2341 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2342 { 2343 struct bwi_ring_data *rd; 2344 struct bwi_txbuf_data *tbd; 2345 uint32_t val, addr_hi, addr_lo; 2346 2347 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2348 rd = &sc->sc_tx_rdata[ring_idx]; 2349 tbd = &sc->sc_tx_bdata[ring_idx]; 2350 2351 tbd->tbd_idx = 0; 2352 tbd->tbd_used = 0; 2353 2354 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2355 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2356 BUS_DMASYNC_PREWRITE); 2357 2358 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2359 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2360 2361 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2362 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2363 BWI_TXRX32_RINGINFO_FUNC_MASK); 2364 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2365 2366 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2367 BWI_TXRX32_CTRL_ENABLE; 2368 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2369 2370 return 0; 2371 } 2372 2373 static void 2374 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2375 bus_addr_t paddr, int hdr_size, int ndesc) 2376 { 2377 uint32_t val, addr_hi, addr_lo; 2378 2379 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2380 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2381 2382 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2383 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2384 BWI_TXRX32_RINGINFO_FUNC_MASK); 2385 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2386 2387 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2388 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2389 BWI_TXRX32_CTRL_ENABLE; 2390 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2391 2392 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2393 (ndesc - 1) * sizeof(struct bwi_desc32)); 2394 } 2395 2396 static int 2397 bwi_init_rx_ring32(struct bwi_softc *sc) 2398 { 2399 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2400 int i, error; 2401 2402 sc->sc_rx_bdata.rbd_idx = 0; 2403 2404 for (i = 0; i < BWI_RX_NDESC; ++i) { 2405 error = bwi_newbuf(sc, i, 1); 2406 if (error) { 2407 device_printf(sc->sc_dev, 2408 "can't allocate %dth RX buffer\n", i); 2409 return error; 2410 } 2411 } 2412 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2413 BUS_DMASYNC_PREWRITE); 2414 2415 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2416 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2417 return 0; 2418 } 2419 2420 static int 2421 bwi_init_txstats32(struct bwi_softc *sc) 2422 { 2423 struct bwi_txstats_data *st = sc->sc_txstats; 2424 bus_addr_t stats_paddr; 2425 int i; 2426 2427 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2428 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2429 2430 st->stats_idx = 0; 2431 2432 stats_paddr = st->stats_paddr; 2433 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2434 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2435 stats_paddr, sizeof(struct bwi_txstats), 0); 2436 stats_paddr += sizeof(struct bwi_txstats); 2437 } 2438 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2439 BUS_DMASYNC_PREWRITE); 2440 2441 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2442 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2443 return 0; 2444 } 2445 2446 static void 2447 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2448 int buf_len) 2449 { 2450 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2451 2452 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2453 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2454 paddr, buf_len, 0); 2455 } 2456 2457 static void 2458 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2459 int buf_idx, bus_addr_t paddr, int buf_len) 2460 { 2461 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2462 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2463 paddr, buf_len, 1); 2464 } 2465 2466 static int 2467 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2468 { 2469 /* TODO:64 */ 2470 return EOPNOTSUPP; 2471 } 2472 2473 static int 2474 bwi_init_rx_ring64(struct bwi_softc *sc) 2475 { 2476 /* TODO:64 */ 2477 return EOPNOTSUPP; 2478 } 2479 2480 static int 2481 bwi_init_txstats64(struct bwi_softc *sc) 2482 { 2483 /* TODO:64 */ 2484 return EOPNOTSUPP; 2485 } 2486 2487 static void 2488 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2489 int buf_len) 2490 { 2491 /* TODO:64 */ 2492 } 2493 2494 static void 2495 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2496 int buf_idx, bus_addr_t paddr, int buf_len) 2497 { 2498 /* TODO:64 */ 2499 } 2500 2501 static void 2502 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2503 bus_size_t mapsz __unused, int error) 2504 { 2505 if (!error) { 2506 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2507 *((bus_addr_t *)arg) = seg->ds_addr; 2508 } 2509 } 2510 2511 static int 2512 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2513 { 2514 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2515 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2516 struct bwi_rxbuf_hdr *hdr; 2517 bus_dmamap_t map; 2518 bus_addr_t paddr; 2519 struct mbuf *m; 2520 int error; 2521 2522 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2523 2524 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2525 if (m == NULL) { 2526 error = ENOBUFS; 2527 2528 /* 2529 * If the NIC is up and running, we need to: 2530 * - Clear RX buffer's header. 2531 * - Restore RX descriptor settings. 2532 */ 2533 if (init) 2534 return error; 2535 else 2536 goto back; 2537 } 2538 m->m_len = m->m_pkthdr.len = MCLBYTES; 2539 2540 /* 2541 * Try to load RX buf into temporary DMA map 2542 */ 2543 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2544 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2545 if (error) { 2546 m_freem(m); 2547 2548 /* 2549 * See the comment above 2550 */ 2551 if (init) 2552 return error; 2553 else 2554 goto back; 2555 } 2556 2557 if (!init) 2558 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2559 rxbuf->rb_mbuf = m; 2560 rxbuf->rb_paddr = paddr; 2561 2562 /* 2563 * Swap RX buf's DMA map with the loaded temporary one 2564 */ 2565 map = rxbuf->rb_dmap; 2566 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2567 rbd->rbd_tmp_dmap = map; 2568 2569 back: 2570 /* 2571 * Clear RX buf header 2572 */ 2573 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2574 bzero(hdr, sizeof(*hdr)); 2575 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2576 2577 /* 2578 * Setup RX buf descriptor 2579 */ 2580 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2581 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2582 return error; 2583 } 2584 2585 static void 2586 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2587 const uint8_t *addr) 2588 { 2589 int i; 2590 2591 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2592 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2593 2594 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2595 uint16_t addr_val; 2596 2597 addr_val = (uint16_t)addr[i * 2] | 2598 (((uint16_t)addr[(i * 2) + 1]) << 8); 2599 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2600 } 2601 } 2602 2603 static int 2604 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2605 { 2606 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2607 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2608 struct ieee80211com *ic = &sc->sc_ic; 2609 int idx, rx_data = 0; 2610 2611 idx = rbd->rbd_idx; 2612 while (idx != end_idx) { 2613 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2614 struct bwi_rxbuf_hdr *hdr; 2615 struct ieee80211_frame_min *wh; 2616 struct ieee80211_node *ni; 2617 struct mbuf *m; 2618 uint32_t plcp; 2619 uint16_t flags2; 2620 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2621 2622 m = rb->rb_mbuf; 2623 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2624 BUS_DMASYNC_POSTREAD); 2625 2626 if (bwi_newbuf(sc, idx, 0)) { 2627 counter_u64_add(ic->ic_ierrors, 1); 2628 goto next; 2629 } 2630 2631 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2632 flags2 = le16toh(hdr->rxh_flags2); 2633 2634 hdr_extra = 0; 2635 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2636 hdr_extra = 2; 2637 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2638 2639 buflen = le16toh(hdr->rxh_buflen); 2640 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2641 device_printf(sc->sc_dev, 2642 "%s: zero length data, hdr_extra %d\n", 2643 __func__, hdr_extra); 2644 counter_u64_add(ic->ic_ierrors, 1); 2645 m_freem(m); 2646 goto next; 2647 } 2648 2649 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2650 rssi = bwi_calc_rssi(sc, hdr); 2651 noise = bwi_calc_noise(sc); 2652 2653 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2654 m_adj(m, sizeof(*hdr) + wh_ofs); 2655 2656 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2657 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2658 else 2659 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2660 2661 /* RX radio tap */ 2662 if (ieee80211_radiotap_active(ic)) 2663 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2664 2665 m_adj(m, -IEEE80211_CRC_LEN); 2666 2667 BWI_UNLOCK(sc); 2668 2669 wh = mtod(m, struct ieee80211_frame_min *); 2670 ni = ieee80211_find_rxnode(ic, wh); 2671 if (ni != NULL) { 2672 type = ieee80211_input(ni, m, rssi - noise, noise); 2673 ieee80211_free_node(ni); 2674 } else 2675 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2676 if (type == IEEE80211_FC0_TYPE_DATA) { 2677 rx_data = 1; 2678 sc->sc_rx_rate = rate; 2679 } 2680 2681 BWI_LOCK(sc); 2682 next: 2683 idx = (idx + 1) % BWI_RX_NDESC; 2684 2685 if (sc->sc_flags & BWI_F_STOP) { 2686 /* 2687 * Take the fast lane, don't do 2688 * any damage to softc 2689 */ 2690 return -1; 2691 } 2692 } 2693 2694 rbd->rbd_idx = idx; 2695 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2696 BUS_DMASYNC_PREWRITE); 2697 2698 return rx_data; 2699 } 2700 2701 static int 2702 bwi_rxeof32(struct bwi_softc *sc) 2703 { 2704 uint32_t val, rx_ctrl; 2705 int end_idx, rx_data; 2706 2707 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2708 2709 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2710 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2711 sizeof(struct bwi_desc32); 2712 2713 rx_data = bwi_rxeof(sc, end_idx); 2714 if (rx_data >= 0) { 2715 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2716 end_idx * sizeof(struct bwi_desc32)); 2717 } 2718 return rx_data; 2719 } 2720 2721 static int 2722 bwi_rxeof64(struct bwi_softc *sc) 2723 { 2724 /* TODO:64 */ 2725 return 0; 2726 } 2727 2728 static void 2729 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2730 { 2731 int i; 2732 2733 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2734 2735 #define NRETRY 10 2736 2737 for (i = 0; i < NRETRY; ++i) { 2738 uint32_t status; 2739 2740 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2741 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2742 BWI_RX32_STATUS_STATE_DISABLED) 2743 break; 2744 2745 DELAY(1000); 2746 } 2747 if (i == NRETRY) 2748 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2749 2750 #undef NRETRY 2751 2752 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2753 } 2754 2755 static void 2756 bwi_free_txstats32(struct bwi_softc *sc) 2757 { 2758 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2759 } 2760 2761 static void 2762 bwi_free_rx_ring32(struct bwi_softc *sc) 2763 { 2764 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2765 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2766 int i; 2767 2768 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2769 2770 for (i = 0; i < BWI_RX_NDESC; ++i) { 2771 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2772 2773 if (rb->rb_mbuf != NULL) { 2774 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2775 m_freem(rb->rb_mbuf); 2776 rb->rb_mbuf = NULL; 2777 } 2778 } 2779 } 2780 2781 static void 2782 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2783 { 2784 struct bwi_ring_data *rd; 2785 struct bwi_txbuf_data *tbd; 2786 uint32_t state, val; 2787 int i; 2788 2789 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2790 rd = &sc->sc_tx_rdata[ring_idx]; 2791 tbd = &sc->sc_tx_bdata[ring_idx]; 2792 2793 #define NRETRY 10 2794 2795 for (i = 0; i < NRETRY; ++i) { 2796 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2797 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2798 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2799 state == BWI_TX32_STATUS_STATE_IDLE || 2800 state == BWI_TX32_STATUS_STATE_STOPPED) 2801 break; 2802 2803 DELAY(1000); 2804 } 2805 if (i == NRETRY) { 2806 device_printf(sc->sc_dev, 2807 "%s: wait for TX ring(%d) stable timed out\n", 2808 __func__, ring_idx); 2809 } 2810 2811 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2812 for (i = 0; i < NRETRY; ++i) { 2813 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2814 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2815 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2816 break; 2817 2818 DELAY(1000); 2819 } 2820 if (i == NRETRY) 2821 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2822 __func__, ring_idx); 2823 2824 #undef NRETRY 2825 2826 DELAY(1000); 2827 2828 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2829 2830 for (i = 0; i < BWI_TX_NDESC; ++i) { 2831 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2832 2833 if (tb->tb_mbuf != NULL) { 2834 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2835 m_freem(tb->tb_mbuf); 2836 tb->tb_mbuf = NULL; 2837 } 2838 if (tb->tb_ni != NULL) { 2839 ieee80211_free_node(tb->tb_ni); 2840 tb->tb_ni = NULL; 2841 } 2842 } 2843 } 2844 2845 static void 2846 bwi_free_txstats64(struct bwi_softc *sc) 2847 { 2848 /* TODO:64 */ 2849 } 2850 2851 static void 2852 bwi_free_rx_ring64(struct bwi_softc *sc) 2853 { 2854 /* TODO:64 */ 2855 } 2856 2857 static void 2858 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2859 { 2860 /* TODO:64 */ 2861 } 2862 2863 /* XXX does not belong here */ 2864 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2865 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2866 2867 static __inline void 2868 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2869 { 2870 uint32_t plcp; 2871 2872 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2873 IEEE80211_OFDM_PLCP_RATE_MASK) | 2874 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2875 *plcp0 = htole32(plcp); 2876 } 2877 2878 static __inline void 2879 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2880 uint8_t rate) 2881 { 2882 int len, service, pkt_bitlen; 2883 2884 pkt_bitlen = pkt_len * NBBY; 2885 len = howmany(pkt_bitlen * 2, rate); 2886 2887 service = IEEE80211_PLCP_SERVICE_LOCKED; 2888 if (rate == (11 * 2)) { 2889 int pkt_bitlen1; 2890 2891 /* 2892 * PLCP service field needs to be adjusted, 2893 * if TX rate is 11Mbytes/s 2894 */ 2895 pkt_bitlen1 = len * 11; 2896 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2897 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2898 } 2899 2900 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2901 plcp->i_service = service; 2902 plcp->i_length = htole16(len); 2903 /* NOTE: do NOT touch i_crc */ 2904 } 2905 2906 static __inline void 2907 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2908 void *plcp, int pkt_len, uint8_t rate) 2909 { 2910 enum ieee80211_phytype modtype; 2911 2912 /* 2913 * Assume caller has zeroed 'plcp' 2914 */ 2915 modtype = ieee80211_rate2phytype(rt, rate); 2916 if (modtype == IEEE80211_T_OFDM) 2917 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2918 else if (modtype == IEEE80211_T_DS) 2919 bwi_ds_plcp_header(plcp, pkt_len, rate); 2920 else 2921 panic("unsupport modulation type %u\n", modtype); 2922 } 2923 2924 static int 2925 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2926 struct ieee80211_node *ni) 2927 { 2928 struct ieee80211vap *vap = ni->ni_vap; 2929 struct ieee80211com *ic = &sc->sc_ic; 2930 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2931 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2932 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2933 struct bwi_mac *mac; 2934 struct bwi_txbuf_hdr *hdr; 2935 struct ieee80211_frame *wh; 2936 const struct ieee80211_txparam *tp = ni->ni_txparms; 2937 uint8_t rate, rate_fb; 2938 uint32_t mac_ctrl; 2939 uint16_t phy_ctrl; 2940 bus_addr_t paddr; 2941 int type, ismcast, pkt_len, error, rix; 2942 #if 0 2943 const uint8_t *p; 2944 int i; 2945 #endif 2946 2947 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2948 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2949 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2950 2951 wh = mtod(m, struct ieee80211_frame *); 2952 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2953 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2954 2955 /* Get 802.11 frame len before prepending TX header */ 2956 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2957 2958 /* 2959 * Find TX rate 2960 */ 2961 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2962 rate = rate_fb = tp->mgmtrate; 2963 } else if (ismcast) { 2964 rate = rate_fb = tp->mcastrate; 2965 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2966 rate = rate_fb = tp->ucastrate; 2967 } else { 2968 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2969 rate = ni->ni_txrate; 2970 2971 if (rix > 0) { 2972 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2973 IEEE80211_RATE_VAL; 2974 } else { 2975 rate_fb = rate; 2976 } 2977 } 2978 tb->tb_rate[0] = rate; 2979 tb->tb_rate[1] = rate_fb; 2980 sc->sc_tx_rate = rate; 2981 2982 /* 2983 * TX radio tap 2984 */ 2985 if (ieee80211_radiotap_active_vap(vap)) { 2986 sc->sc_tx_th.wt_flags = 0; 2987 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2988 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2989 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2990 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2991 rate != (1 * 2)) { 2992 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2993 } 2994 sc->sc_tx_th.wt_rate = rate; 2995 2996 ieee80211_radiotap_tx(vap, m); 2997 } 2998 2999 /* 3000 * Setup the embedded TX header 3001 */ 3002 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3003 if (m == NULL) { 3004 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3005 __func__); 3006 return ENOBUFS; 3007 } 3008 hdr = mtod(m, struct bwi_txbuf_hdr *); 3009 3010 bzero(hdr, sizeof(*hdr)); 3011 3012 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3013 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3014 3015 if (!ismcast) { 3016 uint16_t dur; 3017 3018 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3019 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3020 3021 hdr->txh_fb_duration = htole16(dur); 3022 } 3023 3024 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3025 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3026 3027 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3028 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3029 3030 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3031 BWI_TXH_PHY_C_ANTMODE_MASK); 3032 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3033 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3034 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3035 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3036 3037 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3038 if (!ismcast) 3039 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3040 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3041 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3042 3043 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3044 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3045 3046 /* Catch any further usage */ 3047 hdr = NULL; 3048 wh = NULL; 3049 3050 /* DMA load */ 3051 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3052 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3053 if (error && error != EFBIG) { 3054 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3055 __func__, error); 3056 goto back; 3057 } 3058 3059 if (error) { /* error == EFBIG */ 3060 struct mbuf *m_new; 3061 3062 m_new = m_defrag(m, M_NOWAIT); 3063 if (m_new == NULL) { 3064 device_printf(sc->sc_dev, 3065 "%s: can't defrag TX buffer\n", __func__); 3066 error = ENOBUFS; 3067 goto back; 3068 } else { 3069 m = m_new; 3070 } 3071 3072 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3073 bwi_dma_buf_addr, &paddr, 3074 BUS_DMA_NOWAIT); 3075 if (error) { 3076 device_printf(sc->sc_dev, 3077 "%s: can't load TX buffer (2) %d\n", 3078 __func__, error); 3079 goto back; 3080 } 3081 } 3082 error = 0; 3083 3084 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3085 3086 tb->tb_mbuf = m; 3087 tb->tb_ni = ni; 3088 3089 #if 0 3090 p = mtod(m, const uint8_t *); 3091 for (i = 0; i < m->m_pkthdr.len; ++i) { 3092 if (i != 0 && i % 8 == 0) 3093 printf("\n"); 3094 printf("%02x ", p[i]); 3095 } 3096 printf("\n"); 3097 #endif 3098 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3099 idx, pkt_len, m->m_pkthdr.len); 3100 3101 /* Setup TX descriptor */ 3102 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3103 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3104 BUS_DMASYNC_PREWRITE); 3105 3106 /* Kick start */ 3107 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3108 3109 back: 3110 if (error) 3111 m_freem(m); 3112 return error; 3113 } 3114 3115 static int 3116 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3117 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3118 { 3119 struct ieee80211vap *vap = ni->ni_vap; 3120 struct ieee80211com *ic = ni->ni_ic; 3121 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3122 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3123 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3124 struct bwi_mac *mac; 3125 struct bwi_txbuf_hdr *hdr; 3126 struct ieee80211_frame *wh; 3127 uint8_t rate, rate_fb; 3128 uint32_t mac_ctrl; 3129 uint16_t phy_ctrl; 3130 bus_addr_t paddr; 3131 int ismcast, pkt_len, error; 3132 3133 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3134 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3135 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3136 3137 wh = mtod(m, struct ieee80211_frame *); 3138 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3139 3140 /* Get 802.11 frame len before prepending TX header */ 3141 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3142 3143 /* 3144 * Find TX rate 3145 */ 3146 rate = params->ibp_rate0; 3147 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3148 /* XXX fall back to mcast/mgmt rate? */ 3149 m_freem(m); 3150 return EINVAL; 3151 } 3152 if (params->ibp_try1 != 0) { 3153 rate_fb = params->ibp_rate1; 3154 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3155 /* XXX fall back to rate0? */ 3156 m_freem(m); 3157 return EINVAL; 3158 } 3159 } else 3160 rate_fb = rate; 3161 tb->tb_rate[0] = rate; 3162 tb->tb_rate[1] = rate_fb; 3163 sc->sc_tx_rate = rate; 3164 3165 /* 3166 * TX radio tap 3167 */ 3168 if (ieee80211_radiotap_active_vap(vap)) { 3169 sc->sc_tx_th.wt_flags = 0; 3170 /* XXX IEEE80211_BPF_CRYPTO */ 3171 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3172 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3173 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3174 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3175 sc->sc_tx_th.wt_rate = rate; 3176 3177 ieee80211_radiotap_tx(vap, m); 3178 } 3179 3180 /* 3181 * Setup the embedded TX header 3182 */ 3183 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3184 if (m == NULL) { 3185 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3186 __func__); 3187 return ENOBUFS; 3188 } 3189 hdr = mtod(m, struct bwi_txbuf_hdr *); 3190 3191 bzero(hdr, sizeof(*hdr)); 3192 3193 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3194 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3195 3196 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3197 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3198 uint16_t dur; 3199 3200 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3201 3202 hdr->txh_fb_duration = htole16(dur); 3203 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3204 } 3205 3206 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3207 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3208 3209 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3210 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3211 3212 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3213 BWI_TXH_PHY_C_ANTMODE_MASK); 3214 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3215 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3216 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3217 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3218 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3219 3220 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3221 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3222 3223 /* Catch any further usage */ 3224 hdr = NULL; 3225 wh = NULL; 3226 3227 /* DMA load */ 3228 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3229 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3230 if (error != 0) { 3231 struct mbuf *m_new; 3232 3233 if (error != EFBIG) { 3234 device_printf(sc->sc_dev, 3235 "%s: can't load TX buffer (1) %d\n", 3236 __func__, error); 3237 goto back; 3238 } 3239 m_new = m_defrag(m, M_NOWAIT); 3240 if (m_new == NULL) { 3241 device_printf(sc->sc_dev, 3242 "%s: can't defrag TX buffer\n", __func__); 3243 error = ENOBUFS; 3244 goto back; 3245 } 3246 m = m_new; 3247 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3248 bwi_dma_buf_addr, &paddr, 3249 BUS_DMA_NOWAIT); 3250 if (error) { 3251 device_printf(sc->sc_dev, 3252 "%s: can't load TX buffer (2) %d\n", 3253 __func__, error); 3254 goto back; 3255 } 3256 } 3257 3258 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3259 3260 tb->tb_mbuf = m; 3261 tb->tb_ni = ni; 3262 3263 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3264 idx, pkt_len, m->m_pkthdr.len); 3265 3266 /* Setup TX descriptor */ 3267 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3268 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3269 BUS_DMASYNC_PREWRITE); 3270 3271 /* Kick start */ 3272 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3273 back: 3274 if (error) 3275 m_freem(m); 3276 return error; 3277 } 3278 3279 static void 3280 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3281 { 3282 idx = (idx + 1) % BWI_TX_NDESC; 3283 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3284 idx * sizeof(struct bwi_desc32)); 3285 } 3286 3287 static void 3288 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3289 { 3290 /* TODO:64 */ 3291 } 3292 3293 static void 3294 bwi_txeof_status32(struct bwi_softc *sc) 3295 { 3296 uint32_t val, ctrl_base; 3297 int end_idx; 3298 3299 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3300 3301 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3302 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3303 sizeof(struct bwi_desc32); 3304 3305 bwi_txeof_status(sc, end_idx); 3306 3307 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3308 end_idx * sizeof(struct bwi_desc32)); 3309 3310 bwi_start_locked(sc); 3311 } 3312 3313 static void 3314 bwi_txeof_status64(struct bwi_softc *sc) 3315 { 3316 /* TODO:64 */ 3317 } 3318 3319 static void 3320 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3321 { 3322 struct bwi_txbuf_data *tbd; 3323 struct bwi_txbuf *tb; 3324 int ring_idx, buf_idx; 3325 struct ieee80211_node *ni; 3326 3327 if (tx_id == 0) { 3328 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3329 return; 3330 } 3331 3332 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3333 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3334 3335 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3336 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3337 3338 tbd = &sc->sc_tx_bdata[ring_idx]; 3339 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3340 tbd->tbd_used--; 3341 3342 tb = &tbd->tbd_buf[buf_idx]; 3343 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3344 "acked %d, data_txcnt %d, ni %p\n", 3345 buf_idx, acked, data_txcnt, tb->tb_ni); 3346 3347 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3348 3349 if ((ni = tb->tb_ni) != NULL) { 3350 const struct bwi_txbuf_hdr *hdr = 3351 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3352 struct ieee80211_ratectl_tx_status txs; 3353 3354 /* NB: update rate control only for unicast frames */ 3355 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3356 /* 3357 * Feed back 'acked and data_txcnt'. Note that the 3358 * generic AMRR code only understands one tx rate 3359 * and the estimator doesn't handle real retry counts 3360 * well so to avoid over-aggressive downshifting we 3361 * treat any number of retries as "1". 3362 */ 3363 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 3364 txs.long_retries = acked; 3365 if (data_txcnt > 1) 3366 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 3367 else { 3368 txs.status = 3369 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3370 } 3371 ieee80211_ratectl_tx_complete(ni, &txs); 3372 } 3373 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3374 tb->tb_ni = NULL; 3375 } else 3376 m_freem(tb->tb_mbuf); 3377 tb->tb_mbuf = NULL; 3378 3379 if (tbd->tbd_used == 0) 3380 sc->sc_tx_timer = 0; 3381 } 3382 3383 static void 3384 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3385 { 3386 struct bwi_txstats_data *st = sc->sc_txstats; 3387 int idx; 3388 3389 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3390 3391 idx = st->stats_idx; 3392 while (idx != end_idx) { 3393 const struct bwi_txstats *stats = &st->stats[idx]; 3394 3395 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3396 int data_txcnt; 3397 3398 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3399 BWI_TXS_TXCNT_DATA); 3400 _bwi_txeof(sc, le16toh(stats->txs_id), 3401 stats->txs_flags & BWI_TXS_F_ACKED, 3402 data_txcnt); 3403 } 3404 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3405 } 3406 st->stats_idx = idx; 3407 } 3408 3409 static void 3410 bwi_txeof(struct bwi_softc *sc) 3411 { 3412 3413 for (;;) { 3414 uint32_t tx_status0, tx_status1; 3415 uint16_t tx_id; 3416 int data_txcnt; 3417 3418 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3419 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3420 break; 3421 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3422 3423 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3424 data_txcnt = __SHIFTOUT(tx_status0, 3425 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3426 3427 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3428 continue; 3429 3430 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3431 data_txcnt); 3432 } 3433 3434 bwi_start_locked(sc); 3435 } 3436 3437 static int 3438 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3439 { 3440 bwi_power_on(sc, 1); 3441 return bwi_set_clock_mode(sc, clk_mode); 3442 } 3443 3444 static void 3445 bwi_bbp_power_off(struct bwi_softc *sc) 3446 { 3447 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3448 bwi_power_off(sc, 1); 3449 } 3450 3451 static int 3452 bwi_get_pwron_delay(struct bwi_softc *sc) 3453 { 3454 struct bwi_regwin *com, *old; 3455 struct bwi_clock_freq freq; 3456 uint32_t val; 3457 int error; 3458 3459 com = &sc->sc_com_regwin; 3460 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3461 3462 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3463 return 0; 3464 3465 error = bwi_regwin_switch(sc, com, &old); 3466 if (error) 3467 return error; 3468 3469 bwi_get_clock_freq(sc, &freq); 3470 3471 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3472 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3473 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3474 3475 return bwi_regwin_switch(sc, old, NULL); 3476 } 3477 3478 static int 3479 bwi_bus_attach(struct bwi_softc *sc) 3480 { 3481 struct bwi_regwin *bus, *old; 3482 int error; 3483 3484 bus = &sc->sc_bus_regwin; 3485 3486 error = bwi_regwin_switch(sc, bus, &old); 3487 if (error) 3488 return error; 3489 3490 if (!bwi_regwin_is_enabled(sc, bus)) 3491 bwi_regwin_enable(sc, bus, 0); 3492 3493 /* Disable interripts */ 3494 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3495 3496 return bwi_regwin_switch(sc, old, NULL); 3497 } 3498 3499 static const char * 3500 bwi_regwin_name(const struct bwi_regwin *rw) 3501 { 3502 switch (rw->rw_type) { 3503 case BWI_REGWIN_T_COM: 3504 return "COM"; 3505 case BWI_REGWIN_T_BUSPCI: 3506 return "PCI"; 3507 case BWI_REGWIN_T_MAC: 3508 return "MAC"; 3509 case BWI_REGWIN_T_BUSPCIE: 3510 return "PCIE"; 3511 } 3512 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3513 return NULL; 3514 } 3515 3516 static uint32_t 3517 bwi_regwin_disable_bits(struct bwi_softc *sc) 3518 { 3519 uint32_t busrev; 3520 3521 /* XXX cache this */ 3522 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3523 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3524 "bus rev %u\n", busrev); 3525 3526 if (busrev == BWI_BUSREV_0) 3527 return BWI_STATE_LO_DISABLE1; 3528 else if (busrev == BWI_BUSREV_1) 3529 return BWI_STATE_LO_DISABLE2; 3530 else 3531 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3532 } 3533 3534 int 3535 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3536 { 3537 uint32_t val, disable_bits; 3538 3539 disable_bits = bwi_regwin_disable_bits(sc); 3540 val = CSR_READ_4(sc, BWI_STATE_LO); 3541 3542 if ((val & (BWI_STATE_LO_CLOCK | 3543 BWI_STATE_LO_RESET | 3544 disable_bits)) == BWI_STATE_LO_CLOCK) { 3545 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3546 bwi_regwin_name(rw)); 3547 return 1; 3548 } else { 3549 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3550 bwi_regwin_name(rw)); 3551 return 0; 3552 } 3553 } 3554 3555 void 3556 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3557 { 3558 uint32_t state_lo, disable_bits; 3559 int i; 3560 3561 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3562 3563 /* 3564 * If current regwin is in 'reset' state, it was already disabled. 3565 */ 3566 if (state_lo & BWI_STATE_LO_RESET) { 3567 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3568 "%s was already disabled\n", bwi_regwin_name(rw)); 3569 return; 3570 } 3571 3572 disable_bits = bwi_regwin_disable_bits(sc); 3573 3574 /* 3575 * Disable normal clock 3576 */ 3577 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3578 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3579 3580 /* 3581 * Wait until normal clock is disabled 3582 */ 3583 #define NRETRY 1000 3584 for (i = 0; i < NRETRY; ++i) { 3585 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3586 if (state_lo & disable_bits) 3587 break; 3588 DELAY(10); 3589 } 3590 if (i == NRETRY) { 3591 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3592 bwi_regwin_name(rw)); 3593 } 3594 3595 for (i = 0; i < NRETRY; ++i) { 3596 uint32_t state_hi; 3597 3598 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3599 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3600 break; 3601 DELAY(10); 3602 } 3603 if (i == NRETRY) { 3604 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3605 bwi_regwin_name(rw)); 3606 } 3607 #undef NRETRY 3608 3609 /* 3610 * Reset and disable regwin with gated clock 3611 */ 3612 state_lo = BWI_STATE_LO_RESET | disable_bits | 3613 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3614 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3615 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3616 3617 /* Flush pending bus write */ 3618 CSR_READ_4(sc, BWI_STATE_LO); 3619 DELAY(1); 3620 3621 /* Reset and disable regwin */ 3622 state_lo = BWI_STATE_LO_RESET | disable_bits | 3623 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3624 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3625 3626 /* Flush pending bus write */ 3627 CSR_READ_4(sc, BWI_STATE_LO); 3628 DELAY(1); 3629 } 3630 3631 void 3632 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3633 { 3634 uint32_t state_lo, state_hi, imstate; 3635 3636 bwi_regwin_disable(sc, rw, flags); 3637 3638 /* Reset regwin with gated clock */ 3639 state_lo = BWI_STATE_LO_RESET | 3640 BWI_STATE_LO_CLOCK | 3641 BWI_STATE_LO_GATED_CLOCK | 3642 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3643 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3644 3645 /* Flush pending bus write */ 3646 CSR_READ_4(sc, BWI_STATE_LO); 3647 DELAY(1); 3648 3649 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3650 if (state_hi & BWI_STATE_HI_SERROR) 3651 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3652 3653 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3654 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3655 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3656 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3657 } 3658 3659 /* Enable regwin with gated clock */ 3660 state_lo = BWI_STATE_LO_CLOCK | 3661 BWI_STATE_LO_GATED_CLOCK | 3662 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3663 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3664 3665 /* Flush pending bus write */ 3666 CSR_READ_4(sc, BWI_STATE_LO); 3667 DELAY(1); 3668 3669 /* Enable regwin with normal clock */ 3670 state_lo = BWI_STATE_LO_CLOCK | 3671 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3672 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3673 3674 /* Flush pending bus write */ 3675 CSR_READ_4(sc, BWI_STATE_LO); 3676 DELAY(1); 3677 } 3678 3679 static void 3680 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3681 { 3682 struct bwi_mac *mac; 3683 struct bwi_myaddr_bssid buf; 3684 const uint8_t *p; 3685 uint32_t val; 3686 int n, i; 3687 3688 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3689 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3690 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3691 3692 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3693 3694 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3695 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3696 3697 n = sizeof(buf) / sizeof(val); 3698 p = (const uint8_t *)&buf; 3699 for (i = 0; i < n; ++i) { 3700 int j; 3701 3702 val = 0; 3703 for (j = 0; j < sizeof(val); ++j) 3704 val |= ((uint32_t)(*p++)) << (j * 8); 3705 3706 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3707 } 3708 } 3709 3710 static void 3711 bwi_updateslot(struct ieee80211com *ic) 3712 { 3713 struct bwi_softc *sc = ic->ic_softc; 3714 struct bwi_mac *mac; 3715 3716 BWI_LOCK(sc); 3717 if (sc->sc_flags & BWI_F_RUNNING) { 3718 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3719 3720 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3721 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3722 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3723 3724 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3725 } 3726 BWI_UNLOCK(sc); 3727 } 3728 3729 static void 3730 bwi_calibrate(void *xsc) 3731 { 3732 struct bwi_softc *sc = xsc; 3733 struct bwi_mac *mac; 3734 3735 BWI_ASSERT_LOCKED(sc); 3736 3737 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3738 ("opmode %d", sc->sc_ic.ic_opmode)); 3739 3740 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3741 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3742 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3743 3744 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3745 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3746 3747 /* XXX 15 seconds */ 3748 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3749 } 3750 3751 static int 3752 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3753 { 3754 struct bwi_mac *mac; 3755 3756 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3757 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3758 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3759 3760 return bwi_rf_calc_rssi(mac, hdr); 3761 } 3762 3763 static int 3764 bwi_calc_noise(struct bwi_softc *sc) 3765 { 3766 struct bwi_mac *mac; 3767 3768 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3769 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3770 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3771 3772 return bwi_rf_calc_noise(mac); 3773 } 3774 3775 static __inline uint8_t 3776 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3777 { 3778 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3779 return (ieee80211_plcp2rate(plcp, type)); 3780 } 3781 3782 static void 3783 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3784 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3785 { 3786 const struct ieee80211_frame_min *wh; 3787 3788 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3789 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3790 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3791 3792 wh = mtod(m, const struct ieee80211_frame_min *); 3793 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3794 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3795 3796 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */ 3797 sc->sc_rx_th.wr_rate = rate; 3798 sc->sc_rx_th.wr_antsignal = rssi; 3799 sc->sc_rx_th.wr_antnoise = noise; 3800 } 3801 3802 static void 3803 bwi_led_attach(struct bwi_softc *sc) 3804 { 3805 const uint8_t *led_act = NULL; 3806 uint16_t gpio, val[BWI_LED_MAX]; 3807 int i; 3808 3809 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3810 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3811 led_act = bwi_vendor_led_act[i].led_act; 3812 break; 3813 } 3814 } 3815 if (led_act == NULL) 3816 led_act = bwi_default_led_act; 3817 3818 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3819 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3820 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3821 3822 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3823 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3824 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3825 3826 for (i = 0; i < BWI_LED_MAX; ++i) { 3827 struct bwi_led *led = &sc->sc_leds[i]; 3828 3829 if (val[i] == 0xff) { 3830 led->l_act = led_act[i]; 3831 } else { 3832 if (val[i] & BWI_LED_ACT_LOW) 3833 led->l_flags |= BWI_LED_F_ACTLOW; 3834 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3835 } 3836 led->l_mask = (1 << i); 3837 3838 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3839 led->l_act == BWI_LED_ACT_BLINK_POLL || 3840 led->l_act == BWI_LED_ACT_BLINK) { 3841 led->l_flags |= BWI_LED_F_BLINK; 3842 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3843 led->l_flags |= BWI_LED_F_POLLABLE; 3844 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3845 led->l_flags |= BWI_LED_F_SLOW; 3846 3847 if (sc->sc_blink_led == NULL) { 3848 sc->sc_blink_led = led; 3849 if (led->l_flags & BWI_LED_F_SLOW) 3850 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3851 } 3852 } 3853 3854 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3855 "%dth led, act %d, lowact %d\n", i, 3856 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3857 } 3858 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3859 } 3860 3861 static __inline uint16_t 3862 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3863 { 3864 if (led->l_flags & BWI_LED_F_ACTLOW) 3865 on = !on; 3866 if (on) 3867 val |= led->l_mask; 3868 else 3869 val &= ~led->l_mask; 3870 return val; 3871 } 3872 3873 static void 3874 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3875 { 3876 struct ieee80211com *ic = &sc->sc_ic; 3877 uint16_t val; 3878 int i; 3879 3880 if (nstate == IEEE80211_S_INIT) { 3881 callout_stop(&sc->sc_led_blink_ch); 3882 sc->sc_led_blinking = 0; 3883 } 3884 3885 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3886 return; 3887 3888 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3889 for (i = 0; i < BWI_LED_MAX; ++i) { 3890 struct bwi_led *led = &sc->sc_leds[i]; 3891 int on; 3892 3893 if (led->l_act == BWI_LED_ACT_UNKN || 3894 led->l_act == BWI_LED_ACT_NULL) 3895 continue; 3896 3897 if ((led->l_flags & BWI_LED_F_BLINK) && 3898 nstate != IEEE80211_S_INIT) 3899 continue; 3900 3901 switch (led->l_act) { 3902 case BWI_LED_ACT_ON: /* Always on */ 3903 on = 1; 3904 break; 3905 case BWI_LED_ACT_OFF: /* Always off */ 3906 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3907 on = 0; 3908 break; 3909 default: 3910 on = 1; 3911 switch (nstate) { 3912 case IEEE80211_S_INIT: 3913 on = 0; 3914 break; 3915 case IEEE80211_S_RUN: 3916 if (led->l_act == BWI_LED_ACT_11G && 3917 ic->ic_curmode != IEEE80211_MODE_11G) 3918 on = 0; 3919 break; 3920 default: 3921 if (led->l_act == BWI_LED_ACT_ASSOC) 3922 on = 0; 3923 break; 3924 } 3925 break; 3926 } 3927 3928 val = bwi_led_onoff(led, val, on); 3929 } 3930 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3931 } 3932 static void 3933 bwi_led_event(struct bwi_softc *sc, int event) 3934 { 3935 struct bwi_led *led = sc->sc_blink_led; 3936 int rate; 3937 3938 if (event == BWI_LED_EVENT_POLL) { 3939 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3940 return; 3941 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3942 return; 3943 } 3944 3945 sc->sc_led_ticks = ticks; 3946 if (sc->sc_led_blinking) 3947 return; 3948 3949 switch (event) { 3950 case BWI_LED_EVENT_RX: 3951 rate = sc->sc_rx_rate; 3952 break; 3953 case BWI_LED_EVENT_TX: 3954 rate = sc->sc_tx_rate; 3955 break; 3956 case BWI_LED_EVENT_POLL: 3957 rate = 0; 3958 break; 3959 default: 3960 panic("unknown LED event %d\n", event); 3961 break; 3962 } 3963 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3964 bwi_led_duration[rate].off_dur); 3965 } 3966 3967 static void 3968 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3969 { 3970 struct bwi_led *led = sc->sc_blink_led; 3971 uint16_t val; 3972 3973 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3974 val = bwi_led_onoff(led, val, 1); 3975 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3976 3977 if (led->l_flags & BWI_LED_F_SLOW) { 3978 BWI_LED_SLOWDOWN(on_dur); 3979 BWI_LED_SLOWDOWN(off_dur); 3980 } 3981 3982 sc->sc_led_blinking = 1; 3983 sc->sc_led_blink_offdur = off_dur; 3984 3985 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3986 } 3987 3988 static void 3989 bwi_led_blink_next(void *xsc) 3990 { 3991 struct bwi_softc *sc = xsc; 3992 uint16_t val; 3993 3994 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3995 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3996 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3997 3998 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3999 bwi_led_blink_end, sc); 4000 } 4001 4002 static void 4003 bwi_led_blink_end(void *xsc) 4004 { 4005 struct bwi_softc *sc = xsc; 4006 sc->sc_led_blinking = 0; 4007 } 4008 4009 static void 4010 bwi_restart(void *xsc, int pending) 4011 { 4012 struct bwi_softc *sc = xsc; 4013 4014 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 4015 BWI_LOCK(sc); 4016 bwi_init_statechg(sc, 0); 4017 #if 0 4018 bwi_start_locked(sc); 4019 #endif 4020 BWI_UNLOCK(sc); 4021 } 4022