1 /* 2 * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term 3 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Description: Slow Path Operators (header) 29 */ 30 31 #ifndef __BNXT_QPLIB_SP_H__ 32 #define __BNXT_QPLIB_SP_H__ 33 34 #include <rdma/ib_verbs.h> 35 36 #define BNXT_QPLIB_RESERVED_QP_WRS 128 37 38 /* Resource maximums reported by the firmware */ 39 struct bnxt_qplib_dev_attr { 40 #define FW_VER_ARR_LEN 4 41 u8 fw_ver[FW_VER_ARR_LEN]; 42 u16 max_sgid; 43 u16 max_mrw; 44 u32 max_qp; 45 #define BNXT_QPLIB_MAX_OUT_RD_ATOM 126 46 u32 max_qp_rd_atom; 47 u32 max_qp_init_rd_atom; 48 u32 max_qp_wqes; 49 u32 max_qp_sges; 50 u32 max_cq; 51 /* HW supports only 8K entries in PBL. 52 * So max CQEs that can be supported per CQ is 1M. 53 */ 54 #define BNXT_QPLIB_MAX_CQ_WQES 0xfffff 55 u32 max_cq_wqes; 56 u32 max_cq_sges; 57 u32 max_mr; 58 u64 max_mr_size; 59 #define BNXT_QPLIB_MAX_PD (64 * 1024) 60 u32 max_pd; 61 u32 max_mw; 62 u32 max_raw_ethy_qp; 63 u32 max_ah; 64 u32 max_fmr; 65 u32 max_map_per_fmr; 66 u32 max_srq; 67 u32 max_srq_wqes; 68 u32 max_srq_sges; 69 u32 max_pkey; 70 u32 max_inline_data; 71 u32 l2_db_size; 72 u8 tqm_alloc_reqs[MAX_TQM_ALLOC_REQ]; 73 u8 is_atomic; 74 u16 dev_cap_flags; 75 u64 page_size_cap; 76 u32 max_dpi; 77 }; 78 79 struct bnxt_qplib_pd { 80 u32 id; 81 }; 82 83 struct bnxt_qplib_gid { 84 u8 data[16]; 85 }; 86 87 struct bnxt_qplib_gid_info { 88 struct bnxt_qplib_gid gid; 89 u16 vlan_id; 90 }; 91 92 struct bnxt_qplib_ah { 93 struct bnxt_qplib_gid dgid; 94 struct bnxt_qplib_pd *pd; 95 u32 id; 96 u8 sgid_index; 97 u8 host_sgid_index; /* For Query AH if the hw table and SW table are differnt */ 98 u8 traffic_class; 99 u32 flow_label; 100 u8 hop_limit; 101 u8 sl; 102 u8 dmac[6]; 103 u16 vlan_id; 104 u8 nw_type; 105 u8 enable_cc; 106 }; 107 108 struct bnxt_qplib_mrw { 109 struct bnxt_qplib_pd *pd; 110 int type; 111 u32 flags; 112 #define BNXT_QPLIB_FR_PMR 0x80000000 113 u32 lkey; 114 u32 rkey; 115 #define BNXT_QPLIB_RSVD_LKEY 0xFFFFFFFF 116 u64 va; 117 u64 total_size; 118 u32 npages; 119 u64 mr_handle; 120 struct bnxt_qplib_hwq hwq; 121 }; 122 123 struct bnxt_qplib_mrinfo { 124 struct bnxt_qplib_mrw *mrw; 125 struct bnxt_qplib_sg_info sg; 126 u64 *ptes; 127 bool is_dma; 128 }; 129 130 struct bnxt_qplib_frpl { 131 int max_pg_ptrs; 132 struct bnxt_qplib_hwq hwq; 133 }; 134 135 struct bnxt_qplib_cc_param_ext { 136 u64 ext_mask; 137 u16 inact_th_hi; 138 u16 min_delta_cnp; 139 u16 init_cp; 140 u8 tr_update_mode; 141 u8 tr_update_cyls; 142 u8 fr_rtt; 143 u8 ai_rate_incr; 144 u16 rr_rtt_th; 145 u16 ar_cr_th; 146 u16 cr_min_th; 147 u8 bw_avg_weight; 148 u8 cr_factor; 149 u16 cr_th_max_cp; 150 u8 cp_bias_en; 151 u8 cp_bias; 152 u8 cnp_ecn; 153 u8 rtt_jitter_en; 154 u16 bytes_per_usec; 155 u16 cc_cr_reset_th; 156 u8 cr_width; 157 u8 min_quota; 158 u8 max_quota; 159 u8 abs_max_quota; 160 u16 tr_lb; 161 u8 cr_prob_fac; 162 u8 tr_prob_fac; 163 u16 fair_cr_th; 164 u8 red_div; 165 u8 cnp_ratio_th; 166 u16 ai_ext_rtt; 167 u8 exp_crcp_ratio; 168 u8 low_rate_en; 169 u16 cpcr_update_th; 170 u16 ai_rtt_th1; 171 u16 ai_rtt_th2; 172 u16 cf_rtt_th; 173 u16 sc_cr_th1; /* severe congestion cr threshold 1 */ 174 u16 sc_cr_th2; /* severe congestion cr threshold 2 */ 175 u32 l64B_per_rtt; 176 u8 cc_ack_bytes; 177 u16 reduce_cf_rtt_th; 178 }; 179 180 struct bnxt_qplib_cc_param { 181 u8 alt_vlan_pcp; 182 u16 alt_tos_dscp; 183 #define BNXT_QPLIB_USER_DSCP_VALID 0x80 184 u8 cnp_dscp_user; 185 u8 roce_dscp_user; 186 u8 cc_mode; 187 u8 enable; 188 u16 inact_th; 189 u16 init_cr; 190 u16 init_tr; 191 u16 rtt; 192 u8 g; 193 u8 nph_per_state; 194 u8 time_pph; 195 u8 pkts_pph; 196 u8 tos_ecn; 197 u8 tos_dscp; 198 u8 qp1_tos_dscp; 199 u16 tcp_cp; 200 struct bnxt_qplib_cc_param_ext cc_ext; 201 u8 disable_prio_vlan_tx; 202 /* Mask used while programming the configfs values */ 203 u32 mask; 204 /* Mask used while displaying the configfs values */ 205 u32 cur_mask; 206 u8 roce_pri; 207 #define BNXT_QPLIB_CC_PARAM_MASK_VLAN_TX_DISABLE 0x40000 208 #define BNXT_QPLIB_CC_PARAM_MASK_ROCE_PRI 0x80000 209 /* prev value to clear dscp table */ 210 u8 prev_roce_pri; 211 u8 prev_alt_vlan_pcp; 212 u8 prev_tos_dscp; 213 u16 prev_alt_tos_dscp; 214 /* To track if admin has enabled ECN explicitly */ 215 u8 admin_enable; 216 }; 217 218 struct bnxt_qplib_roce_stats { 219 u64 to_retransmits; 220 u64 seq_err_naks_rcvd; 221 /* seq_err_naks_rcvd is 64 b */ 222 u64 max_retry_exceeded; 223 /* max_retry_exceeded is 64 b */ 224 u64 rnr_naks_rcvd; 225 /* rnr_naks_rcvd is 64 b */ 226 u64 missing_resp; 227 u64 unrecoverable_err; 228 /* unrecoverable_err is 64 b */ 229 u64 bad_resp_err; 230 /* bad_resp_err is 64 b */ 231 u64 local_qp_op_err; 232 /* local_qp_op_err is 64 b */ 233 u64 local_protection_err; 234 /* local_protection_err is 64 b */ 235 u64 mem_mgmt_op_err; 236 /* mem_mgmt_op_err is 64 b */ 237 u64 remote_invalid_req_err; 238 /* remote_invalid_req_err is 64 b */ 239 u64 remote_access_err; 240 /* remote_access_err is 64 b */ 241 u64 remote_op_err; 242 /* remote_op_err is 64 b */ 243 u64 dup_req; 244 /* dup_req is 64 b */ 245 u64 res_exceed_max; 246 /* res_exceed_max is 64 b */ 247 u64 res_length_mismatch; 248 /* res_length_mismatch is 64 b */ 249 u64 res_exceeds_wqe; 250 /* res_exceeds_wqe is 64 b */ 251 u64 res_opcode_err; 252 /* res_opcode_err is 64 b */ 253 u64 res_rx_invalid_rkey; 254 /* res_rx_invalid_rkey is 64 b */ 255 u64 res_rx_domain_err; 256 /* res_rx_domain_err is 64 b */ 257 u64 res_rx_no_perm; 258 /* res_rx_no_perm is 64 b */ 259 u64 res_rx_range_err; 260 /* res_rx_range_err is 64 b */ 261 u64 res_tx_invalid_rkey; 262 /* res_tx_invalid_rkey is 64 b */ 263 u64 res_tx_domain_err; 264 /* res_tx_domain_err is 64 b */ 265 u64 res_tx_no_perm; 266 /* res_tx_no_perm is 64 b */ 267 u64 res_tx_range_err; 268 /* res_tx_range_err is 64 b */ 269 u64 res_irrq_oflow; 270 /* res_irrq_oflow is 64 b */ 271 u64 res_unsup_opcode; 272 /* res_unsup_opcode is 64 b */ 273 u64 res_unaligned_atomic; 274 /* res_unaligned_atomic is 64 b */ 275 u64 res_rem_inv_err; 276 /* res_rem_inv_err is 64 b */ 277 u64 res_mem_error; 278 /* res_mem_error is 64 b */ 279 u64 res_srq_err; 280 /* res_srq_err is 64 b */ 281 u64 res_cmp_err; 282 /* res_cmp_err is 64 b */ 283 u64 res_invalid_dup_rkey; 284 /* res_invalid_dup_rkey is 64 b */ 285 u64 res_wqe_format_err; 286 /* res_wqe_format_err is 64 b */ 287 u64 res_cq_load_err; 288 /* res_cq_load_err is 64 b */ 289 u64 res_srq_load_err; 290 /* res_srq_load_err is 64 b */ 291 u64 res_tx_pci_err; 292 /* res_tx_pci_err is 64 b */ 293 u64 res_rx_pci_err; 294 /* res_rx_pci_err is 64 b */ 295 u64 res_oos_drop_count; 296 /* res_oos_drop_count */ 297 u64 active_qp_count_p0; 298 /* port 0 active qps */ 299 u64 active_qp_count_p1; 300 /* port 1 active qps */ 301 u64 active_qp_count_p2; 302 /* port 2 active qps */ 303 u64 active_qp_count_p3; 304 /* port 3 active qps */ 305 }; 306 307 struct bnxt_qplib_ext_stat { 308 u64 tx_atomic_req; 309 u64 tx_read_req; 310 u64 tx_read_res; 311 u64 tx_write_req; 312 u64 tx_send_req; 313 u64 tx_roce_pkts; 314 u64 tx_roce_bytes; 315 u64 rx_atomic_req; 316 u64 rx_read_req; 317 u64 rx_read_res; 318 u64 rx_write_req; 319 u64 rx_send_req; 320 u64 rx_roce_pkts; 321 u64 rx_roce_bytes; 322 u64 rx_roce_good_pkts; 323 u64 rx_roce_good_bytes; 324 u64 rx_out_of_buffer; 325 u64 rx_out_of_sequence; 326 u64 tx_cnp; 327 u64 rx_cnp; 328 u64 rx_ecn_marked; 329 u64 seq_err_naks_rcvd; 330 u64 rnr_naks_rcvd; 331 u64 missing_resp; 332 u64 to_retransmits; 333 u64 dup_req; 334 u64 rx_dcn_payload_cut; 335 u64 te_bypassed; 336 }; 337 338 #define BNXT_QPLIB_ACCESS_LOCAL_WRITE (1 << 0) 339 #define BNXT_QPLIB_ACCESS_REMOTE_READ (1 << 1) 340 #define BNXT_QPLIB_ACCESS_REMOTE_WRITE (1 << 2) 341 #define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC (1 << 3) 342 #define BNXT_QPLIB_ACCESS_MW_BIND (1 << 4) 343 #define BNXT_QPLIB_ACCESS_ZERO_BASED (1 << 5) 344 #define BNXT_QPLIB_ACCESS_ON_DEMAND (1 << 6) 345 346 int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res, 347 struct bnxt_qplib_sgid_tbl *sgid_tbl, int index, 348 struct bnxt_qplib_gid *gid); 349 int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 350 struct bnxt_qplib_gid *gid, u16 vlan_id, bool update); 351 int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 352 const union ib_gid *gid, const u8 *mac, u16 vlan_id, 353 bool update, u32 *index); 354 int bnxt_qplib_update_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl, 355 struct bnxt_qplib_gid *gid, u16 gid_idx, const u8 *smac); 356 int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw); 357 int bnxt_qplib_set_func_resources(struct bnxt_qplib_res *res); 358 int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 359 bool block); 360 int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah, 361 bool block); 362 int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw); 363 int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw, 364 bool block); 365 int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, 366 struct bnxt_qplib_mrinfo *mrinfo, bool block); 367 int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr); 368 int bnxt_qplib_alloc_fast_reg_mr(struct bnxt_qplib_res *res, 369 struct bnxt_qplib_mrw *mr, int max); 370 int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res, 371 struct bnxt_qplib_frpl *frpl, int max); 372 void bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res, 373 struct bnxt_qplib_frpl *frpl); 374 int bnxt_qplib_map_tc2cos(struct bnxt_qplib_res *res, u16 *cids); 375 int bnxt_qplib_modify_cc(struct bnxt_qplib_res *res, 376 struct bnxt_qplib_cc_param *cc_param); 377 int bnxt_qplib_query_cc_param(struct bnxt_qplib_res *res, 378 struct bnxt_qplib_cc_param *cc_param); 379 int bnxt_qplib_set_link_aggr_mode(struct bnxt_qplib_res *res, 380 u8 aggr_mode, u8 member_port_map, 381 u8 active_port_map, bool aggr_en, 382 u32 stats_fw_id); 383 int bnxt_qplib_get_roce_error_stats(struct bnxt_qplib_rcfw *rcfw, 384 struct bnxt_qplib_roce_stats *stats, 385 struct bnxt_qplib_query_stats_info *sinfo); 386 int bnxt_qplib_qext_stat(struct bnxt_qplib_rcfw *rcfw, u32 fid, 387 struct bnxt_qplib_ext_stat *estat, 388 struct bnxt_qplib_query_stats_info *sinfo); 389 static inline void bnxt_re_set_max_gid(u16 *max_sgid); 390 bool ib_modify_qp_is_ok_compat(enum ib_qp_state cur_state, enum ib_qp_state next_state, 391 enum ib_qp_type type, enum ib_qp_attr_mask mask); 392 393 #define BNXT_MAX_SQ_SIZE 0xFFFF 394 #define BNXT_MAX_VAR_WQE_SIZE 512 395 #define BNXT_SGE_SIZE 16 396 397 /* PF defines */ 398 #define BNXT_RE_MAX_QP_SUPPORTED(chip_gen) \ 399 chip_gen == BNXT_RE_DEFAULT ? (64 * 1024) : 0 400 401 #define BNXT_RE_MAX_MRW_SUPPORTED(chip_gen) \ 402 chip_gen == BNXT_RE_DEFAULT ? (256 * 1024) : 0 403 404 #define BNXT_RE_MAX_CQ_SUPPORTED(chip_gen) \ 405 chip_gen == BNXT_RE_DEFAULT ? (64 * 1024) : 0 406 407 #define BNXT_RE_MAX_SRQ_SUPPORTED(chip_gen) \ 408 chip_gen == BNXT_RE_DEFAULT ? (4 * 1024) : 0 409 410 #define BNXT_RE_MAX_AH_SUPPORTED(chip_gen) \ 411 chip_gen == BNXT_RE_DEFAULT ? (64 * 1024) : 0 412 413 /* VF defines */ 414 #define BNXT_RE_VF_MAX_QP_SUPPORTED(chip_gen) \ 415 chip_gen == BNXT_RE_DEFAULT ? (6 * 1024) : 0 416 417 #define BNXT_RE_VF_MAX_MRW_SUPPORTED(chip_gen) \ 418 chip_gen == BNXT_RE_DEFAULT ? (6 * 1024) : 0 419 420 #define BNXT_RE_VF_MAX_CQ_SUPPORTED(chip_gen) \ 421 chip_gen == BNXT_RE_DEFAULT ? (6 * 1024) : 0 422 423 #define BNXT_RE_VF_MAX_SRQ_SUPPORTED(chip_gen) \ 424 chip_gen == BNXT_RE_DEFAULT ? (4 * 1024) : 0 425 426 static inline void bnxt_re_set_max_gid(u16 *max_sgid) 427 { 428 *max_sgid = max_t(u32, 256, *max_sgid); 429 *max_sgid = min_t(u32, 256, *max_sgid); 430 } 431 432 #endif 433