1*acd884deSSumit Saxena /* 2*acd884deSSumit Saxena * Copyright (c) 2015-2024, Broadcom. All rights reserved. The term 3*acd884deSSumit Saxena * Broadcom refers to Broadcom Limited and/or its subsidiaries. 4*acd884deSSumit Saxena * 5*acd884deSSumit Saxena * Redistribution and use in source and binary forms, with or without 6*acd884deSSumit Saxena * modification, are permitted provided that the following conditions 7*acd884deSSumit Saxena * are met: 8*acd884deSSumit Saxena * 9*acd884deSSumit Saxena * 1. Redistributions of source code must retain the above copyright 10*acd884deSSumit Saxena * notice, this list of conditions and the following disclaimer. 11*acd884deSSumit Saxena * 2. Redistributions in binary form must reproduce the above copyright 12*acd884deSSumit Saxena * notice, this list of conditions and the following disclaimer in 13*acd884deSSumit Saxena * the documentation and/or other materials provided with the 14*acd884deSSumit Saxena * distribution. 15*acd884deSSumit Saxena * 16*acd884deSSumit Saxena * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 17*acd884deSSumit Saxena * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18*acd884deSSumit Saxena * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19*acd884deSSumit Saxena * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20*acd884deSSumit Saxena * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21*acd884deSSumit Saxena * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22*acd884deSSumit Saxena * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23*acd884deSSumit Saxena * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24*acd884deSSumit Saxena * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25*acd884deSSumit Saxena * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26*acd884deSSumit Saxena * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27*acd884deSSumit Saxena * 28*acd884deSSumit Saxena * Description: Uverbs ABI header file 29*acd884deSSumit Saxena */ 30*acd884deSSumit Saxena 31*acd884deSSumit Saxena #ifndef __BNXT_RE_UVERBS_ABI_H__ 32*acd884deSSumit Saxena #define __BNXT_RE_UVERBS_ABI_H__ 33*acd884deSSumit Saxena 34*acd884deSSumit Saxena #include <asm/types.h> 35*acd884deSSumit Saxena #include <linux/types.h> 36*acd884deSSumit Saxena 37*acd884deSSumit Saxena #define BNXT_RE_ABI_VERSION 6 38*acd884deSSumit Saxena 39*acd884deSSumit Saxena enum { 40*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_WC_DPI_ENABLED = 0x01, 41*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_POW2_DISABLED = 0x02, 42*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_RSVD_WQE_DISABLED = 0x04, 43*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_MQP_EX_SUPPORTED = 0x08, 44*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_DBR_PACING_ENABLED = 0x10, 45*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_DBR_RECOVERY_ENABLED = 0x20, 46*acd884deSSumit Saxena BNXT_RE_COMP_MASK_UCNTX_HW_RETX_ENABLED = 0x40 47*acd884deSSumit Saxena }; 48*acd884deSSumit Saxena 49*acd884deSSumit Saxena enum { 50*acd884deSSumit Saxena BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, 51*acd884deSSumit Saxena BNXT_RE_COMP_MASK_REQ_UCNTX_RSVD_WQE = 0x02 52*acd884deSSumit Saxena }; 53*acd884deSSumit Saxena 54*acd884deSSumit Saxena struct bnxt_re_uctx_req { 55*acd884deSSumit Saxena __aligned_u64 comp_mask; 56*acd884deSSumit Saxena }; 57*acd884deSSumit Saxena 58*acd884deSSumit Saxena #define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 59*acd884deSSumit Saxena #define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 60*acd884deSSumit Saxena #define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 61*acd884deSSumit Saxena struct bnxt_re_uctx_resp { 62*acd884deSSumit Saxena __u32 dev_id; 63*acd884deSSumit Saxena __u32 max_qp; 64*acd884deSSumit Saxena __u32 pg_size; 65*acd884deSSumit Saxena __u32 cqe_sz; 66*acd884deSSumit Saxena __u32 max_cqd; 67*acd884deSSumit Saxena __u32 chip_id0; 68*acd884deSSumit Saxena __u32 chip_id1; 69*acd884deSSumit Saxena __u32 modes; 70*acd884deSSumit Saxena __aligned_u64 comp_mask; 71*acd884deSSumit Saxena } __attribute__((packed)); 72*acd884deSSumit Saxena 73*acd884deSSumit Saxena enum { 74*acd884deSSumit Saxena BNXT_RE_COMP_MASK_PD_HAS_WC_DPI = 0x01, 75*acd884deSSumit Saxena BNXT_RE_COMP_MASK_PD_HAS_DBR_BAR_ADDR = 0x02, 76*acd884deSSumit Saxena }; 77*acd884deSSumit Saxena 78*acd884deSSumit Saxena struct bnxt_re_pd_resp { 79*acd884deSSumit Saxena __u32 pdid; 80*acd884deSSumit Saxena __u32 dpi; 81*acd884deSSumit Saxena __u64 dbr; 82*acd884deSSumit Saxena __u64 comp_mask; 83*acd884deSSumit Saxena __u32 wcdpi; 84*acd884deSSumit Saxena __u64 dbr_bar_addr; 85*acd884deSSumit Saxena } __attribute__((packed)); 86*acd884deSSumit Saxena 87*acd884deSSumit Saxena enum { 88*acd884deSSumit Saxena BNXT_RE_COMP_MASK_CQ_HAS_DB_INFO = 0x01, 89*acd884deSSumit Saxena BNXT_RE_COMP_MASK_CQ_HAS_WC_DPI = 0x02, 90*acd884deSSumit Saxena BNXT_RE_COMP_MASK_CQ_HAS_CQ_PAGE = 0x04, 91*acd884deSSumit Saxena }; 92*acd884deSSumit Saxena 93*acd884deSSumit Saxena enum { 94*acd884deSSumit Saxena BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK = 0x1 95*acd884deSSumit Saxena }; 96*acd884deSSumit Saxena 97*acd884deSSumit Saxena enum { 98*acd884deSSumit Saxena BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_RECOVERY = 0x1, 99*acd884deSSumit Saxena BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_PACING_NOTIFY = 0x2 100*acd884deSSumit Saxena }; 101*acd884deSSumit Saxena 102*acd884deSSumit Saxena #define BNXT_RE_IS_DBR_PACING_NOTIFY_CQ(_req) \ 103*acd884deSSumit Saxena (_req.comp_mask & BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK && \ 104*acd884deSSumit Saxena _req.cq_capability & BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_PACING_NOTIFY) 105*acd884deSSumit Saxena 106*acd884deSSumit Saxena #define BNXT_RE_IS_DBR_RECOV_CQ(_req) \ 107*acd884deSSumit Saxena (_req.comp_mask & BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK && \ 108*acd884deSSumit Saxena _req.cq_capability & BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_RECOVERY) 109*acd884deSSumit Saxena 110*acd884deSSumit Saxena struct bnxt_re_cq_req { 111*acd884deSSumit Saxena __u64 cq_va; 112*acd884deSSumit Saxena __u64 cq_handle; 113*acd884deSSumit Saxena __aligned_u64 comp_mask; 114*acd884deSSumit Saxena __u16 cq_capability; 115*acd884deSSumit Saxena } __attribute__((packed)); 116*acd884deSSumit Saxena 117*acd884deSSumit Saxena struct bnxt_re_cq_resp { 118*acd884deSSumit Saxena __u32 cqid; 119*acd884deSSumit Saxena __u32 tail; 120*acd884deSSumit Saxena __u32 phase; 121*acd884deSSumit Saxena __u32 rsvd; 122*acd884deSSumit Saxena __aligned_u64 comp_mask; 123*acd884deSSumit Saxena __u32 dpi; 124*acd884deSSumit Saxena __u64 dbr; 125*acd884deSSumit Saxena __u32 wcdpi; 126*acd884deSSumit Saxena __u64 uctx_cq_page; 127*acd884deSSumit Saxena } __attribute__((packed)); 128*acd884deSSumit Saxena 129*acd884deSSumit Saxena struct bnxt_re_resize_cq_req { 130*acd884deSSumit Saxena __u64 cq_va; 131*acd884deSSumit Saxena } __attribute__((packed)); 132*acd884deSSumit Saxena 133*acd884deSSumit Saxena struct bnxt_re_qp_req { 134*acd884deSSumit Saxena __u64 qpsva; 135*acd884deSSumit Saxena __u64 qprva; 136*acd884deSSumit Saxena __u64 qp_handle; 137*acd884deSSumit Saxena } __attribute__((packed)); 138*acd884deSSumit Saxena 139*acd884deSSumit Saxena struct bnxt_re_qp_resp { 140*acd884deSSumit Saxena __u32 qpid; 141*acd884deSSumit Saxena } __attribute__((packed)); 142*acd884deSSumit Saxena 143*acd884deSSumit Saxena struct bnxt_re_srq_req { 144*acd884deSSumit Saxena __u64 srqva; 145*acd884deSSumit Saxena __u64 srq_handle; 146*acd884deSSumit Saxena } __attribute__((packed)); 147*acd884deSSumit Saxena 148*acd884deSSumit Saxena struct bnxt_re_srq_resp { 149*acd884deSSumit Saxena __u32 srqid; 150*acd884deSSumit Saxena } __attribute__((packed)); 151*acd884deSSumit Saxena 152*acd884deSSumit Saxena /* Modify QP */ 153*acd884deSSumit Saxena enum { 154*acd884deSSumit Saxena BNXT_RE_COMP_MASK_MQP_EX_PPP_REQ_EN_MASK = 0x1, 155*acd884deSSumit Saxena BNXT_RE_COMP_MASK_MQP_EX_PPP_REQ_EN = 0x1, 156*acd884deSSumit Saxena BNXT_RE_COMP_MASK_MQP_EX_PATH_MTU_MASK = 0x2 157*acd884deSSumit Saxena }; 158*acd884deSSumit Saxena 159*acd884deSSumit Saxena struct bnxt_re_modify_qp_ex_req { 160*acd884deSSumit Saxena __aligned_u64 comp_mask; 161*acd884deSSumit Saxena __u32 dpi; 162*acd884deSSumit Saxena __u32 rsvd; 163*acd884deSSumit Saxena } __packed; 164*acd884deSSumit Saxena 165*acd884deSSumit Saxena struct bnxt_re_modify_qp_ex_resp { 166*acd884deSSumit Saxena __aligned_u64 comp_mask; 167*acd884deSSumit Saxena __u32 ppp_st_idx; 168*acd884deSSumit Saxena __u32 path_mtu; 169*acd884deSSumit Saxena } __packed; 170*acd884deSSumit Saxena 171*acd884deSSumit Saxena enum bnxt_re_shpg_offt { 172*acd884deSSumit Saxena BNXT_RE_BEG_RESV_OFFT = 0x00, 173*acd884deSSumit Saxena BNXT_RE_AVID_OFFT = 0x10, 174*acd884deSSumit Saxena BNXT_RE_AVID_SIZE = 0x04, 175*acd884deSSumit Saxena BNXT_RE_END_RESV_OFFT = 0xFF0 176*acd884deSSumit Saxena }; 177*acd884deSSumit Saxena #endif 178