1*050d28e1SChandrakanth patil /*-
2*050d28e1SChandrakanth patil * Broadcom NetXtreme-C/E network driver.
3*050d28e1SChandrakanth patil *
4*050d28e1SChandrakanth patil * Copyright (c) 2024 Broadcom, All Rights Reserved.
5*050d28e1SChandrakanth patil * The term Broadcom refers to Broadcom Limited and/or its subsidiaries
6*050d28e1SChandrakanth patil *
7*050d28e1SChandrakanth patil * Redistribution and use in source and binary forms, with or without
8*050d28e1SChandrakanth patil * modification, are permitted provided that the following conditions
9*050d28e1SChandrakanth patil * are met:
10*050d28e1SChandrakanth patil * 1. Redistributions of source code must retain the above copyright
11*050d28e1SChandrakanth patil * notice, this list of conditions and the following disclaimer.
12*050d28e1SChandrakanth patil * 2. Redistributions in binary form must reproduce the above copyright
13*050d28e1SChandrakanth patil * notice, this list of conditions and the following disclaimer in the
14*050d28e1SChandrakanth patil * documentation and/or other materials provided with the distribution.
15*050d28e1SChandrakanth patil *
16*050d28e1SChandrakanth patil * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
17*050d28e1SChandrakanth patil * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18*050d28e1SChandrakanth patil * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19*050d28e1SChandrakanth patil * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
20*050d28e1SChandrakanth patil * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21*050d28e1SChandrakanth patil * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22*050d28e1SChandrakanth patil * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23*050d28e1SChandrakanth patil * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24*050d28e1SChandrakanth patil * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25*050d28e1SChandrakanth patil * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26*050d28e1SChandrakanth patil * THE POSSIBILITY OF SUCH DAMAGE.
27*050d28e1SChandrakanth patil */
28*050d28e1SChandrakanth patil
29*050d28e1SChandrakanth patil #ifndef BNXT_ULP_H
30*050d28e1SChandrakanth patil #define BNXT_ULP_H
31*050d28e1SChandrakanth patil
32*050d28e1SChandrakanth patil #include <linux/rcupdate.h>
33*050d28e1SChandrakanth patil #include "bnxt.h"
34*050d28e1SChandrakanth patil
35*050d28e1SChandrakanth patil #define BNXT_ROCE_ULP 0
36*050d28e1SChandrakanth patil #define BNXT_OTHER_ULP 1
37*050d28e1SChandrakanth patil #define BNXT_MAX_ULP 2
38*050d28e1SChandrakanth patil
39*050d28e1SChandrakanth patil #define BNXT_MIN_ROCE_CP_RINGS 2
40*050d28e1SChandrakanth patil #define BNXT_MIN_ROCE_STAT_CTXS 1
41*050d28e1SChandrakanth patil
42*050d28e1SChandrakanth patil struct hwrm_async_event_cmpl;
43*050d28e1SChandrakanth patil struct bnxt_softc;
44*050d28e1SChandrakanth patil struct bnxt_bar_info;
45*050d28e1SChandrakanth patil
46*050d28e1SChandrakanth patil struct bnxt_msix_entry {
47*050d28e1SChandrakanth patil uint32_t vector;
48*050d28e1SChandrakanth patil uint32_t ring_idx;
49*050d28e1SChandrakanth patil uint32_t db_offset;
50*050d28e1SChandrakanth patil };
51*050d28e1SChandrakanth patil
52*050d28e1SChandrakanth patil struct bnxt_ulp_ops {
53*050d28e1SChandrakanth patil void (*ulp_async_notifier)(void *, struct hwrm_async_event_cmpl *);
54*050d28e1SChandrakanth patil void (*ulp_stop)(void *);
55*050d28e1SChandrakanth patil void (*ulp_start)(void *);
56*050d28e1SChandrakanth patil void (*ulp_sriov_config)(void *, int);
57*050d28e1SChandrakanth patil void (*ulp_shutdown)(void *);
58*050d28e1SChandrakanth patil void (*ulp_irq_stop)(void *);
59*050d28e1SChandrakanth patil void (*ulp_irq_restart)(void *, struct bnxt_msix_entry *);
60*050d28e1SChandrakanth patil };
61*050d28e1SChandrakanth patil
62*050d28e1SChandrakanth patil struct bnxt_fw_msg {
63*050d28e1SChandrakanth patil void *msg;
64*050d28e1SChandrakanth patil int msg_len;
65*050d28e1SChandrakanth patil void *resp;
66*050d28e1SChandrakanth patil int resp_max_len;
67*050d28e1SChandrakanth patil int timeout;
68*050d28e1SChandrakanth patil };
69*050d28e1SChandrakanth patil
70*050d28e1SChandrakanth patil struct bnxt_ulp {
71*050d28e1SChandrakanth patil void *handle;
72*050d28e1SChandrakanth patil struct bnxt_ulp_ops __rcu *ulp_ops;
73*050d28e1SChandrakanth patil unsigned long *async_events_bmap;
74*050d28e1SChandrakanth patil u16 max_async_event_id;
75*050d28e1SChandrakanth patil u16 msix_requested;
76*050d28e1SChandrakanth patil u16 msix_base;
77*050d28e1SChandrakanth patil atomic_t ref_count;
78*050d28e1SChandrakanth patil };
79*050d28e1SChandrakanth patil
80*050d28e1SChandrakanth patil struct bnxt_en_dev {
81*050d28e1SChandrakanth patil struct ifnet *net;
82*050d28e1SChandrakanth patil struct pci_dev *pdev;
83*050d28e1SChandrakanth patil struct bnxt_softc *softc;
84*050d28e1SChandrakanth patil u32 flags;
85*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_ROCEV1_CAP 0x1
86*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_ROCEV2_CAP 0x2
87*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_ROCE_CAP (BNXT_EN_FLAG_ROCEV1_CAP | \
88*050d28e1SChandrakanth patil BNXT_EN_FLAG_ROCEV2_CAP)
89*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_MSIX_REQUESTED 0x4
90*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_ULP_STOPPED 0x8
91*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_ASYM_Q 0x10
92*050d28e1SChandrakanth patil #define BNXT_EN_FLAG_MULTI_HOST 0x20
93*050d28e1SChandrakanth patil #define BNXT_EN_ASYM_Q(edev) ((edev)->flags & BNXT_EN_FLAG_ASYM_Q)
94*050d28e1SChandrakanth patil #define BNXT_EN_MH(edev) ((edev)->flags & BNXT_EN_FLAG_MULTI_HOST)
95*050d28e1SChandrakanth patil const struct bnxt_en_ops *en_ops;
96*050d28e1SChandrakanth patil struct bnxt_ulp ulp_tbl[BNXT_MAX_ULP];
97*050d28e1SChandrakanth patil int l2_db_size; /* Doorbell BAR size in
98*050d28e1SChandrakanth patil * bytes mapped by L2
99*050d28e1SChandrakanth patil * driver.
100*050d28e1SChandrakanth patil */
101*050d28e1SChandrakanth patil int l2_db_size_nc; /* Doorbell BAR size in
102*050d28e1SChandrakanth patil * bytes mapped as non-
103*050d28e1SChandrakanth patil * cacheable.
104*050d28e1SChandrakanth patil */
105*050d28e1SChandrakanth patil u32 ulp_version; /* bnxt_re checks the
106*050d28e1SChandrakanth patil * ulp_version is correct
107*050d28e1SChandrakanth patil * to ensure compatibility
108*050d28e1SChandrakanth patil * with bnxt_en.
109*050d28e1SChandrakanth patil */
110*050d28e1SChandrakanth patil #define BNXT_ULP_VERSION 0x695a0008 /* Change this when any interface
111*050d28e1SChandrakanth patil * structure or API changes
112*050d28e1SChandrakanth patil * between bnxt_en and bnxt_re.
113*050d28e1SChandrakanth patil */
114*050d28e1SChandrakanth patil unsigned long en_state;
115*050d28e1SChandrakanth patil void __iomem *bar0;
116*050d28e1SChandrakanth patil u16 hw_ring_stats_size;
117*050d28e1SChandrakanth patil u16 pf_port_id;
118*050d28e1SChandrakanth patil u8 port_partition_type;
119*050d28e1SChandrakanth patil #define BNXT_EN_NPAR(edev) ((edev)->port_partition_type)
120*050d28e1SChandrakanth patil u8 port_count;
121*050d28e1SChandrakanth patil struct bnxt_dbr *en_dbr;
122*050d28e1SChandrakanth patil struct bnxt_bar_info hwrm_bar;
123*050d28e1SChandrakanth patil u32 espeed;
124*050d28e1SChandrakanth patil };
125*050d28e1SChandrakanth patil
126*050d28e1SChandrakanth patil struct bnxt_en_ops {
127*050d28e1SChandrakanth patil int (*bnxt_register_device)(struct bnxt_en_dev *, int,
128*050d28e1SChandrakanth patil struct bnxt_ulp_ops *, void *);
129*050d28e1SChandrakanth patil int (*bnxt_unregister_device)(struct bnxt_en_dev *, int);
130*050d28e1SChandrakanth patil int (*bnxt_request_msix)(struct bnxt_en_dev *, int,
131*050d28e1SChandrakanth patil struct bnxt_msix_entry *, int);
132*050d28e1SChandrakanth patil int (*bnxt_free_msix)(struct bnxt_en_dev *, int);
133*050d28e1SChandrakanth patil int (*bnxt_send_fw_msg)(struct bnxt_en_dev *, int,
134*050d28e1SChandrakanth patil struct bnxt_fw_msg *);
135*050d28e1SChandrakanth patil int (*bnxt_register_fw_async_events)(struct bnxt_en_dev *, int,
136*050d28e1SChandrakanth patil unsigned long *, u16);
137*050d28e1SChandrakanth patil int (*bnxt_dbr_complete)(struct bnxt_en_dev *, int, u32);
138*050d28e1SChandrakanth patil };
139*050d28e1SChandrakanth patil
bnxt_ulp_registered(struct bnxt_en_dev * edev,int ulp_id)140*050d28e1SChandrakanth patil static inline bool bnxt_ulp_registered(struct bnxt_en_dev *edev, int ulp_id)
141*050d28e1SChandrakanth patil {
142*050d28e1SChandrakanth patil if (edev && rcu_access_pointer(edev->ulp_tbl[ulp_id].ulp_ops))
143*050d28e1SChandrakanth patil return true;
144*050d28e1SChandrakanth patil return false;
145*050d28e1SChandrakanth patil }
146*050d28e1SChandrakanth patil
147*050d28e1SChandrakanth patil int bnxt_get_ulp_msix_num(struct bnxt_softc *bp);
148*050d28e1SChandrakanth patil int bnxt_get_ulp_msix_base(struct bnxt_softc *bp);
149*050d28e1SChandrakanth patil int bnxt_get_ulp_stat_ctxs(struct bnxt_softc *bp);
150*050d28e1SChandrakanth patil void bnxt_ulp_stop(struct bnxt_softc *bp);
151*050d28e1SChandrakanth patil void bnxt_ulp_start(struct bnxt_softc *bp, int err);
152*050d28e1SChandrakanth patil void bnxt_ulp_sriov_cfg(struct bnxt_softc *bp, int num_vfs);
153*050d28e1SChandrakanth patil void bnxt_ulp_shutdown(struct bnxt_softc *bp);
154*050d28e1SChandrakanth patil void bnxt_ulp_irq_stop(struct bnxt_softc *bp);
155*050d28e1SChandrakanth patil void bnxt_ulp_irq_restart(struct bnxt_softc *bp, int err);
156*050d28e1SChandrakanth patil void bnxt_ulp_async_events(struct bnxt_softc *bp, struct hwrm_async_event_cmpl *cmpl);
157*050d28e1SChandrakanth patil struct bnxt_en_dev *bnxt_ulp_probe(struct net_device *dev);
158*050d28e1SChandrakanth patil void bnxt_aux_dev_release(struct device *dev);
159*050d28e1SChandrakanth patil int bnxt_rdma_aux_device_add(struct bnxt_softc *bp);
160*050d28e1SChandrakanth patil int bnxt_rdma_aux_device_del(struct bnxt_softc *bp);
161*050d28e1SChandrakanth patil #endif
162