1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #ifndef _BNXT_H 31 #define _BNXT_H 32 33 #include <sys/param.h> 34 #include <sys/socket.h> 35 #include <sys/sysctl.h> 36 #include <sys/taskqueue.h> 37 #include <sys/bitstring.h> 38 39 #include <machine/bus.h> 40 41 #include <net/ethernet.h> 42 #include <net/if.h> 43 #include <net/if_var.h> 44 #include <net/iflib.h> 45 #include <linux/types.h> 46 47 #include "hsi_struct_def.h" 48 #include "bnxt_dcb.h" 49 #include "bnxt_auxbus_compat.h" 50 51 #define DFLT_HWRM_CMD_TIMEOUT 500 52 53 /* PCI IDs */ 54 #define BROADCOM_VENDOR_ID 0x14E4 55 56 #define BCM57301 0x16c8 57 #define BCM57302 0x16c9 58 #define BCM57304 0x16ca 59 #define BCM57311 0x16ce 60 #define BCM57312 0x16cf 61 #define BCM57314 0x16df 62 #define BCM57402 0x16d0 63 #define BCM57402_NPAR 0x16d4 64 #define BCM57404 0x16d1 65 #define BCM57404_NPAR 0x16e7 66 #define BCM57406 0x16d2 67 #define BCM57406_NPAR 0x16e8 68 #define BCM57407 0x16d5 69 #define BCM57407_NPAR 0x16ea 70 #define BCM57407_SFP 0x16e9 71 #define BCM57412 0x16d6 72 #define BCM57412_NPAR1 0x16de 73 #define BCM57412_NPAR2 0x16eb 74 #define BCM57414 0x16d7 75 #define BCM57414_NPAR1 0x16ec 76 #define BCM57414_NPAR2 0x16ed 77 #define BCM57416 0x16d8 78 #define BCM57416_NPAR1 0x16ee 79 #define BCM57416_NPAR2 0x16ef 80 #define BCM57416_SFP 0x16e3 81 #define BCM57417 0x16d9 82 #define BCM57417_NPAR1 0x16c0 83 #define BCM57417_NPAR2 0x16cc 84 #define BCM57417_SFP 0x16e2 85 #define BCM57454 0x1614 86 #define BCM58700 0x16cd 87 #define BCM57508 0x1750 88 #define BCM57504 0x1751 89 #define BCM57504_NPAR 0x1801 90 #define BCM57502 0x1752 91 #define NETXTREME_C_VF1 0x16cb 92 #define NETXTREME_C_VF2 0x16e1 93 #define NETXTREME_C_VF3 0x16e5 94 #define NETXTREME_E_VF1 0x16c1 95 #define NETXTREME_E_VF2 0x16d3 96 #define NETXTREME_E_VF3 0x16dc 97 98 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ 99 (((data1) & \ 100 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 101 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) 102 103 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 104 (((data1) & \ 105 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >> \ 106 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 107 108 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ 109 (((data2) & \ 110 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >> \ 111 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) 112 113 #define BNXT_EVENT_DBR_EPOCH(data) \ 114 (((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >> \ 115 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT) 116 117 #define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2) \ 118 (((data2) & \ 119 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >> \ 120 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT) 121 122 #define EVENT_DATA2_NVM_ERR_ADDR(data2) \ 123 (((data2) & \ 124 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >> \ 125 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT) 126 127 #define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1) \ 128 (((data1) & \ 129 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) == \ 130 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING) 131 132 #define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1) \ 133 (((data1) & \ 134 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 135 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE) 136 137 #define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1) \ 138 (((data1) & \ 139 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 140 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE) 141 142 #define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1) \ 143 ((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK) 144 145 #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2) \ 146 ((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK) 147 148 #define EVENT_DATA1_RESET_NOTIFY_FW_ACTIVATION(data1) \ 149 (((data1) & \ 150 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 151 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_ACTIVATION) 152 153 #define EVENT_DATA2_RESET_NOTIFY_FW_STATUS_CODE(data2) \ 154 ((data2) & \ 155 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK) 156 157 #define EVENT_DATA1_RECOVERY_ENABLED(data1) \ 158 !!((data1) & \ 159 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_RECOVERY_ENABLED) 160 161 #define EVENT_DATA1_RECOVERY_MASTER_FUNC(data1) \ 162 !!((data1) & \ 163 HWRM_ASYNC_EVENT_CMPL_ERROR_RECOVERY_EVENT_DATA1_FLAGS_MASTER_FUNC) 164 165 #define INVALID_STATS_CTX_ID -1 166 167 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power 168 * of two. The hardware has no particular limitation. */ 169 #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1) 170 #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1) 171 172 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 173 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 174 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 175 176 #define BNXT_MAX_MTU 9600 177 178 #define BNXT_RSS_HASH_TYPE_TCPV4 0 179 #define BNXT_RSS_HASH_TYPE_UDPV4 1 180 #define BNXT_RSS_HASH_TYPE_IPV4 2 181 #define BNXT_RSS_HASH_TYPE_TCPV6 3 182 #define BNXT_RSS_HASH_TYPE_UDPV6 4 183 #define BNXT_RSS_HASH_TYPE_IPV6 5 184 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) 185 186 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF 187 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ 188 ((softc)->flags & BNXT_FLAG_WOL_CAP )) 189 190 /* 64-bit doorbell */ 191 #define DBR_INDEX_MASK 0x0000000000ffffffULL 192 #define DBR_PI_LO_MASK 0xff000000UL 193 #define DBR_PI_LO_SFT 24 194 #define DBR_XID_MASK 0x000fffff00000000ULL 195 #define DBR_XID_SFT 32 196 #define DBR_PI_HI_MASK 0xf0000000000000ULL 197 #define DBR_PI_HI_SFT 52 198 #define DBR_PATH_L2 (0x1ULL << 56) 199 #define DBR_VALID (0x1ULL << 58) 200 #define DBR_TYPE_SQ (0x0ULL << 60) 201 #define DBR_TYPE_RQ (0x1ULL << 60) 202 #define DBR_TYPE_SRQ (0x2ULL << 60) 203 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 204 #define DBR_TYPE_CQ (0x4ULL << 60) 205 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 206 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 207 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 208 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 209 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 210 #define DBR_TYPE_NQ (0xaULL << 60) 211 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 212 #define DBR_TYPE_PUSH_START (0xcULL << 60) 213 #define DBR_TYPE_PUSH_END (0xdULL << 60) 214 #define DBR_TYPE_NULL (0xfULL << 60) 215 216 #define BNXT_MAX_L2_QUEUES 128 217 #define BNXT_ROCE_IRQ_COUNT 9 218 219 #define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT) 220 221 /* Completion related defines */ 222 #define CMP_VALID(cmp, v_bit) \ 223 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 224 225 /* Chip class phase 5 */ 226 #define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5)) 227 228 #define DB_PF_OFFSET_P5 0x10000 229 #define DB_VF_OFFSET_P5 0x4000 230 #define NQ_VALID(cmp, v_bit) \ 231 ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) ) 232 233 #ifndef DIV_ROUND_UP 234 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 235 #endif 236 #ifndef roundup 237 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 238 #endif 239 240 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 241 if (__predict_false(++(cons) == (ring)->ring_size)) \ 242 ((cons) = 0, (v_bit) = !v_bit); \ 243 } while (0) 244 245 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 246 0 : idx + 1) 247 248 #define CMPL_PREFETCH_NEXT(cpr, idx) \ 249 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 250 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 251 ((cpr)->ring.ring_size - 1)]) 252 253 /* Lock macros */ 254 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 255 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 256 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 257 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 258 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 259 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 260 MA_OWNED) 261 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ 262 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ 263 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ 264 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) 265 266 /* Chip info */ 267 #define BNXT_TSO_SIZE UINT16_MAX 268 269 #define min_t(type, x, y) ({ \ 270 type __min1 = (x); \ 271 type __min2 = (y); \ 272 __min1 < __min2 ? __min1 : __min2; }) 273 274 #define max_t(type, x, y) ({ \ 275 type __max1 = (x); \ 276 type __max2 = (y); \ 277 __max1 > __max2 ? __max1 : __max2; }) 278 279 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 280 281 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ 282 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ 283 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ 284 } while(0) 285 286 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ 287 288 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 289 (offsetof(struct rx_port_stats_ext, counter) / 8) 290 291 #define BNXT_RX_STATS_EXT_NUM_LEGACY \ 292 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks) 293 294 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 295 (offsetof(struct tx_port_stats_ext, counter) / 8) 296 297 extern const char bnxt_driver_version[]; 298 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx); 299 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx); 300 typedef void (*bnxt_doorbell_rx_cq)(void *, bool); 301 typedef void (*bnxt_doorbell_tx_cq)(void *, bool); 302 typedef void (*bnxt_doorbell_nq)(void *, bool); 303 304 typedef struct bnxt_doorbell_ops { 305 bnxt_doorbell_tx bnxt_db_tx; 306 bnxt_doorbell_rx bnxt_db_rx; 307 bnxt_doorbell_rx_cq bnxt_db_rx_cq; 308 bnxt_doorbell_tx_cq bnxt_db_tx_cq; 309 bnxt_doorbell_nq bnxt_db_nq; 310 } bnxt_dooorbell_ops_t; 311 /* NVRAM access */ 312 enum bnxt_nvm_directory_type { 313 BNX_DIR_TYPE_UNUSED = 0, 314 BNX_DIR_TYPE_PKG_LOG = 1, 315 BNX_DIR_TYPE_UPDATE = 2, 316 BNX_DIR_TYPE_CHIMP_PATCH = 3, 317 BNX_DIR_TYPE_BOOTCODE = 4, 318 BNX_DIR_TYPE_VPD = 5, 319 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 320 BNX_DIR_TYPE_AVS = 7, 321 BNX_DIR_TYPE_PCIE = 8, 322 BNX_DIR_TYPE_PORT_MACRO = 9, 323 BNX_DIR_TYPE_APE_FW = 10, 324 BNX_DIR_TYPE_APE_PATCH = 11, 325 BNX_DIR_TYPE_KONG_FW = 12, 326 BNX_DIR_TYPE_KONG_PATCH = 13, 327 BNX_DIR_TYPE_BONO_FW = 14, 328 BNX_DIR_TYPE_BONO_PATCH = 15, 329 BNX_DIR_TYPE_TANG_FW = 16, 330 BNX_DIR_TYPE_TANG_PATCH = 17, 331 BNX_DIR_TYPE_BOOTCODE_2 = 18, 332 BNX_DIR_TYPE_CCM = 19, 333 BNX_DIR_TYPE_PCI_CFG = 20, 334 BNX_DIR_TYPE_TSCF_UCODE = 21, 335 BNX_DIR_TYPE_ISCSI_BOOT = 22, 336 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 337 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 338 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 339 BNX_DIR_TYPE_EXT_PHY = 27, 340 BNX_DIR_TYPE_SHARED_CFG = 40, 341 BNX_DIR_TYPE_PORT_CFG = 41, 342 BNX_DIR_TYPE_FUNC_CFG = 42, 343 BNX_DIR_TYPE_MGMT_CFG = 48, 344 BNX_DIR_TYPE_MGMT_DATA = 49, 345 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 346 BNX_DIR_TYPE_MGMT_WEB_META = 51, 347 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 348 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 349 }; 350 351 enum bnxnvm_pkglog_field_index { 352 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 353 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 354 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 355 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 356 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 357 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 358 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 359 }; 360 361 #define BNX_DIR_ORDINAL_FIRST 0 362 #define BNX_DIR_EXT_NONE 0 363 364 struct bnxt_bar_info { 365 struct resource *res; 366 bus_space_tag_t tag; 367 bus_space_handle_t handle; 368 bus_size_t size; 369 int rid; 370 }; 371 372 struct bnxt_flow_ctrl { 373 bool rx; 374 bool tx; 375 bool autoneg; 376 }; 377 378 struct bnxt_link_info { 379 uint8_t media_type; 380 uint8_t transceiver; 381 uint8_t phy_addr; 382 uint8_t phy_link_status; 383 uint8_t wire_speed; 384 uint8_t loop_back; 385 uint8_t link_up; 386 uint8_t last_link_up; 387 uint8_t duplex; 388 uint8_t last_duplex; 389 uint8_t last_phy_type; 390 struct bnxt_flow_ctrl flow_ctrl; 391 struct bnxt_flow_ctrl last_flow_ctrl; 392 uint8_t duplex_setting; 393 uint8_t auto_mode; 394 #define PHY_VER_LEN 3 395 uint8_t phy_ver[PHY_VER_LEN]; 396 uint8_t phy_type; 397 #define BNXT_PHY_STATE_ENABLED 0 398 #define BNXT_PHY_STATE_DISABLED 1 399 uint8_t phy_state; 400 401 uint16_t link_speed; 402 uint16_t support_speeds; 403 uint16_t support_pam4_speeds; 404 uint16_t auto_link_speeds; 405 uint16_t auto_pam4_link_speeds; 406 uint16_t force_link_speed; 407 uint16_t force_pam4_link_speed; 408 bool force_pam4_speed_set_by_user; 409 410 uint16_t advertising; 411 uint16_t advertising_pam4; 412 413 uint32_t preemphasis; 414 uint16_t support_auto_speeds; 415 uint16_t support_force_speeds; 416 uint16_t support_pam4_auto_speeds; 417 uint16_t support_pam4_force_speeds; 418 #define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ 419 #define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 420 uint8_t req_signal_mode; 421 422 uint8_t active_fec_sig_mode; 423 uint8_t sig_mode; 424 425 /* copy of requested setting */ 426 uint8_t autoneg; 427 #define BNXT_AUTONEG_SPEED 1 428 #define BNXT_AUTONEG_FLOW_CTRL 2 429 uint8_t req_duplex; 430 uint16_t req_link_speed; 431 uint8_t module_status; 432 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 433 }; 434 435 enum bnxt_phy_type { 436 BNXT_MEDIA_CR = 0, 437 BNXT_MEDIA_LR, 438 BNXT_MEDIA_SR, 439 BNXT_MEDIA_KR, 440 BNXT_MEDIA_END 441 }; 442 443 enum bnxt_cp_type { 444 BNXT_DEFAULT, 445 BNXT_TX, 446 BNXT_RX, 447 BNXT_SHARED 448 }; 449 450 struct bnxt_queue_info { 451 uint8_t queue_id; 452 uint8_t queue_profile; 453 }; 454 455 struct bnxt_func_info { 456 uint32_t fw_fid; 457 uint8_t mac_addr[ETHER_ADDR_LEN]; 458 uint16_t max_rsscos_ctxs; 459 uint16_t max_cp_rings; 460 uint16_t max_tx_rings; 461 uint16_t max_rx_rings; 462 uint16_t max_hw_ring_grps; 463 uint16_t max_irqs; 464 uint16_t max_l2_ctxs; 465 uint16_t max_vnics; 466 uint16_t max_stat_ctxs; 467 }; 468 469 struct bnxt_pf_info { 470 #define BNXT_FIRST_PF_FID 1 471 #define BNXT_FIRST_VF_FID 128 472 uint8_t port_id; 473 uint32_t first_vf_id; 474 uint16_t active_vfs; 475 uint16_t max_vfs; 476 uint32_t max_encap_records; 477 uint32_t max_decap_records; 478 uint32_t max_tx_em_flows; 479 uint32_t max_tx_wm_flows; 480 uint32_t max_rx_em_flows; 481 uint32_t max_rx_wm_flows; 482 unsigned long *vf_event_bmap; 483 uint16_t hwrm_cmd_req_pages; 484 void *hwrm_cmd_req_addr[4]; 485 bus_addr_t hwrm_cmd_req_dma_addr[4]; 486 }; 487 488 struct bnxt_vf_info { 489 uint16_t fw_fid; 490 uint8_t mac_addr[ETHER_ADDR_LEN]; 491 uint16_t max_rsscos_ctxs; 492 uint16_t max_cp_rings; 493 uint16_t max_tx_rings; 494 uint16_t max_rx_rings; 495 uint16_t max_hw_ring_grps; 496 uint16_t max_l2_ctxs; 497 uint16_t max_irqs; 498 uint16_t max_vnics; 499 uint16_t max_stat_ctxs; 500 uint32_t vlan; 501 #define BNXT_VF_QOS 0x1 502 #define BNXT_VF_SPOOFCHK 0x2 503 #define BNXT_VF_LINK_FORCED 0x4 504 #define BNXT_VF_LINK_UP 0x8 505 uint32_t flags; 506 uint32_t func_flags; /* func cfg flags */ 507 uint32_t min_tx_rate; 508 uint32_t max_tx_rate; 509 void *hwrm_cmd_req_addr; 510 bus_addr_t hwrm_cmd_req_dma_addr; 511 }; 512 513 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 514 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 515 516 struct bnxt_vlan_tag { 517 SLIST_ENTRY(bnxt_vlan_tag) next; 518 uint64_t filter_id; 519 uint16_t tag; 520 }; 521 522 struct bnxt_vnic_info { 523 uint16_t id; 524 uint16_t def_ring_grp; 525 uint16_t cos_rule; 526 uint16_t lb_rule; 527 uint16_t mru; 528 529 uint32_t rx_mask; 530 struct iflib_dma_info mc_list; 531 int mc_list_count; 532 #define BNXT_MAX_MC_ADDRS 16 533 534 uint32_t flags; 535 #define BNXT_VNIC_FLAG_DEFAULT 0x01 536 #define BNXT_VNIC_FLAG_BD_STALL 0x02 537 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 538 539 uint64_t filter_id; 540 541 uint16_t rss_id; 542 uint32_t rss_hash_type; 543 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 544 struct iflib_dma_info rss_hash_key_tbl; 545 struct iflib_dma_info rss_grp_tbl; 546 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 547 struct iflib_dma_info vlan_tag_list; 548 }; 549 550 struct bnxt_grp_info { 551 uint16_t stats_ctx; 552 uint16_t grp_id; 553 uint16_t rx_ring_id; 554 uint16_t cp_ring_id; 555 uint16_t ag_ring_id; 556 }; 557 558 struct bnxt_ring { 559 uint64_t paddr; 560 vm_offset_t doorbell; 561 caddr_t vaddr; 562 struct bnxt_softc *softc; 563 uint32_t ring_size; /* Must be a power of two */ 564 uint16_t id; /* Logical ID */ 565 uint16_t phys_id; 566 uint16_t idx; 567 struct bnxt_full_tpa_start *tpa_start; 568 }; 569 570 struct bnxt_cp_ring { 571 struct bnxt_ring ring; 572 struct if_irq irq; 573 uint32_t cons; 574 bool v_bit; /* Value of valid bit */ 575 struct ctx_hw_stats *stats; 576 uint32_t stats_ctx_id; 577 uint32_t last_idx; /* Used by RX rings only 578 * set to the last read pidx 579 */ 580 uint64_t int_count; 581 }; 582 583 struct bnxt_full_tpa_start { 584 struct rx_tpa_start_cmpl low; 585 struct rx_tpa_start_cmpl_hi high; 586 }; 587 588 /* All the version information for the part */ 589 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 590 #define BNXT_NAME_SIZE 17 591 #define FW_VER_STR_LEN 32 592 #define BC_HWRM_STR_LEN 21 593 struct bnxt_ver_info { 594 uint8_t hwrm_if_major; 595 uint8_t hwrm_if_minor; 596 uint8_t hwrm_if_update; 597 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 598 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 599 char mgmt_fw_ver[FW_VER_STR_LEN]; 600 char netctrl_fw_ver[FW_VER_STR_LEN]; 601 char roce_fw_ver[FW_VER_STR_LEN]; 602 char fw_ver_str[FW_VER_STR_LEN]; 603 char phy_ver[BNXT_VERSTR_SIZE]; 604 char pkg_ver[64]; 605 606 char hwrm_fw_name[BNXT_NAME_SIZE]; 607 char mgmt_fw_name[BNXT_NAME_SIZE]; 608 char netctrl_fw_name[BNXT_NAME_SIZE]; 609 char roce_fw_name[BNXT_NAME_SIZE]; 610 char phy_vendor[BNXT_NAME_SIZE]; 611 char phy_partnumber[BNXT_NAME_SIZE]; 612 613 uint16_t chip_num; 614 uint8_t chip_rev; 615 uint8_t chip_metal; 616 uint8_t chip_bond_id; 617 uint8_t chip_type; 618 619 uint8_t hwrm_min_major; 620 uint8_t hwrm_min_minor; 621 uint8_t hwrm_min_update; 622 uint64_t fw_ver_code; 623 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ 624 ((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv)) 625 #define BNXT_FW_MAJ(softc) ((softc)->ver_info->fw_ver_code >> 48) 626 #define BNXT_FW_MIN(softc) (((softc)->ver_info->fw_ver_code >> 32) & 0xffff) 627 #define BNXT_FW_BLD(softc) (((softc)->ver_info->fw_ver_code >> 16) & 0xffff) 628 #define BNXT_FW_RSV(softc) (((softc)->ver_info->fw_ver_code) & 0xffff) 629 630 struct sysctl_ctx_list ver_ctx; 631 struct sysctl_oid *ver_oid; 632 }; 633 634 struct bnxt_nvram_info { 635 uint16_t mfg_id; 636 uint16_t device_id; 637 uint32_t sector_size; 638 uint32_t size; 639 uint32_t reserved_size; 640 uint32_t available_size; 641 642 struct sysctl_ctx_list nvm_ctx; 643 struct sysctl_oid *nvm_oid; 644 }; 645 646 struct bnxt_func_qcfg { 647 uint16_t alloc_completion_rings; 648 uint16_t alloc_tx_rings; 649 uint16_t alloc_rx_rings; 650 uint16_t alloc_vnics; 651 }; 652 653 struct bnxt_hw_lro { 654 uint16_t enable; 655 uint16_t is_mode_gro; 656 uint16_t max_agg_segs; 657 uint16_t max_aggs; 658 uint32_t min_agg_len; 659 }; 660 661 /* The hardware supports certain page sizes. Use the supported page sizes 662 * to allocate the rings. 663 */ 664 #if (PAGE_SHIFT < 12) 665 #define BNXT_PAGE_SHIFT 12 666 #elif (PAGE_SHIFT <= 13) 667 #define BNXT_PAGE_SHIFT PAGE_SHIFT 668 #elif (PAGE_SHIFT < 16) 669 #define BNXT_PAGE_SHIFT 13 670 #else 671 #define BNXT_PAGE_SHIFT 16 672 #endif 673 674 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 675 676 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 677 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 678 679 struct bnxt_ring_mem_info { 680 int nr_pages; 681 int page_size; 682 uint16_t flags; 683 #define BNXT_RMEM_VALID_PTE_FLAG 1 684 #define BNXT_RMEM_RING_PTE_FLAG 2 685 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 686 uint16_t depth; 687 struct bnxt_ctx_mem_type *ctx_mem; 688 689 struct iflib_dma_info *pg_arr; 690 struct iflib_dma_info pg_tbl; 691 692 int vmem_size; 693 void **vmem; 694 }; 695 696 struct bnxt_ctx_pg_info { 697 uint32_t entries; 698 uint32_t nr_pages; 699 struct iflib_dma_info ctx_arr[MAX_CTX_PAGES]; 700 struct bnxt_ring_mem_info ring_mem; 701 struct bnxt_ctx_pg_info **ctx_pg_tbl; 702 }; 703 704 #define BNXT_MAX_TQM_SP_RINGS 1 705 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 706 #define BNXT_MAX_TQM_FP_RINGS 9 707 #define BNXT_MAX_TQM_LEGACY_RINGS \ 708 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 709 #define BNXT_MAX_TQM_RINGS \ 710 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 711 712 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 713 #define BNXT_BACKING_STORE_CFG_LEN \ 714 sizeof(struct hwrm_func_backing_store_cfg_input) 715 716 #define BNXT_SET_CTX_PAGE_ATTR(attr) \ 717 do { \ 718 if (BNXT_PAGE_SIZE == 0x2000) \ 719 attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_SRQ_PG_SIZE_PG_8K; \ 720 else if (BNXT_PAGE_SIZE == 0x10000) \ 721 attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_64K; \ 722 else \ 723 attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_4K; \ 724 } while (0) 725 726 struct bnxt_ctx_mem_type { 727 u16 type; 728 u16 entry_size; 729 u32 flags; 730 #define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID 731 u32 instance_bmap; 732 u8 init_value; 733 u8 entry_multiple; 734 u16 init_offset; 735 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff 736 u32 max_entries; 737 u32 min_entries; 738 u8 split_entry_cnt; 739 #define BNXT_MAX_SPLIT_ENTRY 4 740 union { 741 struct { 742 u32 qp_l2_entries; 743 u32 qp_qp1_entries; 744 }; 745 u32 srq_l2_entries; 746 u32 cq_l2_entries; 747 u32 vnic_entries; 748 struct { 749 u32 mrav_av_entries; 750 u32 mrav_num_entries_units; 751 }; 752 u32 split[BNXT_MAX_SPLIT_ENTRY]; 753 }; 754 struct bnxt_ctx_pg_info *pg_info; 755 }; 756 757 #define BNXT_CTX_QP HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP 758 #define BNXT_CTX_SRQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ 759 #define BNXT_CTX_CQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ 760 #define BNXT_CTX_VNIC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC 761 #define BNXT_CTX_STAT HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT 762 #define BNXT_CTX_STQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING 763 #define BNXT_CTX_FTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING 764 #define BNXT_CTX_MRAV HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV 765 #define BNXT_CTX_TIM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM 766 #define BNXT_CTX_TKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC 767 #define BNXT_CTX_RKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC 768 #define BNXT_CTX_MTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING 769 #define BNXT_CTX_SQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW 770 #define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW 771 #define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW 772 #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW 773 #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC 774 #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC 775 #define BNXT_CTX_MAX (BNXT_CTX_TIM + 1) 776 777 struct bnxt_ctx_mem_info { 778 u8 tqm_fp_rings_count; 779 780 u32 flags; 781 #define BNXT_CTX_FLAG_INITED 0x01 782 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_MAX]; 783 }; 784 785 struct bnxt_hw_resc { 786 uint16_t min_rsscos_ctxs; 787 uint16_t max_rsscos_ctxs; 788 uint16_t min_cp_rings; 789 uint16_t max_cp_rings; 790 uint16_t resv_cp_rings; 791 uint16_t min_tx_rings; 792 uint16_t max_tx_rings; 793 uint16_t resv_tx_rings; 794 uint16_t max_tx_sch_inputs; 795 uint16_t min_rx_rings; 796 uint16_t max_rx_rings; 797 uint16_t resv_rx_rings; 798 uint16_t min_hw_ring_grps; 799 uint16_t max_hw_ring_grps; 800 uint16_t resv_hw_ring_grps; 801 uint16_t min_l2_ctxs; 802 uint16_t max_l2_ctxs; 803 uint16_t min_vnics; 804 uint16_t max_vnics; 805 uint16_t resv_vnics; 806 uint16_t min_stat_ctxs; 807 uint16_t max_stat_ctxs; 808 uint16_t resv_stat_ctxs; 809 uint16_t max_nqs; 810 uint16_t max_irqs; 811 uint16_t resv_irqs; 812 }; 813 814 enum bnxt_type_ets { 815 BNXT_TYPE_ETS_TSA = 0, 816 BNXT_TYPE_ETS_PRI2TC, 817 BNXT_TYPE_ETS_TCBW, 818 BNXT_TYPE_ETS_MAX 819 }; 820 821 static const char *const BNXT_ETS_TYPE_STR[] = { 822 "tsa", 823 "pri2tc", 824 "tcbw", 825 }; 826 827 static const char *const BNXT_ETS_HELP_STR[] = { 828 "X is 1 (strict), 0 (ets)", 829 "TC values for pri 0 to 7", 830 "TC BW values for pri 0 to 7, Sum should be 100", 831 }; 832 833 #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len) 834 835 struct bnxt_softc_list { 836 SLIST_ENTRY(bnxt_softc_list) next; 837 struct bnxt_softc *softc; 838 }; 839 840 #ifndef BIT_ULL 841 #define BIT_ULL(nr) (1ULL << (nr)) 842 #endif 843 844 struct bnxt_aux_dev { 845 struct auxiliary_device aux_dev; 846 struct bnxt_en_dev *edev; 847 int id; 848 }; 849 850 struct bnxt_msix_tbl { 851 uint32_t entry; 852 uint32_t vector; 853 }; 854 855 enum bnxt_health_severity { 856 SEVERITY_NORMAL = 0, 857 SEVERITY_WARNING, 858 SEVERITY_RECOVERABLE, 859 SEVERITY_FATAL, 860 }; 861 862 enum bnxt_health_remedy { 863 REMEDY_DEVLINK_RECOVER, 864 REMEDY_POWER_CYCLE_DEVICE, 865 REMEDY_POWER_CYCLE_HOST, 866 REMEDY_FW_UPDATE, 867 REMEDY_HW_REPLACE, 868 }; 869 870 struct bnxt_fw_health { 871 u32 flags; 872 u32 polling_dsecs; 873 u32 master_func_wait_dsecs; 874 u32 normal_func_wait_dsecs; 875 u32 post_reset_wait_dsecs; 876 u32 post_reset_max_wait_dsecs; 877 u32 regs[4]; 878 u32 mapped_regs[4]; 879 #define BNXT_FW_HEALTH_REG 0 880 #define BNXT_FW_HEARTBEAT_REG 1 881 #define BNXT_FW_RESET_CNT_REG 2 882 #define BNXT_FW_RESET_INPROG_REG 3 883 u32 fw_reset_inprog_reg_mask; 884 u32 last_fw_heartbeat; 885 u32 last_fw_reset_cnt; 886 u8 enabled:1; 887 u8 primary:1; 888 u8 status_reliable:1; 889 u8 resets_reliable:1; 890 u8 tmr_multiplier; 891 u8 tmr_counter; 892 u8 fw_reset_seq_cnt; 893 u32 fw_reset_seq_regs[16]; 894 u32 fw_reset_seq_vals[16]; 895 u32 fw_reset_seq_delay_msec[16]; 896 u32 echo_req_data1; 897 u32 echo_req_data2; 898 struct devlink_health_reporter *fw_reporter; 899 struct mutex lock; 900 enum bnxt_health_severity severity; 901 enum bnxt_health_remedy remedy; 902 u32 arrests; 903 u32 discoveries; 904 u32 survivals; 905 u32 fatalities; 906 u32 diagnoses; 907 }; 908 909 #define BNXT_FW_HEALTH_REG_TYPE_MASK 3 910 #define BNXT_FW_HEALTH_REG_TYPE_CFG 0 911 #define BNXT_FW_HEALTH_REG_TYPE_GRC 1 912 #define BNXT_FW_HEALTH_REG_TYPE_BAR0 2 913 #define BNXT_FW_HEALTH_REG_TYPE_BAR1 3 914 915 #define BNXT_FW_HEALTH_REG_TYPE(reg) ((reg) & BNXT_FW_HEALTH_REG_TYPE_MASK) 916 #define BNXT_FW_HEALTH_REG_OFF(reg) ((reg) & ~BNXT_FW_HEALTH_REG_TYPE_MASK) 917 918 #define BNXT_FW_HEALTH_WIN_BASE 0x3000 919 #define BNXT_FW_HEALTH_WIN_MAP_OFF 8 920 921 #define BNXT_FW_HEALTH_WIN_OFF(reg) (BNXT_FW_HEALTH_WIN_BASE + \ 922 ((reg) & BNXT_GRC_OFFSET_MASK)) 923 924 #define BNXT_FW_STATUS_HEALTH_MSK 0xffff 925 #define BNXT_FW_STATUS_HEALTHY 0x8000 926 #define BNXT_FW_STATUS_SHUTDOWN 0x100000 927 #define BNXT_FW_STATUS_RECOVERING 0x400000 928 929 #define BNXT_FW_IS_HEALTHY(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) ==\ 930 BNXT_FW_STATUS_HEALTHY) 931 932 #define BNXT_FW_IS_BOOTING(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) < \ 933 BNXT_FW_STATUS_HEALTHY) 934 935 #define BNXT_FW_IS_ERR(sts) (((sts) & BNXT_FW_STATUS_HEALTH_MSK) > \ 936 BNXT_FW_STATUS_HEALTHY) 937 938 #define BNXT_FW_IS_RECOVERING(sts) (BNXT_FW_IS_ERR(sts) && \ 939 ((sts) & BNXT_FW_STATUS_RECOVERING)) 940 941 #define BNXT_FW_RETRY 5 942 #define BNXT_FW_IF_RETRY 10 943 #define BNXT_FW_SLOT_RESET_RETRY 4 944 945 #define BNXT_GRCPF_REG_CHIMP_COMM 0x0 946 #define BNXT_GRCPF_REG_CHIMP_COMM_TRIGGER 0x100 947 #define BNXT_GRCPF_REG_WINDOW_BASE_OUT 0x400 948 #define BNXT_GRCPF_REG_SYNC_TIME 0x480 949 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ 0x488 950 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_MSK 0xffffffUL 951 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_PER_SFT 0 952 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_MSK 0x1f000000UL 953 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_VAL_SFT 24 954 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_MSK 0x20000000UL 955 #define BNXT_GRCPF_REG_SYNC_TIME_ADJ_SIGN_SFT 29 956 957 #define BNXT_GRC_REG_STATUS_P5 0x520 958 959 #define BNXT_GRCPF_REG_KONG_COMM 0xA00 960 #define BNXT_GRCPF_REG_KONG_COMM_TRIGGER 0xB00 961 962 #define BNXT_CAG_REG_LEGACY_INT_STATUS 0x4014 963 #define BNXT_CAG_REG_BASE 0x300000 964 965 #define BNXT_GRC_REG_CHIP_NUM 0x48 966 #define BNXT_GRC_REG_BASE 0x260000 967 968 #define BNXT_TS_REG_TIMESYNC_TS0_LOWER 0x640180c 969 #define BNXT_TS_REG_TIMESYNC_TS0_UPPER 0x6401810 970 971 #define BNXT_GRC_BASE_MASK 0xfffff000 972 #define BNXT_GRC_OFFSET_MASK 0x00000ffc 973 struct bnxt_softc { 974 device_t dev; 975 if_ctx_t ctx; 976 if_softc_ctx_t scctx; 977 if_shared_ctx_t sctx; 978 if_t ifp; 979 uint32_t domain; 980 uint32_t bus; 981 uint32_t slot; 982 uint32_t function; 983 uint32_t dev_fn; 984 struct ifmedia *media; 985 struct bnxt_ctx_mem_info *ctx_mem; 986 struct bnxt_hw_resc hw_resc; 987 struct bnxt_softc_list list; 988 989 struct bnxt_bar_info hwrm_bar; 990 struct bnxt_bar_info doorbell_bar; 991 struct bnxt_link_info link_info; 992 #define BNXT_FLAG_VF 0x0001 993 #define BNXT_FLAG_NPAR 0x0002 994 #define BNXT_FLAG_WOL_CAP 0x0004 995 #define BNXT_FLAG_SHORT_CMD 0x0008 996 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010 997 #define BNXT_FLAG_CHIP_P5 0x0020 998 #define BNXT_FLAG_TPA 0x0040 999 #define BNXT_FLAG_FW_CAP_EXT_STATS 0x0080 1000 #define BNXT_FLAG_MULTI_HOST 0x0100 1001 #define BNXT_FLAG_MULTI_ROOT 0x0200 1002 #define BNXT_FLAG_ROCEV1_CAP 0x0400 1003 #define BNXT_FLAG_ROCEV2_CAP 0x0800 1004 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP) 1005 uint32_t flags; 1006 #define BNXT_STATE_LINK_CHANGE (0) 1007 #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1) 1008 bitstr_t *state_bv; 1009 1010 uint32_t total_irqs; 1011 struct bnxt_msix_tbl *irq_tbl; 1012 1013 struct bnxt_func_info func; 1014 struct bnxt_func_qcfg fn_qcfg; 1015 struct bnxt_pf_info pf; 1016 struct bnxt_vf_info vf; 1017 1018 uint16_t hwrm_cmd_seq; 1019 uint32_t hwrm_cmd_timeo; /* milliseconds */ 1020 struct iflib_dma_info hwrm_cmd_resp; 1021 struct iflib_dma_info hwrm_short_cmd_req_addr; 1022 /* Interrupt info for HWRM */ 1023 struct if_irq irq; 1024 struct mtx hwrm_lock; 1025 uint16_t hwrm_max_req_len; 1026 uint16_t hwrm_max_ext_req_len; 1027 uint32_t hwrm_spec_code; 1028 1029 #define BNXT_MAX_QUEUE 8 1030 uint8_t max_tc; 1031 uint8_t max_lltc; 1032 struct bnxt_queue_info tx_q_info[BNXT_MAX_QUEUE]; 1033 struct bnxt_queue_info rx_q_info[BNXT_MAX_QUEUE]; 1034 uint8_t tc_to_qidx[BNXT_MAX_QUEUE]; 1035 uint8_t tx_q_ids[BNXT_MAX_QUEUE]; 1036 uint8_t rx_q_ids[BNXT_MAX_QUEUE]; 1037 uint8_t tx_max_q; 1038 uint8_t rx_max_q; 1039 uint8_t is_asym_q; 1040 1041 struct bnxt_ieee_ets *ieee_ets; 1042 struct bnxt_ieee_pfc *ieee_pfc; 1043 uint8_t dcbx_cap; 1044 uint8_t default_pri; 1045 uint8_t max_dscp_value; 1046 1047 uint64_t admin_ticks; 1048 struct iflib_dma_info hw_rx_port_stats; 1049 struct iflib_dma_info hw_tx_port_stats; 1050 struct rx_port_stats *rx_port_stats; 1051 struct tx_port_stats *tx_port_stats; 1052 1053 struct iflib_dma_info hw_tx_port_stats_ext; 1054 struct iflib_dma_info hw_rx_port_stats_ext; 1055 struct tx_port_stats_ext *tx_port_stats_ext; 1056 struct rx_port_stats_ext *rx_port_stats_ext; 1057 1058 uint16_t fw_rx_stats_ext_size; 1059 uint16_t fw_tx_stats_ext_size; 1060 uint16_t hw_ring_stats_size; 1061 1062 uint8_t tx_pri2cos_idx[8]; 1063 uint8_t rx_pri2cos_idx[8]; 1064 bool pri2cos_valid; 1065 1066 uint64_t tx_bytes_pri[8]; 1067 uint64_t tx_packets_pri[8]; 1068 uint64_t rx_bytes_pri[8]; 1069 uint64_t rx_packets_pri[8]; 1070 1071 uint8_t port_count; 1072 int num_cp_rings; 1073 1074 struct bnxt_cp_ring *nq_rings; 1075 1076 struct bnxt_ring *tx_rings; 1077 struct bnxt_cp_ring *tx_cp_rings; 1078 struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES]; 1079 int ntxqsets; 1080 1081 struct bnxt_vnic_info vnic_info; 1082 struct bnxt_ring *ag_rings; 1083 struct bnxt_ring *rx_rings; 1084 struct bnxt_cp_ring *rx_cp_rings; 1085 struct bnxt_grp_info *grp_info; 1086 struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES]; 1087 int nrxqsets; 1088 uint16_t rx_buf_size; 1089 1090 struct bnxt_cp_ring def_cp_ring; 1091 struct bnxt_cp_ring def_nq_ring; 1092 struct iflib_dma_info def_cp_ring_mem; 1093 struct iflib_dma_info def_nq_ring_mem; 1094 struct grouptask def_cp_task; 1095 int db_size; 1096 int legacy_db_size; 1097 struct bnxt_doorbell_ops db_ops; 1098 1099 struct sysctl_ctx_list hw_stats; 1100 struct sysctl_oid *hw_stats_oid; 1101 struct sysctl_ctx_list hw_lro_ctx; 1102 struct sysctl_oid *hw_lro_oid; 1103 struct sysctl_ctx_list flow_ctrl_ctx; 1104 struct sysctl_oid *flow_ctrl_oid; 1105 struct sysctl_ctx_list dcb_ctx; 1106 struct sysctl_oid *dcb_oid; 1107 1108 struct bnxt_ver_info *ver_info; 1109 struct bnxt_nvram_info *nvm_info; 1110 bool wol; 1111 bool is_dev_init; 1112 struct bnxt_hw_lro hw_lro; 1113 uint8_t wol_filter_id; 1114 uint16_t rx_coal_usecs; 1115 uint16_t rx_coal_usecs_irq; 1116 uint16_t rx_coal_frames; 1117 uint16_t rx_coal_frames_irq; 1118 uint16_t tx_coal_usecs; 1119 uint16_t tx_coal_usecs_irq; 1120 uint16_t tx_coal_frames; 1121 uint16_t tx_coal_frames_irq; 1122 1123 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 1124 #define BNXT_DEF_STATS_COAL_TICKS 1000000 1125 #define BNXT_MIN_STATS_COAL_TICKS 250000 1126 #define BNXT_MAX_STATS_COAL_TICKS 1000000 1127 1128 uint64_t fw_cap; 1129 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0) 1130 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1) 1131 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2) 1132 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3) 1133 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4) 1134 #define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5) 1135 #define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6) 1136 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) 1137 #define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8) 1138 #define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9) 1139 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) 1140 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) 1141 #define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12) 1142 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) 1143 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14) 1144 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15) 1145 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16) 1146 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17) 1147 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18) 1148 #define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19) 1149 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20) 1150 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21) 1151 #define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23) 1152 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24) 1153 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25) 1154 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26) 1155 #define BNXT_FW_CAP_CFA_EEM BIT_ULL(27) 1156 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29) 1157 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30) 1158 #define BNXT_FW_CAP_ECN_STATS BIT_ULL(31) 1159 #define BNXT_FW_CAP_TRUFLOW BIT_ULL(32) 1160 #define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33) 1161 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(34) 1162 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35) 1163 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36) 1164 #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37) 1165 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38) 1166 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(39) 1167 #define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40) 1168 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 1169 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41) 1170 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42) 1171 #define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43) 1172 #define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44) 1173 #define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45) 1174 #define BNXT_FW_CAP_PTP_PTM BIT_ULL(46) 1175 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47) 1176 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48) 1177 #define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49) 1178 uint32_t lpi_tmr_lo; 1179 uint32_t lpi_tmr_hi; 1180 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */ 1181 uint16_t phy_flags; 1182 #define BNXT_PHY_FL_EEE_CAP HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED 1183 #define BNXT_PHY_FL_EXT_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED 1184 #define BNXT_PHY_FL_AN_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED 1185 #define BNXT_PHY_FL_SHARED_PORT_CFG HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED 1186 #define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 1187 #define BNXT_PHY_FL_NO_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 1188 #define BNXT_PHY_FL_FW_MANAGED_LKDN HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN 1189 #define BNXT_PHY_FL_NO_FCS HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS 1190 #define BNXT_PHY_FL_NO_PAUSE (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8) 1191 #define BNXT_PHY_FL_NO_PFC (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8) 1192 #define BNXT_PHY_FL_BANK_SEL (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8) 1193 struct bnxt_aux_dev *aux_dev; 1194 struct net_device *net_dev; 1195 struct mtx en_ops_lock; 1196 uint8_t port_partition_type; 1197 struct bnxt_en_dev *edev; 1198 unsigned long state; 1199 #define BNXT_STATE_OPEN 0 1200 #define BNXT_STATE_IN_SP_TASK 1 1201 #define BNXT_STATE_READ_STATS 2 1202 #define BNXT_STATE_FW_RESET_DET 3 1203 #define BNXT_STATE_IN_FW_RESET 4 1204 #define BNXT_STATE_ABORT_ERR 5 1205 #define BNXT_STATE_FW_FATAL_COND 6 1206 #define BNXT_STATE_DRV_REGISTERED 7 1207 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 1208 #define BNXT_STATE_NAPI_DISABLED 9 1209 #define BNXT_STATE_L2_FILTER_RETRY 10 1210 #define BNXT_STATE_FW_ACTIVATE 11 1211 #define BNXT_STATE_RECOVER 12 1212 #define BNXT_STATE_FW_NON_FATAL_COND 13 1213 #define BNXT_STATE_FW_ACTIVATE_RESET 14 1214 #define BNXT_STATE_HALF_OPEN 15 1215 #define BNXT_NO_FW_ACCESS(bp) \ 1216 test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) 1217 struct pci_dev *pdev; 1218 1219 struct work_struct sp_task; 1220 unsigned long sp_event; 1221 #define BNXT_RX_MASK_SP_EVENT 0 1222 #define BNXT_RX_NTP_FLTR_SP_EVENT 1 1223 #define BNXT_LINK_CHNG_SP_EVENT 2 1224 #define BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT 3 1225 #define BNXT_VXLAN_ADD_PORT_SP_EVENT 4 1226 #define BNXT_VXLAN_DEL_PORT_SP_EVENT 5 1227 #define BNXT_RESET_TASK_SP_EVENT 6 1228 #define BNXT_RST_RING_SP_EVENT 7 1229 #define BNXT_HWRM_PF_UNLOAD_SP_EVENT 8 1230 #define BNXT_PERIODIC_STATS_SP_EVENT 9 1231 #define BNXT_HWRM_PORT_MODULE_SP_EVENT 10 1232 #define BNXT_RESET_TASK_SILENT_SP_EVENT 11 1233 #define BNXT_GENEVE_ADD_PORT_SP_EVENT 12 1234 #define BNXT_GENEVE_DEL_PORT_SP_EVENT 13 1235 #define BNXT_LINK_SPEED_CHNG_SP_EVENT 14 1236 #define BNXT_FLOW_STATS_SP_EVENT 15 1237 #define BNXT_UPDATE_PHY_SP_EVENT 16 1238 #define BNXT_RING_COAL_NOW_SP_EVENT 17 1239 #define BNXT_FW_RESET_NOTIFY_SP_EVENT 18 1240 #define BNXT_FW_EXCEPTION_SP_EVENT 19 1241 #define BNXT_VF_VNIC_CHANGE_SP_EVENT 20 1242 #define BNXT_LINK_CFG_CHANGE_SP_EVENT 21 1243 #define BNXT_PTP_CURRENT_TIME_EVENT 22 1244 #define BNXT_FW_ECHO_REQUEST_SP_EVENT 23 1245 #define BNXT_VF_CFG_CHNG_SP_EVENT 24 1246 1247 struct delayed_work fw_reset_task; 1248 int fw_reset_state; 1249 #define BNXT_FW_RESET_STATE_POLL_VF 1 1250 #define BNXT_FW_RESET_STATE_RESET_FW 2 1251 #define BNXT_FW_RESET_STATE_ENABLE_DEV 3 1252 #define BNXT_FW_RESET_STATE_POLL_FW 4 1253 #define BNXT_FW_RESET_STATE_OPENING 5 1254 #define BNXT_FW_RESET_STATE_POLL_FW_DOWN 6 1255 u16 fw_reset_min_dsecs; 1256 #define BNXT_DFLT_FW_RST_MIN_DSECS 20 1257 u16 fw_reset_max_dsecs; 1258 #define BNXT_DFLT_FW_RST_MAX_DSECS 60 1259 unsigned long fw_reset_timestamp; 1260 1261 struct bnxt_fw_health *fw_health; 1262 }; 1263 1264 struct bnxt_filter_info { 1265 STAILQ_ENTRY(bnxt_filter_info) next; 1266 uint64_t fw_l2_filter_id; 1267 #define INVALID_MAC_INDEX ((uint16_t)-1) 1268 uint16_t mac_index; 1269 1270 /* Filter Characteristics */ 1271 uint32_t flags; 1272 uint32_t enables; 1273 uint8_t l2_addr[ETHER_ADDR_LEN]; 1274 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 1275 uint16_t l2_ovlan; 1276 uint16_t l2_ovlan_mask; 1277 uint16_t l2_ivlan; 1278 uint16_t l2_ivlan_mask; 1279 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 1280 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 1281 uint16_t t_l2_ovlan; 1282 uint16_t t_l2_ovlan_mask; 1283 uint16_t t_l2_ivlan; 1284 uint16_t t_l2_ivlan_mask; 1285 uint8_t tunnel_type; 1286 uint16_t mirror_vnic_id; 1287 uint32_t vni; 1288 uint8_t pri_hint; 1289 uint64_t l2_filter_id_hint; 1290 }; 1291 1292 #define I2C_DEV_ADDR_A0 0xa0 1293 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1294 1295 /* Function declarations */ 1296 void bnxt_report_link(struct bnxt_softc *softc); 1297 bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 1298 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name); 1299 int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr, 1300 uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr, 1301 uint16_t data_length, uint8_t *buf); 1302 void bnxt_dcb_init(struct bnxt_softc *softc); 1303 void bnxt_dcb_free(struct bnxt_softc *softc); 1304 uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode); 1305 uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc); 1306 int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1307 int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1308 uint8_t get_phy_type(struct bnxt_softc *softc); 1309 int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1310 int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1311 int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1312 int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1313 int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, int *num_inputs); 1314 1315 #endif /* _BNXT_H */ 1316