1 /*- 2 * Broadcom NetXtreme-C/E network driver. 3 * 4 * Copyright (c) 2016 Broadcom, All Rights Reserved. 5 * The term Broadcom refers to Broadcom Limited and/or its subsidiaries 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #ifndef _BNXT_H 31 #define _BNXT_H 32 33 #include <sys/param.h> 34 #include <sys/socket.h> 35 #include <sys/sysctl.h> 36 #include <sys/taskqueue.h> 37 #include <sys/bitstring.h> 38 39 #include <machine/bus.h> 40 41 #include <net/ethernet.h> 42 #include <net/if.h> 43 #include <net/if_var.h> 44 #include <net/iflib.h> 45 #include <linux/types.h> 46 47 #include "hsi_struct_def.h" 48 #include "bnxt_dcb.h" 49 #include "bnxt_auxbus_compat.h" 50 51 #define DFLT_HWRM_CMD_TIMEOUT 500 52 53 /* PCI IDs */ 54 #define BROADCOM_VENDOR_ID 0x14E4 55 56 #define BCM57301 0x16c8 57 #define BCM57302 0x16c9 58 #define BCM57304 0x16ca 59 #define BCM57311 0x16ce 60 #define BCM57312 0x16cf 61 #define BCM57314 0x16df 62 #define BCM57402 0x16d0 63 #define BCM57402_NPAR 0x16d4 64 #define BCM57404 0x16d1 65 #define BCM57404_NPAR 0x16e7 66 #define BCM57406 0x16d2 67 #define BCM57406_NPAR 0x16e8 68 #define BCM57407 0x16d5 69 #define BCM57407_NPAR 0x16ea 70 #define BCM57407_SFP 0x16e9 71 #define BCM57412 0x16d6 72 #define BCM57412_NPAR1 0x16de 73 #define BCM57412_NPAR2 0x16eb 74 #define BCM57414 0x16d7 75 #define BCM57414_NPAR1 0x16ec 76 #define BCM57414_NPAR2 0x16ed 77 #define BCM57416 0x16d8 78 #define BCM57416_NPAR1 0x16ee 79 #define BCM57416_NPAR2 0x16ef 80 #define BCM57416_SFP 0x16e3 81 #define BCM57417 0x16d9 82 #define BCM57417_NPAR1 0x16c0 83 #define BCM57417_NPAR2 0x16cc 84 #define BCM57417_SFP 0x16e2 85 #define BCM57454 0x1614 86 #define BCM58700 0x16cd 87 #define BCM57508 0x1750 88 #define BCM57504 0x1751 89 #define BCM57502 0x1752 90 #define NETXTREME_C_VF1 0x16cb 91 #define NETXTREME_C_VF2 0x16e1 92 #define NETXTREME_C_VF3 0x16e5 93 #define NETXTREME_E_VF1 0x16c1 94 #define NETXTREME_E_VF2 0x16d3 95 #define NETXTREME_E_VF3 0x16dc 96 97 #define EVENT_DATA1_RESET_NOTIFY_FATAL(data1) \ 98 (((data1) & \ 99 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_MASK) ==\ 100 HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_FATAL) 101 102 #define BNXT_EVENT_ERROR_REPORT_TYPE(data1) \ 103 (((data1) & \ 104 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_MASK) >> \ 105 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_BASE_EVENT_DATA1_ERROR_TYPE_SFT) 106 107 #define BNXT_EVENT_INVALID_SIGNAL_DATA(data2) \ 108 (((data2) & \ 109 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_MASK) >> \ 110 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_INVALID_SIGNAL_EVENT_DATA2_PIN_ID_SFT) 111 112 #define BNXT_EVENT_DBR_EPOCH(data) \ 113 (((data) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_MASK) >> \ 114 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_DOORBELL_DROP_THRESHOLD_EVENT_DATA1_EPOCH_SFT) 115 116 #define BNXT_EVENT_THERMAL_THRESHOLD_TEMP(data2) \ 117 (((data2) & \ 118 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_MASK) >> \ 119 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_THRESHOLD_TEMP_SFT) 120 121 #define EVENT_DATA2_NVM_ERR_ADDR(data2) \ 122 (((data2) & \ 123 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_MASK) >> \ 124 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA2_ERR_ADDR_SFT) 125 126 #define EVENT_DATA1_THERMAL_THRESHOLD_DIR_INCREASING(data1) \ 127 (((data1) & \ 128 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR) == \ 129 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_TRANSITION_DIR_INCREASING) 130 131 #define EVENT_DATA1_NVM_ERR_TYPE_WRITE(data1) \ 132 (((data1) & \ 133 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 134 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_WRITE) 135 136 #define EVENT_DATA1_NVM_ERR_TYPE_ERASE(data1) \ 137 (((data1) & \ 138 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_MASK) == \ 139 HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_NVM_EVENT_DATA1_NVM_ERR_TYPE_ERASE) 140 141 #define EVENT_DATA1_THERMAL_THRESHOLD_TYPE(data1) \ 142 ((data1) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA1_THRESHOLD_TYPE_MASK) 143 144 #define BNXT_EVENT_THERMAL_CURRENT_TEMP(data2) \ 145 ((data2) & HWRM_ASYNC_EVENT_CMPL_ERROR_REPORT_THERMAL_EVENT_DATA2_CURRENT_TEMP_MASK) 146 147 #define INVALID_STATS_CTX_ID -1 148 149 /* Maximum numbers of RX and TX descriptors. iflib requires this to be a power 150 * of two. The hardware has no particular limitation. */ 151 #define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1) 152 #define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1) 153 154 #define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 155 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 156 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 157 158 #define BNXT_MAX_MTU 9600 159 160 #define BNXT_RSS_HASH_TYPE_TCPV4 0 161 #define BNXT_RSS_HASH_TYPE_UDPV4 1 162 #define BNXT_RSS_HASH_TYPE_IPV4 2 163 #define BNXT_RSS_HASH_TYPE_TCPV6 3 164 #define BNXT_RSS_HASH_TYPE_UDPV6 4 165 #define BNXT_RSS_HASH_TYPE_IPV6 5 166 #define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F) 167 168 #define BNXT_NO_MORE_WOL_FILTERS 0xFFFF 169 #define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \ 170 ((softc)->flags & BNXT_FLAG_WOL_CAP )) 171 172 /* 64-bit doorbell */ 173 #define DBR_INDEX_MASK 0x0000000000ffffffULL 174 #define DBR_PI_LO_MASK 0xff000000UL 175 #define DBR_PI_LO_SFT 24 176 #define DBR_XID_MASK 0x000fffff00000000ULL 177 #define DBR_XID_SFT 32 178 #define DBR_PI_HI_MASK 0xf0000000000000ULL 179 #define DBR_PI_HI_SFT 52 180 #define DBR_PATH_L2 (0x1ULL << 56) 181 #define DBR_VALID (0x1ULL << 58) 182 #define DBR_TYPE_SQ (0x0ULL << 60) 183 #define DBR_TYPE_RQ (0x1ULL << 60) 184 #define DBR_TYPE_SRQ (0x2ULL << 60) 185 #define DBR_TYPE_SRQ_ARM (0x3ULL << 60) 186 #define DBR_TYPE_CQ (0x4ULL << 60) 187 #define DBR_TYPE_CQ_ARMSE (0x5ULL << 60) 188 #define DBR_TYPE_CQ_ARMALL (0x6ULL << 60) 189 #define DBR_TYPE_CQ_ARMENA (0x7ULL << 60) 190 #define DBR_TYPE_SRQ_ARMENA (0x8ULL << 60) 191 #define DBR_TYPE_CQ_CUTOFF_ACK (0x9ULL << 60) 192 #define DBR_TYPE_NQ (0xaULL << 60) 193 #define DBR_TYPE_NQ_ARM (0xbULL << 60) 194 #define DBR_TYPE_PUSH_START (0xcULL << 60) 195 #define DBR_TYPE_PUSH_END (0xdULL << 60) 196 #define DBR_TYPE_NULL (0xfULL << 60) 197 198 #define BNXT_MAX_L2_QUEUES 128 199 #define BNXT_ROCE_IRQ_COUNT 9 200 201 #define BNXT_MAX_NUM_QUEUES (BNXT_MAX_L2_QUEUES + BNXT_ROCE_IRQ_COUNT) 202 203 /* Completion related defines */ 204 #define CMP_VALID(cmp, v_bit) \ 205 ((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) ) 206 207 /* Chip class phase 5 */ 208 #define BNXT_CHIP_P5(sc) ((sc->flags & BNXT_FLAG_CHIP_P5)) 209 210 #define DB_PF_OFFSET_P5 0x10000 211 #define DB_VF_OFFSET_P5 0x4000 212 #define NQ_VALID(cmp, v_bit) \ 213 ((!!(((nq_cn_t *)(cmp))->v & htole32(NQ_CN_V))) == !!(v_bit) ) 214 215 #ifndef DIV_ROUND_UP 216 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 217 #endif 218 #ifndef roundup 219 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 220 #endif 221 222 #define NEXT_CP_CONS_V(ring, cons, v_bit) do { \ 223 if (__predict_false(++(cons) == (ring)->ring_size)) \ 224 ((cons) = 0, (v_bit) = !v_bit); \ 225 } while (0) 226 227 #define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \ 228 0 : idx + 1) 229 230 #define CMPL_PREFETCH_NEXT(cpr, idx) \ 231 __builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\ 232 (CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \ 233 ((cpr)->ring.ring_size - 1)]) 234 235 /* Lock macros */ 236 #define BNXT_HWRM_LOCK_INIT(_softc, _name) \ 237 mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF) 238 #define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock) 239 #define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock) 240 #define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock) 241 #define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \ 242 MA_OWNED) 243 #define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \ 244 ((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \ 245 (link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \ 246 (link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg)) 247 248 /* Chip info */ 249 #define BNXT_TSO_SIZE UINT16_MAX 250 251 #define min_t(type, x, y) ({ \ 252 type __min1 = (x); \ 253 type __min2 = (y); \ 254 __min1 < __min2 ? __min1 : __min2; }) 255 256 #define max_t(type, x, y) ({ \ 257 type __max1 = (x); \ 258 type __max2 = (y); \ 259 __max1 > __max2 ? __max1 : __max2; }) 260 261 #define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max) 262 263 #define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \ 264 if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \ 265 ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \ 266 } while(0) 267 268 #define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */ 269 270 #define BNXT_RX_STATS_EXT_OFFSET(counter) \ 271 (offsetof(struct rx_port_stats_ext, counter) / 8) 272 273 #define BNXT_RX_STATS_EXT_NUM_LEGACY \ 274 BNXT_RX_STATS_EXT_OFFSET(rx_fec_corrected_blocks) 275 276 #define BNXT_TX_STATS_EXT_OFFSET(counter) \ 277 (offsetof(struct tx_port_stats_ext, counter) / 8) 278 279 extern const char bnxt_driver_version[]; 280 typedef void (*bnxt_doorbell_tx)(void *, uint16_t idx); 281 typedef void (*bnxt_doorbell_rx)(void *, uint16_t idx); 282 typedef void (*bnxt_doorbell_rx_cq)(void *, bool); 283 typedef void (*bnxt_doorbell_tx_cq)(void *, bool); 284 typedef void (*bnxt_doorbell_nq)(void *, bool); 285 286 typedef struct bnxt_doorbell_ops { 287 bnxt_doorbell_tx bnxt_db_tx; 288 bnxt_doorbell_rx bnxt_db_rx; 289 bnxt_doorbell_rx_cq bnxt_db_rx_cq; 290 bnxt_doorbell_tx_cq bnxt_db_tx_cq; 291 bnxt_doorbell_nq bnxt_db_nq; 292 } bnxt_dooorbell_ops_t; 293 /* NVRAM access */ 294 enum bnxt_nvm_directory_type { 295 BNX_DIR_TYPE_UNUSED = 0, 296 BNX_DIR_TYPE_PKG_LOG = 1, 297 BNX_DIR_TYPE_UPDATE = 2, 298 BNX_DIR_TYPE_CHIMP_PATCH = 3, 299 BNX_DIR_TYPE_BOOTCODE = 4, 300 BNX_DIR_TYPE_VPD = 5, 301 BNX_DIR_TYPE_EXP_ROM_MBA = 6, 302 BNX_DIR_TYPE_AVS = 7, 303 BNX_DIR_TYPE_PCIE = 8, 304 BNX_DIR_TYPE_PORT_MACRO = 9, 305 BNX_DIR_TYPE_APE_FW = 10, 306 BNX_DIR_TYPE_APE_PATCH = 11, 307 BNX_DIR_TYPE_KONG_FW = 12, 308 BNX_DIR_TYPE_KONG_PATCH = 13, 309 BNX_DIR_TYPE_BONO_FW = 14, 310 BNX_DIR_TYPE_BONO_PATCH = 15, 311 BNX_DIR_TYPE_TANG_FW = 16, 312 BNX_DIR_TYPE_TANG_PATCH = 17, 313 BNX_DIR_TYPE_BOOTCODE_2 = 18, 314 BNX_DIR_TYPE_CCM = 19, 315 BNX_DIR_TYPE_PCI_CFG = 20, 316 BNX_DIR_TYPE_TSCF_UCODE = 21, 317 BNX_DIR_TYPE_ISCSI_BOOT = 22, 318 BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24, 319 BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25, 320 BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26, 321 BNX_DIR_TYPE_EXT_PHY = 27, 322 BNX_DIR_TYPE_SHARED_CFG = 40, 323 BNX_DIR_TYPE_PORT_CFG = 41, 324 BNX_DIR_TYPE_FUNC_CFG = 42, 325 BNX_DIR_TYPE_MGMT_CFG = 48, 326 BNX_DIR_TYPE_MGMT_DATA = 49, 327 BNX_DIR_TYPE_MGMT_WEB_DATA = 50, 328 BNX_DIR_TYPE_MGMT_WEB_META = 51, 329 BNX_DIR_TYPE_MGMT_EVENT_LOG = 52, 330 BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53 331 }; 332 333 enum bnxnvm_pkglog_field_index { 334 BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0, 335 BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1, 336 BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2, 337 BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3, 338 BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4, 339 BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5, 340 BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6 341 }; 342 343 #define BNX_DIR_ORDINAL_FIRST 0 344 #define BNX_DIR_EXT_NONE 0 345 346 struct bnxt_bar_info { 347 struct resource *res; 348 bus_space_tag_t tag; 349 bus_space_handle_t handle; 350 bus_size_t size; 351 int rid; 352 }; 353 354 struct bnxt_flow_ctrl { 355 bool rx; 356 bool tx; 357 bool autoneg; 358 }; 359 360 struct bnxt_link_info { 361 uint8_t media_type; 362 uint8_t transceiver; 363 uint8_t phy_addr; 364 uint8_t phy_link_status; 365 uint8_t wire_speed; 366 uint8_t loop_back; 367 uint8_t link_up; 368 uint8_t last_link_up; 369 uint8_t duplex; 370 uint8_t last_duplex; 371 uint8_t last_phy_type; 372 struct bnxt_flow_ctrl flow_ctrl; 373 struct bnxt_flow_ctrl last_flow_ctrl; 374 uint8_t duplex_setting; 375 uint8_t auto_mode; 376 #define PHY_VER_LEN 3 377 uint8_t phy_ver[PHY_VER_LEN]; 378 uint8_t phy_type; 379 #define BNXT_PHY_STATE_ENABLED 0 380 #define BNXT_PHY_STATE_DISABLED 1 381 uint8_t phy_state; 382 383 uint16_t link_speed; 384 uint16_t support_speeds; 385 uint16_t support_pam4_speeds; 386 uint16_t auto_link_speeds; 387 uint16_t auto_pam4_link_speeds; 388 uint16_t force_link_speed; 389 uint16_t force_pam4_link_speed; 390 bool force_pam4_speed_set_by_user; 391 392 uint16_t advertising; 393 uint16_t advertising_pam4; 394 395 uint32_t preemphasis; 396 uint16_t support_auto_speeds; 397 uint16_t support_force_speeds; 398 uint16_t support_pam4_auto_speeds; 399 uint16_t support_pam4_force_speeds; 400 #define BNXT_SIG_MODE_NRZ HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_NRZ 401 #define BNXT_SIG_MODE_PAM4 HWRM_PORT_PHY_QCFG_OUTPUT_SIGNAL_MODE_PAM4 402 uint8_t req_signal_mode; 403 404 uint8_t active_fec_sig_mode; 405 uint8_t sig_mode; 406 407 /* copy of requested setting */ 408 uint8_t autoneg; 409 #define BNXT_AUTONEG_SPEED 1 410 #define BNXT_AUTONEG_FLOW_CTRL 2 411 uint8_t req_duplex; 412 uint16_t req_link_speed; 413 uint8_t module_status; 414 struct hwrm_port_phy_qcfg_output phy_qcfg_resp; 415 }; 416 417 enum bnxt_phy_type { 418 BNXT_MEDIA_CR = 0, 419 BNXT_MEDIA_LR, 420 BNXT_MEDIA_SR, 421 BNXT_MEDIA_KR, 422 BNXT_MEDIA_END 423 }; 424 425 enum bnxt_cp_type { 426 BNXT_DEFAULT, 427 BNXT_TX, 428 BNXT_RX, 429 BNXT_SHARED 430 }; 431 432 struct bnxt_queue_info { 433 uint8_t queue_id; 434 uint8_t queue_profile; 435 }; 436 437 struct bnxt_func_info { 438 uint32_t fw_fid; 439 uint8_t mac_addr[ETHER_ADDR_LEN]; 440 uint16_t max_rsscos_ctxs; 441 uint16_t max_cp_rings; 442 uint16_t max_tx_rings; 443 uint16_t max_rx_rings; 444 uint16_t max_hw_ring_grps; 445 uint16_t max_irqs; 446 uint16_t max_l2_ctxs; 447 uint16_t max_vnics; 448 uint16_t max_stat_ctxs; 449 }; 450 451 struct bnxt_pf_info { 452 #define BNXT_FIRST_PF_FID 1 453 #define BNXT_FIRST_VF_FID 128 454 uint8_t port_id; 455 uint32_t first_vf_id; 456 uint16_t active_vfs; 457 uint16_t max_vfs; 458 uint32_t max_encap_records; 459 uint32_t max_decap_records; 460 uint32_t max_tx_em_flows; 461 uint32_t max_tx_wm_flows; 462 uint32_t max_rx_em_flows; 463 uint32_t max_rx_wm_flows; 464 unsigned long *vf_event_bmap; 465 uint16_t hwrm_cmd_req_pages; 466 void *hwrm_cmd_req_addr[4]; 467 bus_addr_t hwrm_cmd_req_dma_addr[4]; 468 }; 469 470 struct bnxt_vf_info { 471 uint16_t fw_fid; 472 uint8_t mac_addr[ETHER_ADDR_LEN]; 473 uint16_t max_rsscos_ctxs; 474 uint16_t max_cp_rings; 475 uint16_t max_tx_rings; 476 uint16_t max_rx_rings; 477 uint16_t max_hw_ring_grps; 478 uint16_t max_l2_ctxs; 479 uint16_t max_irqs; 480 uint16_t max_vnics; 481 uint16_t max_stat_ctxs; 482 uint32_t vlan; 483 #define BNXT_VF_QOS 0x1 484 #define BNXT_VF_SPOOFCHK 0x2 485 #define BNXT_VF_LINK_FORCED 0x4 486 #define BNXT_VF_LINK_UP 0x8 487 uint32_t flags; 488 uint32_t func_flags; /* func cfg flags */ 489 uint32_t min_tx_rate; 490 uint32_t max_tx_rate; 491 void *hwrm_cmd_req_addr; 492 bus_addr_t hwrm_cmd_req_dma_addr; 493 }; 494 495 #define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF)) 496 #define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF) 497 498 struct bnxt_vlan_tag { 499 SLIST_ENTRY(bnxt_vlan_tag) next; 500 uint64_t filter_id; 501 uint16_t tag; 502 }; 503 504 struct bnxt_vnic_info { 505 uint16_t id; 506 uint16_t def_ring_grp; 507 uint16_t cos_rule; 508 uint16_t lb_rule; 509 uint16_t mru; 510 511 uint32_t rx_mask; 512 struct iflib_dma_info mc_list; 513 int mc_list_count; 514 #define BNXT_MAX_MC_ADDRS 16 515 516 uint32_t flags; 517 #define BNXT_VNIC_FLAG_DEFAULT 0x01 518 #define BNXT_VNIC_FLAG_BD_STALL 0x02 519 #define BNXT_VNIC_FLAG_VLAN_STRIP 0x04 520 521 uint64_t filter_id; 522 523 uint16_t rss_id; 524 uint32_t rss_hash_type; 525 uint8_t rss_hash_key[HW_HASH_KEY_SIZE]; 526 struct iflib_dma_info rss_hash_key_tbl; 527 struct iflib_dma_info rss_grp_tbl; 528 SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags; 529 struct iflib_dma_info vlan_tag_list; 530 }; 531 532 struct bnxt_grp_info { 533 uint16_t stats_ctx; 534 uint16_t grp_id; 535 uint16_t rx_ring_id; 536 uint16_t cp_ring_id; 537 uint16_t ag_ring_id; 538 }; 539 540 struct bnxt_ring { 541 uint64_t paddr; 542 vm_offset_t doorbell; 543 caddr_t vaddr; 544 struct bnxt_softc *softc; 545 uint32_t ring_size; /* Must be a power of two */ 546 uint16_t id; /* Logical ID */ 547 uint16_t phys_id; 548 uint16_t idx; 549 struct bnxt_full_tpa_start *tpa_start; 550 }; 551 552 struct bnxt_cp_ring { 553 struct bnxt_ring ring; 554 struct if_irq irq; 555 uint32_t cons; 556 bool v_bit; /* Value of valid bit */ 557 struct ctx_hw_stats *stats; 558 uint32_t stats_ctx_id; 559 uint32_t last_idx; /* Used by RX rings only 560 * set to the last read pidx 561 */ 562 uint64_t int_count; 563 }; 564 565 struct bnxt_full_tpa_start { 566 struct rx_tpa_start_cmpl low; 567 struct rx_tpa_start_cmpl_hi high; 568 }; 569 570 /* All the version information for the part */ 571 #define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */ 572 #define BNXT_NAME_SIZE 17 573 #define FW_VER_STR_LEN 32 574 #define BC_HWRM_STR_LEN 21 575 struct bnxt_ver_info { 576 uint8_t hwrm_if_major; 577 uint8_t hwrm_if_minor; 578 uint8_t hwrm_if_update; 579 char hwrm_if_ver[BNXT_VERSTR_SIZE]; 580 char driver_hwrm_if_ver[BNXT_VERSTR_SIZE]; 581 char mgmt_fw_ver[FW_VER_STR_LEN]; 582 char netctrl_fw_ver[FW_VER_STR_LEN]; 583 char roce_fw_ver[FW_VER_STR_LEN]; 584 char fw_ver_str[FW_VER_STR_LEN]; 585 char phy_ver[BNXT_VERSTR_SIZE]; 586 char pkg_ver[64]; 587 588 char hwrm_fw_name[BNXT_NAME_SIZE]; 589 char mgmt_fw_name[BNXT_NAME_SIZE]; 590 char netctrl_fw_name[BNXT_NAME_SIZE]; 591 char roce_fw_name[BNXT_NAME_SIZE]; 592 char phy_vendor[BNXT_NAME_SIZE]; 593 char phy_partnumber[BNXT_NAME_SIZE]; 594 595 uint16_t chip_num; 596 uint8_t chip_rev; 597 uint8_t chip_metal; 598 uint8_t chip_bond_id; 599 uint8_t chip_type; 600 601 uint8_t hwrm_min_major; 602 uint8_t hwrm_min_minor; 603 uint8_t hwrm_min_update; 604 uint64_t fw_ver_code; 605 #define BNXT_FW_VER_CODE(maj, min, bld, rsv) \ 606 ((uint64_t)(maj) << 48 | (uint64_t)(min) << 32 | (uint64_t)(bld) << 16 | (rsv)) 607 #define BNXT_FW_MAJ(softc) ((softc)->ver_info->fw_ver_code >> 48) 608 #define BNXT_FW_MIN(softc) (((softc)->ver_info->fw_ver_code >> 32) & 0xffff) 609 #define BNXT_FW_BLD(softc) (((softc)->ver_info->fw_ver_code >> 16) & 0xffff) 610 #define BNXT_FW_RSV(softc) (((softc)->ver_info->fw_ver_code) & 0xffff) 611 612 struct sysctl_ctx_list ver_ctx; 613 struct sysctl_oid *ver_oid; 614 }; 615 616 struct bnxt_nvram_info { 617 uint16_t mfg_id; 618 uint16_t device_id; 619 uint32_t sector_size; 620 uint32_t size; 621 uint32_t reserved_size; 622 uint32_t available_size; 623 624 struct sysctl_ctx_list nvm_ctx; 625 struct sysctl_oid *nvm_oid; 626 }; 627 628 struct bnxt_func_qcfg { 629 uint16_t alloc_completion_rings; 630 uint16_t alloc_tx_rings; 631 uint16_t alloc_rx_rings; 632 uint16_t alloc_vnics; 633 }; 634 635 struct bnxt_hw_lro { 636 uint16_t enable; 637 uint16_t is_mode_gro; 638 uint16_t max_agg_segs; 639 uint16_t max_aggs; 640 uint32_t min_agg_len; 641 }; 642 643 /* The hardware supports certain page sizes. Use the supported page sizes 644 * to allocate the rings. 645 */ 646 #if (PAGE_SHIFT < 12) 647 #define BNXT_PAGE_SHIFT 12 648 #elif (PAGE_SHIFT <= 13) 649 #define BNXT_PAGE_SHIFT PAGE_SHIFT 650 #elif (PAGE_SHIFT < 16) 651 #define BNXT_PAGE_SHIFT 13 652 #else 653 #define BNXT_PAGE_SHIFT 16 654 #endif 655 656 #define BNXT_PAGE_SIZE (1 << BNXT_PAGE_SHIFT) 657 658 #define MAX_CTX_PAGES (BNXT_PAGE_SIZE / 8) 659 #define MAX_CTX_TOTAL_PAGES (MAX_CTX_PAGES * MAX_CTX_PAGES) 660 661 struct bnxt_ring_mem_info { 662 int nr_pages; 663 int page_size; 664 uint16_t flags; 665 #define BNXT_RMEM_VALID_PTE_FLAG 1 666 #define BNXT_RMEM_RING_PTE_FLAG 2 667 #define BNXT_RMEM_USE_FULL_PAGE_FLAG 4 668 uint16_t depth; 669 struct bnxt_ctx_mem_type *ctx_mem; 670 671 struct iflib_dma_info *pg_arr; 672 struct iflib_dma_info pg_tbl; 673 674 int vmem_size; 675 void **vmem; 676 }; 677 678 struct bnxt_ctx_pg_info { 679 uint32_t entries; 680 uint32_t nr_pages; 681 struct iflib_dma_info ctx_arr[MAX_CTX_PAGES]; 682 struct bnxt_ring_mem_info ring_mem; 683 struct bnxt_ctx_pg_info **ctx_pg_tbl; 684 }; 685 686 #define BNXT_MAX_TQM_SP_RINGS 1 687 #define BNXT_MAX_TQM_FP_LEGACY_RINGS 8 688 #define BNXT_MAX_TQM_FP_RINGS 9 689 #define BNXT_MAX_TQM_LEGACY_RINGS \ 690 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_LEGACY_RINGS) 691 #define BNXT_MAX_TQM_RINGS \ 692 (BNXT_MAX_TQM_SP_RINGS + BNXT_MAX_TQM_FP_RINGS) 693 694 #define BNXT_BACKING_STORE_CFG_LEGACY_LEN 256 695 #define BNXT_BACKING_STORE_CFG_LEN \ 696 sizeof(struct hwrm_func_backing_store_cfg_input) 697 698 #define BNXT_SET_CTX_PAGE_ATTR(attr) \ 699 do { \ 700 if (BNXT_PAGE_SIZE == 0x2000) \ 701 attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_SRQ_PG_SIZE_PG_8K; \ 702 else if (BNXT_PAGE_SIZE == 0x10000) \ 703 attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_64K; \ 704 else \ 705 attr = HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_QPC_PG_SIZE_PG_4K; \ 706 } while (0) 707 708 struct bnxt_ctx_mem_type { 709 u16 type; 710 u16 entry_size; 711 u32 flags; 712 #define BNXT_CTX_MEM_TYPE_VALID HWRM_FUNC_BACKING_STORE_QCAPS_V2_OUTPUT_FLAGS_TYPE_VALID 713 u32 instance_bmap; 714 u8 init_value; 715 u8 entry_multiple; 716 u16 init_offset; 717 #define BNXT_CTX_INIT_INVALID_OFFSET 0xffff 718 u32 max_entries; 719 u32 min_entries; 720 u8 split_entry_cnt; 721 #define BNXT_MAX_SPLIT_ENTRY 4 722 union { 723 struct { 724 u32 qp_l2_entries; 725 u32 qp_qp1_entries; 726 }; 727 u32 srq_l2_entries; 728 u32 cq_l2_entries; 729 u32 vnic_entries; 730 struct { 731 u32 mrav_av_entries; 732 u32 mrav_num_entries_units; 733 }; 734 u32 split[BNXT_MAX_SPLIT_ENTRY]; 735 }; 736 struct bnxt_ctx_pg_info *pg_info; 737 }; 738 739 #define BNXT_CTX_QP HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QP 740 #define BNXT_CTX_SRQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ 741 #define BNXT_CTX_CQ HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ 742 #define BNXT_CTX_VNIC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_VNIC 743 #define BNXT_CTX_STAT HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_STAT 744 #define BNXT_CTX_STQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SP_TQM_RING 745 #define BNXT_CTX_FTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_FP_TQM_RING 746 #define BNXT_CTX_MRAV HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MRAV 747 #define BNXT_CTX_TIM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TIM 748 #define BNXT_CTX_TKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_TKC 749 #define BNXT_CTX_RKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RKC 750 #define BNXT_CTX_MTQM HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_MP_TQM_RING 751 #define BNXT_CTX_SQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SQ_DB_SHADOW 752 #define BNXT_CTX_RQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_RQ_DB_SHADOW 753 #define BNXT_CTX_SRQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_SRQ_DB_SHADOW 754 #define BNXT_CTX_CQDBS HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_CQ_DB_SHADOW 755 #define BNXT_CTX_QTKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_TKC 756 #define BNXT_CTX_QRKC HWRM_FUNC_BACKING_STORE_CFG_V2_INPUT_TYPE_QUIC_RKC 757 #define BNXT_CTX_MAX (BNXT_CTX_QRKC + 1) 758 759 struct bnxt_ctx_mem_info { 760 u8 tqm_fp_rings_count; 761 762 u32 flags; 763 #define BNXT_CTX_FLAG_INITED 0x01 764 struct bnxt_ctx_mem_type ctx_arr[BNXT_CTX_MAX]; 765 }; 766 767 struct bnxt_hw_resc { 768 uint16_t min_rsscos_ctxs; 769 uint16_t max_rsscos_ctxs; 770 uint16_t min_cp_rings; 771 uint16_t max_cp_rings; 772 uint16_t resv_cp_rings; 773 uint16_t min_tx_rings; 774 uint16_t max_tx_rings; 775 uint16_t resv_tx_rings; 776 uint16_t max_tx_sch_inputs; 777 uint16_t min_rx_rings; 778 uint16_t max_rx_rings; 779 uint16_t resv_rx_rings; 780 uint16_t min_hw_ring_grps; 781 uint16_t max_hw_ring_grps; 782 uint16_t resv_hw_ring_grps; 783 uint16_t min_l2_ctxs; 784 uint16_t max_l2_ctxs; 785 uint16_t min_vnics; 786 uint16_t max_vnics; 787 uint16_t resv_vnics; 788 uint16_t min_stat_ctxs; 789 uint16_t max_stat_ctxs; 790 uint16_t resv_stat_ctxs; 791 uint16_t max_nqs; 792 uint16_t max_irqs; 793 uint16_t resv_irqs; 794 }; 795 796 enum bnxt_type_ets { 797 BNXT_TYPE_ETS_TSA = 0, 798 BNXT_TYPE_ETS_PRI2TC, 799 BNXT_TYPE_ETS_TCBW, 800 BNXT_TYPE_ETS_MAX 801 }; 802 803 static const char *const BNXT_ETS_TYPE_STR[] = { 804 "tsa", 805 "pri2tc", 806 "tcbw", 807 }; 808 809 static const char *const BNXT_ETS_HELP_STR[] = { 810 "X is 1 (strict), 0 (ets)", 811 "TC values for pri 0 to 7", 812 "TC BW values for pri 0 to 7, Sum should be 100", 813 }; 814 815 #define BNXT_HWRM_MAX_REQ_LEN (softc->hwrm_max_req_len) 816 817 struct bnxt_softc_list { 818 SLIST_ENTRY(bnxt_softc_list) next; 819 struct bnxt_softc *softc; 820 }; 821 822 #ifndef BIT_ULL 823 #define BIT_ULL(nr) (1ULL << (nr)) 824 #endif 825 826 struct bnxt_aux_dev { 827 struct auxiliary_device aux_dev; 828 struct bnxt_en_dev *edev; 829 int id; 830 }; 831 832 struct bnxt_msix_tbl { 833 uint32_t entry; 834 uint32_t vector; 835 }; 836 837 struct bnxt_softc { 838 device_t dev; 839 if_ctx_t ctx; 840 if_softc_ctx_t scctx; 841 if_shared_ctx_t sctx; 842 if_t ifp; 843 uint32_t domain; 844 uint32_t bus; 845 uint32_t slot; 846 uint32_t function; 847 uint32_t dev_fn; 848 struct ifmedia *media; 849 struct bnxt_ctx_mem_info *ctx_mem; 850 struct bnxt_hw_resc hw_resc; 851 struct bnxt_softc_list list; 852 853 struct bnxt_bar_info hwrm_bar; 854 struct bnxt_bar_info doorbell_bar; 855 struct bnxt_link_info link_info; 856 #define BNXT_FLAG_VF 0x0001 857 #define BNXT_FLAG_NPAR 0x0002 858 #define BNXT_FLAG_WOL_CAP 0x0004 859 #define BNXT_FLAG_SHORT_CMD 0x0008 860 #define BNXT_FLAG_FW_CAP_NEW_RM 0x0010 861 #define BNXT_FLAG_CHIP_P5 0x0020 862 #define BNXT_FLAG_TPA 0x0040 863 #define BNXT_FLAG_FW_CAP_EXT_STATS 0x0080 864 #define BNXT_FLAG_MULTI_HOST 0x0100 865 #define BNXT_FLAG_MULTI_ROOT 0x0200 866 #define BNXT_FLAG_ROCEV1_CAP 0x0400 867 #define BNXT_FLAG_ROCEV2_CAP 0x0800 868 #define BNXT_FLAG_ROCE_CAP (BNXT_FLAG_ROCEV1_CAP | BNXT_FLAG_ROCEV2_CAP) 869 uint32_t flags; 870 #define BNXT_STATE_LINK_CHANGE (0) 871 #define BNXT_STATE_MAX (BNXT_STATE_LINK_CHANGE + 1) 872 bitstr_t *state_bv; 873 874 uint32_t total_irqs; 875 struct bnxt_msix_tbl *irq_tbl; 876 877 struct bnxt_func_info func; 878 struct bnxt_func_qcfg fn_qcfg; 879 struct bnxt_pf_info pf; 880 struct bnxt_vf_info vf; 881 882 uint16_t hwrm_cmd_seq; 883 uint32_t hwrm_cmd_timeo; /* milliseconds */ 884 struct iflib_dma_info hwrm_cmd_resp; 885 struct iflib_dma_info hwrm_short_cmd_req_addr; 886 /* Interrupt info for HWRM */ 887 struct if_irq irq; 888 struct mtx hwrm_lock; 889 uint16_t hwrm_max_req_len; 890 uint16_t hwrm_max_ext_req_len; 891 uint32_t hwrm_spec_code; 892 893 #define BNXT_MAX_QUEUE 8 894 uint8_t max_tc; 895 uint8_t max_lltc; 896 struct bnxt_queue_info tx_q_info[BNXT_MAX_QUEUE]; 897 struct bnxt_queue_info rx_q_info[BNXT_MAX_QUEUE]; 898 uint8_t tc_to_qidx[BNXT_MAX_QUEUE]; 899 uint8_t tx_q_ids[BNXT_MAX_QUEUE]; 900 uint8_t rx_q_ids[BNXT_MAX_QUEUE]; 901 uint8_t tx_max_q; 902 uint8_t rx_max_q; 903 uint8_t is_asym_q; 904 905 struct bnxt_ieee_ets *ieee_ets; 906 struct bnxt_ieee_pfc *ieee_pfc; 907 uint8_t dcbx_cap; 908 uint8_t default_pri; 909 uint8_t max_dscp_value; 910 911 uint64_t admin_ticks; 912 struct iflib_dma_info hw_rx_port_stats; 913 struct iflib_dma_info hw_tx_port_stats; 914 struct rx_port_stats *rx_port_stats; 915 struct tx_port_stats *tx_port_stats; 916 917 struct iflib_dma_info hw_tx_port_stats_ext; 918 struct iflib_dma_info hw_rx_port_stats_ext; 919 struct tx_port_stats_ext *tx_port_stats_ext; 920 struct rx_port_stats_ext *rx_port_stats_ext; 921 922 uint16_t fw_rx_stats_ext_size; 923 uint16_t fw_tx_stats_ext_size; 924 uint16_t hw_ring_stats_size; 925 926 uint8_t tx_pri2cos_idx[8]; 927 uint8_t rx_pri2cos_idx[8]; 928 bool pri2cos_valid; 929 930 uint64_t tx_bytes_pri[8]; 931 uint64_t tx_packets_pri[8]; 932 uint64_t rx_bytes_pri[8]; 933 uint64_t rx_packets_pri[8]; 934 935 uint8_t port_count; 936 int num_cp_rings; 937 938 struct bnxt_cp_ring *nq_rings; 939 940 struct bnxt_ring *tx_rings; 941 struct bnxt_cp_ring *tx_cp_rings; 942 struct iflib_dma_info tx_stats[BNXT_MAX_NUM_QUEUES]; 943 int ntxqsets; 944 945 struct bnxt_vnic_info vnic_info; 946 struct bnxt_ring *ag_rings; 947 struct bnxt_ring *rx_rings; 948 struct bnxt_cp_ring *rx_cp_rings; 949 struct bnxt_grp_info *grp_info; 950 struct iflib_dma_info rx_stats[BNXT_MAX_NUM_QUEUES]; 951 int nrxqsets; 952 uint16_t rx_buf_size; 953 954 struct bnxt_cp_ring def_cp_ring; 955 struct bnxt_cp_ring def_nq_ring; 956 struct iflib_dma_info def_cp_ring_mem; 957 struct iflib_dma_info def_nq_ring_mem; 958 struct grouptask def_cp_task; 959 int db_size; 960 int legacy_db_size; 961 struct bnxt_doorbell_ops db_ops; 962 963 struct sysctl_ctx_list hw_stats; 964 struct sysctl_oid *hw_stats_oid; 965 struct sysctl_ctx_list hw_lro_ctx; 966 struct sysctl_oid *hw_lro_oid; 967 struct sysctl_ctx_list flow_ctrl_ctx; 968 struct sysctl_oid *flow_ctrl_oid; 969 struct sysctl_ctx_list dcb_ctx; 970 struct sysctl_oid *dcb_oid; 971 972 struct bnxt_ver_info *ver_info; 973 struct bnxt_nvram_info *nvm_info; 974 bool wol; 975 bool is_dev_init; 976 struct bnxt_hw_lro hw_lro; 977 uint8_t wol_filter_id; 978 uint16_t rx_coal_usecs; 979 uint16_t rx_coal_usecs_irq; 980 uint16_t rx_coal_frames; 981 uint16_t rx_coal_frames_irq; 982 uint16_t tx_coal_usecs; 983 uint16_t tx_coal_usecs_irq; 984 uint16_t tx_coal_frames; 985 uint16_t tx_coal_frames_irq; 986 987 #define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2) 988 #define BNXT_DEF_STATS_COAL_TICKS 1000000 989 #define BNXT_MIN_STATS_COAL_TICKS 250000 990 #define BNXT_MAX_STATS_COAL_TICKS 1000000 991 992 uint64_t fw_cap; 993 #define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0) 994 #define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1) 995 #define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2) 996 #define BNXT_FW_CAP_NEW_RM BIT_ULL(3) 997 #define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4) 998 #define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5) 999 #define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6) 1000 #define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7) 1001 #define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8) 1002 #define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9) 1003 #define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10) 1004 #define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11) 1005 #define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12) 1006 #define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13) 1007 #define BNXT_FW_CAP_PKG_VER BIT_ULL(14) 1008 #define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15) 1009 #define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16) 1010 #define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17) 1011 #define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18) 1012 #define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19) 1013 #define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20) 1014 #define BNXT_FW_CAP_HOT_RESET BIT_ULL(21) 1015 #define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23) 1016 #define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24) 1017 #define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25) 1018 #define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26) 1019 #define BNXT_FW_CAP_CFA_EEM BIT_ULL(27) 1020 #define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29) 1021 #define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30) 1022 #define BNXT_FW_CAP_ECN_STATS BIT_ULL(31) 1023 #define BNXT_FW_CAP_TRUFLOW BIT_ULL(32) 1024 #define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33) 1025 #define BNXT_FW_CAP_PTP_PPS BIT_ULL(34) 1026 #define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35) 1027 #define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36) 1028 #define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37) 1029 #define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38) 1030 #define BNXT_FW_CAP_PTP_RTC BIT_ULL(39) 1031 #define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40) 1032 #define BNXT_TRUFLOW_EN(bp) ((bp)->fw_cap & BNXT_FW_CAP_TRUFLOW_EN) 1033 #define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41) 1034 #define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42) 1035 #define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43) 1036 #define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44) 1037 #define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45) 1038 #define BNXT_FW_CAP_PTP_PTM BIT_ULL(46) 1039 #define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47) 1040 #define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48) 1041 #define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49) 1042 uint32_t lpi_tmr_lo; 1043 uint32_t lpi_tmr_hi; 1044 /* copied from flags and flags2 in hwrm_port_phy_qcaps_output */ 1045 uint16_t phy_flags; 1046 #define BNXT_PHY_FL_EEE_CAP HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EEE_SUPPORTED 1047 #define BNXT_PHY_FL_EXT_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_EXTERNAL_LPBK_SUPPORTED 1048 #define BNXT_PHY_FL_AN_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_AUTONEG_LPBK_SUPPORTED 1049 #define BNXT_PHY_FL_SHARED_PORT_CFG HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_SHARED_PHY_CFG_SUPPORTED 1050 #define BNXT_PHY_FL_PORT_STATS_NO_RESET HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_CUMULATIVE_COUNTERS_ON_RESET 1051 #define BNXT_PHY_FL_NO_PHY_LPBK HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED 1052 #define BNXT_PHY_FL_FW_MANAGED_LKDN HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN 1053 #define BNXT_PHY_FL_NO_FCS HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS 1054 #define BNXT_PHY_FL_NO_PAUSE (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PAUSE_UNSUPPORTED << 8) 1055 #define BNXT_PHY_FL_NO_PFC (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_PFC_UNSUPPORTED << 8) 1056 #define BNXT_PHY_FL_BANK_SEL (HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS2_BANK_ADDR_SUPPORTED << 8) 1057 struct bnxt_aux_dev *aux_dev; 1058 struct net_device *net_dev; 1059 struct mtx en_ops_lock; 1060 uint8_t port_partition_type; 1061 struct bnxt_en_dev *edev; 1062 unsigned long state; 1063 #define BNXT_STATE_OPEN 0 1064 #define BNXT_STATE_IN_SP_TASK 1 1065 #define BNXT_STATE_READ_STATS 2 1066 #define BNXT_STATE_FW_RESET_DET 3 1067 #define BNXT_STATE_IN_FW_RESET 4 1068 #define BNXT_STATE_ABORT_ERR 5 1069 #define BNXT_STATE_FW_FATAL_COND 6 1070 #define BNXT_STATE_DRV_REGISTERED 7 1071 #define BNXT_STATE_PCI_CHANNEL_IO_FROZEN 8 1072 #define BNXT_STATE_NAPI_DISABLED 9 1073 #define BNXT_STATE_L2_FILTER_RETRY 10 1074 #define BNXT_STATE_FW_ACTIVATE 11 1075 #define BNXT_STATE_RECOVER 12 1076 #define BNXT_STATE_FW_NON_FATAL_COND 13 1077 #define BNXT_STATE_FW_ACTIVATE_RESET 14 1078 #define BNXT_STATE_HALF_OPEN 15 1079 #define BNXT_NO_FW_ACCESS(bp) \ 1080 test_bit(BNXT_STATE_FW_FATAL_COND, &(bp)->state) 1081 struct pci_dev *pdev; 1082 1083 int fw_reset_state; 1084 }; 1085 1086 struct bnxt_filter_info { 1087 STAILQ_ENTRY(bnxt_filter_info) next; 1088 uint64_t fw_l2_filter_id; 1089 #define INVALID_MAC_INDEX ((uint16_t)-1) 1090 uint16_t mac_index; 1091 1092 /* Filter Characteristics */ 1093 uint32_t flags; 1094 uint32_t enables; 1095 uint8_t l2_addr[ETHER_ADDR_LEN]; 1096 uint8_t l2_addr_mask[ETHER_ADDR_LEN]; 1097 uint16_t l2_ovlan; 1098 uint16_t l2_ovlan_mask; 1099 uint16_t l2_ivlan; 1100 uint16_t l2_ivlan_mask; 1101 uint8_t t_l2_addr[ETHER_ADDR_LEN]; 1102 uint8_t t_l2_addr_mask[ETHER_ADDR_LEN]; 1103 uint16_t t_l2_ovlan; 1104 uint16_t t_l2_ovlan_mask; 1105 uint16_t t_l2_ivlan; 1106 uint16_t t_l2_ivlan_mask; 1107 uint8_t tunnel_type; 1108 uint16_t mirror_vnic_id; 1109 uint32_t vni; 1110 uint8_t pri_hint; 1111 uint64_t l2_filter_id_hint; 1112 }; 1113 1114 #define I2C_DEV_ADDR_A0 0xa0 1115 #define BNXT_MAX_PHY_I2C_RESP_SIZE 64 1116 1117 /* Function declarations */ 1118 void bnxt_report_link(struct bnxt_softc *softc); 1119 bool bnxt_check_hwrm_version(struct bnxt_softc *softc); 1120 struct bnxt_softc *bnxt_find_dev(uint32_t domain, uint32_t bus, uint32_t dev_fn, char *name); 1121 int bnxt_read_sfp_module_eeprom_info(struct bnxt_softc *bp, uint16_t i2c_addr, 1122 uint16_t page_number, uint8_t bank, bool bank_sel_en, uint16_t start_addr, 1123 uint16_t data_length, uint8_t *buf); 1124 void bnxt_dcb_init(struct bnxt_softc *softc); 1125 void bnxt_dcb_free(struct bnxt_softc *softc); 1126 uint8_t bnxt_dcb_setdcbx(struct bnxt_softc *softc, uint8_t mode); 1127 uint8_t bnxt_dcb_getdcbx(struct bnxt_softc *softc); 1128 int bnxt_dcb_ieee_getets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1129 int bnxt_dcb_ieee_setets(struct bnxt_softc *softc, struct bnxt_ieee_ets *ets); 1130 uint8_t get_phy_type(struct bnxt_softc *softc); 1131 int bnxt_dcb_ieee_getpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1132 int bnxt_dcb_ieee_setpfc(struct bnxt_softc *softc, struct bnxt_ieee_pfc *pfc); 1133 int bnxt_dcb_ieee_setapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1134 int bnxt_dcb_ieee_delapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app); 1135 int bnxt_dcb_ieee_listapp(struct bnxt_softc *softc, struct bnxt_dcb_app *app, int *num_inputs); 1136 1137 #endif /* _BNXT_H */ 1138