1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2017 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Landon Fuller 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 17 * redistribution must be conditioned upon including a substantially 18 * similar Disclaimer requirement for further binary redistribution. 19 * 20 * NO WARRANTY 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGES. 32 * 33 * $FreeBSD$ 34 */ 35 36 #ifndef _SIBA_SIBAVAR_H_ 37 #define _SIBA_SIBAVAR_H_ 38 39 #include <sys/param.h> 40 #include <sys/bitstring.h> 41 #include <sys/bus.h> 42 #include <sys/limits.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 46 #include <machine/bus.h> 47 #include <sys/rman.h> 48 49 #include "siba.h" 50 51 /* 52 * Internal definitions shared by siba(4) driver implementations. 53 */ 54 55 struct siba_addrspace; 56 struct siba_admatch; 57 struct siba_cfg_block; 58 struct siba_devinfo; 59 struct siba_core_id; 60 struct siba_softc; 61 62 int siba_probe(device_t dev); 63 int siba_attach(device_t dev); 64 int siba_detach(device_t dev); 65 int siba_resume(device_t dev); 66 int siba_suspend(device_t dev); 67 u_int siba_get_intr_count(device_t dev, device_t child); 68 int siba_get_intr_ivec(device_t dev, device_t child, 69 u_int intr, u_int *ivec); 70 71 uint16_t siba_get_bhnd_mfgid(uint16_t ocp_vendor); 72 73 int siba_add_children(device_t bus); 74 75 struct siba_devinfo *siba_alloc_dinfo(device_t dev); 76 int siba_init_dinfo(device_t dev, device_t child, 77 struct siba_devinfo *dinfo, 78 const struct siba_core_id *core_id); 79 void siba_free_dinfo(device_t dev, device_t child, 80 struct siba_devinfo *dinfo); 81 82 u_int siba_port_count(struct siba_core_id *core_id, 83 bhnd_port_type port_type); 84 bool siba_is_port_valid(struct siba_core_id *core_id, 85 bhnd_port_type port_type, u_int port); 86 87 u_int siba_port_region_count( 88 struct siba_core_id *core_id, 89 bhnd_port_type port_type, u_int port); 90 91 int siba_cfg_index(struct siba_core_id *core_id, 92 bhnd_port_type type, u_int port, u_int region, 93 u_int *cfgidx); 94 95 int siba_addrspace_index(struct siba_core_id *core_id, 96 bhnd_port_type type, u_int port, u_int region, 97 u_int *addridx); 98 99 u_int siba_addrspace_device_port(u_int addrspace); 100 u_int siba_addrspace_device_region(u_int addrspace); 101 102 u_int siba_cfg_agent_port(u_int cfg); 103 u_int siba_cfg_agent_region(u_int cfg); 104 105 struct siba_addrspace *siba_find_addrspace(struct siba_devinfo *dinfo, 106 bhnd_port_type type, u_int port, u_int region); 107 108 struct siba_cfg_block *siba_find_cfg_block(struct siba_devinfo *dinfo, 109 bhnd_port_type type, u_int port, u_int region); 110 111 u_int siba_admatch_offset(uint8_t addrspace); 112 int siba_parse_admatch(uint32_t am, 113 struct siba_admatch *admatch); 114 115 void siba_write_target_state(device_t dev, 116 struct siba_devinfo *dinfo, bus_size_t reg, 117 uint32_t value, uint32_t mask); 118 int siba_wait_target_state(device_t dev, 119 struct siba_devinfo *dinfo, bus_size_t reg, 120 uint32_t value, uint32_t mask, u_int usec); 121 122 123 /* Sonics configuration register blocks */ 124 #define SIBA_CFG_NUM_2_2 1 /**< sonics <= 2.2 maps SIBA_CFG0. */ 125 #define SIBA_CFG_NUM_2_3 2 /**< sonics <= 2.3 maps SIBA_CFG0 and SIBA_CFG1 */ 126 #define SIBA_MAX_CFG SIBA_CFG_NUM_2_3 /**< maximum number of supported config 127 register blocks */ 128 129 #define SIBA_CFG_RID_BASE 100 /**< base resource ID for SIBA_CFG* register allocations */ 130 #define SIBA_CFG_RID(_dinfo, _cfg) \ 131 (SIBA_CFG_RID_BASE + (_cfg) + \ 132 (_dinfo->core_id.core_info.core_idx * SIBA_MAX_CFG)) 133 134 /* Sonics/OCP address space mappings */ 135 #define SIBA_CORE_ADDRSPACE 0 /**< Address space mapping the primary 136 device registers */ 137 138 #define SIBA_MAX_ADDRSPACE 4 /**< Maximum number of Sonics/OCP 139 * address space mappings for a 140 * single core. */ 141 142 /* bhnd(4) (port,region) representation of siba address space mappings */ 143 #define SIBA_MAX_PORT 2 /**< maximum number of advertised 144 * bhnd(4) ports */ 145 146 /** siba(4) address match descriptor */ 147 struct siba_admatch { 148 uint32_t am_base; /**< base address. */ 149 uint32_t am_size; /**< size. */ 150 bool am_negative; /**< if true, negative matching is performed. */ 151 bool am_enabled; /**< if true, matching on this entry is enabled. */ 152 }; 153 154 /** siba(4) address space descriptor */ 155 struct siba_addrspace { 156 uint32_t sa_base; /**< base address */ 157 uint32_t sa_size; /**< size */ 158 int sa_rid; /**< bus resource id */ 159 uint32_t sa_bus_reserved;/**< number of bytes at high end of 160 * address space reserved for the bus */ 161 }; 162 163 /** siba(4) config block descriptor */ 164 struct siba_cfg_block { 165 uint32_t cb_base; /**< base address */ 166 uint32_t cb_size; /**< size */ 167 int cb_rid; /**< bus resource id */ 168 }; 169 170 /** siba(4) backplane interrupt flag descriptor */ 171 struct siba_intr { 172 bool mapped; /**< if an irq has been mapped */ 173 int rid; /**< bus resource id, or -1 if unassigned */ 174 rman_res_t irq; /**< the mapped bus irq, if any */ 175 }; 176 177 /** 178 * siba(4) per-core identification info. 179 */ 180 struct siba_core_id { 181 struct bhnd_core_info core_info; /**< standard bhnd(4) core info */ 182 uint16_t sonics_vendor; /**< OCP vendor identifier used to generate 183 * the JEDEC-106 bhnd(4) vendor identifier. */ 184 uint8_t sonics_rev; /**< sonics backplane revision code */ 185 bool intr_en; /**< if backplane interrupt distribution is enabled for this core */ 186 u_int intr_flag; /**< backplane interrupt flag # */ 187 struct siba_admatch admatch[SIBA_MAX_ADDRSPACE]; /**< active address match descriptors defined by this core. */ 188 uint8_t num_admatch; /**< number of address match descriptors. */ 189 uint8_t num_cfg_blocks; /**< number of Sonics configuration register 190 blocks mapped to the core's enumeration 191 space */ 192 }; 193 194 /** 195 * siba(4) per-core PMU allocation state. 196 */ 197 typedef enum { 198 SIBA_PMU_NONE, /**< If the core has not yet allocated PMU state */ 199 SIBA_PMU_BHND, /**< If standard bhnd(4) PMU support should be used */ 200 SIBA_PMU_PWRCTL, /**< If legacy PWRCTL PMU support should be used */ 201 SIBA_PMU_FIXED, /**< If legacy fixed (no-op) PMU support should be used */ 202 } siba_pmu_state; 203 204 /** 205 * siba(4) per-device info 206 */ 207 struct siba_devinfo { 208 struct resource_list resources; /**< per-core memory regions. */ 209 struct siba_core_id core_id; /**< core identification info */ 210 struct siba_addrspace addrspace[SIBA_MAX_ADDRSPACE]; /**< memory map descriptors */ 211 struct siba_cfg_block cfg[SIBA_MAX_CFG]; /**< config block descriptors */ 212 struct siba_intr intr; /**< interrupt flag mapping, if any */ 213 214 struct bhnd_resource *cfg_res[SIBA_MAX_CFG]; /**< bus-mapped config block registers */ 215 int cfg_rid[SIBA_MAX_CFG]; /**< bus-mapped config block resource IDs */ 216 siba_pmu_state pmu_state; /**< per-core PMU state */ 217 union { 218 void *bhnd_info; /**< if SIBA_PMU_BHND, bhnd(4)-managed per-core PMU info. */ 219 device_t pwrctl; /**< if SIBA_PMU_PWRCTL, legacy PWRCTL provider. */ 220 } pmu; 221 }; 222 223 /** siba(4) per-instance state */ 224 struct siba_softc { 225 struct bhnd_softc bhnd_sc; /**< bhnd state */ 226 device_t dev; /**< siba device */ 227 struct mtx mtx; /**< state mutex */ 228 }; 229 230 #define SIBA_LOCK_INIT(sc) \ 231 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF) 232 #define SIBA_LOCK(sc) mtx_lock(&(sc)->mtx) 233 #define SIBA_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 234 #define SIBA_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 235 #define SIBA_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 236 237 #endif /* _SIBA_SIBAVAR_H_ */ 238