1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 34 35 #include <dev/bhnd/nvram/bhnd_spromvar.h> 36 37 #include "chipc.h" 38 39 DECLARE_CLASS(bhnd_chipc); 40 extern devclass_t bhnd_chipc_devclass; 41 42 struct chipc_region; 43 44 /** 45 * Supported ChipCommon flash types. 46 */ 47 typedef enum { 48 CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized 49 by the ChipCommon driver */ 50 CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ 51 CHIPC_SFLASH_ST = 2, /**< ST serial flash */ 52 CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ 53 CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ 54 CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ 55 CHIPC_NFLASH = 6, /**< NAND flash */ 56 CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ 57 } chipc_flash; 58 59 /** 60 * ChipCommon capability flags; 61 */ 62 struct chipc_caps { 63 uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ 64 bool mipseb; /**< MIPS is big-endian */ 65 uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ 66 uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ 67 68 uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ 69 chipc_flash flash_type; /**< Flash type */ 70 uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ 71 uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI not present */ 72 73 uint8_t pll_type; /**< PLL type */ 74 bool power_control; /**< Power control available */ 75 bool jtag_master; /**< JTAG Master present */ 76 bool boot_rom; /**< Internal boot ROM is active */ 77 uint8_t backplane_64; /**< Backplane supports 64-bit addressing. 78 Note that this does not gaurantee 79 the CPU itself supports 64-bit 80 addressing. */ 81 bool pmu; /**< PMU is present. */ 82 bool eci; /**< ECI (enhanced coexistence inteface) is present. */ 83 bool seci; /**< SECI (serial ECI) is present */ 84 bool sprom; /**< SPROM is present */ 85 bool gsio; /**< GSIO (SPI/I2C) present */ 86 bool aob; /**< AOB (always on bus) present. 87 If set, PMU and GCI registers are 88 not accessible via ChipCommon, 89 and are instead accessible via 90 dedicated cores on the bhnd bus */ 91 }; 92 93 /* 94 * ChipCommon device quirks / features 95 */ 96 enum { 97 /** No quirks */ 98 CHIPC_QUIRK_NONE = 0, 99 100 /** 101 * ChipCommon-controlled SPROM/OTP is supported, along with the 102 * CHIPC_CAP_SPROM capability flag. 103 */ 104 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 105 106 /** 107 * The BCM4706 NAND flash interface is supported, along with the 108 * CHIPC_CAP_4706_NFLASH capability flag. 109 */ 110 CHIPC_QUIRK_4706_NFLASH = (1<<2), 111 112 /** 113 * The SPROM is attached via muxed pins. The pins must be switched 114 * to allow reading/writing. 115 */ 116 CHIPC_QUIRK_MUX_SPROM = (1<<3), 117 118 /** 119 * Access to the SPROM uses pins shared with the 802.11a external PA. 120 * 121 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 122 * must be cleared to allow SPROM access. 123 */ 124 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 125 CHIPC_QUIRK_MUX_SPROM, 126 127 /** 128 * Access to the SPROM uses pins shared with the 802.11a external PA. 129 * 130 * On modules using these 4331 chip packages, the external PA is 131 * attached via GPIO 2, 5, and sprom_dout pins. 132 * 133 * When enabling and disabling EXTPA to allow SPROM access, the 134 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 135 * respectively. 136 */ 137 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 138 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 139 140 /** 141 * Access to the SPROM uses pins shared with two 802.11a external PAs. 142 * 143 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 144 * be cleared to allow SPROM access. 145 */ 146 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 147 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 148 149 150 /** 151 * SPROM pins are muxed with the FEM control lines on this 4360-family 152 * device. The muxed pins must be switched to allow reading/writing 153 * the SPROM. 154 */ 155 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 156 CHIPC_QUIRK_MUX_SPROM, 157 158 /** Supports CHIPC_CAPABILITIES_EXT register */ 159 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 160 161 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 162 * ChipCommon revisions using the 'IPX' OTP controller. */ 163 CHIPC_QUIRK_IPX_OTPLAYOUT_SIZE = (1<<7), 164 }; 165 166 /** 167 * chipc child device info. 168 */ 169 struct chipc_devinfo { 170 struct resource_list resources; /**< child resources */ 171 }; 172 173 /** 174 * chipc driver instance state. 175 */ 176 struct chipc_softc { 177 device_t dev; 178 179 struct bhnd_resource *core; /**< core registers. */ 180 struct chipc_region *core_region; /**< region containing core registers */ 181 182 struct bhnd_chipid ccid; /**< chip identification */ 183 uint32_t quirks; /**< chipc quirk flags */ 184 struct chipc_caps caps; /**< chipc capabilities */ 185 186 bhnd_nvram_src_t nvram_src; /**< identified NVRAM source */ 187 188 struct mtx mtx; /**< state mutex. */ 189 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 190 struct rman mem_rman; /**< port memory manager */ 191 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 192 }; 193 194 #define CHIPC_LOCK_INIT(sc) \ 195 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 196 "BHND chipc driver lock", MTX_DEF) 197 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 198 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 199 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 200 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 201 202 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 203