1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2017 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by Landon Fuller 9 * under sponsorship from the FreeBSD Foundation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 19 * redistribution must be conditioned upon including a substantially 20 * similar Disclaimer requirement for further binary redistribution. 21 * 22 * NO WARRANTY 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 27 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 31 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGES. 34 * 35 * $FreeBSD$ 36 */ 37 38 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 39 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 40 41 #include <sys/types.h> 42 #include <sys/rman.h> 43 44 #include <dev/bhnd/nvram/bhnd_spromvar.h> 45 46 #include "chipc.h" 47 48 DECLARE_CLASS(bhnd_chipc_driver); 49 extern devclass_t bhnd_chipc_devclass; 50 51 struct chipc_region; 52 53 const char *chipc_flash_name(chipc_flash type); 54 const char *chipc_flash_bus_name(chipc_flash type); 55 const char *chipc_sflash_device_name(chipc_flash type); 56 57 /* 58 * ChipCommon device quirks / features 59 */ 60 enum { 61 /** No quirks */ 62 CHIPC_QUIRK_NONE = 0, 63 64 /** 65 * ChipCommon-controlled SPROM/OTP is supported, along with the 66 * CHIPC_CAP_SPROM capability flag. 67 */ 68 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 69 70 /** 71 * The BCM4706 NAND flash interface is supported, along with the 72 * CHIPC_CAP_4706_NFLASH capability flag. 73 */ 74 CHIPC_QUIRK_4706_NFLASH = (1<<2), 75 76 /** 77 * The SPROM is attached via muxed pins. The pins must be switched 78 * to allow reading/writing. 79 */ 80 CHIPC_QUIRK_MUX_SPROM = (1<<3), 81 82 /** 83 * Access to the SPROM uses pins shared with the 802.11a external PA. 84 * 85 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 86 * must be cleared to allow SPROM access. 87 */ 88 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 89 CHIPC_QUIRK_MUX_SPROM, 90 91 /** 92 * Access to the SPROM uses pins shared with the 802.11a external PA. 93 * 94 * On modules using these 4331 chip packages, the external PA is 95 * attached via GPIO 2, 5, and sprom_dout pins. 96 * 97 * When enabling and disabling EXTPA to allow SPROM access, the 98 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 99 * respectively. 100 */ 101 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 102 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 103 104 /** 105 * Access to the SPROM uses pins shared with two 802.11a external PAs. 106 * 107 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 108 * be cleared to allow SPROM access. 109 */ 110 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 111 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 112 113 /** 114 * SPROM pins are muxed with the FEM control lines on this 4360-family 115 * device. The muxed pins must be switched to allow reading/writing 116 * the SPROM. 117 */ 118 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 119 CHIPC_QUIRK_MUX_SPROM, 120 121 /** Supports CHIPC_CAPABILITIES_EXT register */ 122 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 123 124 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, 125 * CHIPC_OTPPROG) */ 126 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), 127 128 /** Supports HND OTP registers. */ 129 CHIPC_QUIRK_OTP_HND = (1<<8) | 130 CHIPC_QUIRK_SUPPORTS_OTP, 131 132 /** Supports IPX OTP registers. */ 133 CHIPC_QUIRK_OTP_IPX = (1<<9) | 134 CHIPC_QUIRK_SUPPORTS_OTP, 135 136 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 137 * ChipCommon revisions using the 'IPX' OTP controller. */ 138 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) 139 }; 140 141 /** 142 * chipc child device info. 143 */ 144 struct chipc_devinfo { 145 struct resource_list resources; /**< child resources */ 146 rman_res_t irq; /**< child IRQ, if mapped */ 147 bool irq_mapped; /**< true if IRQ mapped, false otherwise */ 148 }; 149 150 /** 151 * chipc driver instance state. 152 */ 153 struct chipc_softc { 154 device_t dev; 155 156 struct bhnd_resource *core; /**< core registers. */ 157 struct chipc_region *core_region; /**< region containing core registers */ 158 159 uint32_t quirks; /**< chipc quirk flags */ 160 struct chipc_caps caps; /**< chipc capabilities */ 161 162 struct mtx mtx; /**< state mutex. */ 163 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 164 struct rman mem_rman; /**< port memory manager */ 165 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 166 }; 167 168 #define CHIPC_LOCK_INIT(sc) \ 169 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 170 "BHND chipc driver lock", MTX_DEF) 171 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 172 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 173 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 174 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 175 176 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 177