1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 34 35 #include <dev/bhnd/nvram/bhnd_spromvar.h> 36 37 #include "chipc.h" 38 39 DECLARE_CLASS(bhnd_chipc); 40 extern devclass_t bhnd_chipc_devclass; 41 42 #define CHIPC_MAX_RES 1 43 #define CHIPC_MAX_RSPEC (CHIPC_MAX_RES+1) 44 45 /* 46 * ChipCommon device quirks / features 47 */ 48 enum { 49 /** No quirks */ 50 CHIPC_QUIRK_NONE = 0, 51 52 /** 53 * ChipCommon-controlled SPROM/OTP is supported, along with the 54 * CHIPC_CAP_SPROM capability flag. 55 */ 56 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 57 58 /** 59 * External NAND NVRAM is supported, along with the CHIPC_CAP_NFLASH 60 * capability flag. 61 */ 62 CHIPC_QUIRK_SUPPORTS_NFLASH = (1<<2), 63 64 /** 65 * The SPROM is attached via muxed pins. The pins must be switched 66 * to allow reading/writing. 67 */ 68 CHIPC_QUIRK_MUX_SPROM = (1<<3), 69 70 /** 71 * Access to the SPROM uses pins shared with the 802.11a external PA. 72 * 73 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 74 * must be cleared to allow SPROM access. 75 */ 76 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 77 CHIPC_QUIRK_MUX_SPROM, 78 79 /** 80 * Access to the SPROM uses pins shared with the 802.11a external PA. 81 * 82 * On modules using these 4331 chip packages, the external PA is 83 * attached via GPIO 2, 5, and sprom_dout pins. 84 * 85 * When enabling and disabling EXTPA to allow SPROM access, the 86 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 87 * respectively. 88 */ 89 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 90 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 91 92 /** 93 * Access to the SPROM uses pins shared with two 802.11a external PAs. 94 * 95 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 96 * be cleared to allow SPROM access. 97 */ 98 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 99 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 100 101 102 /** 103 * SPROM pins are muxed with the FEM control lines on this 4360-family 104 * device. The muxed pins must be switched to allow reading/writing 105 * the SPROM. 106 */ 107 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | CHIPC_QUIRK_MUX_SPROM 108 }; 109 110 struct chipc_softc { 111 device_t dev; 112 113 struct resource_spec rspec[CHIPC_MAX_RSPEC]; 114 struct bhnd_resource *res[CHIPC_MAX_RES]; 115 116 struct bhnd_resource *core; /**< core registers. */ 117 struct bhnd_chipid ccid; /**< chip identification */ 118 uint32_t quirks; /**< CHIPC_QUIRK_* quirk flags */ 119 uint32_t caps; /**< CHIPC_CAP_* capability register flags */ 120 uint32_t cst; /**< CHIPC_CST* status register flags */ 121 bhnd_nvram_src_t nvram_src; /**< NVRAM source */ 122 123 struct mtx mtx; /**< state mutex. */ 124 125 struct bhnd_sprom sprom; /**< OTP/SPROM shadow, if any */ 126 }; 127 128 #define CHIPC_LOCK_INIT(sc) \ 129 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 130 "BHND chipc driver lock", MTX_DEF) 131 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 132 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 133 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 134 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 135 136 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */