1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 34 35 #include <sys/types.h> 36 #include <sys/rman.h> 37 38 #include <dev/bhnd/nvram/bhnd_spromvar.h> 39 40 #include "chipc.h" 41 42 DECLARE_CLASS(bhnd_chipc); 43 extern devclass_t bhnd_chipc_devclass; 44 45 struct chipc_region; 46 47 /** 48 * Supported ChipCommon flash types. 49 */ 50 typedef enum { 51 CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized 52 by the ChipCommon driver */ 53 CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ 54 CHIPC_SFLASH_ST = 2, /**< ST serial flash */ 55 CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ 56 CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ 57 CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ 58 CHIPC_NFLASH = 6, /**< NAND flash */ 59 CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ 60 } chipc_flash; 61 62 const char *chipc_flash_name(chipc_flash type); 63 const char *chipc_flash_bus_name(chipc_flash type); 64 const char *chipc_sflash_device_name(chipc_flash type); 65 66 /** 67 * ChipCommon capability flags; 68 */ 69 struct chipc_caps { 70 uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ 71 bool mipseb; /**< MIPS is big-endian */ 72 uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ 73 uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ 74 75 uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ 76 77 chipc_flash flash_type; /**< flash type */ 78 uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI 79 not present */ 80 81 bhnd_nvram_src nvram_src; /**< identified NVRAM source */ 82 bus_size_t sprom_offset; /**< Offset to SPROM data within 83 SPROM/OTP, 0 if unknown or not 84 present */ 85 uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ 86 87 uint8_t pll_type; /**< PLL type */ 88 bool power_control; /**< Power control available */ 89 bool jtag_master; /**< JTAG Master present */ 90 bool boot_rom; /**< Internal boot ROM is active */ 91 uint8_t backplane_64; /**< Backplane supports 64-bit addressing. 92 Note that this does not gaurantee 93 the CPU itself supports 64-bit 94 addressing. */ 95 bool pmu; /**< PMU is present. */ 96 bool eci; /**< ECI (enhanced coexistence inteface) is present. */ 97 bool seci; /**< SECI (serial ECI) is present */ 98 bool sprom; /**< SPROM is present */ 99 bool gsio; /**< GSIO (SPI/I2C) present */ 100 bool aob; /**< AOB (always on bus) present. 101 If set, PMU and GCI registers are 102 not accessible via ChipCommon, 103 and are instead accessible via 104 dedicated cores on the bhnd bus */ 105 }; 106 107 /* 108 * ChipCommon device quirks / features 109 */ 110 enum { 111 /** No quirks */ 112 CHIPC_QUIRK_NONE = 0, 113 114 /** 115 * ChipCommon-controlled SPROM/OTP is supported, along with the 116 * CHIPC_CAP_SPROM capability flag. 117 */ 118 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 119 120 /** 121 * The BCM4706 NAND flash interface is supported, along with the 122 * CHIPC_CAP_4706_NFLASH capability flag. 123 */ 124 CHIPC_QUIRK_4706_NFLASH = (1<<2), 125 126 /** 127 * The SPROM is attached via muxed pins. The pins must be switched 128 * to allow reading/writing. 129 */ 130 CHIPC_QUIRK_MUX_SPROM = (1<<3), 131 132 /** 133 * Access to the SPROM uses pins shared with the 802.11a external PA. 134 * 135 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 136 * must be cleared to allow SPROM access. 137 */ 138 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 139 CHIPC_QUIRK_MUX_SPROM, 140 141 /** 142 * Access to the SPROM uses pins shared with the 802.11a external PA. 143 * 144 * On modules using these 4331 chip packages, the external PA is 145 * attached via GPIO 2, 5, and sprom_dout pins. 146 * 147 * When enabling and disabling EXTPA to allow SPROM access, the 148 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 149 * respectively. 150 */ 151 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 152 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 153 154 /** 155 * Access to the SPROM uses pins shared with two 802.11a external PAs. 156 * 157 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 158 * be cleared to allow SPROM access. 159 */ 160 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 161 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 162 163 164 /** 165 * SPROM pins are muxed with the FEM control lines on this 4360-family 166 * device. The muxed pins must be switched to allow reading/writing 167 * the SPROM. 168 */ 169 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 170 CHIPC_QUIRK_MUX_SPROM, 171 172 /** Supports CHIPC_CAPABILITIES_EXT register */ 173 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 174 175 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, 176 * CHIPC_OTPPROG) */ 177 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), 178 179 /** Supports HND OTP registers. */ 180 CHIPC_QUIRK_OTP_HND = (1<<8) | 181 CHIPC_QUIRK_SUPPORTS_OTP, 182 183 /** Supports IPX OTP registers. */ 184 CHIPC_QUIRK_OTP_IPX = (1<<9) | 185 CHIPC_QUIRK_SUPPORTS_OTP, 186 187 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 188 * ChipCommon revisions using the 'IPX' OTP controller. */ 189 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) 190 }; 191 192 /** 193 * chipc child device info. 194 */ 195 struct chipc_devinfo { 196 struct resource_list resources; /**< child resources */ 197 }; 198 199 /** 200 * chipc driver instance state. 201 */ 202 struct chipc_softc { 203 device_t dev; 204 205 struct bhnd_resource *core; /**< core registers. */ 206 struct chipc_region *core_region; /**< region containing core registers */ 207 208 uint32_t quirks; /**< chipc quirk flags */ 209 struct chipc_caps caps; /**< chipc capabilities */ 210 211 struct mtx mtx; /**< state mutex. */ 212 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 213 struct rman mem_rman; /**< port memory manager */ 214 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 215 }; 216 217 #define CHIPC_LOCK_INIT(sc) \ 218 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 219 "BHND chipc driver lock", MTX_DEF) 220 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 221 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 222 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 223 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 224 225 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 226