1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2017 The FreeBSD Foundation 6 * All rights reserved. 7 * 8 * Portions of this software were developed by Landon Fuller 9 * under sponsorship from the FreeBSD Foundation. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer, 16 * without modification. 17 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 18 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 19 * redistribution must be conditioned upon including a substantially 20 * similar Disclaimer requirement for further binary redistribution. 21 * 22 * NO WARRANTY 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 26 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 27 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 28 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 31 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGES. 34 * 35 */ 36 37 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 38 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 39 40 #include <sys/types.h> 41 #include <sys/rman.h> 42 43 #include <dev/bhnd/nvram/bhnd_spromvar.h> 44 45 #include "chipc.h" 46 47 DECLARE_CLASS(bhnd_chipc_driver); 48 49 struct chipc_region; 50 51 const char *chipc_flash_name(chipc_flash type); 52 const char *chipc_flash_bus_name(chipc_flash type); 53 const char *chipc_sflash_device_name(chipc_flash type); 54 55 /* 56 * ChipCommon device quirks / features 57 */ 58 enum { 59 /** No quirks */ 60 CHIPC_QUIRK_NONE = 0, 61 62 /** 63 * ChipCommon-controlled SPROM/OTP is supported, along with the 64 * CHIPC_CAP_SPROM capability flag. 65 */ 66 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 67 68 /** 69 * The BCM4706 NAND flash interface is supported, along with the 70 * CHIPC_CAP_4706_NFLASH capability flag. 71 */ 72 CHIPC_QUIRK_4706_NFLASH = (1<<2), 73 74 /** 75 * The SPROM is attached via muxed pins. The pins must be switched 76 * to allow reading/writing. 77 */ 78 CHIPC_QUIRK_MUX_SPROM = (1<<3), 79 80 /** 81 * Access to the SPROM uses pins shared with the 802.11a external PA. 82 * 83 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 84 * must be cleared to allow SPROM access. 85 */ 86 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 87 CHIPC_QUIRK_MUX_SPROM, 88 89 /** 90 * Access to the SPROM uses pins shared with the 802.11a external PA. 91 * 92 * On modules using these 4331 chip packages, the external PA is 93 * attached via GPIO 2, 5, and sprom_dout pins. 94 * 95 * When enabling and disabling EXTPA to allow SPROM access, the 96 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 97 * respectively. 98 */ 99 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 100 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 101 102 /** 103 * Access to the SPROM uses pins shared with two 802.11a external PAs. 104 * 105 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 106 * be cleared to allow SPROM access. 107 */ 108 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 109 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 110 111 /** 112 * SPROM pins are muxed with the FEM control lines on this 4360-family 113 * device. The muxed pins must be switched to allow reading/writing 114 * the SPROM. 115 */ 116 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 117 CHIPC_QUIRK_MUX_SPROM, 118 119 /** Supports CHIPC_CAPABILITIES_EXT register */ 120 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 121 122 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, 123 * CHIPC_OTPPROG) */ 124 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), 125 126 /** Supports HND OTP registers. */ 127 CHIPC_QUIRK_OTP_HND = (1<<8) | 128 CHIPC_QUIRK_SUPPORTS_OTP, 129 130 /** Supports IPX OTP registers. */ 131 CHIPC_QUIRK_OTP_IPX = (1<<9) | 132 CHIPC_QUIRK_SUPPORTS_OTP, 133 134 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 135 * ChipCommon revisions using the 'IPX' OTP controller. */ 136 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) 137 }; 138 139 /** 140 * chipc child device info. 141 */ 142 struct chipc_devinfo { 143 struct resource_list resources; /**< child resources */ 144 rman_res_t irq; /**< child IRQ, if mapped */ 145 bool irq_mapped; /**< true if IRQ mapped, false otherwise */ 146 }; 147 148 /** 149 * chipc driver instance state. 150 */ 151 struct chipc_softc { 152 device_t dev; 153 154 struct bhnd_resource *core; /**< core registers. */ 155 struct chipc_region *core_region; /**< region containing core registers */ 156 157 uint32_t quirks; /**< chipc quirk flags */ 158 struct chipc_caps caps; /**< chipc capabilities */ 159 160 struct mtx mtx; /**< state mutex. */ 161 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 162 struct rman mem_rman; /**< port memory manager */ 163 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 164 }; 165 166 #define CHIPC_LOCK_INIT(sc) \ 167 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 168 "BHND chipc driver lock", MTX_DEF) 169 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 170 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 171 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 172 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 173 174 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 175