1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 34 35 #include <sys/types.h> 36 #include <sys/rman.h> 37 38 #include <dev/bhnd/nvram/bhnd_spromvar.h> 39 40 #include "chipc.h" 41 42 DECLARE_CLASS(bhnd_chipc_driver); 43 extern devclass_t bhnd_chipc_devclass; 44 45 struct chipc_region; 46 47 const char *chipc_flash_name(chipc_flash type); 48 const char *chipc_flash_bus_name(chipc_flash type); 49 const char *chipc_sflash_device_name(chipc_flash type); 50 51 /* 52 * ChipCommon device quirks / features 53 */ 54 enum { 55 /** No quirks */ 56 CHIPC_QUIRK_NONE = 0, 57 58 /** 59 * ChipCommon-controlled SPROM/OTP is supported, along with the 60 * CHIPC_CAP_SPROM capability flag. 61 */ 62 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 63 64 /** 65 * The BCM4706 NAND flash interface is supported, along with the 66 * CHIPC_CAP_4706_NFLASH capability flag. 67 */ 68 CHIPC_QUIRK_4706_NFLASH = (1<<2), 69 70 /** 71 * The SPROM is attached via muxed pins. The pins must be switched 72 * to allow reading/writing. 73 */ 74 CHIPC_QUIRK_MUX_SPROM = (1<<3), 75 76 /** 77 * Access to the SPROM uses pins shared with the 802.11a external PA. 78 * 79 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 80 * must be cleared to allow SPROM access. 81 */ 82 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 83 CHIPC_QUIRK_MUX_SPROM, 84 85 /** 86 * Access to the SPROM uses pins shared with the 802.11a external PA. 87 * 88 * On modules using these 4331 chip packages, the external PA is 89 * attached via GPIO 2, 5, and sprom_dout pins. 90 * 91 * When enabling and disabling EXTPA to allow SPROM access, the 92 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 93 * respectively. 94 */ 95 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 96 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 97 98 /** 99 * Access to the SPROM uses pins shared with two 802.11a external PAs. 100 * 101 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 102 * be cleared to allow SPROM access. 103 */ 104 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 105 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 106 107 108 /** 109 * SPROM pins are muxed with the FEM control lines on this 4360-family 110 * device. The muxed pins must be switched to allow reading/writing 111 * the SPROM. 112 */ 113 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 114 CHIPC_QUIRK_MUX_SPROM, 115 116 /** Supports CHIPC_CAPABILITIES_EXT register */ 117 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 118 119 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, 120 * CHIPC_OTPPROG) */ 121 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), 122 123 /** Supports HND OTP registers. */ 124 CHIPC_QUIRK_OTP_HND = (1<<8) | 125 CHIPC_QUIRK_SUPPORTS_OTP, 126 127 /** Supports IPX OTP registers. */ 128 CHIPC_QUIRK_OTP_IPX = (1<<9) | 129 CHIPC_QUIRK_SUPPORTS_OTP, 130 131 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 132 * ChipCommon revisions using the 'IPX' OTP controller. */ 133 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) 134 }; 135 136 /** 137 * chipc child device info. 138 */ 139 struct chipc_devinfo { 140 struct resource_list resources; /**< child resources */ 141 }; 142 143 /** 144 * chipc driver instance state. 145 */ 146 struct chipc_softc { 147 device_t dev; 148 149 struct bhnd_resource *core; /**< core registers. */ 150 struct chipc_region *core_region; /**< region containing core registers */ 151 152 uint32_t quirks; /**< chipc quirk flags */ 153 struct chipc_caps caps; /**< chipc capabilities */ 154 155 struct mtx mtx; /**< state mutex. */ 156 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 157 struct rman mem_rman; /**< port memory manager */ 158 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 159 }; 160 161 #define CHIPC_LOCK_INIT(sc) \ 162 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 163 "BHND chipc driver lock", MTX_DEF) 164 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 165 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 166 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 167 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 168 169 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 170