1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 34 35 #include <sys/types.h> 36 #include <sys/rman.h> 37 38 #include <dev/bhnd/nvram/bhnd_spromvar.h> 39 40 #include "chipc.h" 41 42 DECLARE_CLASS(bhnd_chipc); 43 extern devclass_t bhnd_chipc_devclass; 44 45 struct chipc_region; 46 47 /** 48 * Supported ChipCommon flash types. 49 */ 50 typedef enum { 51 CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized 52 by the ChipCommon driver */ 53 CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ 54 CHIPC_SFLASH_ST = 2, /**< ST serial flash */ 55 CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ 56 CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ 57 CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ 58 CHIPC_NFLASH = 6, /**< NAND flash */ 59 CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ 60 } chipc_flash; 61 62 /** 63 * ChipCommon capability flags; 64 */ 65 struct chipc_caps { 66 uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ 67 bool mipseb; /**< MIPS is big-endian */ 68 uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ 69 uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ 70 71 uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ 72 chipc_flash flash_type; /**< Flash type */ 73 bhnd_nvram_src nvram_src; /**< identified NVRAM source */ 74 75 bus_size_t sprom_offset; /**< Offset to SPROM data within 76 SPROM/OTP, 0 if unknown or not 77 present */ 78 uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ 79 uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI 80 not present */ 81 82 uint8_t pll_type; /**< PLL type */ 83 bool power_control; /**< Power control available */ 84 bool jtag_master; /**< JTAG Master present */ 85 bool boot_rom; /**< Internal boot ROM is active */ 86 uint8_t backplane_64; /**< Backplane supports 64-bit addressing. 87 Note that this does not gaurantee 88 the CPU itself supports 64-bit 89 addressing. */ 90 bool pmu; /**< PMU is present. */ 91 bool eci; /**< ECI (enhanced coexistence inteface) is present. */ 92 bool seci; /**< SECI (serial ECI) is present */ 93 bool sprom; /**< SPROM is present */ 94 bool gsio; /**< GSIO (SPI/I2C) present */ 95 bool aob; /**< AOB (always on bus) present. 96 If set, PMU and GCI registers are 97 not accessible via ChipCommon, 98 and are instead accessible via 99 dedicated cores on the bhnd bus */ 100 }; 101 102 /* 103 * ChipCommon device quirks / features 104 */ 105 enum { 106 /** No quirks */ 107 CHIPC_QUIRK_NONE = 0, 108 109 /** 110 * ChipCommon-controlled SPROM/OTP is supported, along with the 111 * CHIPC_CAP_SPROM capability flag. 112 */ 113 CHIPC_QUIRK_SUPPORTS_SPROM = (1<<1), 114 115 /** 116 * The BCM4706 NAND flash interface is supported, along with the 117 * CHIPC_CAP_4706_NFLASH capability flag. 118 */ 119 CHIPC_QUIRK_4706_NFLASH = (1<<2), 120 121 /** 122 * The SPROM is attached via muxed pins. The pins must be switched 123 * to allow reading/writing. 124 */ 125 CHIPC_QUIRK_MUX_SPROM = (1<<3), 126 127 /** 128 * Access to the SPROM uses pins shared with the 802.11a external PA. 129 * 130 * On modules using these 4331 packages, the CCTRL4331_EXTPA_EN flag 131 * must be cleared to allow SPROM access. 132 */ 133 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM = (1<<4) | 134 CHIPC_QUIRK_MUX_SPROM, 135 136 /** 137 * Access to the SPROM uses pins shared with the 802.11a external PA. 138 * 139 * On modules using these 4331 chip packages, the external PA is 140 * attached via GPIO 2, 5, and sprom_dout pins. 141 * 142 * When enabling and disabling EXTPA to allow SPROM access, the 143 * CCTRL4331_EXTPA_ON_GPIO2_5 flag must also be set or cleared, 144 * respectively. 145 */ 146 CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM = (1<<5) | 147 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 148 149 /** 150 * Access to the SPROM uses pins shared with two 802.11a external PAs. 151 * 152 * When enabling and disabling EXTPA, the CCTRL4331_EXTPA_EN2 must also 153 * be cleared to allow SPROM access. 154 */ 155 CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM = (1<<6) | 156 CHIPC_QUIRK_4331_EXTPA_MUX_SPROM, 157 158 159 /** 160 * SPROM pins are muxed with the FEM control lines on this 4360-family 161 * device. The muxed pins must be switched to allow reading/writing 162 * the SPROM. 163 */ 164 CHIPC_QUIRK_4360_FEM_MUX_SPROM = (1<<5) | 165 CHIPC_QUIRK_MUX_SPROM, 166 167 /** Supports CHIPC_CAPABILITIES_EXT register */ 168 CHIPC_QUIRK_SUPPORTS_CAP_EXT = (1<<6), 169 170 /** Supports HND or IPX OTP registers (CHIPC_OTPST, CHIPC_OTPCTRL, 171 * CHIPC_OTPPROG) */ 172 CHIPC_QUIRK_SUPPORTS_OTP = (1<<7), 173 174 /** Supports HND OTP registers. */ 175 CHIPC_QUIRK_OTP_HND = (1<<8) | 176 CHIPC_QUIRK_SUPPORTS_OTP, 177 178 /** Supports IPX OTP registers. */ 179 CHIPC_QUIRK_OTP_IPX = (1<<9) | 180 CHIPC_QUIRK_SUPPORTS_OTP, 181 182 /** OTP size is defined via CHIPC_OTPLAYOUT register in later 183 * ChipCommon revisions using the 'IPX' OTP controller. */ 184 CHIPC_QUIRK_IPX_OTPL_SIZE = (1<<10) 185 }; 186 187 /** 188 * chipc child device info. 189 */ 190 struct chipc_devinfo { 191 struct resource_list resources; /**< child resources */ 192 }; 193 194 /** 195 * chipc driver instance state. 196 */ 197 struct chipc_softc { 198 device_t dev; 199 200 struct bhnd_resource *core; /**< core registers. */ 201 struct chipc_region *core_region; /**< region containing core registers */ 202 203 struct bhnd_chipid ccid; /**< chip identification */ 204 uint32_t quirks; /**< chipc quirk flags */ 205 struct chipc_caps caps; /**< chipc capabilities */ 206 207 struct mtx mtx; /**< state mutex. */ 208 size_t sprom_refcnt; /**< SPROM pin enable refcount */ 209 struct rman mem_rman; /**< port memory manager */ 210 STAILQ_HEAD(, chipc_region) mem_regions;/**< memory allocation records */ 211 }; 212 213 #define CHIPC_LOCK_INIT(sc) \ 214 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 215 "BHND chipc driver lock", MTX_DEF) 216 #define CHIPC_LOCK(sc) mtx_lock(&(sc)->mtx) 217 #define CHIPC_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 218 #define CHIPC_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 219 #define CHIPC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 220 221 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */ 222