1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPCVAR_H_ 33 #define _BHND_CORES_CHIPC_CHIPCVAR_H_ 34 35 #include "chipc.h" 36 37 DECLARE_CLASS(bhnd_chipc); 38 extern devclass_t bhnd_chipc_devclass; 39 40 #define CHIPC_MAX_RES 1 41 #define CHIPC_MAX_RSPEC (CHIPC_MAX_RES+1) 42 43 /* 44 * ChipCommon device quirks / features 45 */ 46 enum { 47 /** No quirks */ 48 CHIPC_QUIRK_NONE = 0, 49 50 /** 51 * The device always provides an external SROM. 52 */ 53 CHIPC_QUIRK_ALWAYS_HAS_SPROM = (1<<1), 54 55 56 /** 57 * SROM availability must be determined through chip-specific 58 * ChipStatus flags. 59 */ 60 CHIPC_QUIRK_SPROM_CHECK_CHIPST = (1<<3), 61 62 /** 63 * Use the rev22 chipstatus register format when determining SPROM 64 * availability. 65 */ 66 CHIPC_QUIRK_SPROM_CHECK_CST_R22 = (1<<4)|CHIPC_QUIRK_SPROM_CHECK_CHIPST, 67 68 /** 69 * Use the rev23 chipstatus register format when determining SPROM 70 * availability. 71 */ 72 CHIPC_QUIRK_SPROM_CHECK_CST_R23 = (1<<5)|CHIPC_QUIRK_SPROM_CHECK_CHIPST, 73 74 /** 75 * External NAND NVRAM is supported, along with the CHIPC_CAP_NFLASH 76 * capability flag. 77 */ 78 CHIPC_QUIRK_SUPPORTS_NFLASH = (1<<6), 79 }; 80 81 struct chipc_softc { 82 device_t dev; 83 84 struct resource_spec rspec[CHIPC_MAX_RSPEC]; 85 struct bhnd_resource *res[CHIPC_MAX_RES]; 86 87 struct bhnd_resource *core; /**< core registers. */ 88 struct bhnd_chipid ccid; /**< chip identification */ 89 uint32_t quirks; /**< CHIPC_QUIRK_* quirk flags */ 90 uint32_t caps; /**< CHIPC_CAP_* capability register flags */ 91 uint32_t cst; /**< CHIPC_CST* status register flags */ 92 }; 93 94 #endif /* _BHND_CORES_CHIPC_CHIPCVAR_H_ */