1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_CORES_CHIPC_CHIPC_H_ 33 #define _BHND_CORES_CHIPC_CHIPC_H_ 34 35 #include <dev/bhnd/bhnd.h> 36 #include <dev/bhnd/nvram/bhnd_nvram.h> 37 38 #include "bhnd_chipc_if.h" 39 40 /** 41 * Supported ChipCommon flash types. 42 */ 43 typedef enum { 44 CHIPC_FLASH_NONE = 0, /**< No flash, or a type unrecognized 45 by the ChipCommon driver */ 46 CHIPC_PFLASH_CFI = 1, /**< CFI-compatible parallel flash */ 47 CHIPC_SFLASH_ST = 2, /**< ST serial flash */ 48 CHIPC_SFLASH_AT = 3, /**< Atmel serial flash */ 49 CHIPC_QSFLASH_ST = 4, /**< ST quad-SPI flash */ 50 CHIPC_QSFLASH_AT = 5, /**< Atmel quad-SPI flash */ 51 CHIPC_NFLASH = 6, /**< NAND flash */ 52 CHIPC_NFLASH_4706 = 7 /**< BCM4706 NAND flash */ 53 } chipc_flash; 54 55 /** 56 * ChipCommon capability flags; 57 */ 58 struct chipc_caps { 59 uint8_t num_uarts; /**< Number of attached UARTS (1-3) */ 60 bool mipseb; /**< MIPS is big-endian */ 61 uint8_t uart_clock; /**< UART clock source (see CHIPC_CAP_UCLKSEL_*) */ 62 uint8_t uart_gpio; /**< UARTs own GPIO pins 12-15 */ 63 64 uint8_t extbus_type; /**< ExtBus type (CHIPC_CAP_EXTBUS_*) */ 65 66 chipc_flash flash_type; /**< flash type */ 67 uint8_t cfi_width; /**< CFI bus width, 0 if unknown or CFI 68 not present */ 69 70 bhnd_nvram_src nvram_src; /**< identified NVRAM source */ 71 bus_size_t sprom_offset; /**< Offset to SPROM data within 72 SPROM/OTP, 0 if unknown or not 73 present */ 74 uint8_t otp_size; /**< OTP (row?) size, 0 if not present */ 75 76 uint8_t pll_type; /**< PLL type */ 77 bool pwr_ctrl; /**< Power/clock control available */ 78 bool jtag_master; /**< JTAG Master present */ 79 bool boot_rom; /**< Internal boot ROM is active */ 80 uint8_t backplane_64; /**< Backplane supports 64-bit addressing. 81 Note that this does not gaurantee 82 the CPU itself supports 64-bit 83 addressing. */ 84 bool pmu; /**< PMU is present. */ 85 bool eci; /**< ECI (enhanced coexistence inteface) is present. */ 86 bool seci; /**< SECI (serial ECI) is present */ 87 bool sprom; /**< SPROM is present */ 88 bool gsio; /**< GSIO (SPI/I2C) present */ 89 bool aob; /**< AOB (always on bus) present. 90 If set, PMU and GCI registers are 91 not accessible via ChipCommon, 92 and are instead accessible via 93 dedicated cores on the bhnd bus */ 94 }; 95 96 #endif /* _BHND_CORES_CHIPC_CHIPC_H_ */ 97