xref: /freebsd/sys/dev/bhnd/cores/chipc/chipc.c (revision c66ec88fed842fbaad62c30d510644ceb7bd2d71)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5  * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com>
6  * Copyright (c) 2017 The FreeBSD Foundation
7  * All rights reserved.
8  *
9  * Portions of this software were developed by Landon Fuller
10  * under sponsorship from the FreeBSD Foundation.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions
14  * are met:
15  * 1. Redistributions of source code must retain the above copyright
16  *    notice, this list of conditions and the following disclaimer,
17  *    without modification.
18  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
19  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
20  *    redistribution must be conditioned upon including a substantially
21  *    similar Disclaimer requirement for further binary redistribution.
22  *
23  * NO WARRANTY
24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
27  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
28  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
29  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
32  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
34  * THE POSSIBILITY OF SUCH DAMAGES.
35  */
36 
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
39 
40 /*
41  * Broadcom ChipCommon driver.
42  *
43  * With the exception of some very early chipsets, the ChipCommon core
44  * has been included in all HND SoCs and chipsets based on the siba(4)
45  * and bcma(4) interconnects, providing a common interface to chipset
46  * identification, bus enumeration, UARTs, clocks, watchdog interrupts,
47  * GPIO, flash, etc.
48  */
49 
50 #include <sys/param.h>
51 #include <sys/kernel.h>
52 #include <sys/lock.h>
53 #include <sys/bus.h>
54 #include <sys/rman.h>
55 #include <sys/malloc.h>
56 #include <sys/module.h>
57 #include <sys/mutex.h>
58 #include <sys/systm.h>
59 
60 #include <machine/bus.h>
61 #include <machine/resource.h>
62 
63 #include <dev/bhnd/bhnd.h>
64 #include <dev/bhnd/bhndvar.h>
65 
66 #include "chipcreg.h"
67 #include "chipcvar.h"
68 
69 #include "chipc_private.h"
70 
71 devclass_t bhnd_chipc_devclass;	/**< bhnd(4) chipcommon device class */
72 
73 static struct bhnd_device_quirk chipc_quirks[];
74 
75 /* Supported device identifiers */
76 static const struct bhnd_device chipc_devices[] = {
77 	BHND_DEVICE(BCM, CC, NULL, chipc_quirks),
78 	BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks),
79 	BHND_DEVICE_END
80 };
81 
82 /* Device quirks table */
83 static struct bhnd_device_quirk chipc_quirks[] = {
84 	/* HND OTP controller revisions */
85 	BHND_CORE_QUIRK	(HWREV_EQ (12),		CHIPC_QUIRK_OTP_HND), /* (?) */
86 	BHND_CORE_QUIRK	(HWREV_EQ (17),		CHIPC_QUIRK_OTP_HND), /* BCM4311 */
87 	BHND_CORE_QUIRK	(HWREV_EQ (22),		CHIPC_QUIRK_OTP_HND), /* BCM4312 */
88 
89 	/* IPX OTP controller revisions */
90 	BHND_CORE_QUIRK	(HWREV_EQ (21),		CHIPC_QUIRK_OTP_IPX),
91 	BHND_CORE_QUIRK	(HWREV_GTE(23),		CHIPC_QUIRK_OTP_IPX),
92 
93 	BHND_CORE_QUIRK	(HWREV_GTE(32),		CHIPC_QUIRK_SUPPORTS_SPROM),
94 	BHND_CORE_QUIRK	(HWREV_GTE(35),		CHIPC_QUIRK_SUPPORTS_CAP_EXT),
95 	BHND_CORE_QUIRK	(HWREV_GTE(49),		CHIPC_QUIRK_IPX_OTPL_SIZE),
96 
97 	/* 4706 variant quirks */
98 	BHND_CORE_QUIRK	(HWREV_EQ (38),		CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */
99 	BHND_CHIP_QUIRK	(4706,	HWREV_ANY,	CHIPC_QUIRK_4706_NFLASH),
100 
101 	/* 4331 quirks*/
102 	BHND_CHIP_QUIRK	(4331,	HWREV_ANY,	CHIPC_QUIRK_4331_EXTPA_MUX_SPROM),
103 	BHND_PKG_QUIRK	(4331,	TN,		CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
104 	BHND_PKG_QUIRK	(4331,	TNA0,		CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM),
105 	BHND_PKG_QUIRK	(4331,	TT,		CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM),
106 
107 	/* 4360 quirks */
108 	BHND_CHIP_QUIRK	(4352,	HWREV_LTE(2),	CHIPC_QUIRK_4360_FEM_MUX_SPROM),
109 	BHND_CHIP_QUIRK	(43460,	HWREV_LTE(2),	CHIPC_QUIRK_4360_FEM_MUX_SPROM),
110 	BHND_CHIP_QUIRK	(43462,	HWREV_LTE(2),	CHIPC_QUIRK_4360_FEM_MUX_SPROM),
111 	BHND_CHIP_QUIRK	(43602,	HWREV_LTE(2),	CHIPC_QUIRK_4360_FEM_MUX_SPROM),
112 
113 	BHND_DEVICE_QUIRK_END
114 };
115 
116 static int		 chipc_add_children(struct chipc_softc *sc);
117 
118 static bhnd_nvram_src	 chipc_find_nvram_src(struct chipc_softc *sc,
119 			     struct chipc_caps *caps);
120 static int		 chipc_read_caps(struct chipc_softc *sc,
121 			     struct chipc_caps *caps);
122 
123 static bool		 chipc_should_enable_muxed_sprom(
124 			     struct chipc_softc *sc);
125 static int		 chipc_enable_otp_power(struct chipc_softc *sc);
126 static void		 chipc_disable_otp_power(struct chipc_softc *sc);
127 static int		 chipc_enable_sprom_pins(struct chipc_softc *sc);
128 static void		 chipc_disable_sprom_pins(struct chipc_softc *sc);
129 
130 static int		 chipc_try_activate_resource(struct chipc_softc *sc,
131 			     device_t child, int type, int rid,
132 			     struct resource *r, bool req_direct);
133 
134 static int		 chipc_init_rman(struct chipc_softc *sc);
135 static void		 chipc_free_rman(struct chipc_softc *sc);
136 static struct rman	*chipc_get_rman(struct chipc_softc *sc, int type);
137 
138 /* quirk and capability flag convenience macros */
139 #define	CHIPC_QUIRK(_sc, _name)	\
140     ((_sc)->quirks & CHIPC_QUIRK_ ## _name)
141 
142 #define CHIPC_CAP(_sc, _name)	\
143     ((_sc)->caps._name)
144 
145 #define	CHIPC_ASSERT_QUIRK(_sc, name)	\
146     KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set"))
147 
148 #define	CHIPC_ASSERT_CAP(_sc, name)	\
149     KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set"))
150 
151 static int
152 chipc_probe(device_t dev)
153 {
154 	const struct bhnd_device *id;
155 
156 	id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0]));
157 	if (id == NULL)
158 		return (ENXIO);
159 
160 	bhnd_set_default_core_desc(dev);
161 	return (BUS_PROBE_DEFAULT);
162 }
163 
164 static int
165 chipc_attach(device_t dev)
166 {
167 	struct chipc_softc		*sc;
168 	int				 error;
169 
170 	sc = device_get_softc(dev);
171 	sc->dev = dev;
172 	sc->quirks = bhnd_device_quirks(dev, chipc_devices,
173 	    sizeof(chipc_devices[0]));
174 	sc->sprom_refcnt = 0;
175 
176 	CHIPC_LOCK_INIT(sc);
177 	STAILQ_INIT(&sc->mem_regions);
178 
179 	/* Set up resource management */
180 	if ((error = chipc_init_rman(sc))) {
181 		device_printf(sc->dev,
182 		    "failed to initialize chipc resource state: %d\n", error);
183 		goto failed;
184 	}
185 
186 	/* Allocate the region containing the chipc register block */
187 	if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) {
188 		error = ENXIO;
189 		goto failed;
190 	}
191 
192 	error = chipc_retain_region(sc, sc->core_region,
193 	    RF_ALLOCATED|RF_ACTIVE);
194 	if (error) {
195 		sc->core_region = NULL;
196 		goto failed;
197 	}
198 
199 	/* Save a direct reference to our chipc registers */
200 	sc->core = sc->core_region->cr_res;
201 
202 	/* Fetch and parse capability register(s) */
203 	if ((error = chipc_read_caps(sc, &sc->caps)))
204 		goto failed;
205 
206 	if (bootverbose)
207 		chipc_print_caps(sc->dev, &sc->caps);
208 
209 	/* Attach all supported child devices */
210 	if ((error = chipc_add_children(sc)))
211 		goto failed;
212 
213 	/*
214 	 * Register ourselves with the bus; we're fully initialized and can
215 	 * response to ChipCommin API requests.
216 	 *
217 	 * Since our children may need access to ChipCommon, this must be done
218 	 * before attaching our children below (via bus_generic_attach).
219 	 */
220 	if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC)))
221 		goto failed;
222 
223 	if ((error = bus_generic_attach(dev)))
224 		goto failed;
225 
226 	return (0);
227 
228 failed:
229 	device_delete_children(sc->dev);
230 
231 	if (sc->core_region != NULL) {
232 		chipc_release_region(sc, sc->core_region,
233 		    RF_ALLOCATED|RF_ACTIVE);
234 	}
235 
236 	chipc_free_rman(sc);
237 	CHIPC_LOCK_DESTROY(sc);
238 	return (error);
239 }
240 
241 static int
242 chipc_detach(device_t dev)
243 {
244 	struct chipc_softc	*sc;
245 	int			 error;
246 
247 	sc = device_get_softc(dev);
248 
249 	if ((error = bus_generic_detach(dev)))
250 		return (error);
251 
252 	if ((error = device_delete_children(dev)))
253 		return (error);
254 
255 	if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY)))
256 		return (error);
257 
258 	chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE);
259 	chipc_free_rman(sc);
260 
261 	CHIPC_LOCK_DESTROY(sc);
262 
263 	return (0);
264 }
265 
266 static int
267 chipc_add_children(struct chipc_softc *sc)
268 {
269 	device_t	 child;
270 	const char	*flash_bus;
271 	int		 error;
272 
273 	/* SPROM/OTP */
274 	if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM ||
275 	    sc->caps.nvram_src == BHND_NVRAM_SRC_OTP)
276 	{
277 		child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1);
278 		if (child == NULL) {
279 			device_printf(sc->dev, "failed to add nvram device\n");
280 			return (ENXIO);
281 		}
282 
283 		/* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */
284 		error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP,
285 		    CHIPC_SPROM_OTP_SIZE, 0, 0);
286 		if (error) {
287 			device_printf(sc->dev, "failed to set OTP memory "
288 			    "resource: %d\n", error);
289 			return (error);
290 		}
291 	}
292 
293 	/*
294 	 * PMU/PWR_CTRL
295 	 *
296 	 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is
297 	 * attached directly to the bhnd(4) bus -- not chipc.
298 	 */
299 	if (sc->caps.pmu && !sc->caps.aob) {
300 		child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1);
301 		if (child == NULL) {
302 			device_printf(sc->dev, "failed to add pmu\n");
303 			return (ENXIO);
304 		}
305 	} else if (sc->caps.pwr_ctrl) {
306 		child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1);
307 		if (child == NULL) {
308 			device_printf(sc->dev, "failed to add pwrctl\n");
309 			return (ENXIO);
310 		}
311 	}
312 
313 	/* GPIO */
314 	child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1);
315 	if (child == NULL) {
316 		device_printf(sc->dev, "failed to add gpio\n");
317 		return (ENXIO);
318 	}
319 
320 	error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0);
321 	if (error) {
322 		device_printf(sc->dev, "failed to set gpio memory resource: "
323 		    "%d\n", error);
324 		return (error);
325 	}
326 
327 	/* All remaining devices are SoC-only */
328 	if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE)
329 		return (0);
330 
331 	/* UARTs */
332 	for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) {
333 		int irq_rid, mem_rid;
334 
335 		irq_rid = 0;
336 		mem_rid = 0;
337 
338 		child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1);
339 		if (child == NULL) {
340 			device_printf(sc->dev, "failed to add uart%u\n", i);
341 			return (ENXIO);
342 		}
343 
344 		/* Shared IRQ */
345 		error = chipc_set_irq_resource(sc, child, irq_rid, 0);
346 		if (error) {
347 			device_printf(sc->dev, "failed to set uart%u irq %u\n",
348 			    i, 0);
349 			return (error);
350 		}
351 
352 		/* UART registers are mapped sequentially */
353 		error = chipc_set_mem_resource(sc, child, mem_rid,
354 		    CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0);
355 		if (error) {
356 			device_printf(sc->dev, "failed to set uart%u memory "
357 			    "resource: %d\n", i, error);
358 			return (error);
359 		}
360 	}
361 
362 	/* Flash */
363 	flash_bus = chipc_flash_bus_name(sc->caps.flash_type);
364 	if (flash_bus != NULL) {
365 		int rid;
366 
367 		child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1);
368 		if (child == NULL) {
369 			device_printf(sc->dev, "failed to add %s device\n",
370 			    flash_bus);
371 			return (ENXIO);
372 		}
373 
374 		/* flash memory mapping */
375 		rid = 0;
376 		error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1,
377 		    1);
378 		if (error) {
379 			device_printf(sc->dev, "failed to set flash memory "
380 			    "resource %d: %d\n", rid, error);
381 			return (error);
382 		}
383 
384 		/* flashctrl registers */
385 		rid++;
386 		error = chipc_set_mem_resource(sc, child, rid,
387 		    CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0);
388 		if (error) {
389 			device_printf(sc->dev, "failed to set flash memory "
390 			    "resource %d: %d\n", rid, error);
391 			return (error);
392 		}
393 	}
394 
395 	return (0);
396 }
397 
398 /**
399  * Determine the NVRAM data source for this device.
400  *
401  * The SPROM, OTP, and flash capability flags must be fully populated in
402  * @p caps.
403  *
404  * @param sc chipc driver state.
405  * @param caps capability flags to be used to derive NVRAM configuration.
406  */
407 static bhnd_nvram_src
408 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps)
409 {
410 	uint32_t		 otp_st, srom_ctrl;
411 
412 	/*
413 	 * We check for hardware presence in order of precedence. For example,
414 	 * SPROM is is always used in preference to internal OTP if found.
415 	 */
416 	if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) {
417 		srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL);
418 		if (srom_ctrl & CHIPC_SRC_PRESENT)
419 			return (BHND_NVRAM_SRC_SPROM);
420 	}
421 
422 	/* Check for programmed OTP H/W subregion (contains SROM data) */
423 	if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) {
424 		/* TODO: need access to HND-OTP device */
425 		if (!CHIPC_QUIRK(sc, OTP_HND)) {
426 			device_printf(sc->dev,
427 			    "NVRAM unavailable: unsupported OTP controller.\n");
428 			return (BHND_NVRAM_SRC_UNKNOWN);
429 		}
430 
431 		otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST);
432 		if (otp_st & CHIPC_OTPS_GUP_HW)
433 			return (BHND_NVRAM_SRC_OTP);
434 	}
435 
436 	/* Check for flash */
437 	if (caps->flash_type != CHIPC_FLASH_NONE)
438 		return (BHND_NVRAM_SRC_FLASH);
439 
440 	/* No NVRAM hardware capability declared */
441 	return (BHND_NVRAM_SRC_UNKNOWN);
442 }
443 
444 /* Read and parse chipc capabilities */
445 static int
446 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps)
447 {
448 	uint32_t	cap_reg;
449 	uint32_t	cap_ext_reg;
450 	uint32_t	regval;
451 
452 	/* Fetch cap registers */
453 	cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES);
454 	cap_ext_reg = 0;
455 	if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT))
456 		cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT);
457 
458 	/* Extract values */
459 	caps->num_uarts		= CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART);
460 	caps->mipseb		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB);
461 	caps->uart_gpio		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO);
462 	caps->uart_clock	= CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL);
463 
464 	caps->extbus_type	= CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS);
465 	caps->pwr_ctrl		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL);
466 	caps->jtag_master	= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP);
467 
468 	caps->pll_type		= CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL);
469 	caps->backplane_64	= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64);
470 	caps->boot_rom		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM);
471 	caps->pmu		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU);
472 	caps->eci		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI);
473 	caps->sprom		= CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM);
474 	caps->otp_size		= CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE);
475 
476 	caps->seci		= CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI);
477 	caps->gsio		= CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO);
478 	caps->aob		= CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB);
479 
480 	/* Fetch OTP size for later IPX controller revisions */
481 	if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) {
482 		regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
483 		caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE);
484 	}
485 
486 	/* Determine flash type and parameters */
487 	caps->cfi_width = 0;
488 	switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) {
489 	case CHIPC_CAP_SFLASH_ST:
490 		caps->flash_type = CHIPC_SFLASH_ST;
491 		break;
492 	case CHIPC_CAP_SFLASH_AT:
493 		caps->flash_type = CHIPC_SFLASH_AT;
494 		break;
495 	case CHIPC_CAP_NFLASH:
496 		/* unimplemented */
497 		caps->flash_type = CHIPC_NFLASH;
498 		break;
499 	case CHIPC_CAP_PFLASH:
500 		caps->flash_type = CHIPC_PFLASH_CFI;
501 
502 		/* determine cfi width */
503 		regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG);
504 		if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS))
505 			caps->cfi_width = 2;
506 		else
507 			caps->cfi_width = 1;
508 
509 		break;
510 	case CHIPC_CAP_FLASH_NONE:
511 		caps->flash_type = CHIPC_FLASH_NONE;
512 		break;
513 
514 	}
515 
516 	/* Handle 4706_NFLASH fallback */
517 	if (CHIPC_QUIRK(sc, 4706_NFLASH) &&
518 	    CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH))
519 	{
520 		caps->flash_type = CHIPC_NFLASH_4706;
521 	}
522 
523 	/* Determine NVRAM source. Must occur after the SPROM/OTP/flash
524 	 * capability flags have been populated. */
525 	caps->nvram_src = chipc_find_nvram_src(sc, caps);
526 
527 	/* Determine the SPROM offset within OTP (if any). SPROM-formatted
528 	 * data is placed within the OTP general use region. */
529 	caps->sprom_offset = 0;
530 	if (caps->nvram_src == BHND_NVRAM_SRC_OTP) {
531 		CHIPC_ASSERT_QUIRK(sc, OTP_IPX);
532 
533 		/* Bit offset to GUP HW subregion containing SPROM data */
534 		regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT);
535 		caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP);
536 
537 		/* Convert to bytes */
538 		caps->sprom_offset /= 8;
539 	}
540 
541 	return (0);
542 }
543 
544 static int
545 chipc_suspend(device_t dev)
546 {
547 	return (bus_generic_suspend(dev));
548 }
549 
550 static int
551 chipc_resume(device_t dev)
552 {
553 	return (bus_generic_resume(dev));
554 }
555 
556 static void
557 chipc_probe_nomatch(device_t dev, device_t child)
558 {
559 	struct resource_list	*rl;
560 	const char		*name;
561 
562 	name = device_get_name(child);
563 	if (name == NULL)
564 		name = "unknown device";
565 
566 	device_printf(dev, "<%s> at", name);
567 
568 	rl = BUS_GET_RESOURCE_LIST(dev, child);
569 	if (rl != NULL) {
570 		resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx");
571 		resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd");
572 	}
573 
574 	printf(" (no driver attached)\n");
575 }
576 
577 static int
578 chipc_print_child(device_t dev, device_t child)
579 {
580 	struct resource_list	*rl;
581 	int			 retval = 0;
582 
583 	retval += bus_print_child_header(dev, child);
584 
585 	rl = BUS_GET_RESOURCE_LIST(dev, child);
586 	if (rl != NULL) {
587 		retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY,
588 		    "%#jx");
589 		retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ,
590 		    "%jd");
591 	}
592 
593 	retval += bus_print_child_domain(dev, child);
594 	retval += bus_print_child_footer(dev, child);
595 
596 	return (retval);
597 }
598 
599 static int
600 chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf,
601     size_t buflen)
602 {
603 	if (buflen == 0)
604 		return (EOVERFLOW);
605 
606 	*buf = '\0';
607 	return (0);
608 }
609 
610 static int
611 chipc_child_location_str(device_t dev, device_t child, char *buf,
612     size_t buflen)
613 {
614 	if (buflen == 0)
615 		return (EOVERFLOW);
616 
617 	*buf = '\0';
618 	return (ENXIO);
619 }
620 
621 static device_t
622 chipc_add_child(device_t dev, u_int order, const char *name, int unit)
623 {
624 	struct chipc_softc	*sc;
625 	struct chipc_devinfo	*dinfo;
626 	device_t		 child;
627 
628 	sc = device_get_softc(dev);
629 
630 	child = device_add_child_ordered(dev, order, name, unit);
631 	if (child == NULL)
632 		return (NULL);
633 
634 	dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT);
635 	if (dinfo == NULL) {
636 		device_delete_child(dev, child);
637 		return (NULL);
638 	}
639 
640 	resource_list_init(&dinfo->resources);
641 	dinfo->irq_mapped = false;
642 	device_set_ivars(child, dinfo);
643 
644 	return (child);
645 }
646 
647 static void
648 chipc_child_deleted(device_t dev, device_t child)
649 {
650 	struct chipc_devinfo *dinfo = device_get_ivars(child);
651 
652 	if (dinfo != NULL) {
653 		/* Free the child's resource list */
654 		resource_list_free(&dinfo->resources);
655 
656 		/* Unmap the child's IRQ */
657 		if (dinfo->irq_mapped) {
658 			bhnd_unmap_intr(dev, dinfo->irq);
659 			dinfo->irq_mapped = false;
660 		}
661 
662 		free(dinfo, M_BHND);
663 	}
664 
665 	device_set_ivars(child, NULL);
666 }
667 
668 static struct resource_list *
669 chipc_get_resource_list(device_t dev, device_t child)
670 {
671 	struct chipc_devinfo *dinfo = device_get_ivars(child);
672 	return (&dinfo->resources);
673 }
674 
675 /* Allocate region records for the given port, and add the port's memory
676  * range to the mem_rman */
677 static int
678 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type,
679     u_int port)
680 {
681 	struct	chipc_region	*cr;
682 	rman_res_t		 start, end;
683 	u_int			 num_regions;
684 	int			 error;
685 
686 	num_regions = bhnd_get_region_count(sc->dev, type, port);
687 	for (u_int region = 0; region < num_regions; region++) {
688 		/* Allocate new region record */
689 		cr = chipc_alloc_region(sc, type, port, region);
690 		if (cr == NULL)
691 			return (ENODEV);
692 
693 		/* Can't manage regions that cannot be allocated */
694 		if (cr->cr_rid < 0) {
695 			BHND_DEBUG_DEV(sc->dev, "no rid for chipc region "
696 			    "%s%u.%u", bhnd_port_type_name(type), port, region);
697 			chipc_free_region(sc, cr);
698 			continue;
699 		}
700 
701 		/* Add to rman's managed range */
702 		start = cr->cr_addr;
703 		end = cr->cr_end;
704 		if ((error = rman_manage_region(&sc->mem_rman, start, end))) {
705 			chipc_free_region(sc, cr);
706 			return (error);
707 		}
708 
709 		/* Add to region list */
710 		STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link);
711 	}
712 
713 	return (0);
714 }
715 
716 /* Initialize memory state for all chipc port regions */
717 static int
718 chipc_init_rman(struct chipc_softc *sc)
719 {
720 	u_int	num_ports;
721 	int	error;
722 
723 	/* Port types for which we'll register chipc_region mappings */
724 	bhnd_port_type types[] = {
725 	    BHND_PORT_DEVICE
726 	};
727 
728 	/* Initialize resource manager */
729 	sc->mem_rman.rm_start = 0;
730 	sc->mem_rman.rm_end = BUS_SPACE_MAXADDR;
731 	sc->mem_rman.rm_type = RMAN_ARRAY;
732 	sc->mem_rman.rm_descr = "ChipCommon Device Memory";
733 	if ((error = rman_init(&sc->mem_rman))) {
734 		device_printf(sc->dev, "could not initialize mem_rman: %d\n",
735 		    error);
736 		return (error);
737 	}
738 
739 	/* Populate per-port-region state */
740 	for (u_int i = 0; i < nitems(types); i++) {
741 		num_ports = bhnd_get_port_count(sc->dev, types[i]);
742 		for (u_int port = 0; port < num_ports; port++) {
743 			error = chipc_rman_init_regions(sc, types[i], port);
744 			if (error) {
745 				device_printf(sc->dev,
746 				    "region init failed for %s%u: %d\n",
747 				     bhnd_port_type_name(types[i]), port,
748 				     error);
749 
750 				goto failed;
751 			}
752 		}
753 	}
754 
755 	return (0);
756 
757 failed:
758 	chipc_free_rman(sc);
759 	return (error);
760 }
761 
762 /* Free memory management state */
763 static void
764 chipc_free_rman(struct chipc_softc *sc)
765 {
766 	struct chipc_region *cr, *cr_next;
767 
768 	STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next)
769 		chipc_free_region(sc, cr);
770 
771 	rman_fini(&sc->mem_rman);
772 }
773 
774 /**
775  * Return the rman instance for a given resource @p type, if any.
776  *
777  * @param sc The chipc device state.
778  * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...)
779  */
780 static struct rman *
781 chipc_get_rman(struct chipc_softc *sc, int type)
782 {
783 	switch (type) {
784 	case SYS_RES_MEMORY:
785 		return (&sc->mem_rman);
786 
787 	case SYS_RES_IRQ:
788 		/* We delegate IRQ resource management to the parent bus */
789 		return (NULL);
790 
791 	default:
792 		return (NULL);
793 	};
794 }
795 
796 static struct resource *
797 chipc_alloc_resource(device_t dev, device_t child, int type,
798     int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
799 {
800 	struct chipc_softc		*sc;
801 	struct chipc_region		*cr;
802 	struct resource_list_entry	*rle;
803 	struct resource			*rv;
804 	struct rman			*rm;
805 	int				 error;
806 	bool				 passthrough, isdefault;
807 
808 	sc = device_get_softc(dev);
809 	passthrough = (device_get_parent(child) != dev);
810 	isdefault = RMAN_IS_DEFAULT_RANGE(start, end);
811 	rle = NULL;
812 
813 	/* Fetch the resource manager, delegate request if necessary */
814 	rm = chipc_get_rman(sc, type);
815 	if (rm == NULL) {
816 		/* Requested resource type is delegated to our parent */
817 		rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
818 		    start, end, count, flags);
819 		return (rv);
820 	}
821 
822 	/* Populate defaults */
823 	if (!passthrough && isdefault) {
824 		/* Fetch the resource list entry. */
825 		rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child),
826 		    type, *rid);
827 		if (rle == NULL) {
828 			device_printf(dev,
829 			    "default resource %#x type %d for child %s "
830 			    "not found\n", *rid, type,
831 			    device_get_nameunit(child));
832 			return (NULL);
833 		}
834 
835 		if (rle->res != NULL) {
836 			device_printf(dev,
837 			    "resource entry %#x type %d for child %s is busy "
838 			    "[%d]\n",
839 			    *rid, type, device_get_nameunit(child),
840 			    rman_get_flags(rle->res));
841 
842 			return (NULL);
843 		}
844 
845 		start = rle->start;
846 		end = rle->end;
847 		count = ulmax(count, rle->count);
848 	}
849 
850 	/* Locate a mapping region */
851 	if ((cr = chipc_find_region(sc, start, end)) == NULL) {
852 		/* Resource requests outside our shared port regions can be
853 		 * delegated to our parent. */
854 		rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
855 		    start, end, count, flags);
856 		return (rv);
857 	}
858 
859 	/*
860 	 * As a special case, children that map the complete ChipCommon register
861 	 * block are delegated to our parent.
862 	 *
863 	 * The rman API does not support sharing resources that are not
864 	 * identical in size; since we allocate subregions to various children,
865 	 * any children that need to map the entire register block (e.g. because
866 	 * they require access to discontiguous register ranges) must make the
867 	 * allocation through our parent, where we hold a compatible
868 	 * RF_SHAREABLE allocation.
869 	 */
870 	if (cr == sc->core_region && cr->cr_addr == start &&
871 	    cr->cr_end == end && cr->cr_count == count)
872 	{
873 		rv = bus_generic_rl_alloc_resource(dev, child, type, rid,
874 		    start, end, count, flags);
875 		return (rv);
876 	}
877 
878 	/* Try to retain a region reference */
879 	if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED)))
880 		return (NULL);
881 
882 	/* Make our rman reservation */
883 	rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE,
884 	    child);
885 	if (rv == NULL) {
886 		chipc_release_region(sc, cr, RF_ALLOCATED);
887 		return (NULL);
888 	}
889 
890 	rman_set_rid(rv, *rid);
891 
892 	/* Activate */
893 	if (flags & RF_ACTIVE) {
894 		error = bus_activate_resource(child, type, *rid, rv);
895 		if (error) {
896 			device_printf(dev,
897 			    "failed to activate entry %#x type %d for "
898 				"child %s: %d\n",
899 			     *rid, type, device_get_nameunit(child), error);
900 
901 			chipc_release_region(sc, cr, RF_ALLOCATED);
902 			rman_release_resource(rv);
903 
904 			return (NULL);
905 		}
906 	}
907 
908 	/* Update child's resource list entry */
909 	if (rle != NULL) {
910 		rle->res = rv;
911 		rle->start = rman_get_start(rv);
912 		rle->end = rman_get_end(rv);
913 		rle->count = rman_get_size(rv);
914 	}
915 
916 	return (rv);
917 }
918 
919 static int
920 chipc_release_resource(device_t dev, device_t child, int type, int rid,
921     struct resource *r)
922 {
923 	struct chipc_softc		*sc;
924 	struct chipc_region		*cr;
925 	struct rman			*rm;
926 	struct resource_list_entry	*rle;
927 	int			 	 error;
928 
929 	sc = device_get_softc(dev);
930 
931 	/* Handled by parent bus? */
932 	rm = chipc_get_rman(sc, type);
933 	if (rm == NULL || !rman_is_region_manager(r, rm)) {
934 		return (bus_generic_rl_release_resource(dev, child, type, rid,
935 		    r));
936 	}
937 
938 	/* Locate the mapping region */
939 	cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
940 	if (cr == NULL)
941 		return (EINVAL);
942 
943 	/* Deactivate resources */
944 	if (rman_get_flags(r) & RF_ACTIVE) {
945 		error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r);
946 		if (error)
947 			return (error);
948 	}
949 
950 	if ((error = rman_release_resource(r)))
951 		return (error);
952 
953 	/* Drop allocation reference */
954 	chipc_release_region(sc, cr, RF_ALLOCATED);
955 
956 	/* Clear reference from the resource list entry if exists */
957 	rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid);
958 	if (rle != NULL)
959 		rle->res = NULL;
960 
961 	return (0);
962 }
963 
964 static int
965 chipc_adjust_resource(device_t dev, device_t child, int type,
966     struct resource *r, rman_res_t start, rman_res_t end)
967 {
968 	struct chipc_softc		*sc;
969 	struct chipc_region		*cr;
970 	struct rman			*rm;
971 
972 	sc = device_get_softc(dev);
973 
974 	/* Handled by parent bus? */
975 	rm = chipc_get_rman(sc, type);
976 	if (rm == NULL || !rman_is_region_manager(r, rm)) {
977 		return (bus_generic_adjust_resource(dev, child, type, r, start,
978 		    end));
979 	}
980 
981 	/* The range is limited to the existing region mapping */
982 	cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
983 	if (cr == NULL)
984 		return (EINVAL);
985 
986 	if (end <= start)
987 		return (EINVAL);
988 
989 	if (start < cr->cr_addr || end > cr->cr_end)
990 		return (EINVAL);
991 
992 	/* Range falls within the existing region */
993 	return (rman_adjust_resource(r, start, end));
994 }
995 
996 /**
997  * Retain an RF_ACTIVE reference to the region mapping @p r, and
998  * configure @p r with its subregion values.
999  *
1000  * @param sc Driver instance state.
1001  * @param child Requesting child device.
1002  * @param type resource type of @p r.
1003  * @param rid resource id of @p r
1004  * @param r resource to be activated.
1005  * @param req_direct If true, failure to allocate a direct bhnd resource
1006  * will be treated as an error. If false, the resource will not be marked
1007  * as RF_ACTIVE if bhnd direct resource allocation fails.
1008  */
1009 static int
1010 chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type,
1011     int rid, struct resource *r, bool req_direct)
1012 {
1013 	struct rman		*rm;
1014 	struct chipc_region	*cr;
1015 	bhnd_size_t		 cr_offset;
1016 	rman_res_t		 r_start, r_end, r_size;
1017 	int			 error;
1018 
1019 	rm = chipc_get_rman(sc, type);
1020 	if (rm == NULL || !rman_is_region_manager(r, rm))
1021 		return (EINVAL);
1022 
1023 	r_start = rman_get_start(r);
1024 	r_end = rman_get_end(r);
1025 	r_size = rman_get_size(r);
1026 
1027 	/* Find the corresponding chipc region */
1028 	cr = chipc_find_region(sc, r_start, r_end);
1029 	if (cr == NULL)
1030 		return (EINVAL);
1031 
1032 	/* Calculate subregion offset within the chipc region */
1033 	cr_offset = r_start - cr->cr_addr;
1034 
1035 	/* Retain (and activate, if necessary) the chipc region */
1036 	if ((error = chipc_retain_region(sc, cr, RF_ACTIVE)))
1037 		return (error);
1038 
1039 	/* Configure child resource with its subregion values. */
1040 	if (cr->cr_res->direct) {
1041 		error = chipc_init_child_resource(r, cr->cr_res->res,
1042 		    cr_offset, r_size);
1043 		if (error)
1044 			goto cleanup;
1045 
1046 		/* Mark active */
1047 		if ((error = rman_activate_resource(r)))
1048 			goto cleanup;
1049 	} else if (req_direct) {
1050 		error = ENOMEM;
1051 		goto cleanup;
1052 	}
1053 
1054 	return (0);
1055 
1056 cleanup:
1057 	chipc_release_region(sc, cr, RF_ACTIVE);
1058 	return (error);
1059 }
1060 
1061 static int
1062 chipc_activate_bhnd_resource(device_t dev, device_t child, int type,
1063     int rid, struct bhnd_resource *r)
1064 {
1065 	struct chipc_softc	*sc;
1066 	struct rman		*rm;
1067 	int			 error;
1068 
1069 	sc = device_get_softc(dev);
1070 
1071 	/* Delegate non-locally managed resources to parent */
1072 	rm = chipc_get_rman(sc, type);
1073 	if (rm == NULL || !rman_is_region_manager(r->res, rm)) {
1074 		return (bhnd_bus_generic_activate_resource(dev, child, type,
1075 		    rid, r));
1076 	}
1077 
1078 	/* Try activating the chipc region resource */
1079 	error = chipc_try_activate_resource(sc, child, type, rid, r->res,
1080 	    false);
1081 	if (error)
1082 		return (error);
1083 
1084 	/* Mark the child resource as direct according to the returned resource
1085 	 * state */
1086 	if (rman_get_flags(r->res) & RF_ACTIVE)
1087 		r->direct = true;
1088 
1089 	return (0);
1090 }
1091 
1092 static int
1093 chipc_activate_resource(device_t dev, device_t child, int type, int rid,
1094     struct resource *r)
1095 {
1096 	struct chipc_softc	*sc;
1097 	struct rman		*rm;
1098 
1099 	sc = device_get_softc(dev);
1100 
1101 	/* Delegate non-locally managed resources to parent */
1102 	rm = chipc_get_rman(sc, type);
1103 	if (rm == NULL || !rman_is_region_manager(r, rm)) {
1104 		return (bus_generic_activate_resource(dev, child, type, rid,
1105 		    r));
1106 	}
1107 
1108 	/* Try activating the chipc region-based resource */
1109 	return (chipc_try_activate_resource(sc, child, type, rid, r, true));
1110 }
1111 
1112 /**
1113  * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE().
1114  */
1115 static int
1116 chipc_deactivate_resource(device_t dev, device_t child, int type,
1117     int rid, struct resource *r)
1118 {
1119 	struct chipc_softc	*sc;
1120 	struct chipc_region	*cr;
1121 	struct rman		*rm;
1122 	int			 error;
1123 
1124 	sc = device_get_softc(dev);
1125 
1126 	/* Handled by parent bus? */
1127 	rm = chipc_get_rman(sc, type);
1128 	if (rm == NULL || !rman_is_region_manager(r, rm)) {
1129 		return (bus_generic_deactivate_resource(dev, child, type, rid,
1130 		    r));
1131 	}
1132 
1133 	/* Find the corresponding chipc region */
1134 	cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r));
1135 	if (cr == NULL)
1136 		return (EINVAL);
1137 
1138 	/* Mark inactive */
1139 	if ((error = rman_deactivate_resource(r)))
1140 		return (error);
1141 
1142 	/* Drop associated RF_ACTIVE reference */
1143 	chipc_release_region(sc, cr, RF_ACTIVE);
1144 
1145 	return (0);
1146 }
1147 
1148 /**
1149  * Examine bus state and make a best effort determination of whether it's
1150  * likely safe to enable the muxed SPROM pins.
1151  *
1152  * On devices that do not use SPROM pin muxing, always returns true.
1153  *
1154  * @param sc chipc driver state.
1155  */
1156 static bool
1157 chipc_should_enable_muxed_sprom(struct chipc_softc *sc)
1158 {
1159 	device_t	*devs;
1160 	device_t	 hostb;
1161 	device_t	 parent;
1162 	int		 devcount;
1163 	int		 error;
1164 	bool		 result;
1165 
1166 	/* Nothing to do? */
1167 	if (!CHIPC_QUIRK(sc, MUX_SPROM))
1168 		return (true);
1169 
1170 	mtx_lock(&Giant);	/* for newbus */
1171 
1172 	parent = device_get_parent(sc->dev);
1173 	hostb = bhnd_bus_find_hostb_device(parent);
1174 
1175 	if ((error = device_get_children(parent, &devs, &devcount))) {
1176 		mtx_unlock(&Giant);
1177 		return (false);
1178 	}
1179 
1180 	/* Reject any active devices other than ChipCommon, or the
1181 	 * host bridge (if any). */
1182 	result = true;
1183 	for (int i = 0; i < devcount; i++) {
1184 		if (devs[i] == hostb || devs[i] == sc->dev)
1185 			continue;
1186 
1187 		if (!device_is_attached(devs[i]))
1188 			continue;
1189 
1190 		if (device_is_suspended(devs[i]))
1191 			continue;
1192 
1193 		/* Active device; assume SPROM is busy */
1194 		result = false;
1195 		break;
1196 	}
1197 
1198 	free(devs, M_TEMP);
1199 	mtx_unlock(&Giant);
1200 	return (result);
1201 }
1202 
1203 static int
1204 chipc_enable_sprom(device_t dev)
1205 {
1206 	struct chipc_softc	*sc;
1207 	int			 error;
1208 
1209 	sc = device_get_softc(dev);
1210 	CHIPC_LOCK(sc);
1211 
1212 	/* Already enabled? */
1213 	if (sc->sprom_refcnt >= 1) {
1214 		sc->sprom_refcnt++;
1215 		CHIPC_UNLOCK(sc);
1216 
1217 		return (0);
1218 	}
1219 
1220 	switch (sc->caps.nvram_src) {
1221 	case BHND_NVRAM_SRC_SPROM:
1222 		error = chipc_enable_sprom_pins(sc);
1223 		break;
1224 	case BHND_NVRAM_SRC_OTP:
1225 		error = chipc_enable_otp_power(sc);
1226 		break;
1227 	default:
1228 		error = 0;
1229 		break;
1230 	}
1231 
1232 	/* Bump the reference count */
1233 	if (error == 0)
1234 		sc->sprom_refcnt++;
1235 
1236 	CHIPC_UNLOCK(sc);
1237 	return (error);
1238 }
1239 
1240 static void
1241 chipc_disable_sprom(device_t dev)
1242 {
1243 	struct chipc_softc	*sc;
1244 
1245 	sc = device_get_softc(dev);
1246 	CHIPC_LOCK(sc);
1247 
1248 	/* Check reference count, skip disable if in-use. */
1249 	KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease"));
1250 	sc->sprom_refcnt--;
1251 	if (sc->sprom_refcnt > 0) {
1252 		CHIPC_UNLOCK(sc);
1253 		return;
1254 	}
1255 
1256 	switch (sc->caps.nvram_src) {
1257 	case BHND_NVRAM_SRC_SPROM:
1258 		chipc_disable_sprom_pins(sc);
1259 		break;
1260 	case BHND_NVRAM_SRC_OTP:
1261 		chipc_disable_otp_power(sc);
1262 		break;
1263 	default:
1264 		break;
1265 	}
1266 
1267 	CHIPC_UNLOCK(sc);
1268 }
1269 
1270 static int
1271 chipc_enable_otp_power(struct chipc_softc *sc)
1272 {
1273 	// TODO: Enable OTP resource via PMU, and wait up to 100 usec for
1274 	// OTPS_READY to be set in `optstatus`.
1275 	return (0);
1276 }
1277 
1278 static void
1279 chipc_disable_otp_power(struct chipc_softc *sc)
1280 {
1281 	// TODO: Disable OTP resource via PMU
1282 }
1283 
1284 /**
1285  * If required by this device, enable access to the SPROM.
1286  *
1287  * @param sc chipc driver state.
1288  */
1289 static int
1290 chipc_enable_sprom_pins(struct chipc_softc *sc)
1291 {
1292 	uint32_t		 cctrl;
1293 
1294 	CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1295 	KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled"));
1296 
1297 	/* Nothing to do? */
1298 	if (!CHIPC_QUIRK(sc, MUX_SPROM))
1299 		return (0);
1300 
1301 	/* Check whether bus is busy */
1302 	if (!chipc_should_enable_muxed_sprom(sc))
1303 		return (EBUSY);
1304 
1305 	cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1306 
1307 	/* 4331 devices */
1308 	if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1309 		cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN;
1310 
1311 		if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1312 			cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1313 
1314 		if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1315 			cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2;
1316 
1317 		bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1318 		return (0);
1319 	}
1320 
1321 	/* 4360 devices */
1322 	if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1323 		/* Unimplemented */
1324 	}
1325 
1326 	/* Refuse to proceed on unsupported devices with muxed SPROM pins */
1327 	device_printf(sc->dev, "muxed sprom lines on unrecognized device\n");
1328 	return (ENXIO);
1329 }
1330 
1331 /**
1332  * If required by this device, revert any GPIO/pin configuration applied
1333  * to allow SPROM access.
1334  *
1335  * @param sc chipc driver state.
1336  */
1337 static void
1338 chipc_disable_sprom_pins(struct chipc_softc *sc)
1339 {
1340 	uint32_t		 cctrl;
1341 
1342 	/* Nothing to do? */
1343 	if (!CHIPC_QUIRK(sc, MUX_SPROM))
1344 		return;
1345 
1346 	CHIPC_LOCK_ASSERT(sc, MA_OWNED);
1347 	KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use"));
1348 
1349 	cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1350 
1351 	/* 4331 devices */
1352 	if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) {
1353 		cctrl |= CHIPC_CCTRL4331_EXTPA_EN;
1354 
1355 		if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM))
1356 			cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5;
1357 
1358 		if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM))
1359 			cctrl |= CHIPC_CCTRL4331_EXTPA_EN2;
1360 
1361 		bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1362 		return;
1363 	}
1364 
1365 	/* 4360 devices */
1366 	if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) {
1367 		/* Unimplemented */
1368 	}
1369 }
1370 
1371 static uint32_t
1372 chipc_read_chipst(device_t dev)
1373 {
1374 	struct chipc_softc *sc = device_get_softc(dev);
1375 	return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST));
1376 }
1377 
1378 static void
1379 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask)
1380 {
1381 	struct chipc_softc	*sc;
1382 	uint32_t		 cctrl;
1383 
1384 	sc = device_get_softc(dev);
1385 
1386 	CHIPC_LOCK(sc);
1387 
1388 	cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL);
1389 	cctrl = (cctrl & ~mask) | (value | mask);
1390 	bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl);
1391 
1392 	CHIPC_UNLOCK(sc);
1393 }
1394 
1395 static struct chipc_caps *
1396 chipc_get_caps(device_t dev)
1397 {
1398 	struct chipc_softc	*sc;
1399 
1400 	sc = device_get_softc(dev);
1401 	return (&sc->caps);
1402 }
1403 
1404 static device_method_t chipc_methods[] = {
1405 	/* Device interface */
1406 	DEVMETHOD(device_probe,			chipc_probe),
1407 	DEVMETHOD(device_attach,		chipc_attach),
1408 	DEVMETHOD(device_detach,		chipc_detach),
1409 	DEVMETHOD(device_suspend,		chipc_suspend),
1410 	DEVMETHOD(device_resume,		chipc_resume),
1411 
1412 	/* Bus interface */
1413 	DEVMETHOD(bus_probe_nomatch,		chipc_probe_nomatch),
1414 	DEVMETHOD(bus_print_child,		chipc_print_child),
1415 	DEVMETHOD(bus_child_pnpinfo_str,	chipc_child_pnpinfo_str),
1416 	DEVMETHOD(bus_child_location_str,	chipc_child_location_str),
1417 
1418 	DEVMETHOD(bus_add_child,		chipc_add_child),
1419 	DEVMETHOD(bus_child_deleted,		chipc_child_deleted),
1420 
1421 	DEVMETHOD(bus_set_resource,		bus_generic_rl_set_resource),
1422 	DEVMETHOD(bus_get_resource,		bus_generic_rl_get_resource),
1423 	DEVMETHOD(bus_delete_resource,		bus_generic_rl_delete_resource),
1424 	DEVMETHOD(bus_alloc_resource,		chipc_alloc_resource),
1425 	DEVMETHOD(bus_release_resource,		chipc_release_resource),
1426 	DEVMETHOD(bus_adjust_resource,		chipc_adjust_resource),
1427 	DEVMETHOD(bus_activate_resource,	chipc_activate_resource),
1428 	DEVMETHOD(bus_deactivate_resource,	chipc_deactivate_resource),
1429 	DEVMETHOD(bus_get_resource_list,	chipc_get_resource_list),
1430 
1431 	DEVMETHOD(bus_setup_intr,		bus_generic_setup_intr),
1432 	DEVMETHOD(bus_teardown_intr,		bus_generic_teardown_intr),
1433 	DEVMETHOD(bus_config_intr,		bus_generic_config_intr),
1434 	DEVMETHOD(bus_bind_intr,		bus_generic_bind_intr),
1435 	DEVMETHOD(bus_describe_intr,		bus_generic_describe_intr),
1436 
1437 	/* BHND bus inteface */
1438 	DEVMETHOD(bhnd_bus_activate_resource,	chipc_activate_bhnd_resource),
1439 
1440 	/* ChipCommon interface */
1441 	DEVMETHOD(bhnd_chipc_read_chipst,	chipc_read_chipst),
1442 	DEVMETHOD(bhnd_chipc_write_chipctrl,	chipc_write_chipctrl),
1443 	DEVMETHOD(bhnd_chipc_enable_sprom,	chipc_enable_sprom),
1444 	DEVMETHOD(bhnd_chipc_disable_sprom,	chipc_disable_sprom),
1445 	DEVMETHOD(bhnd_chipc_get_caps,		chipc_get_caps),
1446 
1447 	DEVMETHOD_END
1448 };
1449 
1450 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc));
1451 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0,
1452     BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
1453 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1);
1454 MODULE_VERSION(bhnd_chipc, 1);
1455