1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 6 * Copyright (c) 2017 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Landon Fuller 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 20 * redistribution must be conditioned upon including a substantially 21 * similar Disclaimer requirement for further binary redistribution. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 /* 39 * Broadcom ChipCommon driver. 40 * 41 * With the exception of some very early chipsets, the ChipCommon core 42 * has been included in all HND SoCs and chipsets based on the siba(4) 43 * and bcma(4) interconnects, providing a common interface to chipset 44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 45 * GPIO, flash, etc. 46 */ 47 48 #include <sys/param.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/malloc.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/systm.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <dev/bhnd/bhnd.h> 62 #include <dev/bhnd/bhndvar.h> 63 64 #include "chipcreg.h" 65 #include "chipcvar.h" 66 67 #include "chipc_private.h" 68 69 static struct bhnd_device_quirk chipc_quirks[]; 70 71 /* Supported device identifiers */ 72 static const struct bhnd_device chipc_devices[] = { 73 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 74 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 75 BHND_DEVICE_END 76 }; 77 78 /* Device quirks table */ 79 static struct bhnd_device_quirk chipc_quirks[] = { 80 /* HND OTP controller revisions */ 81 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 82 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 83 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 84 85 /* IPX OTP controller revisions */ 86 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 87 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 88 89 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 90 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 91 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 92 93 /* 4706 variant quirks */ 94 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 95 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 96 97 /* 4331 quirks*/ 98 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 99 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 100 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 101 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 102 103 /* 4360 quirks */ 104 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 105 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 106 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 107 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 108 109 BHND_DEVICE_QUIRK_END 110 }; 111 112 static int chipc_add_children(struct chipc_softc *sc); 113 114 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 115 struct chipc_caps *caps); 116 static int chipc_read_caps(struct chipc_softc *sc, 117 struct chipc_caps *caps); 118 119 static bool chipc_should_enable_muxed_sprom( 120 struct chipc_softc *sc); 121 static int chipc_enable_otp_power(struct chipc_softc *sc); 122 static void chipc_disable_otp_power(struct chipc_softc *sc); 123 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 124 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 125 126 static int chipc_try_activate_resource(device_t dev, 127 device_t child, int type, int rid, 128 struct resource *r, bool req_direct); 129 130 static int chipc_init_rman(struct chipc_softc *sc); 131 static void chipc_free_rman(struct chipc_softc *sc); 132 static struct rman *chipc_get_rman(device_t dev, int type, u_int flags); 133 134 /* quirk and capability flag convenience macros */ 135 #define CHIPC_QUIRK(_sc, _name) \ 136 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 137 138 #define CHIPC_CAP(_sc, _name) \ 139 ((_sc)->caps._name) 140 141 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 142 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 143 144 #define CHIPC_ASSERT_CAP(_sc, name) \ 145 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 146 147 static int 148 chipc_probe(device_t dev) 149 { 150 const struct bhnd_device *id; 151 152 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 153 if (id == NULL) 154 return (ENXIO); 155 156 bhnd_set_default_core_desc(dev); 157 return (BUS_PROBE_DEFAULT); 158 } 159 160 static int 161 chipc_attach(device_t dev) 162 { 163 struct chipc_softc *sc; 164 int error; 165 166 sc = device_get_softc(dev); 167 sc->dev = dev; 168 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 169 sizeof(chipc_devices[0])); 170 sc->sprom_refcnt = 0; 171 172 CHIPC_LOCK_INIT(sc); 173 STAILQ_INIT(&sc->mem_regions); 174 175 /* Set up resource management */ 176 if ((error = chipc_init_rman(sc))) { 177 device_printf(sc->dev, 178 "failed to initialize chipc resource state: %d\n", error); 179 goto failed; 180 } 181 182 /* Allocate the region containing the chipc register block */ 183 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 184 error = ENXIO; 185 goto failed; 186 } 187 188 error = chipc_retain_region(sc, sc->core_region, 189 RF_ALLOCATED|RF_ACTIVE); 190 if (error) { 191 sc->core_region = NULL; 192 goto failed; 193 } 194 195 /* Save a direct reference to our chipc registers */ 196 sc->core = sc->core_region->cr_res; 197 198 /* Fetch and parse capability register(s) */ 199 if ((error = chipc_read_caps(sc, &sc->caps))) 200 goto failed; 201 202 if (bootverbose) 203 chipc_print_caps(sc->dev, &sc->caps); 204 205 /* Attach all supported child devices */ 206 if ((error = chipc_add_children(sc))) 207 goto failed; 208 209 /* 210 * Register ourselves with the bus; we're fully initialized and can 211 * response to ChipCommin API requests. 212 * 213 * Since our children may need access to ChipCommon, this must be done 214 * before attaching our children below (via bus_generic_attach). 215 */ 216 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 217 goto failed; 218 219 if ((error = bus_generic_attach(dev))) 220 goto failed; 221 222 return (0); 223 224 failed: 225 device_delete_children(sc->dev); 226 227 if (sc->core_region != NULL) { 228 chipc_release_region(sc, sc->core_region, 229 RF_ALLOCATED|RF_ACTIVE); 230 } 231 232 chipc_free_rman(sc); 233 CHIPC_LOCK_DESTROY(sc); 234 return (error); 235 } 236 237 static int 238 chipc_detach(device_t dev) 239 { 240 struct chipc_softc *sc; 241 int error; 242 243 sc = device_get_softc(dev); 244 245 if ((error = bus_generic_detach(dev))) 246 return (error); 247 248 if ((error = device_delete_children(dev))) 249 return (error); 250 251 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 252 return (error); 253 254 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 255 chipc_free_rman(sc); 256 257 CHIPC_LOCK_DESTROY(sc); 258 259 return (0); 260 } 261 262 static int 263 chipc_add_children(struct chipc_softc *sc) 264 { 265 device_t child; 266 const char *flash_bus; 267 int error; 268 269 /* SPROM/OTP */ 270 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 271 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 272 { 273 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 274 if (child == NULL) { 275 device_printf(sc->dev, "failed to add nvram device\n"); 276 return (ENXIO); 277 } 278 279 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 280 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 281 CHIPC_SPROM_OTP_SIZE, 0, 0); 282 if (error) { 283 device_printf(sc->dev, "failed to set OTP memory " 284 "resource: %d\n", error); 285 return (error); 286 } 287 } 288 289 /* 290 * PMU/PWR_CTRL 291 * 292 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 293 * attached directly to the bhnd(4) bus -- not chipc. 294 */ 295 if (sc->caps.pmu && !sc->caps.aob) { 296 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 297 if (child == NULL) { 298 device_printf(sc->dev, "failed to add pmu\n"); 299 return (ENXIO); 300 } 301 } else if (sc->caps.pwr_ctrl) { 302 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1); 303 if (child == NULL) { 304 device_printf(sc->dev, "failed to add pwrctl\n"); 305 return (ENXIO); 306 } 307 } 308 309 /* GPIO */ 310 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1); 311 if (child == NULL) { 312 device_printf(sc->dev, "failed to add gpio\n"); 313 return (ENXIO); 314 } 315 316 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0); 317 if (error) { 318 device_printf(sc->dev, "failed to set gpio memory resource: " 319 "%d\n", error); 320 return (error); 321 } 322 323 /* All remaining devices are SoC-only */ 324 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 325 return (0); 326 327 /* UARTs */ 328 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 329 int irq_rid, mem_rid; 330 331 irq_rid = 0; 332 mem_rid = 0; 333 334 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 335 if (child == NULL) { 336 device_printf(sc->dev, "failed to add uart%u\n", i); 337 return (ENXIO); 338 } 339 340 /* Shared IRQ */ 341 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 342 if (error) { 343 device_printf(sc->dev, "failed to set uart%u irq %u\n", 344 i, 0); 345 return (error); 346 } 347 348 /* UART registers are mapped sequentially */ 349 error = chipc_set_mem_resource(sc, child, mem_rid, 350 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 351 if (error) { 352 device_printf(sc->dev, "failed to set uart%u memory " 353 "resource: %d\n", i, error); 354 return (error); 355 } 356 } 357 358 /* Flash */ 359 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 360 if (flash_bus != NULL) { 361 int rid; 362 363 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 364 if (child == NULL) { 365 device_printf(sc->dev, "failed to add %s device\n", 366 flash_bus); 367 return (ENXIO); 368 } 369 370 /* flash memory mapping */ 371 rid = 0; 372 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 373 1); 374 if (error) { 375 device_printf(sc->dev, "failed to set flash memory " 376 "resource %d: %d\n", rid, error); 377 return (error); 378 } 379 380 /* flashctrl registers */ 381 rid++; 382 error = chipc_set_mem_resource(sc, child, rid, 383 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 384 if (error) { 385 device_printf(sc->dev, "failed to set flash memory " 386 "resource %d: %d\n", rid, error); 387 return (error); 388 } 389 } 390 391 return (0); 392 } 393 394 /** 395 * Determine the NVRAM data source for this device. 396 * 397 * The SPROM, OTP, and flash capability flags must be fully populated in 398 * @p caps. 399 * 400 * @param sc chipc driver state. 401 * @param caps capability flags to be used to derive NVRAM configuration. 402 */ 403 static bhnd_nvram_src 404 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 405 { 406 uint32_t otp_st, srom_ctrl; 407 408 /* 409 * We check for hardware presence in order of precedence. For example, 410 * SPROM is always used in preference to internal OTP if found. 411 */ 412 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 413 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 414 if (srom_ctrl & CHIPC_SRC_PRESENT) 415 return (BHND_NVRAM_SRC_SPROM); 416 } 417 418 /* Check for programmed OTP H/W subregion (contains SROM data) */ 419 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 420 /* TODO: need access to HND-OTP device */ 421 if (!CHIPC_QUIRK(sc, OTP_HND)) { 422 device_printf(sc->dev, 423 "NVRAM unavailable: unsupported OTP controller.\n"); 424 return (BHND_NVRAM_SRC_UNKNOWN); 425 } 426 427 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 428 if (otp_st & CHIPC_OTPS_GUP_HW) 429 return (BHND_NVRAM_SRC_OTP); 430 } 431 432 /* Check for flash */ 433 if (caps->flash_type != CHIPC_FLASH_NONE) 434 return (BHND_NVRAM_SRC_FLASH); 435 436 /* No NVRAM hardware capability declared */ 437 return (BHND_NVRAM_SRC_UNKNOWN); 438 } 439 440 /* Read and parse chipc capabilities */ 441 static int 442 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 443 { 444 uint32_t cap_reg; 445 uint32_t cap_ext_reg; 446 uint32_t regval; 447 448 /* Fetch cap registers */ 449 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 450 cap_ext_reg = 0; 451 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 452 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 453 454 /* Extract values */ 455 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 456 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 457 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 458 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 459 460 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 461 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 462 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 463 464 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 465 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 466 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 467 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 468 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 469 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 470 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 471 472 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 473 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 474 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 475 476 /* Fetch OTP size for later IPX controller revisions */ 477 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 478 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 479 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 480 } 481 482 /* Determine flash type and parameters */ 483 caps->cfi_width = 0; 484 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 485 case CHIPC_CAP_SFLASH_ST: 486 caps->flash_type = CHIPC_SFLASH_ST; 487 break; 488 case CHIPC_CAP_SFLASH_AT: 489 caps->flash_type = CHIPC_SFLASH_AT; 490 break; 491 case CHIPC_CAP_NFLASH: 492 /* unimplemented */ 493 caps->flash_type = CHIPC_NFLASH; 494 break; 495 case CHIPC_CAP_PFLASH: 496 caps->flash_type = CHIPC_PFLASH_CFI; 497 498 /* determine cfi width */ 499 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 500 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 501 caps->cfi_width = 2; 502 else 503 caps->cfi_width = 1; 504 505 break; 506 case CHIPC_CAP_FLASH_NONE: 507 caps->flash_type = CHIPC_FLASH_NONE; 508 break; 509 510 } 511 512 /* Handle 4706_NFLASH fallback */ 513 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 514 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 515 { 516 caps->flash_type = CHIPC_NFLASH_4706; 517 } 518 519 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 520 * capability flags have been populated. */ 521 caps->nvram_src = chipc_find_nvram_src(sc, caps); 522 523 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 524 * data is placed within the OTP general use region. */ 525 caps->sprom_offset = 0; 526 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 527 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 528 529 /* Bit offset to GUP HW subregion containing SPROM data */ 530 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 531 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 532 533 /* Convert to bytes */ 534 caps->sprom_offset /= 8; 535 } 536 537 return (0); 538 } 539 540 static int 541 chipc_suspend(device_t dev) 542 { 543 return (bus_generic_suspend(dev)); 544 } 545 546 static int 547 chipc_resume(device_t dev) 548 { 549 return (bus_generic_resume(dev)); 550 } 551 552 static void 553 chipc_probe_nomatch(device_t dev, device_t child) 554 { 555 struct resource_list *rl; 556 const char *name; 557 558 name = device_get_name(child); 559 if (name == NULL) 560 name = "unknown device"; 561 562 device_printf(dev, "<%s> at", name); 563 564 rl = BUS_GET_RESOURCE_LIST(dev, child); 565 if (rl != NULL) { 566 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 567 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 568 } 569 570 printf(" (no driver attached)\n"); 571 } 572 573 static int 574 chipc_print_child(device_t dev, device_t child) 575 { 576 struct resource_list *rl; 577 int retval = 0; 578 579 retval += bus_print_child_header(dev, child); 580 581 rl = BUS_GET_RESOURCE_LIST(dev, child); 582 if (rl != NULL) { 583 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 584 "%#jx"); 585 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 586 "%jd"); 587 } 588 589 retval += bus_print_child_domain(dev, child); 590 retval += bus_print_child_footer(dev, child); 591 592 return (retval); 593 } 594 595 static device_t 596 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 597 { 598 struct chipc_devinfo *dinfo; 599 device_t child; 600 601 child = device_add_child_ordered(dev, order, name, unit); 602 if (child == NULL) 603 return (NULL); 604 605 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 606 if (dinfo == NULL) { 607 device_delete_child(dev, child); 608 return (NULL); 609 } 610 611 resource_list_init(&dinfo->resources); 612 dinfo->irq_mapped = false; 613 device_set_ivars(child, dinfo); 614 615 return (child); 616 } 617 618 static void 619 chipc_child_deleted(device_t dev, device_t child) 620 { 621 struct chipc_devinfo *dinfo = device_get_ivars(child); 622 623 if (dinfo != NULL) { 624 /* Free the child's resource list */ 625 resource_list_free(&dinfo->resources); 626 627 /* Unmap the child's IRQ */ 628 if (dinfo->irq_mapped) { 629 bhnd_unmap_intr(dev, dinfo->irq); 630 dinfo->irq_mapped = false; 631 } 632 633 free(dinfo, M_BHND); 634 } 635 636 device_set_ivars(child, NULL); 637 } 638 639 static struct resource_list * 640 chipc_get_resource_list(device_t dev, device_t child) 641 { 642 struct chipc_devinfo *dinfo = device_get_ivars(child); 643 return (&dinfo->resources); 644 } 645 646 /* Allocate region records for the given port, and add the port's memory 647 * range to the mem_rman */ 648 static int 649 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 650 u_int port) 651 { 652 struct chipc_region *cr; 653 rman_res_t start, end; 654 u_int num_regions; 655 int error; 656 657 num_regions = bhnd_get_region_count(sc->dev, type, port); 658 for (u_int region = 0; region < num_regions; region++) { 659 /* Allocate new region record */ 660 cr = chipc_alloc_region(sc, type, port, region); 661 if (cr == NULL) 662 return (ENODEV); 663 664 /* Can't manage regions that cannot be allocated */ 665 if (cr->cr_rid < 0) { 666 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 667 "%s%u.%u", bhnd_port_type_name(type), port, region); 668 chipc_free_region(sc, cr); 669 continue; 670 } 671 672 /* Add to rman's managed range */ 673 start = cr->cr_addr; 674 end = cr->cr_end; 675 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 676 chipc_free_region(sc, cr); 677 return (error); 678 } 679 680 /* Add to region list */ 681 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 682 } 683 684 return (0); 685 } 686 687 /* Initialize memory state for all chipc port regions */ 688 static int 689 chipc_init_rman(struct chipc_softc *sc) 690 { 691 u_int num_ports; 692 int error; 693 694 /* Port types for which we'll register chipc_region mappings */ 695 bhnd_port_type types[] = { 696 BHND_PORT_DEVICE 697 }; 698 699 /* Initialize resource manager */ 700 sc->mem_rman.rm_start = 0; 701 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 702 sc->mem_rman.rm_type = RMAN_ARRAY; 703 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 704 if ((error = rman_init(&sc->mem_rman))) { 705 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 706 error); 707 return (error); 708 } 709 710 /* Populate per-port-region state */ 711 for (u_int i = 0; i < nitems(types); i++) { 712 num_ports = bhnd_get_port_count(sc->dev, types[i]); 713 for (u_int port = 0; port < num_ports; port++) { 714 error = chipc_rman_init_regions(sc, types[i], port); 715 if (error) { 716 device_printf(sc->dev, 717 "region init failed for %s%u: %d\n", 718 bhnd_port_type_name(types[i]), port, 719 error); 720 721 goto failed; 722 } 723 } 724 } 725 726 return (0); 727 728 failed: 729 chipc_free_rman(sc); 730 return (error); 731 } 732 733 /* Free memory management state */ 734 static void 735 chipc_free_rman(struct chipc_softc *sc) 736 { 737 struct chipc_region *cr, *cr_next; 738 739 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 740 chipc_free_region(sc, cr); 741 742 rman_fini(&sc->mem_rman); 743 } 744 745 /** 746 * Return the rman instance for a given resource @p type, if any. 747 * 748 * @param sc The chipc device state. 749 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 750 * @param flags Resource flags (e.g. RF_PREFETCHABLE) 751 */ 752 static struct rman * 753 chipc_get_rman(device_t dev, int type, u_int flags) 754 { 755 struct chipc_softc *sc = device_get_softc(dev); 756 757 switch (type) { 758 case SYS_RES_MEMORY: 759 return (&sc->mem_rman); 760 761 case SYS_RES_IRQ: 762 /* We delegate IRQ resource management to the parent bus */ 763 return (NULL); 764 765 default: 766 return (NULL); 767 }; 768 } 769 770 static struct resource * 771 chipc_alloc_resource(device_t dev, device_t child, int type, 772 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 773 { 774 struct chipc_softc *sc; 775 struct chipc_region *cr; 776 struct resource_list_entry *rle; 777 struct resource *rv; 778 struct rman *rm; 779 int error; 780 bool passthrough, isdefault; 781 782 sc = device_get_softc(dev); 783 passthrough = (device_get_parent(child) != dev); 784 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 785 rle = NULL; 786 787 /* Fetch the resource manager, delegate request if necessary */ 788 rm = chipc_get_rman(dev, type, flags); 789 if (rm == NULL) { 790 /* Requested resource type is delegated to our parent */ 791 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 792 start, end, count, flags); 793 return (rv); 794 } 795 796 /* Populate defaults */ 797 if (!passthrough && isdefault) { 798 /* Fetch the resource list entry. */ 799 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 800 type, *rid); 801 if (rle == NULL) { 802 device_printf(dev, 803 "default resource %#x type %d for child %s " 804 "not found\n", *rid, type, 805 device_get_nameunit(child)); 806 return (NULL); 807 } 808 809 if (rle->res != NULL) { 810 device_printf(dev, 811 "resource entry %#x type %d for child %s is busy " 812 "[%d]\n", 813 *rid, type, device_get_nameunit(child), 814 rman_get_flags(rle->res)); 815 816 return (NULL); 817 } 818 819 start = rle->start; 820 end = rle->end; 821 count = ulmax(count, rle->count); 822 } 823 824 /* Locate a mapping region */ 825 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 826 /* Resource requests outside our shared port regions can be 827 * delegated to our parent. */ 828 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 829 start, end, count, flags); 830 return (rv); 831 } 832 833 /* 834 * As a special case, children that map the complete ChipCommon register 835 * block are delegated to our parent. 836 * 837 * The rman API does not support sharing resources that are not 838 * identical in size; since we allocate subregions to various children, 839 * any children that need to map the entire register block (e.g. because 840 * they require access to discontiguous register ranges) must make the 841 * allocation through our parent, where we hold a compatible 842 * RF_SHAREABLE allocation. 843 */ 844 if (cr == sc->core_region && cr->cr_addr == start && 845 cr->cr_end == end && cr->cr_count == count) 846 { 847 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 848 start, end, count, flags); 849 return (rv); 850 } 851 852 /* Try to retain a region reference */ 853 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 854 return (NULL); 855 856 /* Make our rman reservation */ 857 rv = bus_generic_rman_alloc_resource(dev, child, type, rid, start, end, 858 count, flags); 859 if (rv == NULL) { 860 chipc_release_region(sc, cr, RF_ALLOCATED); 861 return (NULL); 862 } 863 864 /* Update child's resource list entry */ 865 if (rle != NULL) { 866 rle->res = rv; 867 rle->start = rman_get_start(rv); 868 rle->end = rman_get_end(rv); 869 rle->count = rman_get_size(rv); 870 } 871 872 return (rv); 873 } 874 875 static int 876 chipc_release_resource(device_t dev, device_t child, int type, int rid, 877 struct resource *r) 878 { 879 struct chipc_softc *sc; 880 struct chipc_region *cr; 881 struct rman *rm; 882 struct resource_list_entry *rle; 883 int error; 884 885 sc = device_get_softc(dev); 886 887 /* Handled by parent bus? */ 888 rm = chipc_get_rman(dev, type, rman_get_flags(r)); 889 if (rm == NULL || !rman_is_region_manager(r, rm)) { 890 return (bus_generic_rl_release_resource(dev, child, type, rid, 891 r)); 892 } 893 894 /* Locate the mapping region */ 895 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 896 if (cr == NULL) 897 return (EINVAL); 898 899 /* Deactivate resources */ 900 error = bus_generic_rman_release_resource(dev, child, type, rid, r); 901 if (error != 0) 902 return (error); 903 904 /* Drop allocation reference */ 905 chipc_release_region(sc, cr, RF_ALLOCATED); 906 907 /* Clear reference from the resource list entry if exists */ 908 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 909 if (rle != NULL) 910 rle->res = NULL; 911 912 return (0); 913 } 914 915 static int 916 chipc_adjust_resource(device_t dev, device_t child, int type, 917 struct resource *r, rman_res_t start, rman_res_t end) 918 { 919 struct chipc_softc *sc; 920 struct chipc_region *cr; 921 struct rman *rm; 922 923 sc = device_get_softc(dev); 924 925 /* Handled by parent bus? */ 926 rm = chipc_get_rman(dev, type, rman_get_flags(r)); 927 if (rm == NULL || !rman_is_region_manager(r, rm)) { 928 return (bus_generic_adjust_resource(dev, child, type, r, start, 929 end)); 930 } 931 932 /* The range is limited to the existing region mapping */ 933 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 934 if (cr == NULL) 935 return (EINVAL); 936 937 if (end <= start) 938 return (EINVAL); 939 940 if (start < cr->cr_addr || end > cr->cr_end) 941 return (EINVAL); 942 943 /* Range falls within the existing region */ 944 return (rman_adjust_resource(r, start, end)); 945 } 946 947 /** 948 * Retain an RF_ACTIVE reference to the region mapping @p r, and 949 * configure @p r with its subregion values. 950 * 951 * @param sc Driver instance state. 952 * @param child Requesting child device. 953 * @param type resource type of @p r. 954 * @param rid resource id of @p r 955 * @param r resource to be activated. 956 * @param req_direct If true, failure to allocate a direct bhnd resource 957 * will be treated as an error. If false, the resource will not be marked 958 * as RF_ACTIVE if bhnd direct resource allocation fails. 959 */ 960 static int 961 chipc_try_activate_resource(device_t dev, device_t child, int type, 962 int rid, struct resource *r, bool req_direct) 963 { 964 struct chipc_softc *sc = device_get_softc(dev); 965 struct rman *rm; 966 struct chipc_region *cr; 967 bhnd_size_t cr_offset; 968 rman_res_t r_start, r_end, r_size; 969 int error; 970 971 rm = chipc_get_rman(dev, type, rman_get_flags(r)); 972 if (rm == NULL || !rman_is_region_manager(r, rm)) 973 return (EINVAL); 974 975 r_start = rman_get_start(r); 976 r_end = rman_get_end(r); 977 r_size = rman_get_size(r); 978 979 /* Find the corresponding chipc region */ 980 cr = chipc_find_region(sc, r_start, r_end); 981 if (cr == NULL) 982 return (EINVAL); 983 984 /* Calculate subregion offset within the chipc region */ 985 cr_offset = r_start - cr->cr_addr; 986 987 /* Retain (and activate, if necessary) the chipc region */ 988 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 989 return (error); 990 991 /* Configure child resource with its subregion values. */ 992 if (cr->cr_res->direct) { 993 error = chipc_init_child_resource(r, cr->cr_res->res, 994 cr_offset, r_size); 995 if (error) 996 goto cleanup; 997 998 /* Mark active */ 999 if ((error = rman_activate_resource(r))) 1000 goto cleanup; 1001 } else if (req_direct) { 1002 error = ENOMEM; 1003 goto cleanup; 1004 } 1005 1006 return (0); 1007 1008 cleanup: 1009 chipc_release_region(sc, cr, RF_ACTIVE); 1010 return (error); 1011 } 1012 1013 static int 1014 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1015 int rid, struct bhnd_resource *r) 1016 { 1017 struct rman *rm; 1018 int error; 1019 1020 /* Delegate non-locally managed resources to parent */ 1021 rm = chipc_get_rman(dev, type, rman_get_flags(r->res)); 1022 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1023 return (bhnd_bus_generic_activate_resource(dev, child, type, 1024 rid, r)); 1025 } 1026 1027 /* Try activating the chipc region resource */ 1028 error = chipc_try_activate_resource(dev, child, type, rid, r->res, 1029 false); 1030 if (error) 1031 return (error); 1032 1033 /* Mark the child resource as direct according to the returned resource 1034 * state */ 1035 if (rman_get_flags(r->res) & RF_ACTIVE) 1036 r->direct = true; 1037 1038 return (0); 1039 } 1040 1041 static int 1042 chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1043 struct resource *r) 1044 { 1045 struct rman *rm; 1046 1047 /* Delegate non-locally managed resources to parent */ 1048 rm = chipc_get_rman(dev, type, rman_get_flags(r)); 1049 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1050 return (bus_generic_activate_resource(dev, child, type, rid, 1051 r)); 1052 } 1053 1054 /* Try activating the chipc region-based resource */ 1055 return (chipc_try_activate_resource(dev, child, type, rid, r, true)); 1056 } 1057 1058 /** 1059 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1060 */ 1061 static int 1062 chipc_deactivate_resource(device_t dev, device_t child, int type, 1063 int rid, struct resource *r) 1064 { 1065 struct chipc_softc *sc; 1066 struct chipc_region *cr; 1067 struct rman *rm; 1068 int error; 1069 1070 sc = device_get_softc(dev); 1071 1072 /* Handled by parent bus? */ 1073 rm = chipc_get_rman(dev, type, rman_get_flags(r)); 1074 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1075 return (bus_generic_deactivate_resource(dev, child, type, rid, 1076 r)); 1077 } 1078 1079 /* Find the corresponding chipc region */ 1080 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1081 if (cr == NULL) 1082 return (EINVAL); 1083 1084 /* Mark inactive */ 1085 if ((error = rman_deactivate_resource(r))) 1086 return (error); 1087 1088 /* Drop associated RF_ACTIVE reference */ 1089 chipc_release_region(sc, cr, RF_ACTIVE); 1090 1091 return (0); 1092 } 1093 1094 /** 1095 * Examine bus state and make a best effort determination of whether it's 1096 * likely safe to enable the muxed SPROM pins. 1097 * 1098 * On devices that do not use SPROM pin muxing, always returns true. 1099 * 1100 * @param sc chipc driver state. 1101 */ 1102 static bool 1103 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1104 { 1105 device_t *devs; 1106 device_t hostb; 1107 device_t parent; 1108 int devcount; 1109 int error; 1110 bool result; 1111 1112 /* Nothing to do? */ 1113 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1114 return (true); 1115 1116 bus_topo_lock(); 1117 1118 parent = device_get_parent(sc->dev); 1119 hostb = bhnd_bus_find_hostb_device(parent); 1120 1121 if ((error = device_get_children(parent, &devs, &devcount))) { 1122 bus_topo_unlock(); 1123 return (false); 1124 } 1125 1126 /* Reject any active devices other than ChipCommon, or the 1127 * host bridge (if any). */ 1128 result = true; 1129 for (int i = 0; i < devcount; i++) { 1130 if (devs[i] == hostb || devs[i] == sc->dev) 1131 continue; 1132 1133 if (!device_is_attached(devs[i])) 1134 continue; 1135 1136 if (device_is_suspended(devs[i])) 1137 continue; 1138 1139 /* Active device; assume SPROM is busy */ 1140 result = false; 1141 break; 1142 } 1143 1144 free(devs, M_TEMP); 1145 bus_topo_unlock(); 1146 return (result); 1147 } 1148 1149 static int 1150 chipc_enable_sprom(device_t dev) 1151 { 1152 struct chipc_softc *sc; 1153 int error; 1154 1155 sc = device_get_softc(dev); 1156 CHIPC_LOCK(sc); 1157 1158 /* Already enabled? */ 1159 if (sc->sprom_refcnt >= 1) { 1160 sc->sprom_refcnt++; 1161 CHIPC_UNLOCK(sc); 1162 1163 return (0); 1164 } 1165 1166 switch (sc->caps.nvram_src) { 1167 case BHND_NVRAM_SRC_SPROM: 1168 error = chipc_enable_sprom_pins(sc); 1169 break; 1170 case BHND_NVRAM_SRC_OTP: 1171 error = chipc_enable_otp_power(sc); 1172 break; 1173 default: 1174 error = 0; 1175 break; 1176 } 1177 1178 /* Bump the reference count */ 1179 if (error == 0) 1180 sc->sprom_refcnt++; 1181 1182 CHIPC_UNLOCK(sc); 1183 return (error); 1184 } 1185 1186 static void 1187 chipc_disable_sprom(device_t dev) 1188 { 1189 struct chipc_softc *sc; 1190 1191 sc = device_get_softc(dev); 1192 CHIPC_LOCK(sc); 1193 1194 /* Check reference count, skip disable if in-use. */ 1195 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1196 sc->sprom_refcnt--; 1197 if (sc->sprom_refcnt > 0) { 1198 CHIPC_UNLOCK(sc); 1199 return; 1200 } 1201 1202 switch (sc->caps.nvram_src) { 1203 case BHND_NVRAM_SRC_SPROM: 1204 chipc_disable_sprom_pins(sc); 1205 break; 1206 case BHND_NVRAM_SRC_OTP: 1207 chipc_disable_otp_power(sc); 1208 break; 1209 default: 1210 break; 1211 } 1212 1213 CHIPC_UNLOCK(sc); 1214 } 1215 1216 static int 1217 chipc_enable_otp_power(struct chipc_softc *sc) 1218 { 1219 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1220 // OTPS_READY to be set in `optstatus`. 1221 return (0); 1222 } 1223 1224 static void 1225 chipc_disable_otp_power(struct chipc_softc *sc) 1226 { 1227 // TODO: Disable OTP resource via PMU 1228 } 1229 1230 /** 1231 * If required by this device, enable access to the SPROM. 1232 * 1233 * @param sc chipc driver state. 1234 */ 1235 static int 1236 chipc_enable_sprom_pins(struct chipc_softc *sc) 1237 { 1238 uint32_t cctrl; 1239 1240 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1241 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1242 1243 /* Nothing to do? */ 1244 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1245 return (0); 1246 1247 /* Check whether bus is busy */ 1248 if (!chipc_should_enable_muxed_sprom(sc)) 1249 return (EBUSY); 1250 1251 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1252 1253 /* 4331 devices */ 1254 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1255 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1256 1257 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1258 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1259 1260 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1261 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1262 1263 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1264 return (0); 1265 } 1266 1267 /* 4360 devices */ 1268 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1269 /* Unimplemented */ 1270 } 1271 1272 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1273 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1274 return (ENXIO); 1275 } 1276 1277 /** 1278 * If required by this device, revert any GPIO/pin configuration applied 1279 * to allow SPROM access. 1280 * 1281 * @param sc chipc driver state. 1282 */ 1283 static void 1284 chipc_disable_sprom_pins(struct chipc_softc *sc) 1285 { 1286 uint32_t cctrl; 1287 1288 /* Nothing to do? */ 1289 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1290 return; 1291 1292 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1293 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1294 1295 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1296 1297 /* 4331 devices */ 1298 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1299 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1300 1301 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1302 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1303 1304 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1305 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1306 1307 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1308 return; 1309 } 1310 1311 /* 4360 devices */ 1312 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1313 /* Unimplemented */ 1314 } 1315 } 1316 1317 static uint32_t 1318 chipc_read_chipst(device_t dev) 1319 { 1320 struct chipc_softc *sc = device_get_softc(dev); 1321 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1322 } 1323 1324 static void 1325 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1326 { 1327 struct chipc_softc *sc; 1328 uint32_t cctrl; 1329 1330 sc = device_get_softc(dev); 1331 1332 CHIPC_LOCK(sc); 1333 1334 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1335 cctrl = (cctrl & ~mask) | (value | mask); 1336 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1337 1338 CHIPC_UNLOCK(sc); 1339 } 1340 1341 static struct chipc_caps * 1342 chipc_get_caps(device_t dev) 1343 { 1344 struct chipc_softc *sc; 1345 1346 sc = device_get_softc(dev); 1347 return (&sc->caps); 1348 } 1349 1350 static device_method_t chipc_methods[] = { 1351 /* Device interface */ 1352 DEVMETHOD(device_probe, chipc_probe), 1353 DEVMETHOD(device_attach, chipc_attach), 1354 DEVMETHOD(device_detach, chipc_detach), 1355 DEVMETHOD(device_suspend, chipc_suspend), 1356 DEVMETHOD(device_resume, chipc_resume), 1357 1358 /* Bus interface */ 1359 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1360 DEVMETHOD(bus_print_child, chipc_print_child), 1361 1362 DEVMETHOD(bus_add_child, chipc_add_child), 1363 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1364 1365 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1366 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1367 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1368 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1369 DEVMETHOD(bus_release_resource, chipc_release_resource), 1370 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1371 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1372 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1373 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1374 DEVMETHOD(bus_get_rman, chipc_get_rman), 1375 1376 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1377 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1378 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1379 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1380 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1381 1382 /* BHND bus inteface */ 1383 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1384 1385 /* ChipCommon interface */ 1386 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1387 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1388 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1389 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1390 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1391 1392 DEVMETHOD_END 1393 }; 1394 1395 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1396 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, 0, 0, 1397 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1398 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1399 MODULE_VERSION(bhnd_chipc, 1); 1400