1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 6 * Copyright (c) 2017 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Landon Fuller 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 20 * redistribution must be conditioned upon including a substantially 21 * similar Disclaimer requirement for further binary redistribution. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 /* 39 * Broadcom ChipCommon driver. 40 * 41 * With the exception of some very early chipsets, the ChipCommon core 42 * has been included in all HND SoCs and chipsets based on the siba(4) 43 * and bcma(4) interconnects, providing a common interface to chipset 44 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 45 * GPIO, flash, etc. 46 */ 47 48 #include <sys/param.h> 49 #include <sys/kernel.h> 50 #include <sys/lock.h> 51 #include <sys/bus.h> 52 #include <sys/rman.h> 53 #include <sys/malloc.h> 54 #include <sys/module.h> 55 #include <sys/mutex.h> 56 #include <sys/systm.h> 57 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 61 #include <dev/bhnd/bhnd.h> 62 #include <dev/bhnd/bhndvar.h> 63 64 #include "chipcreg.h" 65 #include "chipcvar.h" 66 67 #include "chipc_private.h" 68 69 static struct bhnd_device_quirk chipc_quirks[]; 70 71 /* Supported device identifiers */ 72 static const struct bhnd_device chipc_devices[] = { 73 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 74 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 75 BHND_DEVICE_END 76 }; 77 78 /* Device quirks table */ 79 static struct bhnd_device_quirk chipc_quirks[] = { 80 /* HND OTP controller revisions */ 81 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 82 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 83 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 84 85 /* IPX OTP controller revisions */ 86 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 87 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 88 89 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 90 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 91 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 92 93 /* 4706 variant quirks */ 94 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 95 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 96 97 /* 4331 quirks*/ 98 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 99 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 100 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 101 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 102 103 /* 4360 quirks */ 104 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 105 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 106 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 107 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 108 109 BHND_DEVICE_QUIRK_END 110 }; 111 112 static int chipc_add_children(struct chipc_softc *sc); 113 114 static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 115 struct chipc_caps *caps); 116 static int chipc_read_caps(struct chipc_softc *sc, 117 struct chipc_caps *caps); 118 119 static bool chipc_should_enable_muxed_sprom( 120 struct chipc_softc *sc); 121 static int chipc_enable_otp_power(struct chipc_softc *sc); 122 static void chipc_disable_otp_power(struct chipc_softc *sc); 123 static int chipc_enable_sprom_pins(struct chipc_softc *sc); 124 static void chipc_disable_sprom_pins(struct chipc_softc *sc); 125 126 static int chipc_try_activate_resource(device_t dev, 127 device_t child, struct resource *r, 128 bool req_direct); 129 130 static int chipc_init_rman(struct chipc_softc *sc); 131 static void chipc_free_rman(struct chipc_softc *sc); 132 static struct rman *chipc_get_rman(device_t dev, int type, u_int flags); 133 134 /* quirk and capability flag convenience macros */ 135 #define CHIPC_QUIRK(_sc, _name) \ 136 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 137 138 #define CHIPC_CAP(_sc, _name) \ 139 ((_sc)->caps._name) 140 141 #define CHIPC_ASSERT_QUIRK(_sc, name) \ 142 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 143 144 #define CHIPC_ASSERT_CAP(_sc, name) \ 145 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 146 147 static int 148 chipc_probe(device_t dev) 149 { 150 const struct bhnd_device *id; 151 152 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 153 if (id == NULL) 154 return (ENXIO); 155 156 bhnd_set_default_core_desc(dev); 157 return (BUS_PROBE_DEFAULT); 158 } 159 160 static int 161 chipc_attach(device_t dev) 162 { 163 struct chipc_softc *sc; 164 int error; 165 166 sc = device_get_softc(dev); 167 sc->dev = dev; 168 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 169 sizeof(chipc_devices[0])); 170 sc->sprom_refcnt = 0; 171 172 CHIPC_LOCK_INIT(sc); 173 STAILQ_INIT(&sc->mem_regions); 174 175 /* Set up resource management */ 176 if ((error = chipc_init_rman(sc))) { 177 device_printf(sc->dev, 178 "failed to initialize chipc resource state: %d\n", error); 179 goto failed; 180 } 181 182 /* Allocate the region containing the chipc register block */ 183 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 184 error = ENXIO; 185 goto failed; 186 } 187 188 error = chipc_retain_region(sc, sc->core_region, 189 RF_ALLOCATED|RF_ACTIVE); 190 if (error) { 191 sc->core_region = NULL; 192 goto failed; 193 } 194 195 /* Save a direct reference to our chipc registers */ 196 sc->core = sc->core_region->cr_res; 197 198 /* Fetch and parse capability register(s) */ 199 if ((error = chipc_read_caps(sc, &sc->caps))) 200 goto failed; 201 202 if (bootverbose) 203 chipc_print_caps(sc->dev, &sc->caps); 204 205 /* Attach all supported child devices */ 206 if ((error = chipc_add_children(sc))) 207 goto failed; 208 209 /* 210 * Register ourselves with the bus; we're fully initialized and can 211 * response to ChipCommin API requests. 212 * 213 * Since our children may need access to ChipCommon, this must be done 214 * before attaching our children below (via bus_attach_children). 215 */ 216 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 217 goto failed; 218 219 bus_attach_children(dev); 220 221 return (0); 222 223 failed: 224 device_delete_children(sc->dev); 225 226 if (sc->core_region != NULL) { 227 chipc_release_region(sc, sc->core_region, 228 RF_ALLOCATED|RF_ACTIVE); 229 } 230 231 chipc_free_rman(sc); 232 CHIPC_LOCK_DESTROY(sc); 233 return (error); 234 } 235 236 static int 237 chipc_detach(device_t dev) 238 { 239 struct chipc_softc *sc; 240 int error; 241 242 sc = device_get_softc(dev); 243 244 if ((error = bus_generic_detach(dev))) 245 return (error); 246 247 if ((error = device_delete_children(dev))) 248 return (error); 249 250 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 251 return (error); 252 253 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 254 chipc_free_rman(sc); 255 256 CHIPC_LOCK_DESTROY(sc); 257 258 return (0); 259 } 260 261 static int 262 chipc_add_children(struct chipc_softc *sc) 263 { 264 device_t child; 265 const char *flash_bus; 266 int error; 267 268 /* SPROM/OTP */ 269 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 270 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 271 { 272 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", DEVICE_UNIT_ANY); 273 if (child == NULL) { 274 device_printf(sc->dev, "failed to add nvram device\n"); 275 return (ENXIO); 276 } 277 278 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 279 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 280 CHIPC_SPROM_OTP_SIZE, 0, 0); 281 if (error) { 282 device_printf(sc->dev, "failed to set OTP memory " 283 "resource: %d\n", error); 284 return (error); 285 } 286 } 287 288 /* 289 * PMU/PWR_CTRL 290 * 291 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 292 * attached directly to the bhnd(4) bus -- not chipc. 293 */ 294 if (sc->caps.pmu && !sc->caps.aob) { 295 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", DEVICE_UNIT_ANY); 296 if (child == NULL) { 297 device_printf(sc->dev, "failed to add pmu\n"); 298 return (ENXIO); 299 } 300 } else if (sc->caps.pwr_ctrl) { 301 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", DEVICE_UNIT_ANY); 302 if (child == NULL) { 303 device_printf(sc->dev, "failed to add pwrctl\n"); 304 return (ENXIO); 305 } 306 } 307 308 /* GPIO */ 309 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", DEVICE_UNIT_ANY); 310 if (child == NULL) { 311 device_printf(sc->dev, "failed to add gpio\n"); 312 return (ENXIO); 313 } 314 315 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0); 316 if (error) { 317 device_printf(sc->dev, "failed to set gpio memory resource: " 318 "%d\n", error); 319 return (error); 320 } 321 322 /* All remaining devices are SoC-only */ 323 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 324 return (0); 325 326 /* UARTs */ 327 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 328 int irq_rid, mem_rid; 329 330 irq_rid = 0; 331 mem_rid = 0; 332 333 child = BUS_ADD_CHILD(sc->dev, 0, "uart", DEVICE_UNIT_ANY); 334 if (child == NULL) { 335 device_printf(sc->dev, "failed to add uart%u\n", i); 336 return (ENXIO); 337 } 338 339 /* Shared IRQ */ 340 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 341 if (error) { 342 device_printf(sc->dev, "failed to set uart%u irq %u\n", 343 i, 0); 344 return (error); 345 } 346 347 /* UART registers are mapped sequentially */ 348 error = chipc_set_mem_resource(sc, child, mem_rid, 349 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 350 if (error) { 351 device_printf(sc->dev, "failed to set uart%u memory " 352 "resource: %d\n", i, error); 353 return (error); 354 } 355 } 356 357 /* Flash */ 358 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 359 if (flash_bus != NULL) { 360 int rid; 361 362 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, DEVICE_UNIT_ANY); 363 if (child == NULL) { 364 device_printf(sc->dev, "failed to add %s device\n", 365 flash_bus); 366 return (ENXIO); 367 } 368 369 /* flash memory mapping */ 370 rid = 0; 371 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 372 1); 373 if (error) { 374 device_printf(sc->dev, "failed to set flash memory " 375 "resource %d: %d\n", rid, error); 376 return (error); 377 } 378 379 /* flashctrl registers */ 380 rid++; 381 error = chipc_set_mem_resource(sc, child, rid, 382 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 383 if (error) { 384 device_printf(sc->dev, "failed to set flash memory " 385 "resource %d: %d\n", rid, error); 386 return (error); 387 } 388 } 389 390 return (0); 391 } 392 393 /** 394 * Determine the NVRAM data source for this device. 395 * 396 * The SPROM, OTP, and flash capability flags must be fully populated in 397 * @p caps. 398 * 399 * @param sc chipc driver state. 400 * @param caps capability flags to be used to derive NVRAM configuration. 401 */ 402 static bhnd_nvram_src 403 chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 404 { 405 uint32_t otp_st, srom_ctrl; 406 407 /* 408 * We check for hardware presence in order of precedence. For example, 409 * SPROM is always used in preference to internal OTP if found. 410 */ 411 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 412 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 413 if (srom_ctrl & CHIPC_SRC_PRESENT) 414 return (BHND_NVRAM_SRC_SPROM); 415 } 416 417 /* Check for programmed OTP H/W subregion (contains SROM data) */ 418 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 419 /* TODO: need access to HND-OTP device */ 420 if (!CHIPC_QUIRK(sc, OTP_HND)) { 421 device_printf(sc->dev, 422 "NVRAM unavailable: unsupported OTP controller.\n"); 423 return (BHND_NVRAM_SRC_UNKNOWN); 424 } 425 426 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 427 if (otp_st & CHIPC_OTPS_GUP_HW) 428 return (BHND_NVRAM_SRC_OTP); 429 } 430 431 /* Check for flash */ 432 if (caps->flash_type != CHIPC_FLASH_NONE) 433 return (BHND_NVRAM_SRC_FLASH); 434 435 /* No NVRAM hardware capability declared */ 436 return (BHND_NVRAM_SRC_UNKNOWN); 437 } 438 439 /* Read and parse chipc capabilities */ 440 static int 441 chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 442 { 443 uint32_t cap_reg; 444 uint32_t cap_ext_reg; 445 uint32_t regval; 446 447 /* Fetch cap registers */ 448 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 449 cap_ext_reg = 0; 450 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 451 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 452 453 /* Extract values */ 454 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 455 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 456 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 457 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 458 459 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 460 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 461 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 462 463 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 464 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 465 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 466 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 467 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 468 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 469 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 470 471 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 472 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 473 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 474 475 /* Fetch OTP size for later IPX controller revisions */ 476 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 477 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 478 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 479 } 480 481 /* Determine flash type and parameters */ 482 caps->cfi_width = 0; 483 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 484 case CHIPC_CAP_SFLASH_ST: 485 caps->flash_type = CHIPC_SFLASH_ST; 486 break; 487 case CHIPC_CAP_SFLASH_AT: 488 caps->flash_type = CHIPC_SFLASH_AT; 489 break; 490 case CHIPC_CAP_NFLASH: 491 /* unimplemented */ 492 caps->flash_type = CHIPC_NFLASH; 493 break; 494 case CHIPC_CAP_PFLASH: 495 caps->flash_type = CHIPC_PFLASH_CFI; 496 497 /* determine cfi width */ 498 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 499 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 500 caps->cfi_width = 2; 501 else 502 caps->cfi_width = 1; 503 504 break; 505 case CHIPC_CAP_FLASH_NONE: 506 caps->flash_type = CHIPC_FLASH_NONE; 507 break; 508 509 } 510 511 /* Handle 4706_NFLASH fallback */ 512 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 513 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 514 { 515 caps->flash_type = CHIPC_NFLASH_4706; 516 } 517 518 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 519 * capability flags have been populated. */ 520 caps->nvram_src = chipc_find_nvram_src(sc, caps); 521 522 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 523 * data is placed within the OTP general use region. */ 524 caps->sprom_offset = 0; 525 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 526 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 527 528 /* Bit offset to GUP HW subregion containing SPROM data */ 529 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 530 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 531 532 /* Convert to bytes */ 533 caps->sprom_offset /= 8; 534 } 535 536 return (0); 537 } 538 539 static int 540 chipc_suspend(device_t dev) 541 { 542 return (bus_generic_suspend(dev)); 543 } 544 545 static int 546 chipc_resume(device_t dev) 547 { 548 return (bus_generic_resume(dev)); 549 } 550 551 static void 552 chipc_probe_nomatch(device_t dev, device_t child) 553 { 554 struct resource_list *rl; 555 const char *name; 556 557 name = device_get_name(child); 558 if (name == NULL) 559 name = "unknown device"; 560 561 device_printf(dev, "<%s> at", name); 562 563 rl = BUS_GET_RESOURCE_LIST(dev, child); 564 if (rl != NULL) { 565 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 566 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 567 } 568 569 printf(" (no driver attached)\n"); 570 } 571 572 static int 573 chipc_print_child(device_t dev, device_t child) 574 { 575 struct resource_list *rl; 576 int retval = 0; 577 578 retval += bus_print_child_header(dev, child); 579 580 rl = BUS_GET_RESOURCE_LIST(dev, child); 581 if (rl != NULL) { 582 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 583 "%#jx"); 584 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 585 "%jd"); 586 } 587 588 retval += bus_print_child_domain(dev, child); 589 retval += bus_print_child_footer(dev, child); 590 591 return (retval); 592 } 593 594 static device_t 595 chipc_add_child(device_t dev, u_int order, const char *name, int unit) 596 { 597 struct chipc_devinfo *dinfo; 598 device_t child; 599 600 child = device_add_child_ordered(dev, order, name, unit); 601 if (child == NULL) 602 return (NULL); 603 604 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 605 if (dinfo == NULL) { 606 device_delete_child(dev, child); 607 return (NULL); 608 } 609 610 resource_list_init(&dinfo->resources); 611 dinfo->irq_mapped = false; 612 device_set_ivars(child, dinfo); 613 614 return (child); 615 } 616 617 static void 618 chipc_child_deleted(device_t dev, device_t child) 619 { 620 struct chipc_devinfo *dinfo = device_get_ivars(child); 621 622 if (dinfo != NULL) { 623 /* Free the child's resource list */ 624 resource_list_free(&dinfo->resources); 625 626 /* Unmap the child's IRQ */ 627 if (dinfo->irq_mapped) { 628 bhnd_unmap_intr(dev, dinfo->irq); 629 dinfo->irq_mapped = false; 630 } 631 632 free(dinfo, M_BHND); 633 } 634 635 device_set_ivars(child, NULL); 636 } 637 638 static struct resource_list * 639 chipc_get_resource_list(device_t dev, device_t child) 640 { 641 struct chipc_devinfo *dinfo = device_get_ivars(child); 642 return (&dinfo->resources); 643 } 644 645 /* Allocate region records for the given port, and add the port's memory 646 * range to the mem_rman */ 647 static int 648 chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 649 u_int port) 650 { 651 struct chipc_region *cr; 652 rman_res_t start, end; 653 u_int num_regions; 654 int error; 655 656 num_regions = bhnd_get_region_count(sc->dev, type, port); 657 for (u_int region = 0; region < num_regions; region++) { 658 /* Allocate new region record */ 659 cr = chipc_alloc_region(sc, type, port, region); 660 if (cr == NULL) 661 return (ENODEV); 662 663 /* Can't manage regions that cannot be allocated */ 664 if (cr->cr_rid < 0) { 665 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 666 "%s%u.%u", bhnd_port_type_name(type), port, region); 667 chipc_free_region(sc, cr); 668 continue; 669 } 670 671 /* Add to rman's managed range */ 672 start = cr->cr_addr; 673 end = cr->cr_end; 674 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 675 chipc_free_region(sc, cr); 676 return (error); 677 } 678 679 /* Add to region list */ 680 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 681 } 682 683 return (0); 684 } 685 686 /* Initialize memory state for all chipc port regions */ 687 static int 688 chipc_init_rman(struct chipc_softc *sc) 689 { 690 u_int num_ports; 691 int error; 692 693 /* Port types for which we'll register chipc_region mappings */ 694 bhnd_port_type types[] = { 695 BHND_PORT_DEVICE 696 }; 697 698 /* Initialize resource manager */ 699 sc->mem_rman.rm_start = 0; 700 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 701 sc->mem_rman.rm_type = RMAN_ARRAY; 702 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 703 if ((error = rman_init(&sc->mem_rman))) { 704 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 705 error); 706 return (error); 707 } 708 709 /* Populate per-port-region state */ 710 for (u_int i = 0; i < nitems(types); i++) { 711 num_ports = bhnd_get_port_count(sc->dev, types[i]); 712 for (u_int port = 0; port < num_ports; port++) { 713 error = chipc_rman_init_regions(sc, types[i], port); 714 if (error) { 715 device_printf(sc->dev, 716 "region init failed for %s%u: %d\n", 717 bhnd_port_type_name(types[i]), port, 718 error); 719 720 goto failed; 721 } 722 } 723 } 724 725 return (0); 726 727 failed: 728 chipc_free_rman(sc); 729 return (error); 730 } 731 732 /* Free memory management state */ 733 static void 734 chipc_free_rman(struct chipc_softc *sc) 735 { 736 struct chipc_region *cr, *cr_next; 737 738 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 739 chipc_free_region(sc, cr); 740 741 rman_fini(&sc->mem_rman); 742 } 743 744 /** 745 * Return the rman instance for a given resource @p type, if any. 746 * 747 * @param sc The chipc device state. 748 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 749 * @param flags Resource flags (e.g. RF_PREFETCHABLE) 750 */ 751 static struct rman * 752 chipc_get_rman(device_t dev, int type, u_int flags) 753 { 754 struct chipc_softc *sc = device_get_softc(dev); 755 756 switch (type) { 757 case SYS_RES_MEMORY: 758 return (&sc->mem_rman); 759 760 case SYS_RES_IRQ: 761 /* We delegate IRQ resource management to the parent bus */ 762 return (NULL); 763 764 default: 765 return (NULL); 766 }; 767 } 768 769 static struct resource * 770 chipc_alloc_resource(device_t dev, device_t child, int type, 771 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 772 { 773 struct chipc_softc *sc; 774 struct chipc_region *cr; 775 struct resource_list_entry *rle; 776 struct resource *rv; 777 struct rman *rm; 778 int error; 779 bool passthrough, isdefault; 780 781 sc = device_get_softc(dev); 782 passthrough = (device_get_parent(child) != dev); 783 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 784 rle = NULL; 785 786 /* Fetch the resource manager, delegate request if necessary */ 787 rm = chipc_get_rman(dev, type, flags); 788 if (rm == NULL) { 789 /* Requested resource type is delegated to our parent */ 790 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 791 start, end, count, flags); 792 return (rv); 793 } 794 795 /* Populate defaults */ 796 if (!passthrough && isdefault) { 797 /* Fetch the resource list entry. */ 798 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 799 type, *rid); 800 if (rle == NULL) { 801 device_printf(dev, 802 "default resource %#x type %d for child %s " 803 "not found\n", *rid, type, 804 device_get_nameunit(child)); 805 return (NULL); 806 } 807 808 if (rle->res != NULL) { 809 device_printf(dev, 810 "resource entry %#x type %d for child %s is busy " 811 "[%d]\n", 812 *rid, type, device_get_nameunit(child), 813 rman_get_flags(rle->res)); 814 815 return (NULL); 816 } 817 818 start = rle->start; 819 end = rle->end; 820 count = ulmax(count, rle->count); 821 } 822 823 /* Locate a mapping region */ 824 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 825 /* Resource requests outside our shared port regions can be 826 * delegated to our parent. */ 827 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 828 start, end, count, flags); 829 return (rv); 830 } 831 832 /* 833 * As a special case, children that map the complete ChipCommon register 834 * block are delegated to our parent. 835 * 836 * The rman API does not support sharing resources that are not 837 * identical in size; since we allocate subregions to various children, 838 * any children that need to map the entire register block (e.g. because 839 * they require access to discontiguous register ranges) must make the 840 * allocation through our parent, where we hold a compatible 841 * RF_SHAREABLE allocation. 842 */ 843 if (cr == sc->core_region && cr->cr_addr == start && 844 cr->cr_end == end && cr->cr_count == count) 845 { 846 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 847 start, end, count, flags); 848 return (rv); 849 } 850 851 /* Try to retain a region reference */ 852 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 853 return (NULL); 854 855 /* Make our rman reservation */ 856 rv = bus_generic_rman_alloc_resource(dev, child, type, rid, start, end, 857 count, flags); 858 if (rv == NULL) { 859 chipc_release_region(sc, cr, RF_ALLOCATED); 860 return (NULL); 861 } 862 863 /* Update child's resource list entry */ 864 if (rle != NULL) { 865 rle->res = rv; 866 rle->start = rman_get_start(rv); 867 rle->end = rman_get_end(rv); 868 rle->count = rman_get_size(rv); 869 } 870 871 return (rv); 872 } 873 874 static int 875 chipc_release_resource(device_t dev, device_t child, struct resource *r) 876 { 877 struct chipc_softc *sc; 878 struct chipc_region *cr; 879 struct rman *rm; 880 struct resource_list_entry *rle; 881 int error; 882 883 sc = device_get_softc(dev); 884 885 /* Handled by parent bus? */ 886 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r)); 887 if (rm == NULL || !rman_is_region_manager(r, rm)) { 888 return (bus_generic_rl_release_resource(dev, child, r)); 889 } 890 891 /* Locate the mapping region */ 892 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 893 if (cr == NULL) 894 return (EINVAL); 895 896 /* Cache rle */ 897 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 898 rman_get_type(r), rman_get_rid(r)); 899 900 /* Deactivate resources */ 901 error = bus_generic_rman_release_resource(dev, child, r); 902 if (error != 0) 903 return (error); 904 905 /* Drop allocation reference */ 906 chipc_release_region(sc, cr, RF_ALLOCATED); 907 908 /* Clear reference from the resource list entry if exists */ 909 if (rle != NULL) 910 rle->res = NULL; 911 912 return (0); 913 } 914 915 static int 916 chipc_adjust_resource(device_t dev, device_t child, 917 struct resource *r, rman_res_t start, rman_res_t end) 918 { 919 struct chipc_softc *sc; 920 struct chipc_region *cr; 921 struct rman *rm; 922 923 sc = device_get_softc(dev); 924 925 /* Handled by parent bus? */ 926 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r)); 927 if (rm == NULL || !rman_is_region_manager(r, rm)) { 928 return (bus_generic_adjust_resource(dev, child, r, start, end)); 929 } 930 931 /* The range is limited to the existing region mapping */ 932 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 933 if (cr == NULL) 934 return (EINVAL); 935 936 if (end <= start) 937 return (EINVAL); 938 939 if (start < cr->cr_addr || end > cr->cr_end) 940 return (EINVAL); 941 942 /* Range falls within the existing region */ 943 return (rman_adjust_resource(r, start, end)); 944 } 945 946 /** 947 * Retain an RF_ACTIVE reference to the region mapping @p r, and 948 * configure @p r with its subregion values. 949 * 950 * @param sc Driver instance state. 951 * @param child Requesting child device. 952 * @param r resource to be activated. 953 * @param req_direct If true, failure to allocate a direct bhnd resource 954 * will be treated as an error. If false, the resource will not be marked 955 * as RF_ACTIVE if bhnd direct resource allocation fails. 956 */ 957 static int 958 chipc_try_activate_resource(device_t dev, device_t child, 959 struct resource *r, bool req_direct) 960 { 961 struct chipc_softc *sc = device_get_softc(dev); 962 struct rman *rm; 963 struct chipc_region *cr; 964 bhnd_size_t cr_offset; 965 rman_res_t r_start, r_end, r_size; 966 int error; 967 968 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r)); 969 if (rm == NULL || !rman_is_region_manager(r, rm)) 970 return (EINVAL); 971 972 r_start = rman_get_start(r); 973 r_end = rman_get_end(r); 974 r_size = rman_get_size(r); 975 976 /* Find the corresponding chipc region */ 977 cr = chipc_find_region(sc, r_start, r_end); 978 if (cr == NULL) 979 return (EINVAL); 980 981 /* Calculate subregion offset within the chipc region */ 982 cr_offset = r_start - cr->cr_addr; 983 984 /* Retain (and activate, if necessary) the chipc region */ 985 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 986 return (error); 987 988 /* Configure child resource with its subregion values. */ 989 if (cr->cr_res->direct) { 990 error = chipc_init_child_resource(r, cr->cr_res->res, 991 cr_offset, r_size); 992 if (error) 993 goto cleanup; 994 995 /* Mark active */ 996 if ((error = rman_activate_resource(r))) 997 goto cleanup; 998 } else if (req_direct) { 999 error = ENOMEM; 1000 goto cleanup; 1001 } 1002 1003 return (0); 1004 1005 cleanup: 1006 chipc_release_region(sc, cr, RF_ACTIVE); 1007 return (error); 1008 } 1009 1010 static int 1011 chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1012 int rid, struct bhnd_resource *r) 1013 { 1014 struct rman *rm; 1015 int error; 1016 1017 /* Delegate non-locally managed resources to parent */ 1018 rm = chipc_get_rman(dev, type, rman_get_flags(r->res)); 1019 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1020 return (bhnd_bus_generic_activate_resource(dev, child, type, 1021 rid, r)); 1022 } 1023 1024 /* Try activating the chipc region resource */ 1025 error = chipc_try_activate_resource(dev, child, r->res, false); 1026 if (error) 1027 return (error); 1028 1029 /* Mark the child resource as direct according to the returned resource 1030 * state */ 1031 if (rman_get_flags(r->res) & RF_ACTIVE) 1032 r->direct = true; 1033 1034 return (0); 1035 } 1036 1037 static int 1038 chipc_activate_resource(device_t dev, device_t child, struct resource *r) 1039 { 1040 struct rman *rm; 1041 1042 /* Delegate non-locally managed resources to parent */ 1043 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r)); 1044 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1045 return (bus_generic_activate_resource(dev, child, r)); 1046 } 1047 1048 /* Try activating the chipc region-based resource */ 1049 return (chipc_try_activate_resource(dev, child, r, true)); 1050 } 1051 1052 /** 1053 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1054 */ 1055 static int 1056 chipc_deactivate_resource(device_t dev, device_t child, 1057 struct resource *r) 1058 { 1059 struct chipc_softc *sc; 1060 struct chipc_region *cr; 1061 struct rman *rm; 1062 int error; 1063 1064 sc = device_get_softc(dev); 1065 1066 /* Handled by parent bus? */ 1067 rm = chipc_get_rman(dev, rman_get_type(r), rman_get_flags(r)); 1068 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1069 return (bus_generic_deactivate_resource(dev, child, r)); 1070 } 1071 1072 /* Find the corresponding chipc region */ 1073 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1074 if (cr == NULL) 1075 return (EINVAL); 1076 1077 /* Mark inactive */ 1078 if ((error = rman_deactivate_resource(r))) 1079 return (error); 1080 1081 /* Drop associated RF_ACTIVE reference */ 1082 chipc_release_region(sc, cr, RF_ACTIVE); 1083 1084 return (0); 1085 } 1086 1087 /** 1088 * Examine bus state and make a best effort determination of whether it's 1089 * likely safe to enable the muxed SPROM pins. 1090 * 1091 * On devices that do not use SPROM pin muxing, always returns true. 1092 * 1093 * @param sc chipc driver state. 1094 */ 1095 static bool 1096 chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1097 { 1098 device_t *devs; 1099 device_t hostb; 1100 device_t parent; 1101 int devcount; 1102 int error; 1103 bool result; 1104 1105 /* Nothing to do? */ 1106 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1107 return (true); 1108 1109 bus_topo_lock(); 1110 1111 parent = device_get_parent(sc->dev); 1112 hostb = bhnd_bus_find_hostb_device(parent); 1113 1114 if ((error = device_get_children(parent, &devs, &devcount))) { 1115 bus_topo_unlock(); 1116 return (false); 1117 } 1118 1119 /* Reject any active devices other than ChipCommon, or the 1120 * host bridge (if any). */ 1121 result = true; 1122 for (int i = 0; i < devcount; i++) { 1123 if (devs[i] == hostb || devs[i] == sc->dev) 1124 continue; 1125 1126 if (!device_is_attached(devs[i])) 1127 continue; 1128 1129 if (device_is_suspended(devs[i])) 1130 continue; 1131 1132 /* Active device; assume SPROM is busy */ 1133 result = false; 1134 break; 1135 } 1136 1137 free(devs, M_TEMP); 1138 bus_topo_unlock(); 1139 return (result); 1140 } 1141 1142 static int 1143 chipc_enable_sprom(device_t dev) 1144 { 1145 struct chipc_softc *sc; 1146 int error; 1147 1148 sc = device_get_softc(dev); 1149 CHIPC_LOCK(sc); 1150 1151 /* Already enabled? */ 1152 if (sc->sprom_refcnt >= 1) { 1153 sc->sprom_refcnt++; 1154 CHIPC_UNLOCK(sc); 1155 1156 return (0); 1157 } 1158 1159 switch (sc->caps.nvram_src) { 1160 case BHND_NVRAM_SRC_SPROM: 1161 error = chipc_enable_sprom_pins(sc); 1162 break; 1163 case BHND_NVRAM_SRC_OTP: 1164 error = chipc_enable_otp_power(sc); 1165 break; 1166 default: 1167 error = 0; 1168 break; 1169 } 1170 1171 /* Bump the reference count */ 1172 if (error == 0) 1173 sc->sprom_refcnt++; 1174 1175 CHIPC_UNLOCK(sc); 1176 return (error); 1177 } 1178 1179 static void 1180 chipc_disable_sprom(device_t dev) 1181 { 1182 struct chipc_softc *sc; 1183 1184 sc = device_get_softc(dev); 1185 CHIPC_LOCK(sc); 1186 1187 /* Check reference count, skip disable if in-use. */ 1188 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1189 sc->sprom_refcnt--; 1190 if (sc->sprom_refcnt > 0) { 1191 CHIPC_UNLOCK(sc); 1192 return; 1193 } 1194 1195 switch (sc->caps.nvram_src) { 1196 case BHND_NVRAM_SRC_SPROM: 1197 chipc_disable_sprom_pins(sc); 1198 break; 1199 case BHND_NVRAM_SRC_OTP: 1200 chipc_disable_otp_power(sc); 1201 break; 1202 default: 1203 break; 1204 } 1205 1206 CHIPC_UNLOCK(sc); 1207 } 1208 1209 static int 1210 chipc_enable_otp_power(struct chipc_softc *sc) 1211 { 1212 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1213 // OTPS_READY to be set in `optstatus`. 1214 return (0); 1215 } 1216 1217 static void 1218 chipc_disable_otp_power(struct chipc_softc *sc) 1219 { 1220 // TODO: Disable OTP resource via PMU 1221 } 1222 1223 /** 1224 * If required by this device, enable access to the SPROM. 1225 * 1226 * @param sc chipc driver state. 1227 */ 1228 static int 1229 chipc_enable_sprom_pins(struct chipc_softc *sc) 1230 { 1231 uint32_t cctrl; 1232 1233 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1234 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1235 1236 /* Nothing to do? */ 1237 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1238 return (0); 1239 1240 /* Check whether bus is busy */ 1241 if (!chipc_should_enable_muxed_sprom(sc)) 1242 return (EBUSY); 1243 1244 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1245 1246 /* 4331 devices */ 1247 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1248 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1249 1250 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1251 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1252 1253 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1254 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1255 1256 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1257 return (0); 1258 } 1259 1260 /* 4360 devices */ 1261 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1262 /* Unimplemented */ 1263 } 1264 1265 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1266 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1267 return (ENXIO); 1268 } 1269 1270 /** 1271 * If required by this device, revert any GPIO/pin configuration applied 1272 * to allow SPROM access. 1273 * 1274 * @param sc chipc driver state. 1275 */ 1276 static void 1277 chipc_disable_sprom_pins(struct chipc_softc *sc) 1278 { 1279 uint32_t cctrl; 1280 1281 /* Nothing to do? */ 1282 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1283 return; 1284 1285 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1286 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1287 1288 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1289 1290 /* 4331 devices */ 1291 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1292 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1293 1294 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1295 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1296 1297 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1298 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1299 1300 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1301 return; 1302 } 1303 1304 /* 4360 devices */ 1305 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1306 /* Unimplemented */ 1307 } 1308 } 1309 1310 static uint32_t 1311 chipc_read_chipst(device_t dev) 1312 { 1313 struct chipc_softc *sc = device_get_softc(dev); 1314 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1315 } 1316 1317 static void 1318 chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1319 { 1320 struct chipc_softc *sc; 1321 uint32_t cctrl; 1322 1323 sc = device_get_softc(dev); 1324 1325 CHIPC_LOCK(sc); 1326 1327 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1328 cctrl = (cctrl & ~mask) | (value | mask); 1329 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1330 1331 CHIPC_UNLOCK(sc); 1332 } 1333 1334 static struct chipc_caps * 1335 chipc_get_caps(device_t dev) 1336 { 1337 struct chipc_softc *sc; 1338 1339 sc = device_get_softc(dev); 1340 return (&sc->caps); 1341 } 1342 1343 static device_method_t chipc_methods[] = { 1344 /* Device interface */ 1345 DEVMETHOD(device_probe, chipc_probe), 1346 DEVMETHOD(device_attach, chipc_attach), 1347 DEVMETHOD(device_detach, chipc_detach), 1348 DEVMETHOD(device_suspend, chipc_suspend), 1349 DEVMETHOD(device_resume, chipc_resume), 1350 1351 /* Bus interface */ 1352 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1353 DEVMETHOD(bus_print_child, chipc_print_child), 1354 1355 DEVMETHOD(bus_add_child, chipc_add_child), 1356 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1357 1358 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1359 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1360 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1361 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1362 DEVMETHOD(bus_release_resource, chipc_release_resource), 1363 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1364 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1365 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1366 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1367 DEVMETHOD(bus_get_rman, chipc_get_rman), 1368 1369 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1370 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1371 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1372 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1373 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1374 1375 /* BHND bus inteface */ 1376 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1377 1378 /* ChipCommon interface */ 1379 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1380 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1381 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1382 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1383 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1384 1385 DEVMETHOD_END 1386 }; 1387 1388 DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1389 EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, 0, 0, 1390 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1391 MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1392 MODULE_VERSION(bhnd_chipc, 1); 1393