xref: /freebsd/sys/dev/bhnd/bhndreg.h (revision 55141f2c8991b2a6adbf30bb0fe3e6cbc303f06d)
1 /*-
2  * SPDX-License-Identifier: ISC
3  *
4  * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org>
5  * Copyright (c) 2010 Broadcom Corporation
6  * All rights reserved.
7  *
8  * Portions of this file were derived from the sbchipc.h header contributed by
9  * Broadcom to to the Linux staging repository, as well as later revisions of
10  * sbchipc.h distributed with the Asus RT-N16 firmware source code release.
11  *
12  * Permission to use, copy, modify, and/or distribute this software for any
13  * purpose with or without fee is hereby granted, provided that the above
14  * copyright notice and this permission notice appear in all copies.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
17  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
18  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
19  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
20  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
21  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
22  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23  */
24 
25 #ifndef _BHND_BHNDREG_H_
26 #define _BHND_BHNDREG_H_
27 
28 /**
29  * The default address at which the ChipCommon core is mapped on all siba(4)
30  * devices, and most (all?) bcma(4) devices.
31  */
32 #define	BHND_DEFAULT_CHIPC_ADDR	0x18000000
33 
34 /**
35  * The standard size of a primary BHND_PORT_DEVICE or BHND_PORT_AGENT
36  * register block.
37  */
38 #define	BHND_DEFAULT_CORE_SIZE	0x1000
39 
40 /**
41  * The standard size of the siba(4) and bcma(4) enumeration space.
42  */
43 #define	BHND_DEFAULT_ENUM_SIZE	0x00100000
44 
45 /*
46  * Common per-core clock control/status register available on PMU-equipped
47  * devices.
48  *
49  * Clock Mode		Name	Description
50  * High Throughput	(HT)	Full bandwidth, low latency. Generally supplied
51  * 				from PLL.
52  * Active Low Power	(ALP)	Register access, low speed DMA.
53  * Idle Low Power	(ILP)	No interconnect activity, or if long latency
54  * 				is permitted.
55  */
56 #define BHND_CLK_CTL_ST			0x1e0		/**< clock control and status */
57 #define	BHND_CCS_FORCEALP		0x00000001	/**< force ALP request */
58 #define	BHND_CCS_FORCEHT		0x00000002	/**< force HT request */
59 #define	BHND_CCS_FORCEILP		0x00000004	/**< force ILP request */
60 #define	BHND_CCS_FORCE_MASK		0x0000000F
61 
62 #define	BHND_CCS_ALPAREQ		0x00000008	/**< ALP Avail Request */
63 #define	BHND_CCS_HTAREQ			0x00000010	/**< HT Avail Request */
64 #define	BHND_CCS_AREQ_MASK		0x00000018
65 
66 #define	BHND_CCS_FORCEHWREQOFF		0x00000020	/**< Force HW Clock Request Off */
67 
68 #define	BHND_CCS_ERSRC_REQ_MASK		0x00000700	/**< external resource requests */
69 #define	BHND_CCS_ERSRC_REQ_SHIFT	8
70 #define	BHND_CCS_ERSRC_MAX		2		/**< maximum ERSRC value (corresponding to bits 0-2) */
71 
72 #define	BHND_CCS_ALPAVAIL		0x00010000	/**< ALP is available */
73 #define	BHND_CCS_HTAVAIL		0x00020000	/**< HT is available */
74 #define	BHND_CCS_AVAIL_MASK		0x00030000
75 
76 #define	BHND_CCS_BP_ON_APL		0x00040000	/**< RO: Backplane is running on ALP clock */
77 #define	BHND_CCS_BP_ON_HT		0x00080000	/**< RO: Backplane is running on HT clock */
78 #define	BHND_CCS_ERSRC_STS_MASK		0x07000000	/**< external resource status */
79 #define	BHND_CCS_ERSRC_STS_SHIFT	24
80 
81 #define	BHND_CCS0_HTAVAIL		0x00010000	/**< HT avail in chipc and pcmcia on 4328a0 */
82 #define	BHND_CCS0_ALPAVAIL		0x00020000	/**< ALP avail in chipc and pcmcia on 4328a0 */
83 
84 #define BHND_CCS_GET_FLAG(_value, _flag)	\
85 	(((_value) & _flag) != 0)
86 #define	BHND_CCS_GET_BITS(_value, _field)	\
87 	(((_value) & _field ## _MASK) >> _field ## _SHIFT)
88 #define	BHND_CCS_SET_BITS(_value, _field)	\
89 	(((_value) << _field ## _SHIFT) & _field ## _MASK)
90 
91 #endif /* _BHND_BHNDREG_H_ */
92