1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2017 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by Landon Fuller 7 * under sponsorship from the FreeBSD Foundation. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer, 14 * without modification. 15 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 16 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 17 * redistribution must be conditioned upon including a substantially 18 * similar Disclaimer requirement for further binary redistribution. 19 * 20 * NO WARRANTY 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 24 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 25 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 26 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 29 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGES. 32 * 33 */ 34 35 #ifndef _BHND_BHNDB_PCIVAR_H_ 36 #define _BHND_BHNDB_PCIVAR_H_ 37 38 #include "bhndbvar.h" 39 40 /* 41 * bhndb(4) PCI driver subclass. 42 */ 43 44 DECLARE_CLASS(bhndb_pci_driver); 45 46 struct bhndb_pci_softc; 47 48 /* 49 * An interconnect-specific function implementing BHNDB_SET_WINDOW_ADDR 50 */ 51 typedef int (*bhndb_pci_set_regwin_t)(device_t dev, device_t pci_dev, 52 const struct bhndb_regwin *rw, bhnd_addr_t addr); 53 54 /** 55 * PCI/PCIe bridge-level device quirks 56 */ 57 enum { 58 /** No quirks */ 59 BHNDB_PCI_QUIRK_NONE = 0, 60 61 /** 62 * The core requires fixup of the BAR0 SROM shadow to point at the 63 * current PCI core. 64 */ 65 BHNDB_PCI_QUIRK_SRSH_WAR = (1<<0), 66 67 /** 68 * The PCI (rev <= 5) core does not provide interrupt status/mask 69 * registers; these siba-only devices require routing backplane 70 * interrupt flags via the SIBA_CFG0_INTVEC register. 71 */ 72 BHNDB_PCI_QUIRK_SIBA_INTVEC = (1<<1), 73 }; 74 75 /** bhndb_pci quirk table entry */ 76 struct bhndb_pci_quirk { 77 struct bhnd_chip_match chip_desc; /**< chip match descriptor */ 78 struct bhnd_core_match core_desc; /**< core match descriptor */ 79 uint32_t quirks; /**< quirk flags */ 80 }; 81 82 #define BHNDB_PCI_QUIRK(_rev, _flags) { \ 83 { BHND_MATCH_ANY }, \ 84 { BHND_MATCH_CORE_REV(_rev) }, \ 85 _flags, \ 86 } 87 88 #define BHNDB_PCI_QUIRK_END \ 89 { { BHND_MATCH_ANY }, { BHND_MATCH_ANY }, 0 } 90 91 #define BHNDB_PCI_IS_QUIRK_END(_q) \ 92 (BHND_MATCH_IS_ANY(&(_q)->core_desc) && \ 93 BHND_MATCH_IS_ANY(&(_q)->chip_desc) && \ 94 (_q)->quirks == 0) 95 96 /** bhndb_pci core table entry */ 97 struct bhndb_pci_core { 98 struct bhnd_core_match match; /**< core match descriptor */ 99 struct bhndb_pci_quirk *quirks; /**< quirk table */ 100 }; 101 102 #define BHNDB_PCI_CORE(_device, _quirks) { \ 103 { BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_ ## _device) }, \ 104 _quirks \ 105 } 106 #define BHNDB_PCI_CORE_END { { BHND_MATCH_ANY }, NULL } 107 #define BHNDB_PCI_IS_CORE_END(_c) BHND_MATCH_IS_ANY(&(_c)->match) 108 109 struct bhndb_pci_softc { 110 struct bhndb_softc bhndb; /**< parent softc */ 111 device_t dev; /**< bridge device */ 112 device_t parent; /**< parent PCI device */ 113 bhnd_devclass_t pci_devclass; /**< PCI core's devclass */ 114 uint32_t pci_quirks; /**< PCI bridge-level quirks */ 115 int msi_count; /**< MSI count, or 0 */ 116 struct bhndb_intr_isrc *isrc; /**< host interrupt source */ 117 118 struct mtx mtx; 119 bhndb_pci_set_regwin_t set_regwin; /**< regwin handler */ 120 }; 121 122 #define BHNDB_PCI_LOCK_INIT(sc) \ 123 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 124 "bhndb_pc state", MTX_DEF) 125 #define BHNDB_PCI_LOCK(sc) mtx_lock(&(sc)->mtx) 126 #define BHNDB_PCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 127 #define BHNDB_PCI_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 128 #define BHNDB_PCI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 129 130 #endif /* _BHND_BHNDB_PCIVAR_H_ */ 131