1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _BHND_BHNDB_PCIVAR_H_ 33 #define _BHND_BHNDB_PCIVAR_H_ 34 35 #include <sys/stdint.h> 36 37 #include <dev/bhnd/cores/pci/bhnd_pcivar.h> 38 39 #include "bhndbvar.h" 40 41 /* 42 * bhndb(4) PCI driver subclass. 43 */ 44 45 DECLARE_CLASS(bhndb_pci_driver); 46 47 struct bhndb_pci_softc; 48 49 /* 50 * An interconnect-specific function implementing BHNDB_SET_WINDOW_ADDR 51 */ 52 typedef int (*bhndb_pci_set_regwin_t)(struct bhndb_pci_softc *sc, 53 const struct bhndb_regwin *rw, bhnd_addr_t addr); 54 55 56 /** 57 * PCI bridge core identification table. 58 */ 59 struct bhndb_pci_id { 60 uint16_t device; /**< bhnd device ID */ 61 bhnd_pci_regfmt_t regfmt; /**< register format */ 62 struct bhnd_device_quirk *quirks; /**< quirks table */ 63 }; 64 65 struct bhndb_pci_softc { 66 struct bhndb_softc bhndb; /**< parent softc */ 67 device_t dev; /**< bridge device */ 68 bhnd_devclass_t pci_devclass; /**< PCI core's devclass */ 69 bhndb_pci_set_regwin_t set_regwin; /**< regwin handler */ 70 71 /* 72 * Initialized in BHNDB_INIT_FULL_CONFIG() 73 */ 74 75 device_t mdio; /**< PCIe MDIO device. NULL if not PCIe. */ 76 bhnd_pci_regfmt_t regfmt; /**< device register format */ 77 78 struct resource *mem_res; /**< pci core's registers (borrowed reference) */ 79 bus_size_t mem_off; /**< offset to the PCI core's registers within `mem_res` . */ 80 81 struct bhnd_resource bhnd_mem_res; /**< bhnd resource representation of mem_res. 82 this is a simple 'direct' resource mapping */ 83 84 uint32_t quirks; /**< BHNDB_PCI(E)_QUIRK flags */ 85 86 /** 87 * Driver state specific to BHNDB_PCIE_QUIRK_SDR9_POLARITY. 88 */ 89 struct { 90 /** 91 * PCIe SerDes RX polarity. 92 * 93 * Initialized to the PCIe link's RX polarity 94 * at attach time. This is used to restore the 95 * correct polarity on resume */ 96 bool inv; 97 } sdr9_quirk_polarity; 98 }; 99 100 /* 101 * PCI/PCIe-Gen1 endpoint-mode device quirks 102 */ 103 enum { 104 /** No quirks */ 105 BHNDB_PCI_QUIRK_NONE = 0, 106 107 /** 108 * BCM4306 chips (and possibly others) do not support the idle 109 * low-power clock. Clocking must be bootstrapped at attach/resume by 110 * directly adjusting GPIO registers exposed in the PCI config space, 111 * and correspondingly, explicitly shutdown at detach/suspend. 112 */ 113 BHNDB_PCI_QUIRK_EXT_CLOCK_GATING = (1<<1), 114 115 /** 116 * SBTOPCI_PREF and SBTOPCI_BURST must be set on the 117 * SSB_PCICORE_SBTOPCI2 register. 118 */ 119 BHNDB_PCI_QUIRK_SBTOPCI2_PREF_BURST = (1<<2), 120 121 /** 122 * SBTOPCI_RC_READMULTI must be set on the SSB_PCICORE_SBTOPCI2 123 * register. 124 */ 125 BHNDB_PCI_QUIRK_SBTOPCI2_READMULTI = (1<<3), 126 127 /** 128 * Interrupt masking is handled via the interconnect configuration 129 * registers (SBINTVEC on siba), rather than the PCI_INT_MASK 130 * config register. 131 */ 132 BHNDB_PCI_QUIRK_SBINTVEC = (1<<4), 133 134 /** 135 * PCI CLKRUN# should be disabled on attach (via CLKRUN_DSBL). 136 * 137 * The purpose of this work-around is unclear; there is some 138 * documentation regarding earlier Broadcom drivers supporting 139 * a "force CLKRUN#" *enable* registry key for use on mobile 140 * hardware. 141 */ 142 BHNDB_PCI_QUIRK_CLKRUN_DSBL = (1<<5), 143 144 /** 145 * TLP workaround for unmatched address handling is required. 146 * 147 * This TLP workaround will enable setting of the PCIe UR status bit 148 * on memory access to an unmatched address. 149 */ 150 BHNDB_PCIE_QUIRK_UR_STATUS_FIX = (1<<6), 151 152 /** 153 * PCI-PM power management must be explicitly enabled via 154 * the data link control register. 155 */ 156 BHNDB_PCIE_QUIRK_PCIPM_REQEN = (1<<7), 157 158 /** 159 * Fix L0s to L0 exit transition on SerDes <= rev9 devices. 160 * 161 * On these devices, PCIe/SerDes symbol lock can be lost if the 162 * reference clock has not fully stabilized during the L0s to L0 163 * exit transition, triggering an internal reset of the chip. 164 * 165 * The SerDes RX CDR phase lock timers and proportional/integral 166 * filters must be tweaked to ensure the CDR has fully stabilized 167 * before asserting receive sequencer completion. 168 */ 169 BHNDB_PCIE_QUIRK_SDR9_L0s_HANG = (1<<8), 170 171 /** 172 * The idle time for entering L1 low-power state must be 173 * explicitly set (to 114ns) to fix slow L1->L0 transition issues. 174 */ 175 BHNDB_PCIE_QUIRK_L1_IDLE_THRESH = (1<<9), 176 177 /** 178 * The ASPM L1 entry timer should be extended for better performance, 179 * and restored for better power savings. 180 */ 181 BHNDB_PCIE_QUIRK_L1_TIMER_PERF = (1<<10), 182 183 /** 184 * ASPM and ECPM settings must be overridden manually. 185 * 186 * The override behavior is controlled by the BHND_BFL2_PCIEWAR_OVR 187 * flag. If this flag is set, ASPM/CLKREQ should be overridden as 188 * enabled; otherwise, they should be overridden as disabled. 189 * 190 * Attach/Resume: 191 * - Set SRSH_ASPM_ENB flag in the SPROM ASPM register. 192 * - Set ASPM L0S/L1 in the PCIER_LINK_CTL register. 193 * - Set SRSH_CLKREQ_ENB flag in the SPROM CLKREQ_REV5 register. 194 * - Clear ECPM in the PCIER_LINK_CTL register. 195 * 196 * Detach/Suspend: 197 * - 198 * - When the device enters D3 state, or system enters S3/S4 state, 199 * clear ASPM L1 in the PCIER_LINK_CTL register. 200 */ 201 BHNDB_PCIE_QUIRK_ASPM_OVR = (1<<11), 202 203 /** 204 * Fix SerDes polarity on SerDes <= rev9 devices. 205 * 206 * The SerDes polarity must be saved at device attachment, and 207 * restored on suspend/resume. 208 */ 209 BHNDB_PCIE_QUIRK_SDR9_POLARITY = (1<<12), 210 211 /** 212 * The SerDes PLL override flag (CHIPCTRL_4321_PLL_DOWN) must be set on 213 * the ChipCommon core on resume. 214 */ 215 BHNDB_PCIE_QUIRK_SERDES_NOPLLDOWN = (1<<13), 216 217 /** 218 * On attach and resume, consult the SPROM to determine whether 219 * the L2/L3-Ready w/o PCI RESET work-around must be applied. 220 * 221 * If L23READY_EXIT_NOPRST is not already set in the SPROM, set it 222 */ 223 BHNDB_PCIE_QUIRK_SPROM_L23_PCI_RESET = (1<<14), 224 225 /** 226 * The PCIe SerDes supports non-standard extended MDIO register access. 227 * 228 * The PCIe SerDes supports access to extended MDIO registers via 229 * a non-standard Clause 22 address extension mechanism. 230 */ 231 BHNDB_PCIE_QUIRK_SD_C22_EXTADDR = (1<<15), 232 233 /** 234 * The PCIe SerDes PLL must be configured to not retry the startup 235 * sequence upon frequency detection failure on SerDes <= rev9 devices 236 * 237 * The issue this workaround resolves has not be determined. 238 */ 239 BHNDB_PCIE_QUIRK_SDR9_NO_FREQRETRY = (1<<16), 240 }; 241 242 #endif /* _BHND_BHNDB_PCIVAR_H_ */