14ad7e9b0SAdrian Chadd /*- 2caeff9a3SLandon J. Fuller * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3caeff9a3SLandon J. Fuller * Copyright (c) 2017 The FreeBSD Foundation 44ad7e9b0SAdrian Chadd * All rights reserved. 54ad7e9b0SAdrian Chadd * 6caeff9a3SLandon J. Fuller * Portions of this software were developed by Landon Fuller 7caeff9a3SLandon J. Fuller * under sponsorship from the FreeBSD Foundation. 8caeff9a3SLandon J. Fuller * 94ad7e9b0SAdrian Chadd * Redistribution and use in source and binary forms, with or without 104ad7e9b0SAdrian Chadd * modification, are permitted provided that the following conditions 114ad7e9b0SAdrian Chadd * are met: 124ad7e9b0SAdrian Chadd * 1. Redistributions of source code must retain the above copyright 134ad7e9b0SAdrian Chadd * notice, this list of conditions and the following disclaimer, 144ad7e9b0SAdrian Chadd * without modification. 154ad7e9b0SAdrian Chadd * 2. Redistributions in binary form must reproduce at minimum a disclaimer 164ad7e9b0SAdrian Chadd * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 174ad7e9b0SAdrian Chadd * redistribution must be conditioned upon including a substantially 184ad7e9b0SAdrian Chadd * similar Disclaimer requirement for further binary redistribution. 194ad7e9b0SAdrian Chadd * 204ad7e9b0SAdrian Chadd * NO WARRANTY 214ad7e9b0SAdrian Chadd * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 224ad7e9b0SAdrian Chadd * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 234ad7e9b0SAdrian Chadd * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 244ad7e9b0SAdrian Chadd * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 254ad7e9b0SAdrian Chadd * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 264ad7e9b0SAdrian Chadd * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 274ad7e9b0SAdrian Chadd * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 284ad7e9b0SAdrian Chadd * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 294ad7e9b0SAdrian Chadd * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 304ad7e9b0SAdrian Chadd * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 314ad7e9b0SAdrian Chadd * THE POSSIBILITY OF SUCH DAMAGES. 324ad7e9b0SAdrian Chadd * 334ad7e9b0SAdrian Chadd */ 344ad7e9b0SAdrian Chadd 354ad7e9b0SAdrian Chadd #ifndef _BHND_BHNDB_PCIVAR_H_ 364ad7e9b0SAdrian Chadd #define _BHND_BHNDB_PCIVAR_H_ 374ad7e9b0SAdrian Chadd 384ad7e9b0SAdrian Chadd #include "bhndbvar.h" 394ad7e9b0SAdrian Chadd 404ad7e9b0SAdrian Chadd /* 414ad7e9b0SAdrian Chadd * bhndb(4) PCI driver subclass. 424ad7e9b0SAdrian Chadd */ 434ad7e9b0SAdrian Chadd 444ad7e9b0SAdrian Chadd DECLARE_CLASS(bhndb_pci_driver); 454ad7e9b0SAdrian Chadd 464ad7e9b0SAdrian Chadd struct bhndb_pci_softc; 474ad7e9b0SAdrian Chadd 484ad7e9b0SAdrian Chadd /* 494ad7e9b0SAdrian Chadd * An interconnect-specific function implementing BHNDB_SET_WINDOW_ADDR 504ad7e9b0SAdrian Chadd */ 5189294a78SLandon J. Fuller typedef int (*bhndb_pci_set_regwin_t)(device_t dev, device_t pci_dev, 524ad7e9b0SAdrian Chadd const struct bhndb_regwin *rw, bhnd_addr_t addr); 534ad7e9b0SAdrian Chadd 54caeff9a3SLandon J. Fuller /** 55caeff9a3SLandon J. Fuller * PCI/PCIe bridge-level device quirks 56caeff9a3SLandon J. Fuller */ 57caeff9a3SLandon J. Fuller enum { 58caeff9a3SLandon J. Fuller /** No quirks */ 59caeff9a3SLandon J. Fuller BHNDB_PCI_QUIRK_NONE = 0, 60caeff9a3SLandon J. Fuller 61caeff9a3SLandon J. Fuller /** 62caeff9a3SLandon J. Fuller * The core requires fixup of the BAR0 SROM shadow to point at the 63caeff9a3SLandon J. Fuller * current PCI core. 64caeff9a3SLandon J. Fuller */ 65caeff9a3SLandon J. Fuller BHNDB_PCI_QUIRK_SRSH_WAR = (1<<0), 66caeff9a3SLandon J. Fuller 67caeff9a3SLandon J. Fuller /** 68caeff9a3SLandon J. Fuller * The PCI (rev <= 5) core does not provide interrupt status/mask 69caeff9a3SLandon J. Fuller * registers; these siba-only devices require routing backplane 70caeff9a3SLandon J. Fuller * interrupt flags via the SIBA_CFG0_INTVEC register. 71caeff9a3SLandon J. Fuller */ 72caeff9a3SLandon J. Fuller BHNDB_PCI_QUIRK_SIBA_INTVEC = (1<<1), 73824b48efSLandon J. Fuller }; 74824b48efSLandon J. Fuller 75caeff9a3SLandon J. Fuller /** bhndb_pci quirk table entry */ 76caeff9a3SLandon J. Fuller struct bhndb_pci_quirk { 77caeff9a3SLandon J. Fuller struct bhnd_chip_match chip_desc; /**< chip match descriptor */ 78caeff9a3SLandon J. Fuller struct bhnd_core_match core_desc; /**< core match descriptor */ 79caeff9a3SLandon J. Fuller uint32_t quirks; /**< quirk flags */ 80caeff9a3SLandon J. Fuller }; 81caeff9a3SLandon J. Fuller 82caeff9a3SLandon J. Fuller #define BHNDB_PCI_QUIRK(_rev, _flags) { \ 83caeff9a3SLandon J. Fuller { BHND_MATCH_ANY }, \ 84caeff9a3SLandon J. Fuller { BHND_MATCH_CORE_REV(_rev) }, \ 85caeff9a3SLandon J. Fuller _flags, \ 86caeff9a3SLandon J. Fuller } 87caeff9a3SLandon J. Fuller 88caeff9a3SLandon J. Fuller #define BHNDB_PCI_QUIRK_END \ 89caeff9a3SLandon J. Fuller { { BHND_MATCH_ANY }, { BHND_MATCH_ANY }, 0 } 90caeff9a3SLandon J. Fuller 91caeff9a3SLandon J. Fuller #define BHNDB_PCI_IS_QUIRK_END(_q) \ 92caeff9a3SLandon J. Fuller (BHND_MATCH_IS_ANY(&(_q)->core_desc) && \ 93caeff9a3SLandon J. Fuller BHND_MATCH_IS_ANY(&(_q)->chip_desc) && \ 94caeff9a3SLandon J. Fuller (_q)->quirks == 0) 95caeff9a3SLandon J. Fuller 96caeff9a3SLandon J. Fuller /** bhndb_pci core table entry */ 97caeff9a3SLandon J. Fuller struct bhndb_pci_core { 98caeff9a3SLandon J. Fuller struct bhnd_core_match match; /**< core match descriptor */ 99caeff9a3SLandon J. Fuller struct bhndb_pci_quirk *quirks; /**< quirk table */ 100caeff9a3SLandon J. Fuller }; 101caeff9a3SLandon J. Fuller 102*84d6a5d4SLandon J. Fuller #define BHNDB_PCI_CORE(_device, _quirks) { \ 103caeff9a3SLandon J. Fuller { BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_ ## _device) }, \ 104caeff9a3SLandon J. Fuller _quirks \ 105caeff9a3SLandon J. Fuller } 106*84d6a5d4SLandon J. Fuller #define BHNDB_PCI_CORE_END { { BHND_MATCH_ANY }, NULL } 107caeff9a3SLandon J. Fuller #define BHNDB_PCI_IS_CORE_END(_c) BHND_MATCH_IS_ANY(&(_c)->match) 108caeff9a3SLandon J. Fuller 1094ad7e9b0SAdrian Chadd struct bhndb_pci_softc { 1104ad7e9b0SAdrian Chadd struct bhndb_softc bhndb; /**< parent softc */ 1114ad7e9b0SAdrian Chadd device_t dev; /**< bridge device */ 112e83ce340SAdrian Chadd device_t parent; /**< parent PCI device */ 1134ad7e9b0SAdrian Chadd bhnd_devclass_t pci_devclass; /**< PCI core's devclass */ 114caeff9a3SLandon J. Fuller uint32_t pci_quirks; /**< PCI bridge-level quirks */ 115caeff9a3SLandon J. Fuller int msi_count; /**< MSI count, or 0 */ 116caeff9a3SLandon J. Fuller struct bhndb_intr_isrc *isrc; /**< host interrupt source */ 117824b48efSLandon J. Fuller 118caeff9a3SLandon J. Fuller struct mtx mtx; 1194ad7e9b0SAdrian Chadd bhndb_pci_set_regwin_t set_regwin; /**< regwin handler */ 1204ad7e9b0SAdrian Chadd }; 1214ad7e9b0SAdrian Chadd 122caeff9a3SLandon J. Fuller #define BHNDB_PCI_LOCK_INIT(sc) \ 123caeff9a3SLandon J. Fuller mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \ 124caeff9a3SLandon J. Fuller "bhndb_pc state", MTX_DEF) 125caeff9a3SLandon J. Fuller #define BHNDB_PCI_LOCK(sc) mtx_lock(&(sc)->mtx) 126caeff9a3SLandon J. Fuller #define BHNDB_PCI_UNLOCK(sc) mtx_unlock(&(sc)->mtx) 127caeff9a3SLandon J. Fuller #define BHNDB_PCI_LOCK_ASSERT(sc, what) mtx_assert(&(sc)->mtx, what) 128caeff9a3SLandon J. Fuller #define BHNDB_PCI_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx) 129caeff9a3SLandon J. Fuller 1304ad7e9b0SAdrian Chadd #endif /* _BHND_BHNDB_PCIVAR_H_ */ 131