1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2010 Broadcom Corporation 4 * 5 * Portions of this file were derived from the bcmdevs.h header contributed by 6 * Broadcom to Android's bcmdhd driver module, and the pcicfg.h header 7 * distributed with Broadcom's initial brcm80211 Linux driver release. 8 * 9 * Permission to use, copy, modify, and/or distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 16 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 18 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 19 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 * 21 */ 22 23 #ifndef _BHND_BHNDB_PCIREG_H_ 24 #define _BHND_BHNDB_PCIREG_H_ 25 26 /* 27 * Common PCI/PCIE Bridge Configuration Registers. 28 * 29 * = MAJOR CORE REVISIONS = 30 * 31 * There have been four revisions to the BAR0 memory mappings used 32 * in BHND PCI/PCIE bridge cores: 33 * 34 * == PCI_V0 == 35 * Applies to: 36 * - PCI (cid=0x804, revision <= 12) 37 * BAR0 size: 8KB 38 * Address Map: 39 * [offset+ size] type description 40 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 41 * [0x1000+0x0800] fixed SPROM shadow 42 * [0x1800+0x0E00] fixed pci core device registers 43 * [0x1E00+0x0200] fixed pci core siba config registers 44 * 45 * == PCI_V1 == 46 * Applies to: 47 * - PCI (cid=0x804, revision >= 13) 48 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 49 * BAR0 size: 16KB 50 * Address Map: 51 * [offset+ size] type description 52 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 53 * [0x1000+0x1000] fixed SPROM shadow 54 * [0x2000+0x1000] fixed pci/pcie core registers 55 * [0x3000+0x1000] fixed chipcommon core registers 56 * 57 * == PCI_V2 == 58 * Applies to: 59 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 60 * BAR0 size: 16KB 61 * Address Map: 62 * [offset+ size] type description 63 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 64 * [0x1000+0x1000] dynamic mapped backplane address space (window 1). 65 * [0x2000+0x1000] fixed pci/pcie core registers 66 * [0x3000+0x1000] fixed chipcommon core registers 67 * 68 * == PCI_V3 == 69 * Applies to: 70 * - PCIE Gen 2 (cid=0x83c) 71 * BAR0 size: 32KB 72 * Address Map: 73 * [offset+ size] type description 74 * [0x0000+0x1000] dynamic mapped backplane address space (window 0). 75 * [0x1000+0x1000] dynamic mapped backplane address space (window 1). 76 * [0x2000+0x1000] fixed pci/pcie core registers 77 * [0x3000+0x1000] fixed chipcommon core registers 78 * [???] 79 * BAR1 size: varies 80 * Address Map: 81 * [offset+ size] type description 82 * [0x0000+0x????] fixed ARM tightly-coupled memory (TCM). 83 * While fullmac chipsets provided a fixed 84 * 4KB mapping, newer devices will vary. 85 * 86 * = MINOR CORE REVISIONS = 87 * 88 * == PCI Cores Revision >= 3 == 89 * - Mapped GPIO CSRs into the PCI config space. Refer to 90 * BHND_PCI_GPIO_*. 91 * 92 * == PCI/PCIE Cores Revision >= 14 == 93 * - Mapped the clock CSR into the PCI config space. Refer to 94 * BHND_PCI_CLK_CTL_ST 95 */ 96 97 /* Common PCI/PCIE Config Registers */ 98 #define BHNDB_PCI_SPROM_CONTROL 0x88 /* sprom property control */ 99 #define BHNDB_PCI_BAR1_CONTROL 0x8c /* BAR1 region prefetch/burst control */ 100 #define BHNDB_PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */ 101 #define BHNDB_PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */ 102 #define BHNDB_PCI_TO_SB_MB 0x98 /* signal backplane interrupts */ 103 #define BHNDB_PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */ 104 #define BHNDB_PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */ 105 106 /* PCI (non-PCIe) GPIO/Clock Config Registers */ 107 #define BHNDB_PCI_CLK_CTL 0xa8 /* clock control/status (pci >=rev14) */ 108 #define BHNDB_PCI_GPIO_IN 0xb0 /* gpio input (pci >=rev3) */ 109 #define BHNDB_PCI_GPIO_OUT 0xb4 /* gpio output (pci >=rev3) */ 110 #define BHNDB_PCI_GPIO_OUTEN 0xb8 /* gpio output enable (pci >=rev3) */ 111 112 /* Hardware revisions used to determine PCI revision */ 113 #define BHNDB_PCI_V0_MAX_PCI_HWREV 12 114 #define BHNDB_PCI_V1_MIN_PCI_HWREV 13 115 #define BHNDB_PCI_V1_MAX_CHIPC_HWREV 31 116 #define BHNDB_PCI_V2_MIN_CHIPC_HWREV 32 117 118 /** 119 * Number of times to retry writing to a PCI window address register. 120 * 121 * On siba(4) devices, it's possible that writing a PCI window register may 122 * not succeed; it's necessary to immediately read the configuration register 123 * and retry if not set to the desired value. 124 */ 125 #define BHNDB_PCI_BARCTRL_WRITE_RETRY 50 126 127 /* PCI_V0 */ 128 #define BHNDB_PCI_V0_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 129 #define BHNDB_PCI_V0_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 130 131 #define BHNDB_PCI_V0_BAR0_SIZE 0x2000 /* 8KB BAR0 */ 132 #define BHNDB_PCI_V0_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 133 #define BHNDB_PCI_V0_BAR0_WIN0_SIZE 0x1000 134 #define BHNDB_PCI_V0_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */ 135 #define BHNDB_PCI_V0_BAR0_SPROM_SIZE 0x0800 136 #define BHNDB_PCI_V0_BAR0_PCIREG_OFFSET 0x1800 /* bar0 + 6K accesses pci core registers (not including SSB CFG registers) */ 137 #define BHNDB_PCI_V0_BAR0_PCIREG_SIZE 0x0E00 138 #define BHNDB_PCI_V0_BAR0_PCISB_OFFSET 0x1E00 /* bar0 + 7.5K accesses pci core's SSB CFG register blocks */ 139 #define BHNDB_PCI_V0_BAR0_PCISB_SIZE 0x0200 140 #define BHNDB_PCI_V0_BAR0_PCISB_COREOFF 0xE00 /* mapped offset relative to the core base address */ 141 142 /* PCI_V1 */ 143 #define BHNDB_PCI_V1_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 144 #define BHNDB_PCI_V1_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 145 146 #define BHNDB_PCI_V1_BAR0_SIZE 0x4000 /* 16KB BAR0 */ 147 #define BHNDB_PCI_V1_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 148 #define BHNDB_PCI_V1_BAR0_WIN0_SIZE 0x1000 149 #define BHNDB_PCI_V1_BAR0_SPROM_OFFSET 0x1000 /* bar0 + 4K accesses sprom shadow (in pci core) */ 150 #define BHNDB_PCI_V1_BAR0_SPROM_SIZE 0x1000 151 #define BHNDB_PCI_V1_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 152 #define BHNDB_PCI_V1_BAR0_PCIREG_SIZE 0x1000 153 #define BHNDB_PCI_V1_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 154 #define BHNDB_PCI_V1_BAR0_CCREGS_SIZE 0x1000 155 156 /* PCI_V2 */ 157 #define BHNDB_PCI_V2_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 158 #define BHNDB_PCI_V2_BAR1_WIN0_CONTROL 0x84 /* backplane address space accessed by BAR1/WIN0. */ 159 #define BHNDB_PCI_V2_BAR0_WIN1_CONTROL 0xAC /* backplane address space accessed by BAR0/WIN1 */ 160 161 #define BHNDB_PCI_V2_BAR0_SIZE 0x4000 /* 16KB BAR0 */ 162 #define BHNDB_PCI_V2_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 163 #define BHNDB_PCI_V2_BAR0_WIN0_SIZE 0x1000 164 #define BHNDB_PCI_V2_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ 165 #define BHNDB_PCI_V2_BAR0_WIN1_SIZE 0x1000 166 #define BHNDB_PCI_V2_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 167 #define BHNDB_PCI_V2_BAR0_PCIREG_SIZE 0x1000 168 #define BHNDB_PCI_V2_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 169 #define BHNDB_PCI_V2_BAR0_CCREGS_SIZE 0x1000 170 171 /* PCI_V3 (PCIe-G2) */ 172 #define BHNDB_PCI_V3_BAR0_WIN0_CONTROL 0x80 /* backplane address space accessed by BAR0/WIN0 */ 173 #define BHNDB_PCI_V3_BAR0_WIN1_CONTROL 0x70 /* backplane address space accessed by BAR0/WIN1 */ 174 175 #define BHNDB_PCI_V3_BAR0_SIZE 0x8000 /* 32KB BAR0 */ 176 #define BHNDB_PCI_V3_BAR0_WIN0_OFFSET 0x0 /* bar0 + 0x0 accesses configurable 4K region of backplane address space */ 177 #define BHNDB_PCI_V3_BAR0_WIN0_SIZE 0x1000 178 #define BHNDB_PCI_V3_BAR0_WIN1_OFFSET 0x1000 /* bar0 + 4K accesses second 4K window */ 179 #define BHNDB_PCI_V3_BAR0_WIN1_SIZE 0x1000 180 #define BHNDB_PCI_V3_BAR0_PCIREG_OFFSET 0x2000 /* bar0 + 8K accesses pci/pcie core registers */ 181 #define BHNDB_PCI_V3_BAR0_PCIREG_SIZE 0x1000 182 #define BHNDB_PCI_V3_BAR0_CCREGS_OFFSET 0x3000 /* bar0 + 12K accesses chipc core registers */ 183 #define BHNDB_PCI_V3_BAR0_CCREGS_SIZE 0x1000 184 185 /* BHNDB_PCI_INT_STATUS */ 186 #define BHNDB_PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */ 187 188 /* BHNDB_PCI_INT_MASK */ 189 #define BHNDB_PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */ 190 #define BHNDB_PCI_SBIM_COREIDX_MAX 15 /**< maximum representible core index (in 16 bit field) */ 191 #define BHNDB_PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */ 192 #define BHNDB_PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */ 193 194 /* BHNDB_PCI_SPROM_CONTROL */ 195 #define BHNDB_PCI_SPROM_SZ_MASK 0x03 /**< sprom size mask */ 196 #define BHNDB_PCI_SPROM_SZ_1KB 0x00 /**< 1KB sprom size */ 197 #define BHNDB_PCI_SPROM_SZ_4KB 0x01 /**< 4KB sprom size */ 198 #define BHNDB_PCI_SPROM_SZ_16KB 0x02 /**< 16KB sprom size */ 199 #define BHNDB_PCI_SPROM_SZ_RESERVED 0x03 /**< unsupported sprom size */ 200 #define BHNDB_PCI_SPROM_LOCKED 0x08 /**< sprom locked */ 201 #define BHNDB_PCI_SPROM_BLANK 0x04 /**< sprom blank */ 202 #define BHNDB_PCI_SPROM_WRITEEN 0x10 /**< sprom write enable */ 203 #define BHNDB_PCI_SPROM_BOOTROM_WE 0x20 /**< external bootrom write enable */ 204 #define BHNDB_PCI_SPROM_BACKPLANE_EN 0x40 /**< enable indirect backplane access (BHNDB_PCI_BACKPLANE_*) */ 205 #define BHNDB_PCI_SPROM_OTPIN_USE 0x80 /**< device OTP in use */ 206 207 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN */ 208 #define BHNDB_PCI_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */ 209 #define BHNDB_PCI_GPIO_HWRAD_OFF 0x20 /* PCI config space GPIO 13 for hw radio disable */ 210 #define BHNDB_PCI_GPIO_XTAL_ON 0x40 /* PCI config space GPIO 14 for Xtal power-up */ 211 #define BHNDB_PCI_GPIO_PLL_OFF 0x80 /* PCI config space GPIO 15 for PLL power-down */ 212 213 #endif /* _BHND_BHNDB_PCIREG_H_ */ 214