xref: /freebsd/sys/dev/bhnd/bhndb/bhndb_pcireg.h (revision 56e53cb8ef000c3ef72337a4095987a932cdedef)
1 /*-
2  * Copyright (c) 2015 Landon Fuller <landon@landonf.org>
3  * Copyright (c) 2010 Broadcom Corporation
4  *
5  * Portions of this file were derived from the bcmdevs.h header contributed by
6  * Broadcom to Android's bcmdhd driver module, and the pcicfg.h header
7  * distributed with Broadcom's initial brcm80211 Linux driver release.
8  *
9  * Permission to use, copy, modify, and/or distribute this software for any
10  * purpose with or without fee is hereby granted, provided that the above
11  * copyright notice and this permission notice appear in all copies.
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
16  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
18  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
19  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20  *
21  * $FreeBSD$
22  */
23 
24 #ifndef _BHND_BHNDB_PCIREG_H_
25 #define _BHND_BHNDB_PCIREG_H_
26 
27 /*
28  * Common PCI/PCIE Bridge Configuration Registers.
29  *
30  * = MAJOR CORE REVISIONS =
31  *
32  * There have been four revisions to the BAR0 memory mappings used
33  * in BHND PCI/PCIE bridge cores:
34  *
35  * == PCI_V0 ==
36  * Applies to:
37  * -  PCI (cid=0x804, revision <= 12)
38  * BAR0 size: 8KB
39  * Address Map:
40  *	[offset+  size]	type	description
41  * 	[0x0000+0x1000]	dynamic mapped backplane address space (window 0).
42  * 	[0x1000+0x0800]	fixed	SPROM shadow
43  * 	[0x1800+0x0E00]	fixed	pci core device registers
44  *	[0x1E00+0x0200]	fixed	pci core siba config registers
45  *
46  * == PCI_V1 ==
47  * Applies to:
48  * -  PCI (cid=0x804, revision >= 13)
49  * -  PCIE (cid=0x820) with ChipCommon (revision <= 31)
50  * BAR0 size: 16KB
51  * Address Map:
52  *	[offset+  size]	type	description
53  *	[0x0000+0x1000]	dynamic	mapped backplane address space (window 0).
54  *	[0x1000+0x1000]	fixed	SPROM shadow
55  *	[0x2000+0x1000]	fixed	pci/pcie core registers
56  *	[0x3000+0x1000]	fixed	chipcommon core registers
57  *
58  * == PCI_V2 ==
59  * Applies to:
60  * - PCIE (cid=0x820) with ChipCommon (revision >= 32)
61  * BAR0 size: 16KB
62  * Address Map:
63  *	[offset+  size]	type	description
64  *	[0x0000+0x1000]	dynamic	mapped backplane address space (window 0).
65  *	[0x1000+0x1000]	dynamic	mapped backplane address space (window 1).
66  *	[0x2000+0x1000]	fixed	pci/pcie core registers
67  *	[0x3000+0x1000]	fixed	chipcommon core registers
68  *
69  * == PCI_V3 ==
70  * Applies to:
71  * - PCIE Gen 2 (cid=0x83c)
72  * BAR0 size: 32KB
73  * Address Map:
74  *	[offset+  size]	type	description
75  *	[0x0000+0x1000]	dynamic	mapped backplane address space (window 0).
76  *	[0x1000+0x1000]	dynamic	mapped backplane address space (window 1).
77  *	[0x2000+0x1000]	fixed	pci/pcie core registers
78  *	[0x3000+0x1000]	fixed	chipcommon core registers
79  *	[???]
80  * BAR1 size: varies
81  * Address Map:
82  *	[offset+  size]	type	description
83  *	[0x0000+0x????]	fixed	ARM tightly-coupled memory (TCM).
84  *				While fullmac chipsets provided a fixed
85  *				4KB mapping, newer devices will vary.
86  *
87  * = MINOR CORE REVISIONS =
88  *
89  * == PCI Cores Revision >= 3 ==
90  * - Mapped GPIO CSRs into the PCI config space. Refer to
91  *   BHND_PCI_GPIO_*.
92  *
93  * == PCI/PCIE Cores Revision >= 14 ==
94  * - Mapped the clock CSR into the PCI config space. Refer to
95  *   BHND_PCI_CLK_CTL_ST
96  */
97 
98 /* Common PCI/PCIE Config Registers */
99 #define	BHNDB_PCI_SPROM_CONTROL		0x88	/* sprom property control */
100 #define	BHNDB_PCI_BAR1_CONTROL		0x8c	/* BAR1 region prefetch/burst control */
101 #define	BHNDB_PCI_INT_STATUS		0x90	/* PCI and other cores interrupts */
102 #define	BHNDB_PCI_INT_MASK		0x94	/* mask of PCI and other cores interrupts */
103 #define	BHNDB_PCI_TO_SB_MB		0x98	/* signal backplane interrupts */
104 #define	BHNDB_PCI_BACKPLANE_ADDR	0xa0	/* address an arbitrary location on the system backplane */
105 #define	BHNDB_PCI_BACKPLANE_DATA	0xa4	/* data at the location specified by above address */
106 
107 /* PCI (non-PCIe) GPIO/Clock Config Registers */
108 #define	BHNDB_PCI_CLK_CTL		0xa8	/* clock control/status (pci >=rev14) */
109 #define	BHNDB_PCI_GPIO_IN		0xb0	/* gpio input (pci >=rev3) */
110 #define	BHNDB_PCI_GPIO_OUT		0xb4	/* gpio output (pci >=rev3) */
111 #define	BHNDB_PCI_GPIO_OUTEN		0xb8	/* gpio output enable (pci >=rev3) */
112 
113 /* Hardware revisions used to determine PCI revision */
114 #define	BHNDB_PCI_V0_MAX_PCI_HWREV	12
115 #define	BHNDB_PCI_V1_MIN_PCI_HWREV	13
116 #define	BHNDB_PCI_V1_MAX_CHIPC_HWREV	31
117 #define	BHNDB_PCI_V2_MIN_CHIPC_HWREV	32
118 
119 /**
120  * Number of times to retry writing to a PCI window address register.
121  *
122  * On siba(4) devices, it's possible that writing a PCI window register may
123  * not succeed; it's necessary to immediately read the configuration register
124  * and retry if not set to the desired value.
125  */
126 #define	BHNDB_PCI_BARCTRL_WRITE_RETRY	50
127 
128 /* PCI_V0  */
129 #define	BHNDB_PCI_V0_BAR0_WIN0_CONTROL	0x80	/* backplane address space accessed by BAR0/WIN0 */
130 #define	BHNDB_PCI_V0_BAR1_WIN0_CONTROL	0x84	/* backplane address space accessed by BAR1/WIN0. */
131 
132 #define	BHNDB_PCI_V0_BAR0_SIZE		0x2000	/* 8KB BAR0 */
133 #define	BHNDB_PCI_V0_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplane address space */
134 #define	BHNDB_PCI_V0_BAR0_WIN0_SIZE	0x1000
135 #define	BHNDB_PCI_V0_BAR0_SPROM_OFFSET	0x1000	/* bar0 + 4K accesses sprom shadow (in pci core) */
136 #define BHNDB_PCI_V0_BAR0_SPROM_SIZE	0x0800
137 #define	BHNDB_PCI_V0_BAR0_PCIREG_OFFSET	0x1800	/* bar0 + 6K accesses pci core registers (not including SSB CFG registers) */
138 #define	BHNDB_PCI_V0_BAR0_PCIREG_SIZE	0x0E00
139 #define	BHNDB_PCI_V0_BAR0_PCISB_OFFSET	0x1E00	/* bar0 + 7.5K accesses pci core's SSB CFG register blocks */
140 #define	BHNDB_PCI_V0_BAR0_PCISB_SIZE	0x0200
141 #define	BHNDB_PCI_V0_BAR0_PCISB_COREOFF	0xE00	/* mapped offset relative to the core base address */
142 
143 /* PCI_V1 */
144 #define	BHNDB_PCI_V1_BAR0_WIN0_CONTROL	0x80	/* backplane address space accessed by BAR0/WIN0 */
145 #define	BHNDB_PCI_V1_BAR1_WIN0_CONTROL	0x84	/* backplane address space accessed by BAR1/WIN0. */
146 
147 #define	BHNDB_PCI_V1_BAR0_SIZE		0x4000	/* 16KB BAR0 */
148 #define	BHNDB_PCI_V1_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplane address space */
149 #define	BHNDB_PCI_V1_BAR0_WIN0_SIZE	0x1000
150 #define	BHNDB_PCI_V1_BAR0_SPROM_OFFSET	0x1000	/* bar0 + 4K accesses sprom shadow (in pci core) */
151 #define BHNDB_PCI_V1_BAR0_SPROM_SIZE	0x1000
152 #define	BHNDB_PCI_V1_BAR0_PCIREG_OFFSET	0x2000	/* bar0 + 8K accesses pci/pcie core registers */
153 #define	BHNDB_PCI_V1_BAR0_PCIREG_SIZE	0x1000
154 #define	BHNDB_PCI_V1_BAR0_CCREGS_OFFSET	0x3000	/* bar0 + 12K accesses chipc core registers */
155 #define	BHNDB_PCI_V1_BAR0_CCREGS_SIZE	0x1000
156 
157 /* PCI_V2 */
158 #define	BHNDB_PCI_V2_BAR0_WIN0_CONTROL	0x80	/* backplane address space accessed by BAR0/WIN0 */
159 #define	BHNDB_PCI_V2_BAR1_WIN0_CONTROL	0x84	/* backplane address space accessed by BAR1/WIN0. */
160 #define	BHNDB_PCI_V2_BAR0_WIN1_CONTROL	0xAC	/* backplane address space accessed by BAR0/WIN1 */
161 
162 #define	BHNDB_PCI_V2_BAR0_SIZE		0x4000	/* 16KB BAR0 */
163 #define	BHNDB_PCI_V2_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplane address space */
164 #define	BHNDB_PCI_V2_BAR0_WIN0_SIZE	0x1000
165 #define	BHNDB_PCI_V2_BAR0_WIN1_OFFSET	0x1000	/* bar0 + 4K accesses second 4K window */
166 #define BHNDB_PCI_V2_BAR0_WIN1_SIZE	0x1000
167 #define	BHNDB_PCI_V2_BAR0_PCIREG_OFFSET	0x2000	/* bar0 + 8K accesses pci/pcie core registers */
168 #define	BHNDB_PCI_V2_BAR0_PCIREG_SIZE	0x1000
169 #define	BHNDB_PCI_V2_BAR0_CCREGS_OFFSET	0x3000	/* bar0 + 12K accesses chipc core registers */
170 #define	BHNDB_PCI_V2_BAR0_CCREGS_SIZE	0x1000
171 
172 /* PCI_V3 (PCIe-G2) */
173 #define	BHNDB_PCI_V3_BAR0_WIN0_CONTROL	0x80	/* backplane address space accessed by BAR0/WIN0 */
174 #define BHNDB_PCI_V3_BAR0_WIN1_CONTROL	0x70	/* backplane address space accessed by BAR0/WIN1 */
175 
176 #define	BHNDB_PCI_V3_BAR0_SIZE		0x8000	/* 32KB BAR0 */
177 #define	BHNDB_PCI_V3_BAR0_WIN0_OFFSET	0x0	/* bar0 + 0x0 accesses configurable 4K region of backplane address space */
178 #define	BHNDB_PCI_V3_BAR0_WIN0_SIZE	0x1000
179 #define	BHNDB_PCI_V3_BAR0_WIN1_OFFSET	0x1000	/* bar0 + 4K accesses second 4K window */
180 #define BHNDB_PCI_V3_BAR0_WIN1_SIZE	0x1000
181 #define	BHNDB_PCI_V3_BAR0_PCIREG_OFFSET	0x2000	/* bar0 + 8K accesses pci/pcie core registers */
182 #define	BHNDB_PCI_V3_BAR0_PCIREG_SIZE	0x1000
183 #define	BHNDB_PCI_V3_BAR0_CCREGS_OFFSET	0x3000	/* bar0 + 12K accesses chipc core registers */
184 #define	BHNDB_PCI_V3_BAR0_CCREGS_SIZE	0x1000
185 
186 /* BHNDB_PCI_INT_STATUS */
187 #define	BHNDB_PCI_SBIM_STATUS_SERR	0x4	/* backplane SBErr interrupt status */
188 
189 /* BHNDB_PCI_INT_MASK */
190 #define	BHNDB_PCI_SBIM_SHIFT		8	/* backplane core interrupt mask bits offset */
191 #define	BHNDB_PCI_SBIM_COREIDX_MAX	15	/**< maximum representible core index (in 16 bit field) */
192 #define	BHNDB_PCI_SBIM_MASK		0xff00	/* backplane core interrupt mask */
193 #define	BHNDB_PCI_SBIM_MASK_SERR	0x4	/* backplane SBErr interrupt mask */
194 
195 /* BHNDB_PCI_SPROM_CONTROL */
196 #define	BHNDB_PCI_SPROM_SZ_MASK		0x03	/**< sprom size mask */
197 #define	BHNDB_PCI_SPROM_SZ_1KB		0x00	/**< 1KB sprom size */
198 #define	BHNDB_PCI_SPROM_SZ_4KB		0x01	/**< 4KB sprom size */
199 #define	BHNDB_PCI_SPROM_SZ_16KB		0x02	/**< 16KB sprom size */
200 #define	BHNDB_PCI_SPROM_SZ_RESERVED	0x03	/**< unsupported sprom size */
201 #define	BHNDB_PCI_SPROM_LOCKED		0x08	/**< sprom locked */
202 #define	BHNDB_PCI_SPROM_BLANK		0x04	/**< sprom blank */
203 #define	BHNDB_PCI_SPROM_WRITEEN		0x10	/**< sprom write enable */
204 #define	BHNDB_PCI_SPROM_BOOTROM_WE	0x20	/**< external bootrom write enable */
205 #define	BHNDB_PCI_SPROM_BACKPLANE_EN	0x40	/**< enable indirect backplane access (BHNDB_PCI_BACKPLANE_*) */
206 #define	BHNDB_PCI_SPROM_OTPIN_USE	0x80	/**< device OTP in use */
207 
208 
209 /* PCI (non-PCIe) BHNDB_PCI_GPIO_OUTEN  */
210 #define	BHNDB_PCI_GPIO_SCS		0x10	/* PCI config space bit 4 for 4306c0 slow clock source */
211 #define	BHNDB_PCI_GPIO_HWRAD_OFF		0x20	/* PCI config space GPIO 13 for hw radio disable */
212 #define	BHNDB_PCI_GPIO_XTAL_ON		0x40	/* PCI config space GPIO 14 for Xtal power-up */
213 #define	BHNDB_PCI_GPIO_PLL_OFF		0x80	/* PCI config space GPIO 15 for PLL power-down */
214 
215 #endif /* _BHND_BHNDB_PCIREG_H_ */
216