1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Resource specifications and register maps for Broadcom PCI/PCIe cores 35 * configured as PCI-BHND bridges. 36 */ 37 38 #include <sys/param.h> 39 #include <sys/bus.h> 40 41 #include <machine/bus.h> 42 #include <sys/rman.h> 43 #include <machine/resource.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 48 #include "bhndbvar.h" 49 #include "bhndb_pcireg.h" 50 51 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 52 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 53 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 54 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 55 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 56 57 /** 58 * Define a bhndb_hw match entry. 59 * 60 * @param _name The entry name. 61 * @param _vers The configuration version associated with this entry. 62 */ 63 #define BHNDB_HW_MATCH(_name, _vers, ...) { \ 64 .name = _name, \ 65 .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 66 .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 67 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 68 .cfg = &bhndb_pci_hwcfg_ ## _vers \ 69 } 70 71 #define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 72 73 /** 74 * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 75 * PCI devices; this configuration is adequate for enumerating a bridged 76 * siba(4) bus to determine the full hardware configuration. 77 * 78 * @par Compatibility 79 * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 80 * - Compatible with siba(4) bus enumeration. 81 * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 82 * at the default enumeration address (0x18000000). 83 */ 84 const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 85 .resource_specs = (const struct resource_spec[]) { 86 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 87 { -1, 0, 0 } 88 }, 89 90 .register_windows = (const struct bhndb_regwin[]) { 91 /* bar0+0x0000: configurable backplane window */ 92 { 93 .win_type = BHNDB_REGWIN_T_DYN, 94 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 95 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 96 .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 97 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 98 }, 99 BHNDB_REGWIN_TABLE_END 100 }, 101 }; 102 103 104 /** 105 * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 106 * PCI devices; this configuration is adequate for enumerating a bridged 107 * bcma(4) bus to determine the full hardware configuration. 108 * 109 * @par Compatibility 110 * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 111 * - Compatible with both siba(4) and bcma(4) bus enumeration. 112 */ 113 const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 114 .resource_specs = (const struct resource_spec[]) { 115 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 116 { -1, 0, 0 } 117 }, 118 119 .register_windows = (const struct bhndb_regwin[]) { 120 /* bar0+0x0000: configurable backplane window */ 121 { 122 .win_type = BHNDB_REGWIN_T_DYN, 123 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 124 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 125 .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 126 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 127 }, 128 129 /* bar0+0x3000: chipc core registers */ 130 { 131 .win_type = BHNDB_REGWIN_T_CORE, 132 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 133 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 134 .core = { 135 .class = BHND_DEVCLASS_CC, 136 .unit = 0, 137 .port = 0, 138 .region = 0, 139 .port_type = BHND_PORT_DEVICE 140 }, 141 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 142 }, 143 144 BHNDB_REGWIN_TABLE_END 145 }, 146 }; 147 148 /** 149 * Hardware configuration tables for Broadcom HND PCI NICs. 150 */ 151 const struct bhndb_hw bhndb_pci_generic_hw_table[] = { 152 /* PCI/V0 WLAN */ 153 BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 154 /* PCI Core */ 155 { 156 .vendor = BHND_MFGID_BCM, 157 .device = BHND_COREID_PCI, 158 .hwrev = { 159 .start = 0, 160 .end = BHNDB_PCI_V0_MAX_PCI_HWREV 161 }, 162 .class = BHND_DEVCLASS_PCI, 163 .unit = 0 164 }, 165 166 /* 802.11 Core */ 167 { 168 .vendor = BHND_MFGID_BCM, 169 .device = BHND_COREID_INVALID, 170 .hwrev = { 171 .start = 0, 172 .end = BHND_HWREV_INVALID 173 }, 174 .class = BHND_DEVCLASS_WLAN, 175 .unit = 0 176 } 177 ), 178 179 /* PCI/V1 WLAN */ 180 BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 181 /* PCI Core */ 182 { 183 .vendor = BHND_MFGID_BCM, 184 .device = BHND_COREID_PCI, 185 .hwrev = { 186 .start = BHNDB_PCI_V1_MIN_PCI_HWREV, 187 .end = BHND_HWREV_INVALID 188 }, 189 .class = BHND_DEVCLASS_PCI, 190 .unit = 0 191 }, 192 193 /* 802.11 Core */ 194 { 195 .vendor = BHND_MFGID_BCM, 196 .device = BHND_COREID_INVALID, 197 .hwrev = { 198 .start = 0, 199 .end = BHND_HWREV_INVALID 200 }, 201 .class = BHND_DEVCLASS_WLAN, 202 .unit = 0 203 } 204 ), 205 206 /* PCIE/V1 WLAN */ 207 BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 208 /* PCIe Core */ 209 { 210 .vendor = BHND_MFGID_BCM, 211 .device = BHND_COREID_PCIE, 212 .hwrev = { 213 .start = 0, 214 .end = BHND_HWREV_INVALID 215 }, 216 .class = BHND_DEVCLASS_PCIE, 217 .unit = 0 218 }, 219 220 /* ChipCommon (revision <= 31) */ 221 { 222 .vendor = BHND_MFGID_BCM, 223 .device = BHND_COREID_CC, 224 .hwrev = { 225 .start = 0, 226 .end = BHNDB_PCI_V1_MAX_CHIPC_HWREV 227 }, 228 .class = BHND_DEVCLASS_CC, 229 .unit = 0 230 }, 231 232 /* 802.11 Core */ 233 { 234 .vendor = BHND_MFGID_BCM, 235 .device = BHND_COREID_INVALID, 236 .hwrev = { 237 .start = 0, 238 .end = BHND_HWREV_INVALID 239 }, 240 .class = BHND_DEVCLASS_WLAN, 241 .unit = 0 242 } 243 ), 244 245 /* PCIE/V2 WLAN */ 246 BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 247 /* PCIe Core */ 248 { 249 .vendor = BHND_MFGID_BCM, 250 .device = BHND_COREID_PCIE, 251 .hwrev = { 0, BHND_HWREV_INVALID }, 252 .class = BHND_DEVCLASS_PCIE, 253 .unit = 0 254 }, 255 256 /* ChipCommon (revision >= 32) */ 257 { 258 .vendor = BHND_MFGID_BCM, 259 .device = BHND_COREID_CC, 260 .hwrev = { 261 .start = BHNDB_PCI_V2_MIN_CHIPC_HWREV, 262 .end = BHND_HWREV_INVALID 263 }, 264 .class = BHND_DEVCLASS_CC, 265 .unit = 0 266 }, 267 268 /* 802.11 Core */ 269 { 270 .vendor = BHND_MFGID_BCM, 271 .device = BHND_COREID_INVALID, 272 .hwrev = { 273 .start = 0, 274 .end = BHND_HWREV_INVALID 275 }, 276 .class = BHND_DEVCLASS_WLAN, 277 .unit = 0 278 } 279 ), 280 281 282 /* PCIE/V3 WLAN */ 283 BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 284 /* PCIe Gen2 Core */ 285 { 286 .vendor = BHND_MFGID_BCM, 287 .device = BHND_COREID_PCIE2, 288 .hwrev = { 289 .start = 0, 290 .end = BHND_HWREV_INVALID 291 }, 292 .class = BHND_DEVCLASS_PCIE, 293 .unit = 0 294 }, 295 296 /* 802.11 Core */ 297 { 298 .vendor = BHND_MFGID_BCM, 299 .device = BHND_COREID_INVALID, 300 .hwrev = { 301 .start = 0, 302 .end = BHND_HWREV_INVALID 303 }, 304 .class = BHND_DEVCLASS_WLAN, 305 .unit = 0 306 } 307 ), 308 309 { NULL, NULL, 0, NULL } 310 }; 311 312 /** 313 * PCI_V0 hardware configuration. 314 * 315 * Applies to: 316 * - PCI (cid=0x804, revision <= 12) 317 */ 318 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 319 .resource_specs = (const struct resource_spec[]) { 320 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 321 { -1, 0, 0 } 322 }, 323 324 .register_windows = (const struct bhndb_regwin[]) { 325 /* bar0+0x0000: configurable backplane window */ 326 { 327 .win_type = BHNDB_REGWIN_T_DYN, 328 .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 329 .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 330 .dyn.cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL, 331 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 332 }, 333 334 /* bar0+0x1000: sprom shadow */ 335 { 336 .win_type = BHNDB_REGWIN_T_SPROM, 337 .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 338 .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 339 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 340 }, 341 342 /* bar0+0x1800: pci core registers */ 343 { 344 .win_type = BHNDB_REGWIN_T_CORE, 345 .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 346 .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 347 .core = { 348 .class = BHND_DEVCLASS_PCI, 349 .unit = 0, 350 .port = 0, 351 .region = 0, 352 .port_type = BHND_PORT_DEVICE 353 }, 354 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 355 }, 356 BHNDB_REGWIN_TABLE_END 357 }, 358 }; 359 360 /** 361 * PCI_V1 (PCI-only) hardware configuration (PCI version) 362 * 363 * Applies to: 364 * - PCI (cid=0x804, revision >= 13) 365 */ 366 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 367 .resource_specs = (const struct resource_spec[]) { 368 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 369 { -1, 0, 0 } 370 }, 371 372 .register_windows = (const struct bhndb_regwin[]) { 373 /* bar0+0x0000: configurable backplane window */ 374 { 375 .win_type = BHNDB_REGWIN_T_DYN, 376 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 377 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 378 .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 379 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 380 }, 381 382 /* bar0+0x1000: sprom shadow */ 383 { 384 .win_type = BHNDB_REGWIN_T_SPROM, 385 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 386 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 387 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 388 }, 389 390 /* bar0+0x2000: pci core registers */ 391 { 392 .win_type = BHNDB_REGWIN_T_CORE, 393 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 394 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 395 .core = { 396 .class = BHND_DEVCLASS_PCI, 397 .unit = 0, 398 .port = 0, 399 .region = 0, 400 .port_type = BHND_PORT_DEVICE 401 }, 402 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 403 }, 404 405 /* bar0+0x3000: chipc core registers */ 406 { 407 .win_type = BHNDB_REGWIN_T_CORE, 408 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 409 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 410 .core = { 411 .class = BHND_DEVCLASS_CC, 412 .unit = 0, 413 .port = 0, 414 .region = 0, 415 .port_type = BHND_PORT_DEVICE 416 }, 417 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 418 }, 419 420 BHNDB_REGWIN_TABLE_END 421 }, 422 }; 423 424 /** 425 * PCI_V1 hardware configuration (PCIE version). 426 * 427 * Applies to: 428 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 429 */ 430 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 431 .resource_specs = (const struct resource_spec[]) { 432 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 433 { -1, 0, 0 } 434 }, 435 436 .register_windows = (const struct bhndb_regwin[]) { 437 /* bar0+0x0000: configurable backplane window */ 438 { 439 .win_type = BHNDB_REGWIN_T_DYN, 440 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 441 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 442 .dyn.cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 443 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 444 }, 445 446 /* bar0+0x1000: sprom shadow */ 447 { 448 .win_type = BHNDB_REGWIN_T_SPROM, 449 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 450 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 451 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 452 }, 453 454 /* bar0+0x2000: pci core registers */ 455 { 456 .win_type = BHNDB_REGWIN_T_CORE, 457 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 458 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 459 .core = { 460 .class = BHND_DEVCLASS_PCIE, 461 .unit = 0, 462 .port = 0, 463 .region = 0, 464 .port_type = BHND_PORT_DEVICE 465 }, 466 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 467 }, 468 469 /* bar0+0x3000: chipc core registers */ 470 { 471 .win_type = BHNDB_REGWIN_T_CORE, 472 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 473 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 474 .core = { 475 .class = BHND_DEVCLASS_CC, 476 .unit = 0, 477 .port = 0, 478 .region = 0, 479 .port_type = BHND_PORT_DEVICE 480 }, 481 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 482 }, 483 484 BHNDB_REGWIN_TABLE_END 485 }, 486 }; 487 488 /** 489 * PCI_V2 hardware configuration. 490 * 491 * Applies to: 492 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 493 */ 494 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 495 .resource_specs = (const struct resource_spec[]) { 496 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 497 { -1, 0, 0 } 498 }, 499 500 .register_windows = (const struct bhndb_regwin[]) { 501 /* bar0+0x0000: configurable backplane window */ 502 { 503 .win_type = BHNDB_REGWIN_T_DYN, 504 .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 505 .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 506 .dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 507 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 508 }, 509 510 /* bar0+0x1000: configurable backplane window */ 511 { 512 .win_type = BHNDB_REGWIN_T_DYN, 513 .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 514 .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 515 .dyn.cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 516 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 517 }, 518 519 /* bar0+0x2000: pcie core registers */ 520 { 521 .win_type = BHNDB_REGWIN_T_CORE, 522 .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 523 .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 524 .core = { 525 .class = BHND_DEVCLASS_PCIE, 526 .unit = 0, 527 .port = 0, 528 .region = 0, 529 .port_type = BHND_PORT_DEVICE 530 }, 531 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 532 }, 533 534 /* bar0+0x3000: chipc core registers */ 535 { 536 .win_type = BHNDB_REGWIN_T_CORE, 537 .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 538 .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 539 .core = { 540 .class = BHND_DEVCLASS_CC, 541 .unit = 0, 542 .port = 0, 543 .region = 0, 544 .port_type = BHND_PORT_DEVICE 545 }, 546 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 547 }, 548 549 BHNDB_REGWIN_TABLE_END 550 }, 551 }; 552 553 /** 554 * PCI_V3 hardware configuration. 555 * 556 * Applies to: 557 * - PCIE2 (cid=0x83c) 558 */ 559 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 560 .resource_specs = (const struct resource_spec[]) { 561 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 562 { -1, 0, 0 } 563 }, 564 565 .register_windows = (const struct bhndb_regwin[]) { 566 /* bar0+0x0000: configurable backplane window */ 567 { 568 .win_type = BHNDB_REGWIN_T_DYN, 569 .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 570 .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 571 .dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 572 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 573 }, 574 575 /* bar0+0x1000: configurable backplane window */ 576 { 577 .win_type = BHNDB_REGWIN_T_DYN, 578 .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 579 .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 580 .dyn.cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 581 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 582 }, 583 584 /* bar0+0x2000: pcie core registers */ 585 { 586 .win_type = BHNDB_REGWIN_T_CORE, 587 .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 588 .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 589 .core = { 590 .class = BHND_DEVCLASS_PCIE, 591 .unit = 0, 592 .port = 0, 593 .region = 0, 594 .port_type = BHND_PORT_DEVICE 595 }, 596 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 597 }, 598 599 /* bar0+0x3000: chipc core registers */ 600 { 601 .win_type = BHNDB_REGWIN_T_CORE, 602 .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 603 .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 604 .core = { 605 .class = BHND_DEVCLASS_CC, 606 .unit = 0, 607 .port = 0, 608 .region = 0, 609 .port_type = BHND_PORT_DEVICE 610 }, 611 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 612 }, 613 614 BHNDB_REGWIN_TABLE_END 615 }, 616 }; 617