1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 /* 32 * Resource specifications and register maps for Broadcom PCI/PCIe cores 33 * configured as PCI-BHND bridges. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/bus.h> 38 39 #include <machine/bus.h> 40 #include <sys/rman.h> 41 #include <machine/resource.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 46 #include <dev/bhnd/cores/pci/bhnd_pcireg.h> 47 #include <dev/bhnd/cores/pcie2/bhnd_pcie2_reg.h> 48 49 #include "bhndbvar.h" 50 #include "bhndb_pcireg.h" 51 52 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0; 53 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci; 54 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie; 55 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2; 56 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3; 57 58 /** 59 * Define a bhndb_hw match entry. 60 * 61 * @param _name The entry name. 62 * @param _vers The configuration version associated with this entry. 63 */ 64 #define BHNDB_HW_MATCH(_name, _vers, ...) { \ 65 .name = _name, \ 66 .hw_reqs = _BHNDB_HW_REQ_ARRAY(__VA_ARGS__), \ 67 .num_hw_reqs = (sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)) / \ 68 sizeof(_BHNDB_HW_REQ_ARRAY(__VA_ARGS__)[0])), \ 69 .cfg = &bhndb_pci_hwcfg_ ## _vers \ 70 } 71 #define _BHNDB_HW_REQ_ARRAY(...) (struct bhnd_core_match[]) { __VA_ARGS__ } 72 73 /** 74 * Generic PCI-SIBA bridge configuration usable with all known siba(4)-based 75 * PCI devices; this configuration is adequate for enumerating a bridged 76 * siba(4) bus to determine the full hardware configuration. 77 * 78 * @par Compatibility 79 * - Compatible with PCI_V0, PCI_V1, PCI_V2, and PCI_V3 devices. 80 * - Compatible with siba(4) bus enumeration. 81 * - Compatible with bcma(4) bus enumeration if the ChipCommon core is mapped 82 * at the default enumeration address (0x18000000). 83 */ 84 const struct bhndb_hwcfg bhndb_pci_siba_generic_hwcfg = { 85 .resource_specs = (const struct resource_spec[]) { 86 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 87 { -1, 0, 0 } 88 }, 89 90 .register_windows = (const struct bhndb_regwin[]) { 91 /* bar0+0x0000: configurable backplane window */ 92 { 93 .win_type = BHNDB_REGWIN_T_DYN, 94 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 95 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 96 .d.dyn = { 97 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 98 }, 99 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 100 }, 101 BHNDB_REGWIN_TABLE_END 102 }, 103 104 /* DMA unsupported under generic configuration */ 105 .dma_translations = NULL, 106 }; 107 108 /** 109 * Generic PCI-BCMA bridge configuration usable with all known bcma(4)-based 110 * PCI devices; this configuration is adequate for enumerating a bridged 111 * bcma(4) bus to determine the full hardware configuration. 112 * 113 * @par Compatibility 114 * - Compatible with PCI_V1, PCI_V2, and PCI_V3 devices. 115 * - Compatible with both siba(4) and bcma(4) bus enumeration. 116 */ 117 const struct bhndb_hwcfg bhndb_pci_bcma_generic_hwcfg = { 118 .resource_specs = (const struct resource_spec[]) { 119 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 120 { -1, 0, 0 } 121 }, 122 123 .register_windows = (const struct bhndb_regwin[]) { 124 /* bar0+0x0000: configurable backplane window */ 125 { 126 .win_type = BHNDB_REGWIN_T_DYN, 127 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 128 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 129 .d.dyn = { 130 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL, 131 }, 132 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 133 }, 134 135 /* bar0+0x3000: chipc core registers */ 136 { 137 .win_type = BHNDB_REGWIN_T_CORE, 138 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 139 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 140 .d.core = { 141 .class = BHND_DEVCLASS_CC, 142 .unit = 0, 143 .port = 0, 144 .region = 0, 145 .port_type = BHND_PORT_DEVICE 146 }, 147 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 148 }, 149 150 BHNDB_REGWIN_TABLE_END 151 }, 152 153 /* DMA unsupported under generic configuration */ 154 .dma_translations = NULL, 155 }; 156 157 /** 158 * Hardware configuration tables for Broadcom HND PCI NICs. 159 */ 160 const struct bhndb_hw bhndb_pci_generic_hw_table[] = { 161 /* PCI/V0 WLAN */ 162 BHNDB_HW_MATCH("PCI/v0 WLAN", v0, 163 /* PCI Core */ 164 { 165 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 166 BHND_MATCH_CORE_ID (BHND_COREID_PCI), 167 BHND_MATCH_CORE_REV( 168 HWREV_LTE (BHNDB_PCI_V0_MAX_PCI_HWREV)), 169 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 170 BHND_MATCH_CORE_UNIT (0) 171 }, 172 173 /* 802.11 Core */ 174 { 175 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 176 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 177 BHND_MATCH_CORE_UNIT (0) 178 } 179 ), 180 181 /* PCI/V1 WLAN */ 182 BHNDB_HW_MATCH("PCI/v1 WLAN", v1_pci, 183 /* PCI Core */ 184 { 185 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 186 BHND_MATCH_CORE_ID (BHND_COREID_PCI), 187 BHND_MATCH_CORE_REV( 188 HWREV_GTE (BHNDB_PCI_V1_MIN_PCI_HWREV)), 189 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCI), 190 BHND_MATCH_CORE_UNIT (0) 191 }, 192 193 /* 802.11 Core */ 194 { 195 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 196 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 197 BHND_MATCH_CORE_UNIT (0) 198 } 199 ), 200 201 /* PCIE/V1 WLAN */ 202 BHNDB_HW_MATCH("PCIe/v1 WLAN", v1_pcie, 203 /* PCIe Core */ 204 { 205 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 206 BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 207 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 208 BHND_MATCH_CORE_UNIT (0) 209 }, 210 211 /* ChipCommon (revision <= 31) */ 212 { 213 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 214 BHND_MATCH_CORE_ID (BHND_COREID_CC), 215 BHND_MATCH_CORE_REV( 216 HWREV_LTE (BHNDB_PCI_V1_MAX_CHIPC_HWREV)), 217 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 218 BHND_MATCH_CORE_UNIT (0) 219 }, 220 221 /* 802.11 Core */ 222 { 223 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 224 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 225 BHND_MATCH_CORE_UNIT (0) 226 } 227 ), 228 229 /* PCIE/V2 WLAN */ 230 BHNDB_HW_MATCH("PCIe/v2 WLAN", v2, 231 /* PCIe Core */ 232 { 233 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 234 BHND_MATCH_CORE_ID (BHND_COREID_PCIE), 235 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 236 BHND_MATCH_CORE_UNIT (0) 237 }, 238 239 /* ChipCommon (revision >= 32) */ 240 { 241 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 242 BHND_MATCH_CORE_ID (BHND_COREID_CC), 243 BHND_MATCH_CORE_REV( 244 HWREV_GTE (BHNDB_PCI_V2_MIN_CHIPC_HWREV)), 245 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_CC), 246 BHND_MATCH_CORE_UNIT (0) 247 }, 248 249 /* 802.11 Core */ 250 { 251 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 252 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 253 BHND_MATCH_CORE_UNIT (0) 254 } 255 ), 256 257 /* PCIE/V3 WLAN */ 258 BHNDB_HW_MATCH("PCIe-Gen2/v3 WLAN", v3, 259 /* PCIe Gen2 Core */ 260 { 261 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 262 BHND_MATCH_CORE_ID (BHND_COREID_PCIE2), 263 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_PCIE), 264 BHND_MATCH_CORE_UNIT (0) 265 }, 266 267 /* 802.11 Core */ 268 { 269 BHND_MATCH_CORE_VENDOR (BHND_MFGID_BCM), 270 BHND_MATCH_CORE_CLASS (BHND_DEVCLASS_WLAN), 271 BHND_MATCH_CORE_UNIT (0) 272 } 273 ), 274 { NULL, NULL, 0, NULL } 275 }; 276 277 /** 278 * PCI_V0 hardware configuration. 279 * 280 * Applies to: 281 * - PCI (cid=0x804, revision <= 12) 282 */ 283 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v0 = { 284 .resource_specs = (const struct resource_spec[]) { 285 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 286 { -1, 0, 0 } 287 }, 288 289 .register_windows = (const struct bhndb_regwin[]) { 290 /* bar0+0x0000: configurable backplane window */ 291 { 292 .win_type = BHNDB_REGWIN_T_DYN, 293 .win_offset = BHNDB_PCI_V0_BAR0_WIN0_OFFSET, 294 .win_size = BHNDB_PCI_V0_BAR0_WIN0_SIZE, 295 .d.dyn = { 296 .cfg_offset = BHNDB_PCI_V0_BAR0_WIN0_CONTROL 297 }, 298 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 299 }, 300 301 /* bar0+0x1000: sprom shadow */ 302 { 303 .win_type = BHNDB_REGWIN_T_SPROM, 304 .win_offset = BHNDB_PCI_V0_BAR0_SPROM_OFFSET, 305 .win_size = BHNDB_PCI_V0_BAR0_SPROM_SIZE, 306 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 307 }, 308 309 /* 310 * bar0+0x1800: pci core registers. 311 * 312 * Does not include the SSB CFG registers found at the end of 313 * the 4K core register block; these are mapped non-contigiously 314 * by the next entry. 315 */ 316 { 317 .win_type = BHNDB_REGWIN_T_CORE, 318 .win_offset = BHNDB_PCI_V0_BAR0_PCIREG_OFFSET, 319 .win_size = BHNDB_PCI_V0_BAR0_PCIREG_SIZE, 320 .d.core = { 321 .class = BHND_DEVCLASS_PCI, 322 .unit = 0, 323 .port = 0, 324 .region = 0, 325 .port_type = BHND_PORT_DEVICE, 326 }, 327 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 328 }, 329 330 /* bar0+0x1E00: pci core (SSB CFG registers) */ 331 { 332 .win_type = BHNDB_REGWIN_T_CORE, 333 .win_offset = BHNDB_PCI_V0_BAR0_PCISB_OFFSET , 334 .win_size = BHNDB_PCI_V0_BAR0_PCISB_SIZE, 335 .d.core = { 336 .class = BHND_DEVCLASS_PCI, 337 .unit = 0, 338 .port = 0, 339 .region = 0, 340 .offset = BHNDB_PCI_V0_BAR0_PCISB_COREOFF, 341 .port_type = BHND_PORT_DEVICE 342 }, 343 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 344 }, 345 346 BHNDB_REGWIN_TABLE_END 347 }, 348 349 .dma_translations = (const struct bhnd_dma_translation[]) { 350 { 351 .base_addr = BHND_PCI_DMA32_TRANSLATION, 352 .addr_mask = ~BHND_PCI_DMA32_MASK, 353 .addrext_mask = BHND_PCI_DMA32_MASK 354 }, 355 BHND_DMA_TRANSLATION_TABLE_END 356 } 357 }; 358 359 /** 360 * PCI_V1 (PCI-only) hardware configuration (PCI version) 361 * 362 * Applies to: 363 * - PCI (cid=0x804, revision >= 13) 364 */ 365 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pci = { 366 .resource_specs = (const struct resource_spec[]) { 367 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 368 { -1, 0, 0 } 369 }, 370 371 .register_windows = (const struct bhndb_regwin[]) { 372 /* bar0+0x0000: configurable backplane window */ 373 { 374 .win_type = BHNDB_REGWIN_T_DYN, 375 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 376 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 377 .d.dyn = { 378 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 379 }, 380 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 381 }, 382 383 /* bar0+0x1000: sprom shadow */ 384 { 385 .win_type = BHNDB_REGWIN_T_SPROM, 386 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 387 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 388 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 389 }, 390 391 /* bar0+0x2000: pci core registers */ 392 { 393 .win_type = BHNDB_REGWIN_T_CORE, 394 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 395 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 396 .d.core = { 397 .class = BHND_DEVCLASS_PCI, 398 .unit = 0, 399 .port = 0, 400 .region = 0, 401 .port_type = BHND_PORT_DEVICE 402 }, 403 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 404 }, 405 406 /* bar0+0x3000: chipc core registers */ 407 { 408 .win_type = BHNDB_REGWIN_T_CORE, 409 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 410 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 411 .d.core = { 412 .class = BHND_DEVCLASS_CC, 413 .unit = 0, 414 .port = 0, 415 .region = 0, 416 .port_type = BHND_PORT_DEVICE 417 }, 418 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 419 }, 420 421 BHNDB_REGWIN_TABLE_END 422 }, 423 424 .dma_translations = (const struct bhnd_dma_translation[]) { 425 { 426 .base_addr = BHND_PCI_DMA32_TRANSLATION, 427 .addr_mask = ~BHND_PCI_DMA32_MASK, 428 .addrext_mask = BHND_PCI_DMA32_MASK 429 }, 430 BHND_DMA_TRANSLATION_TABLE_END 431 } 432 }; 433 434 /** 435 * PCI_V1 hardware configuration (PCIE version). 436 * 437 * Applies to: 438 * - PCIE (cid=0x820) with ChipCommon (revision <= 31) 439 */ 440 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v1_pcie = { 441 .resource_specs = (const struct resource_spec[]) { 442 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 443 { -1, 0, 0 } 444 }, 445 446 .register_windows = (const struct bhndb_regwin[]) { 447 /* bar0+0x0000: configurable backplane window */ 448 { 449 .win_type = BHNDB_REGWIN_T_DYN, 450 .win_offset = BHNDB_PCI_V1_BAR0_WIN0_OFFSET, 451 .win_size = BHNDB_PCI_V1_BAR0_WIN0_SIZE, 452 .d.dyn = { 453 .cfg_offset = BHNDB_PCI_V1_BAR0_WIN0_CONTROL 454 }, 455 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 456 }, 457 458 /* bar0+0x1000: sprom shadow */ 459 { 460 .win_type = BHNDB_REGWIN_T_SPROM, 461 .win_offset = BHNDB_PCI_V1_BAR0_SPROM_OFFSET, 462 .win_size = BHNDB_PCI_V1_BAR0_SPROM_SIZE, 463 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 464 }, 465 466 /* bar0+0x2000: pci core registers */ 467 { 468 .win_type = BHNDB_REGWIN_T_CORE, 469 .win_offset = BHNDB_PCI_V1_BAR0_PCIREG_OFFSET, 470 .win_size = BHNDB_PCI_V1_BAR0_PCIREG_SIZE, 471 .d.core = { 472 .class = BHND_DEVCLASS_PCIE, 473 .unit = 0, 474 .port = 0, 475 .region = 0, 476 .port_type = BHND_PORT_DEVICE 477 }, 478 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 479 }, 480 481 /* bar0+0x3000: chipc core registers */ 482 { 483 .win_type = BHNDB_REGWIN_T_CORE, 484 .win_offset = BHNDB_PCI_V1_BAR0_CCREGS_OFFSET, 485 .win_size = BHNDB_PCI_V1_BAR0_CCREGS_SIZE, 486 .d.core = { 487 .class = BHND_DEVCLASS_CC, 488 .unit = 0, 489 .port = 0, 490 .region = 0, 491 .port_type = BHND_PORT_DEVICE 492 }, 493 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 494 }, 495 496 BHNDB_REGWIN_TABLE_END 497 }, 498 499 .dma_translations = (const struct bhnd_dma_translation[]) { 500 { 501 .base_addr = BHND_PCIE_DMA32_TRANSLATION, 502 .addr_mask = ~BHND_PCIE_DMA32_MASK, 503 .addrext_mask = BHND_PCIE_DMA32_MASK 504 }, 505 { 506 .base_addr = BHND_PCIE_DMA64_TRANSLATION, 507 .addr_mask = ~BHND_PCIE_DMA64_MASK, 508 .addrext_mask = BHND_PCIE_DMA64_MASK 509 }, 510 BHND_DMA_TRANSLATION_TABLE_END 511 } 512 }; 513 514 /** 515 * PCI_V2 hardware configuration. 516 * 517 * Applies to: 518 * - PCIE (cid=0x820) with ChipCommon (revision >= 32) 519 */ 520 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v2 = { 521 .resource_specs = (const struct resource_spec[]) { 522 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 523 { -1, 0, 0 } 524 }, 525 526 .register_windows = (const struct bhndb_regwin[]) { 527 /* bar0+0x0000: configurable backplane window */ 528 { 529 .win_type = BHNDB_REGWIN_T_DYN, 530 .win_offset = BHNDB_PCI_V2_BAR0_WIN0_OFFSET, 531 .win_size = BHNDB_PCI_V2_BAR0_WIN0_SIZE, 532 .d.dyn = { 533 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN0_CONTROL, 534 }, 535 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 536 }, 537 538 /* bar0+0x1000: configurable backplane window */ 539 { 540 .win_type = BHNDB_REGWIN_T_DYN, 541 .win_offset = BHNDB_PCI_V2_BAR0_WIN1_OFFSET, 542 .win_size = BHNDB_PCI_V2_BAR0_WIN1_SIZE, 543 .d.dyn = { 544 .cfg_offset = BHNDB_PCI_V2_BAR0_WIN1_CONTROL, 545 }, 546 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 547 }, 548 549 /* bar0+0x2000: pcie core registers */ 550 { 551 .win_type = BHNDB_REGWIN_T_CORE, 552 .win_offset = BHNDB_PCI_V2_BAR0_PCIREG_OFFSET, 553 .win_size = BHNDB_PCI_V2_BAR0_PCIREG_SIZE, 554 .d.core = { 555 .class = BHND_DEVCLASS_PCIE, 556 .unit = 0, 557 .port = 0, 558 .region = 0, 559 .port_type = BHND_PORT_DEVICE 560 }, 561 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 562 }, 563 564 /* bar0+0x3000: chipc core registers */ 565 { 566 .win_type = BHNDB_REGWIN_T_CORE, 567 .win_offset = BHNDB_PCI_V2_BAR0_CCREGS_OFFSET, 568 .win_size = BHNDB_PCI_V2_BAR0_CCREGS_SIZE, 569 .d.core = { 570 .class = BHND_DEVCLASS_CC, 571 .unit = 0, 572 .port = 0, 573 .region = 0, 574 .port_type = BHND_PORT_DEVICE 575 }, 576 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 577 }, 578 579 BHNDB_REGWIN_TABLE_END 580 }, 581 582 .dma_translations = (const struct bhnd_dma_translation[]) { 583 { 584 .base_addr = BHND_PCIE_DMA32_TRANSLATION, 585 .addr_mask = ~BHND_PCIE_DMA32_MASK, 586 .addrext_mask = BHND_PCIE_DMA32_MASK 587 }, 588 { 589 .base_addr = BHND_PCIE_DMA64_TRANSLATION, 590 .addr_mask = ~BHND_PCIE_DMA64_MASK, 591 .addrext_mask = BHND_PCIE_DMA64_MASK 592 }, 593 BHND_DMA_TRANSLATION_TABLE_END 594 } 595 }; 596 597 /** 598 * PCI_V3 hardware configuration. 599 * 600 * Applies to: 601 * - PCIE2 (cid=0x83c) 602 */ 603 static const struct bhndb_hwcfg bhndb_pci_hwcfg_v3 = { 604 .resource_specs = (const struct resource_spec[]) { 605 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 606 { -1, 0, 0 } 607 }, 608 609 .register_windows = (const struct bhndb_regwin[]) { 610 /* bar0+0x0000: configurable backplane window */ 611 { 612 .win_type = BHNDB_REGWIN_T_DYN, 613 .win_offset = BHNDB_PCI_V3_BAR0_WIN0_OFFSET, 614 .win_size = BHNDB_PCI_V3_BAR0_WIN0_SIZE, 615 .d.dyn = { 616 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN0_CONTROL, 617 }, 618 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 619 }, 620 621 /* bar0+0x1000: configurable backplane window */ 622 { 623 .win_type = BHNDB_REGWIN_T_DYN, 624 .win_offset = BHNDB_PCI_V3_BAR0_WIN1_OFFSET, 625 .win_size = BHNDB_PCI_V3_BAR0_WIN1_SIZE, 626 .d.dyn = { 627 .cfg_offset = BHNDB_PCI_V3_BAR0_WIN1_CONTROL, 628 }, 629 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 630 }, 631 632 /* bar0+0x2000: pcie core registers */ 633 { 634 .win_type = BHNDB_REGWIN_T_CORE, 635 .win_offset = BHNDB_PCI_V3_BAR0_PCIREG_OFFSET, 636 .win_size = BHNDB_PCI_V3_BAR0_PCIREG_SIZE, 637 .d.core = { 638 .class = BHND_DEVCLASS_PCIE, 639 .unit = 0, 640 .port = 0, 641 .region = 0, 642 .port_type = BHND_PORT_DEVICE 643 }, 644 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 645 }, 646 647 /* bar0+0x3000: chipc core registers */ 648 { 649 .win_type = BHNDB_REGWIN_T_CORE, 650 .win_offset = BHNDB_PCI_V3_BAR0_CCREGS_OFFSET, 651 .win_size = BHNDB_PCI_V3_BAR0_CCREGS_SIZE, 652 .d.core = { 653 .class = BHND_DEVCLASS_CC, 654 .unit = 0, 655 .port = 0, 656 .region = 0, 657 .port_type = BHND_PORT_DEVICE 658 }, 659 .res = { SYS_RES_MEMORY, PCIR_BAR(0) } 660 }, 661 662 BHNDB_REGWIN_TABLE_END 663 }, 664 665 .dma_translations = (const struct bhnd_dma_translation[]) { 666 { 667 .base_addr = BHND_PCIE2_DMA64_TRANSLATION, 668 .addr_mask = ~BHND_PCIE2_DMA64_MASK, 669 .addrext_mask = BHND_PCIE_DMA64_MASK 670 }, 671 BHND_DMA_TRANSLATION_TABLE_END 672 } 673 }; 674