1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 35 #include <dev/bhnd/bhnd_ids.h> 36 #include <dev/bhnd/bhndreg.h> 37 #include <dev/bhnd/bhnd.h> 38 39 #include "bhndb_hwdata.h" 40 41 /* 42 * Resource priority specifications shared by all bhndb(4) bridge 43 * implementations. 44 */ 45 46 /* 47 * Define a bhndb_port_priority table. 48 */ 49 #define BHNDB_PORTS(...) \ 50 .ports = _BHNDB_PORT_ARRAY(__VA_ARGS__), \ 51 .num_ports = nitems(_BHNDB_PORT_ARRAY(__VA_ARGS__)) 52 53 #define _BHNDB_PORT_ARRAY(...) (const struct bhndb_port_priority[]) { \ 54 __VA_ARGS__ \ 55 } 56 57 /* 58 * Define a core priority record for all cores matching @p devclass 59 */ 60 #define BHNDB_CLASS_PRIO(_devclass, _priority, ...) { \ 61 .match = { \ 62 BHND_MATCH_CORE_CLASS(BHND_DEVCLASS_ ## _devclass), \ 63 }, \ 64 .priority = (BHNDB_PRIORITY_ ## _priority), \ 65 BHNDB_PORTS(__VA_ARGS__) \ 66 } 67 68 /* 69 * Define a default core priority record 70 */ 71 #define BHNDB_DEFAULT_PRIO(...) { \ 72 .match = { \ 73 BHND_MATCH_ANY , \ 74 }, \ 75 .priority = (BHNDB_PRIORITY_DEFAULT), \ 76 BHNDB_PORTS(__VA_ARGS__) \ 77 } 78 79 /* Define a port priority record for the type/port/region 80 * triplet. */ 81 #define BHNDB_PORT_PRIO(_type, _port, _region, _priority) { \ 82 .type = (BHND_PORT_ ## _type), \ 83 .port = _port, \ 84 .region = _region, \ 85 .priority = (BHNDB_PRIORITY_ ## _priority) \ 86 } 87 88 /* Define a port priority record for the default (_type, 0, 0) type/port/region 89 * triplet. */ 90 #define BHNDB_PORT0_PRIO(_type, _priority) \ 91 BHNDB_PORT_PRIO(_type, 0, 0, _priority) 92 93 /** 94 * Generic resource priority configuration usable with all currently supported 95 * bcma(4)-based PCI devices. 96 */ 97 const struct bhndb_hw_priority bhndb_bcma_priority_table[] = { 98 /* 99 * Ignorable device classes. 100 * 101 * Runtime access to these cores is not required, and no register 102 * windows should be reserved for these device types. 103 */ 104 BHNDB_CLASS_PRIO(SOC_ROUTER, NONE), 105 BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE), 106 BHNDB_CLASS_PRIO(EROM, NONE), 107 BHNDB_CLASS_PRIO(OTHER, NONE), 108 109 /* 110 * Low priority device classes. 111 * 112 * These devices do not sit in a performance-critical path and can be 113 * treated as a low allocation priority. 114 */ 115 BHNDB_CLASS_PRIO(CC, LOW, 116 /* Device Block */ 117 BHNDB_PORT0_PRIO(DEVICE, LOW), 118 119 /* CC agent registers are not accessed via the bridge. */ 120 BHNDB_PORT0_PRIO(AGENT, NONE) 121 ), 122 123 BHNDB_CLASS_PRIO(PMU, LOW, 124 /* Device Block */ 125 BHNDB_PORT0_PRIO(DEVICE, LOW), 126 127 /* PMU agent registers are not accessed via the bridge. */ 128 BHNDB_PORT0_PRIO(AGENT, NONE) 129 ), 130 131 /* 132 * Default Core Behavior 133 * 134 * All other cores are assumed to require efficient runtime access to 135 * the default device port, and if supported by the bus, an agent port. 136 */ 137 BHNDB_DEFAULT_PRIO( 138 /* Device Block */ 139 BHNDB_PORT0_PRIO(DEVICE, HIGH), 140 141 /* Agent Block */ 142 BHNDB_PORT0_PRIO(AGENT, DEFAULT) 143 ), 144 145 BHNDB_HW_PRIORITY_TABLE_END 146 }; 147 148 /** 149 * Generic resource priority configuration usable with all currently supported 150 * siba(4)-based PCI devices. 151 */ 152 const struct bhndb_hw_priority bhndb_siba_priority_table[] = { 153 /* 154 * Ignorable device classes. 155 * 156 * Runtime access to these cores is not required, and no register 157 * windows should be reserved for these device types. 158 */ 159 BHNDB_CLASS_PRIO(SOC_ROUTER, NONE), 160 BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE), 161 BHNDB_CLASS_PRIO(EROM, NONE), 162 BHNDB_CLASS_PRIO(OTHER, NONE), 163 164 /* 165 * Low priority device classes. 166 * 167 * These devices do not sit in a performance-critical path and can be 168 * treated as a low allocation priority. 169 * 170 * Agent ports are marked as 'NONE' on siba(4) devices, as they 171 * will be fully mappable via register windows shared with the 172 * device0.0 port. 173 */ 174 BHNDB_CLASS_PRIO(CC, LOW, 175 /* Device Block */ 176 BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW) 177 ), 178 179 BHNDB_CLASS_PRIO(PMU, LOW, 180 /* Device Block */ 181 BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW) 182 ), 183 184 /* 185 * Default Core Behavior 186 * 187 * All other cores are assumed to require efficient runtime access to 188 * the device port. 189 */ 190 BHNDB_DEFAULT_PRIO( 191 /* Device Block */ 192 BHNDB_PORT_PRIO(DEVICE, 0, 0, HIGH) 193 ), 194 195 BHNDB_HW_PRIORITY_TABLE_END 196 };