1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 #include <sys/param.h> 32 33 #include <dev/bhnd/bhnd_ids.h> 34 #include <dev/bhnd/bhndreg.h> 35 #include <dev/bhnd/bhnd.h> 36 37 #include "bhndb_hwdata.h" 38 39 /* 40 * Resource priority specifications shared by all bhndb(4) bridge 41 * implementations. 42 */ 43 44 /* 45 * Define a bhndb_port_priority table. 46 */ 47 #define BHNDB_PORTS(...) \ 48 .ports = _BHNDB_PORT_ARRAY(__VA_ARGS__), \ 49 .num_ports = nitems(_BHNDB_PORT_ARRAY(__VA_ARGS__)) 50 51 #define _BHNDB_PORT_ARRAY(...) (const struct bhndb_port_priority[]) { \ 52 __VA_ARGS__ \ 53 } 54 55 /* 56 * Define a core priority record for all cores matching @p devclass 57 */ 58 #define BHNDB_CLASS_PRIO(_devclass, _priority, ...) { \ 59 .match = { \ 60 BHND_MATCH_CORE_CLASS(BHND_DEVCLASS_ ## _devclass), \ 61 }, \ 62 .priority = (BHNDB_PRIORITY_ ## _priority), \ 63 BHNDB_PORTS(__VA_ARGS__) \ 64 } 65 66 /* 67 * Define a default core priority record 68 */ 69 #define BHNDB_DEFAULT_PRIO(...) { \ 70 .match = { \ 71 BHND_MATCH_ANY , \ 72 }, \ 73 .priority = (BHNDB_PRIORITY_DEFAULT), \ 74 BHNDB_PORTS(__VA_ARGS__) \ 75 } 76 77 /* Define a port priority record for the type/port/region triplet, optionally 78 * specifying port allocation flags as the final argument */ 79 #define BHNDB_PORT_PRIO(_type, _port, _region, _priority, ...) \ 80 _BHNDB_PORT_PRIO(_type, _port, _region, _priority, ## __VA_ARGS__, 0) 81 82 #define _BHNDB_PORT_PRIO(_type, _port, _region, _priority, _flags, ...) \ 83 { \ 84 .type = (BHND_PORT_ ## _type), \ 85 .port = _port, \ 86 .region = _region, \ 87 .priority = (BHNDB_PRIORITY_ ## _priority), \ 88 .alloc_flags = (_flags) \ 89 } 90 91 /* Define a port priority record for the default (_type, 0, 0) type/port/region 92 * triplet. */ 93 #define BHNDB_PORT0_PRIO(_type, _priority, ...) \ 94 BHNDB_PORT_PRIO(_type, 0, 0, _priority, ## __VA_ARGS__, 0) 95 96 /** 97 * Generic resource priority configuration usable with all currently supported 98 * bcma(4)-based PCI devices. 99 */ 100 const struct bhndb_hw_priority bhndb_bcma_priority_table[] = { 101 /* 102 * Ignorable device classes. 103 * 104 * Runtime access to these cores is not required, and no register 105 * windows should be reserved for these device types. 106 */ 107 BHNDB_CLASS_PRIO(SOC_ROUTER, NONE), 108 BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE), 109 BHNDB_CLASS_PRIO(EROM, NONE), 110 BHNDB_CLASS_PRIO(OTHER, NONE), 111 112 /* 113 * Low priority device classes. 114 * 115 * These devices do not sit in a performance-critical path and can be 116 * treated as a low allocation priority. 117 */ 118 BHNDB_CLASS_PRIO(CC, LOW, 119 /* Device Block */ 120 BHNDB_PORT0_PRIO(DEVICE, LOW), 121 122 /* CC agent registers are not accessed via the bridge. */ 123 BHNDB_PORT0_PRIO(AGENT, NONE) 124 ), 125 126 BHNDB_CLASS_PRIO(PMU, LOW, 127 /* Device Block */ 128 BHNDB_PORT0_PRIO(DEVICE, LOW), 129 130 /* PMU agent registers are not accessed via the bridge. */ 131 BHNDB_PORT0_PRIO(AGENT, NONE) 132 ), 133 134 /* 135 * Default Core Behavior 136 * 137 * All other cores are assumed to require efficient runtime access to 138 * the default device port, and if supported by the bus, an agent port. 139 */ 140 BHNDB_DEFAULT_PRIO( 141 /* Device Block */ 142 BHNDB_PORT0_PRIO(DEVICE, HIGH), 143 144 /* Agent Block */ 145 BHNDB_PORT0_PRIO(AGENT, DEFAULT) 146 ), 147 148 BHNDB_HW_PRIORITY_TABLE_END 149 }; 150 151 /** 152 * Generic resource priority configuration usable with all currently supported 153 * siba(4)-based PCI devices. 154 */ 155 const struct bhndb_hw_priority bhndb_siba_priority_table[] = { 156 /* 157 * Ignorable device classes. 158 * 159 * Runtime access to these cores is not required, and no register 160 * windows should be reserved for these device types. 161 */ 162 BHNDB_CLASS_PRIO(SOC_ROUTER, NONE), 163 BHNDB_CLASS_PRIO(SOC_BRIDGE, NONE), 164 BHNDB_CLASS_PRIO(EROM, NONE), 165 BHNDB_CLASS_PRIO(OTHER, NONE), 166 167 /* 168 * Low priority device classes. 169 * 170 * These devices do not sit in a performance-critical path and can be 171 * treated as a low allocation priority. 172 * 173 * Agent ports are marked as 'NONE' on siba(4) devices, as they 174 * will be fully mappable via register windows shared with the 175 * device0.0 port. 176 * 177 * To support early PCI_V0 devices, we enable FULFILL_ON_OVERCOMMIT for 178 * ChipCommon. 179 */ 180 BHNDB_CLASS_PRIO(CC, LOW, 181 /* Device Block */ 182 BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW, 183 BHNDB_ALLOC_FULFILL_ON_OVERCOMMIT) 184 ), 185 186 BHNDB_CLASS_PRIO(PMU, LOW, 187 /* Device Block */ 188 BHNDB_PORT_PRIO(DEVICE, 0, 0, LOW) 189 ), 190 191 /* 192 * Default Core Behavior 193 * 194 * All other cores are assumed to require efficient runtime access to 195 * the device port. 196 */ 197 BHNDB_DEFAULT_PRIO( 198 /* Device Block */ 199 BHNDB_PORT_PRIO(DEVICE, 0, 0, HIGH) 200 ), 201 202 BHNDB_HW_PRIORITY_TABLE_END 203 }; 204