1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64 #define BGE_PAGE_ZERO 0x00000000 65 #define BGE_PAGE_ZERO_END 0x000000FF 66 #define BGE_SEND_RING_RCB 0x00000100 67 #define BGE_SEND_RING_RCB_END 0x000001FF 68 #define BGE_RX_RETURN_RING_RCB 0x00000200 69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70 #define BGE_STATS_BLOCK 0x00000300 71 #define BGE_STATS_BLOCK_END 0x00000AFF 72 #define BGE_STATUS_BLOCK 0x00000B00 73 #define BGE_STATUS_BLOCK_END 0x00000B4F 74 #define BGE_SOFTWARE_GENCOMM 0x00000B50 75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77 #define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78 #define BGE_FW_DRV_ALIVE 0x00000001 79 #define BGE_FW_PAUSE 0x00000002 80 #define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 81 #define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 82 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 83 #define BGE_UNMAPPED 0x00001000 84 #define BGE_UNMAPPED_END 0x00001FFF 85 #define BGE_DMA_DESCRIPTORS 0x00002000 86 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 87 #define BGE_SEND_RING_1_TO_4 0x00004000 88 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 89 90 /* Mappings for internal memory configuration */ 91 #define BGE_STD_RX_RINGS 0x00006000 92 #define BGE_STD_RX_RINGS_END 0x00006FFF 93 #define BGE_JUMBO_RX_RINGS 0x00007000 94 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 95 #define BGE_BUFFPOOL_1 0x00008000 96 #define BGE_BUFFPOOL_1_END 0x0000FFFF 97 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 98 #define BGE_BUFFPOOL_2_END 0x00017FFF 99 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 100 #define BGE_BUFFPOOL_3_END 0x0001FFFF 101 102 /* Mappings for external SSRAM configurations */ 103 #define BGE_SEND_RING_5_TO_6 0x00006000 104 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 105 #define BGE_SEND_RING_7_TO_8 0x00007000 106 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 107 #define BGE_SEND_RING_9_TO_16 0x00008000 108 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 109 #define BGE_EXT_STD_RX_RINGS 0x0000C000 110 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 111 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 112 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 113 #define BGE_MINI_RX_RINGS 0x0000E000 114 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 115 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 116 #define BGE_AVAIL_REGION1_END 0x00017FFF 117 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 118 #define BGE_AVAIL_REGION2_END 0x0001FFFF 119 #define BGE_EXT_SSRAM 0x00020000 120 #define BGE_EXT_SSRAM_END 0x000FFFFF 121 122 123 /* 124 * BCM570x register offsets. These are memory mapped registers 125 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 126 * Each register must be accessed using 32 bit operations. 127 * 128 * All registers are accessed through a 32K shared memory block. 129 * The first group of registers are actually copies of the PCI 130 * configuration space registers. 131 */ 132 133 /* 134 * PCI registers defined in the PCI 2.2 spec. 135 */ 136 #define BGE_PCI_VID 0x00 137 #define BGE_PCI_DID 0x02 138 #define BGE_PCI_CMD 0x04 139 #define BGE_PCI_STS 0x06 140 #define BGE_PCI_REV 0x08 141 #define BGE_PCI_CLASS 0x09 142 #define BGE_PCI_CACHESZ 0x0C 143 #define BGE_PCI_LATTIMER 0x0D 144 #define BGE_PCI_HDRTYPE 0x0E 145 #define BGE_PCI_BIST 0x0F 146 #define BGE_PCI_BAR0 0x10 147 #define BGE_PCI_BAR1 0x14 148 #define BGE_PCI_SUBSYS 0x2C 149 #define BGE_PCI_SUBVID 0x2E 150 #define BGE_PCI_ROMBASE 0x30 151 #define BGE_PCI_CAPPTR 0x34 152 #define BGE_PCI_INTLINE 0x3C 153 #define BGE_PCI_INTPIN 0x3D 154 #define BGE_PCI_MINGNT 0x3E 155 #define BGE_PCI_MAXLAT 0x3F 156 #define BGE_PCI_PCIXCAP 0x40 157 #define BGE_PCI_NEXTPTR_PM 0x41 158 #define BGE_PCI_PCIX_CMD 0x42 159 #define BGE_PCI_PCIX_STS 0x44 160 #define BGE_PCI_PWRMGMT_CAPID 0x48 161 #define BGE_PCI_NEXTPTR_VPD 0x49 162 #define BGE_PCI_PWRMGMT_CAPS 0x4A 163 #define BGE_PCI_PWRMGMT_CMD 0x4C 164 #define BGE_PCI_PWRMGMT_STS 0x4D 165 #define BGE_PCI_PWRMGMT_DATA 0x4F 166 #define BGE_PCI_VPD_CAPID 0x50 167 #define BGE_PCI_NEXTPTR_MSI 0x51 168 #define BGE_PCI_VPD_ADDR 0x52 169 #define BGE_PCI_VPD_DATA 0x54 170 #define BGE_PCI_MSI_CAPID 0x58 171 #define BGE_PCI_NEXTPTR_NONE 0x59 172 #define BGE_PCI_MSI_CTL 0x5A 173 #define BGE_PCI_MSI_ADDR_HI 0x5C 174 #define BGE_PCI_MSI_ADDR_LO 0x60 175 #define BGE_PCI_MSI_DATA 0x64 176 177 /* PCI MSI. ??? */ 178 #define BGE_PCIE_CAPID_REG 0xD0 179 #define BGE_PCIE_CAPID 0x10 180 181 /* 182 * PCI registers specific to the BCM570x family. 183 */ 184 #define BGE_PCI_MISC_CTL 0x68 185 #define BGE_PCI_DMA_RW_CTL 0x6C 186 #define BGE_PCI_PCISTATE 0x70 187 #define BGE_PCI_CLKCTL 0x74 188 #define BGE_PCI_REG_BASEADDR 0x78 189 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 190 #define BGE_PCI_REG_DATA 0x80 191 #define BGE_PCI_MEMWIN_DATA 0x84 192 #define BGE_PCI_MODECTL 0x88 193 #define BGE_PCI_MISC_CFG 0x8C 194 #define BGE_PCI_MISC_LOCALCTL 0x90 195 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 196 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 197 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 198 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 199 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 200 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 201 #define BGE_PCI_ISR_MBX_HI 0xB0 202 #define BGE_PCI_ISR_MBX_LO 0xB4 203 204 /* PCI Misc. Host control register */ 205 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 206 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 207 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 208 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 209 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 210 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 211 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 212 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 213 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 214 215 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 216 #if BYTE_ORDER == LITTLE_ENDIAN 217 #define BGE_DMA_SWAP_OPTIONS \ 218 BGE_MODECTL_WORDSWAP_NONFRAME| \ 219 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 220 #else 221 #define BGE_DMA_SWAP_OPTIONS \ 222 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 223 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 224 #endif 225 226 #define BGE_INIT \ 227 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 228 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 229 230 #define BGE_CHIPID_TIGON_I 0x40000000 231 #define BGE_CHIPID_TIGON_II 0x60000000 232 #define BGE_CHIPID_BCM5700_A0 0x70000000 233 #define BGE_CHIPID_BCM5700_A1 0x70010000 234 #define BGE_CHIPID_BCM5700_B0 0x71000000 235 #define BGE_CHIPID_BCM5700_B1 0x71010000 236 #define BGE_CHIPID_BCM5700_B2 0x71020000 237 #define BGE_CHIPID_BCM5700_B3 0x71030000 238 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 239 #define BGE_CHIPID_BCM5700_C0 0x72000000 240 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 241 #define BGE_CHIPID_BCM5701_B0 0x01000000 242 #define BGE_CHIPID_BCM5701_B2 0x01020000 243 #define BGE_CHIPID_BCM5701_B5 0x01050000 244 #define BGE_CHIPID_BCM5703_A0 0x10000000 245 #define BGE_CHIPID_BCM5703_A1 0x10010000 246 #define BGE_CHIPID_BCM5703_A2 0x10020000 247 #define BGE_CHIPID_BCM5703_A3 0x10030000 248 #define BGE_CHIPID_BCM5703_B0 0x11000000 249 #define BGE_CHIPID_BCM5704_A0 0x20000000 250 #define BGE_CHIPID_BCM5704_A1 0x20010000 251 #define BGE_CHIPID_BCM5704_A2 0x20020000 252 #define BGE_CHIPID_BCM5704_A3 0x20030000 253 #define BGE_CHIPID_BCM5704_B0 0x21000000 254 #define BGE_CHIPID_BCM5705_A0 0x30000000 255 #define BGE_CHIPID_BCM5705_A1 0x30010000 256 #define BGE_CHIPID_BCM5705_A2 0x30020000 257 #define BGE_CHIPID_BCM5705_A3 0x30030000 258 #define BGE_CHIPID_BCM5750_A0 0x40000000 259 #define BGE_CHIPID_BCM5750_A1 0x40010000 260 #define BGE_CHIPID_BCM5750_A3 0x40030000 261 #define BGE_CHIPID_BCM5750_B0 0x41000000 262 #define BGE_CHIPID_BCM5750_B1 0x41010000 263 #define BGE_CHIPID_BCM5750_C0 0x42000000 264 #define BGE_CHIPID_BCM5750_C1 0x42010000 265 #define BGE_CHIPID_BCM5750_C2 0x42020000 266 #define BGE_CHIPID_BCM5714_A0 0x50000000 267 #define BGE_CHIPID_BCM5752_A0 0x60000000 268 #define BGE_CHIPID_BCM5752_A1 0x60010000 269 #define BGE_CHIPID_BCM5752_A2 0x60020000 270 #define BGE_CHIPID_BCM5714_B0 0x80000000 271 #define BGE_CHIPID_BCM5714_B3 0x80030000 272 #define BGE_CHIPID_BCM5715_A0 0x90000000 273 #define BGE_CHIPID_BCM5715_A1 0x90010000 274 #define BGE_CHIPID_BCM5755_A0 0xa0000000 275 #define BGE_CHIPID_BCM5755_A1 0xa0010000 276 #define BGE_CHIPID_BCM5755_A2 0xa0020000 277 #define BGE_CHIPID_BCM5754_A0 0xb0000000 278 #define BGE_CHIPID_BCM5754_A1 0xb0010000 279 #define BGE_CHIPID_BCM5754_A2 0xb0020000 280 #define BGE_CHIPID_BCM5787_A0 0xb0000000 281 #define BGE_CHIPID_BCM5787_A1 0xb0010000 282 #define BGE_CHIPID_BCM5787_A2 0xb0020000 283 284 /* shorthand one */ 285 #define BGE_ASICREV(x) ((x) >> 28) 286 #define BGE_ASICREV_BCM5701 0x00 287 #define BGE_ASICREV_BCM5703 0x01 288 #define BGE_ASICREV_BCM5704 0x02 289 #define BGE_ASICREV_BCM5705 0x03 290 #define BGE_ASICREV_BCM5750 0x04 291 #define BGE_ASICREV_BCM5714_A0 0x05 292 #define BGE_ASICREV_BCM5752 0x06 293 #define BGE_ASICREV_BCM5700 0x07 294 #define BGE_ASICREV_BCM5780 0x08 295 #define BGE_ASICREV_BCM5714 0x09 296 #define BGE_ASICREV_BCM5755 0x0a 297 #define BGE_ASICREV_BCM5754 0x0b 298 #define BGE_ASICREV_BCM5787 0x0b 299 300 /* chip revisions */ 301 #define BGE_CHIPREV(x) ((x) >> 24) 302 #define BGE_CHIPREV_5700_AX 0x70 303 #define BGE_CHIPREV_5700_BX 0x71 304 #define BGE_CHIPREV_5700_CX 0x72 305 #define BGE_CHIPREV_5701_AX 0x00 306 #define BGE_CHIPREV_5750_AX 0x40 307 #define BGE_CHIPREV_5750_BX 0x41 308 309 /* PCI DMA Read/Write Control register */ 310 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 311 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 312 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 313 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 314 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 315 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 316 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 317 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 318 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 319 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 320 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 321 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 322 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 323 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 324 325 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 326 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 327 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 328 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 329 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 330 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 331 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 332 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 333 334 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 335 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 336 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 337 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 338 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 339 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 340 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 341 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 342 343 /* 344 * PCI state register -- note, this register is read only 345 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 346 * register is set. 347 */ 348 #define BGE_PCISTATE_FORCE_RESET 0x00000001 349 #define BGE_PCISTATE_INTR_STATE 0x00000002 350 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 351 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 352 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 353 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 354 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 355 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 356 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 357 358 /* 359 * PCI Clock Control register -- note, this register is read only 360 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 361 * register is set. 362 */ 363 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 364 #define BGE_PCICLOCKCTL_M66EN 0x00000080 365 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 366 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 367 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 368 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 369 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 370 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 371 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 372 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 373 374 375 #ifndef PCIM_CMD_MWIEN 376 #define PCIM_CMD_MWIEN 0x0010 377 #endif 378 379 /* 380 * High priority mailbox registers 381 * Each mailbox is 64-bits wide, though we only use the 382 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 383 * first. The NIC will load the mailbox after the lower 32 bit word 384 * has been updated. 385 */ 386 #define BGE_MBX_IRQ0_HI 0x0200 387 #define BGE_MBX_IRQ0_LO 0x0204 388 #define BGE_MBX_IRQ1_HI 0x0208 389 #define BGE_MBX_IRQ1_LO 0x020C 390 #define BGE_MBX_IRQ2_HI 0x0210 391 #define BGE_MBX_IRQ2_LO 0x0214 392 #define BGE_MBX_IRQ3_HI 0x0218 393 #define BGE_MBX_IRQ3_LO 0x021C 394 #define BGE_MBX_GEN0_HI 0x0220 395 #define BGE_MBX_GEN0_LO 0x0224 396 #define BGE_MBX_GEN1_HI 0x0228 397 #define BGE_MBX_GEN1_LO 0x022C 398 #define BGE_MBX_GEN2_HI 0x0230 399 #define BGE_MBX_GEN2_LO 0x0234 400 #define BGE_MBX_GEN3_HI 0x0228 401 #define BGE_MBX_GEN3_LO 0x022C 402 #define BGE_MBX_GEN4_HI 0x0240 403 #define BGE_MBX_GEN4_LO 0x0244 404 #define BGE_MBX_GEN5_HI 0x0248 405 #define BGE_MBX_GEN5_LO 0x024C 406 #define BGE_MBX_GEN6_HI 0x0250 407 #define BGE_MBX_GEN6_LO 0x0254 408 #define BGE_MBX_GEN7_HI 0x0258 409 #define BGE_MBX_GEN7_LO 0x025C 410 #define BGE_MBX_RELOAD_STATS_HI 0x0260 411 #define BGE_MBX_RELOAD_STATS_LO 0x0264 412 #define BGE_MBX_RX_STD_PROD_HI 0x0268 413 #define BGE_MBX_RX_STD_PROD_LO 0x026C 414 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 415 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 416 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 417 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 418 #define BGE_MBX_RX_CONS0_HI 0x0280 419 #define BGE_MBX_RX_CONS0_LO 0x0284 420 #define BGE_MBX_RX_CONS1_HI 0x0288 421 #define BGE_MBX_RX_CONS1_LO 0x028C 422 #define BGE_MBX_RX_CONS2_HI 0x0290 423 #define BGE_MBX_RX_CONS2_LO 0x0294 424 #define BGE_MBX_RX_CONS3_HI 0x0298 425 #define BGE_MBX_RX_CONS3_LO 0x029C 426 #define BGE_MBX_RX_CONS4_HI 0x02A0 427 #define BGE_MBX_RX_CONS4_LO 0x02A4 428 #define BGE_MBX_RX_CONS5_HI 0x02A8 429 #define BGE_MBX_RX_CONS5_LO 0x02AC 430 #define BGE_MBX_RX_CONS6_HI 0x02B0 431 #define BGE_MBX_RX_CONS6_LO 0x02B4 432 #define BGE_MBX_RX_CONS7_HI 0x02B8 433 #define BGE_MBX_RX_CONS7_LO 0x02BC 434 #define BGE_MBX_RX_CONS8_HI 0x02C0 435 #define BGE_MBX_RX_CONS8_LO 0x02C4 436 #define BGE_MBX_RX_CONS9_HI 0x02C8 437 #define BGE_MBX_RX_CONS9_LO 0x02CC 438 #define BGE_MBX_RX_CONS10_HI 0x02D0 439 #define BGE_MBX_RX_CONS10_LO 0x02D4 440 #define BGE_MBX_RX_CONS11_HI 0x02D8 441 #define BGE_MBX_RX_CONS11_LO 0x02DC 442 #define BGE_MBX_RX_CONS12_HI 0x02E0 443 #define BGE_MBX_RX_CONS12_LO 0x02E4 444 #define BGE_MBX_RX_CONS13_HI 0x02E8 445 #define BGE_MBX_RX_CONS13_LO 0x02EC 446 #define BGE_MBX_RX_CONS14_HI 0x02F0 447 #define BGE_MBX_RX_CONS14_LO 0x02F4 448 #define BGE_MBX_RX_CONS15_HI 0x02F8 449 #define BGE_MBX_RX_CONS15_LO 0x02FC 450 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 451 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 452 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 453 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 454 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 455 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 456 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 457 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 458 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 459 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 460 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 461 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 462 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 463 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 464 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 465 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 466 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 467 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 468 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 469 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 470 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 471 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 472 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 473 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 474 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 475 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 476 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 477 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 478 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 479 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 480 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 481 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 482 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 483 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 484 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 485 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 486 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 487 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 488 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 489 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 490 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 491 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 492 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 493 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 494 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 495 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 496 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 497 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 498 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 499 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 500 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 501 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 502 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 503 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 504 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 505 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 506 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 507 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 508 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 509 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 510 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 511 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 512 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 513 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 514 515 #define BGE_TX_RINGS_MAX 4 516 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 517 #define BGE_RX_RINGS_MAX 16 518 519 /* Ethernet MAC control registers */ 520 #define BGE_MAC_MODE 0x0400 521 #define BGE_MAC_STS 0x0404 522 #define BGE_MAC_EVT_ENB 0x0408 523 #define BGE_MAC_LED_CTL 0x040C 524 #define BGE_MAC_ADDR1_LO 0x0410 525 #define BGE_MAC_ADDR1_HI 0x0414 526 #define BGE_MAC_ADDR2_LO 0x0418 527 #define BGE_MAC_ADDR2_HI 0x041C 528 #define BGE_MAC_ADDR3_LO 0x0420 529 #define BGE_MAC_ADDR3_HI 0x0424 530 #define BGE_MAC_ADDR4_LO 0x0428 531 #define BGE_MAC_ADDR4_HI 0x042C 532 #define BGE_WOL_PATPTR 0x0430 533 #define BGE_WOL_PATCFG 0x0434 534 #define BGE_TX_RANDOM_BACKOFF 0x0438 535 #define BGE_RX_MTU 0x043C 536 #define BGE_GBIT_PCS_TEST 0x0440 537 #define BGE_TX_TBI_AUTONEG 0x0444 538 #define BGE_RX_TBI_AUTONEG 0x0448 539 #define BGE_MI_COMM 0x044C 540 #define BGE_MI_STS 0x0450 541 #define BGE_MI_MODE 0x0454 542 #define BGE_AUTOPOLL_STS 0x0458 543 #define BGE_TX_MODE 0x045C 544 #define BGE_TX_STS 0x0460 545 #define BGE_TX_LENGTHS 0x0464 546 #define BGE_RX_MODE 0x0468 547 #define BGE_RX_STS 0x046C 548 #define BGE_MAR0 0x0470 549 #define BGE_MAR1 0x0474 550 #define BGE_MAR2 0x0478 551 #define BGE_MAR3 0x047C 552 #define BGE_RX_BD_RULES_CTL0 0x0480 553 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 554 #define BGE_RX_BD_RULES_CTL1 0x0488 555 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 556 #define BGE_RX_BD_RULES_CTL2 0x0490 557 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 558 #define BGE_RX_BD_RULES_CTL3 0x0498 559 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 560 #define BGE_RX_BD_RULES_CTL4 0x04A0 561 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 562 #define BGE_RX_BD_RULES_CTL5 0x04A8 563 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 564 #define BGE_RX_BD_RULES_CTL6 0x04B0 565 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 566 #define BGE_RX_BD_RULES_CTL7 0x04B8 567 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 568 #define BGE_RX_BD_RULES_CTL8 0x04C0 569 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 570 #define BGE_RX_BD_RULES_CTL9 0x04C8 571 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 572 #define BGE_RX_BD_RULES_CTL10 0x04D0 573 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 574 #define BGE_RX_BD_RULES_CTL11 0x04D8 575 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 576 #define BGE_RX_BD_RULES_CTL12 0x04E0 577 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 578 #define BGE_RX_BD_RULES_CTL13 0x04E8 579 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 580 #define BGE_RX_BD_RULES_CTL14 0x04F0 581 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 582 #define BGE_RX_BD_RULES_CTL15 0x04F8 583 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 584 #define BGE_RX_RULES_CFG 0x0500 585 #define BGE_SERDES_CFG 0x0590 586 #define BGE_SERDES_STS 0x0594 587 #define BGE_SGDIG_CFG 0x05B0 588 #define BGE_SGDIG_STS 0x05B4 589 #define BGE_MAC_STATS 0x0800 590 591 /* Ethernet MAC Mode register */ 592 #define BGE_MACMODE_RESET 0x00000001 593 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 594 #define BGE_MACMODE_PORTMODE 0x0000000C 595 #define BGE_MACMODE_LOOPBACK 0x00000010 596 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 597 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 598 #define BGE_MACMODE_MAX_DEFER 0x00000200 599 #define BGE_MACMODE_LINK_POLARITY 0x00000400 600 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 601 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 602 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 603 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 604 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 605 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 606 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 607 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 608 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 609 #define BGE_MACMODE_MIP_ENB 0x00100000 610 #define BGE_MACMODE_TXDMA_ENB 0x00200000 611 #define BGE_MACMODE_RXDMA_ENB 0x00400000 612 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 613 614 #define BGE_PORTMODE_NONE 0x00000000 615 #define BGE_PORTMODE_MII 0x00000004 616 #define BGE_PORTMODE_GMII 0x00000008 617 #define BGE_PORTMODE_TBI 0x0000000C 618 619 /* MAC Status register */ 620 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 621 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 622 #define BGE_MACSTAT_RX_CFG 0x00000004 623 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 624 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 625 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 626 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 627 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 628 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 629 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 630 #define BGE_MACSTAT_ODI_ERROR 0x02000000 631 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 632 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 633 634 /* MAC Event Enable Register */ 635 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 636 #define BGE_EVTENB_LINK_CHANGED 0x00001000 637 #define BGE_EVTENB_MI_COMPLETE 0x00400000 638 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 639 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 640 #define BGE_EVTENB_ODI_ERROR 0x02000000 641 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 642 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 643 644 /* LED Control Register */ 645 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 646 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 647 #define BGE_LEDCTL_100MBPS_LED 0x00000004 648 #define BGE_LEDCTL_10MBPS_LED 0x00000008 649 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 650 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 651 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 652 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 653 #define BGE_LEDCTL_100MBPS_STS 0x00000100 654 #define BGE_LEDCTL_10MBPS_STS 0x00000200 655 #define BGE_LEDCTL_TRADLED_STS 0x00000400 656 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 657 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 658 659 /* TX backoff seed register */ 660 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 661 662 /* Autopoll status register */ 663 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 664 665 /* Transmit MAC mode register */ 666 #define BGE_TXMODE_RESET 0x00000001 667 #define BGE_TXMODE_ENABLE 0x00000002 668 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 669 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 670 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 671 672 /* Transmit MAC status register */ 673 #define BGE_TXSTAT_RX_XOFFED 0x00000001 674 #define BGE_TXSTAT_SENT_XOFF 0x00000002 675 #define BGE_TXSTAT_SENT_XON 0x00000004 676 #define BGE_TXSTAT_LINK_UP 0x00000008 677 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 678 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 679 680 /* Transmit MAC lengths register */ 681 #define BGE_TXLEN_SLOTTIME 0x000000FF 682 #define BGE_TXLEN_IPG 0x00000F00 683 #define BGE_TXLEN_CRS 0x00003000 684 685 /* Receive MAC mode register */ 686 #define BGE_RXMODE_RESET 0x00000001 687 #define BGE_RXMODE_ENABLE 0x00000002 688 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 689 #define BGE_RXMODE_RX_GIANTS 0x00000020 690 #define BGE_RXMODE_RX_RUNTS 0x00000040 691 #define BGE_RXMODE_8022_LENCHECK 0x00000080 692 #define BGE_RXMODE_RX_PROMISC 0x00000100 693 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 694 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 695 696 /* Receive MAC status register */ 697 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 698 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 699 #define BGE_RXSTAT_RCVD_XON 0x00000004 700 701 /* Receive Rules Control register */ 702 #define BGE_RXRULECTL_OFFSET 0x000000FF 703 #define BGE_RXRULECTL_CLASS 0x00001F00 704 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 705 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 706 #define BGE_RXRULECTL_MAP 0x01000000 707 #define BGE_RXRULECTL_DISCARD 0x02000000 708 #define BGE_RXRULECTL_MASK 0x04000000 709 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 710 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 711 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 712 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 713 714 /* Receive Rules Mask register */ 715 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 716 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 717 718 /* SERDES configuration register */ 719 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 720 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 721 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 722 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 723 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 724 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 725 #define BGE_SERDESCFG_TXMODE 0x00001000 726 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 727 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 728 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 729 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 730 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 731 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 732 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 733 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 734 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 735 736 /* SERDES status register */ 737 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 738 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 739 740 /* SGDIG config (not documented) */ 741 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 742 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 743 #define BGE_SGDIGCFG_SEND 0x40000000 744 #define BGE_SGDIGCFG_AUTO 0x80000000 745 746 /* SGDIG status (not documented) */ 747 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 748 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 749 #define BGE_SGDIGSTS_DONE 0x00000002 750 751 752 /* MI communication register */ 753 #define BGE_MICOMM_DATA 0x0000FFFF 754 #define BGE_MICOMM_REG 0x001F0000 755 #define BGE_MICOMM_PHY 0x03E00000 756 #define BGE_MICOMM_CMD 0x0C000000 757 #define BGE_MICOMM_READFAIL 0x10000000 758 #define BGE_MICOMM_BUSY 0x20000000 759 760 #define BGE_MIREG(x) ((x & 0x1F) << 16) 761 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 762 #define BGE_MICMD_WRITE 0x04000000 763 #define BGE_MICMD_READ 0x08000000 764 765 /* MI status register */ 766 #define BGE_MISTS_LINK 0x00000001 767 #define BGE_MISTS_10MBPS 0x00000002 768 769 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 770 #define BGE_MIMODE_AUTOPOLL 0x00000010 771 #define BGE_MIMODE_CLKCNT 0x001F0000 772 773 774 /* 775 * Send data initiator control registers. 776 */ 777 #define BGE_SDI_MODE 0x0C00 778 #define BGE_SDI_STATUS 0x0C04 779 #define BGE_SDI_STATS_CTL 0x0C08 780 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 781 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 782 #define BGE_LOCSTATS_COS0 0x0C80 783 #define BGE_LOCSTATS_COS1 0x0C84 784 #define BGE_LOCSTATS_COS2 0x0C88 785 #define BGE_LOCSTATS_COS3 0x0C8C 786 #define BGE_LOCSTATS_COS4 0x0C90 787 #define BGE_LOCSTATS_COS5 0x0C84 788 #define BGE_LOCSTATS_COS6 0x0C98 789 #define BGE_LOCSTATS_COS7 0x0C9C 790 #define BGE_LOCSTATS_COS8 0x0CA0 791 #define BGE_LOCSTATS_COS9 0x0CA4 792 #define BGE_LOCSTATS_COS10 0x0CA8 793 #define BGE_LOCSTATS_COS11 0x0CAC 794 #define BGE_LOCSTATS_COS12 0x0CB0 795 #define BGE_LOCSTATS_COS13 0x0CB4 796 #define BGE_LOCSTATS_COS14 0x0CB8 797 #define BGE_LOCSTATS_COS15 0x0CBC 798 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 799 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 800 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 801 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 802 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 803 #define BGE_LOCSTATS_IRQS 0x0CD4 804 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 805 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 806 807 /* Send Data Initiator mode register */ 808 #define BGE_SDIMODE_RESET 0x00000001 809 #define BGE_SDIMODE_ENABLE 0x00000002 810 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 811 812 /* Send Data Initiator stats register */ 813 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 814 815 /* Send Data Initiator stats control register */ 816 #define BGE_SDISTATSCTL_ENABLE 0x00000001 817 #define BGE_SDISTATSCTL_FASTER 0x00000002 818 #define BGE_SDISTATSCTL_CLEAR 0x00000004 819 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 820 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 821 822 /* 823 * Send Data Completion Control registers 824 */ 825 #define BGE_SDC_MODE 0x1000 826 #define BGE_SDC_STATUS 0x1004 827 828 /* Send Data completion mode register */ 829 #define BGE_SDCMODE_RESET 0x00000001 830 #define BGE_SDCMODE_ENABLE 0x00000002 831 #define BGE_SDCMODE_ATTN 0x00000004 832 833 /* Send Data completion status register */ 834 #define BGE_SDCSTAT_ATTN 0x00000004 835 836 /* 837 * Send BD Ring Selector Control registers 838 */ 839 #define BGE_SRS_MODE 0x1400 840 #define BGE_SRS_STATUS 0x1404 841 #define BGE_SRS_HWDIAG 0x1408 842 #define BGE_SRS_LOC_NIC_CONS0 0x1440 843 #define BGE_SRS_LOC_NIC_CONS1 0x1444 844 #define BGE_SRS_LOC_NIC_CONS2 0x1448 845 #define BGE_SRS_LOC_NIC_CONS3 0x144C 846 #define BGE_SRS_LOC_NIC_CONS4 0x1450 847 #define BGE_SRS_LOC_NIC_CONS5 0x1454 848 #define BGE_SRS_LOC_NIC_CONS6 0x1458 849 #define BGE_SRS_LOC_NIC_CONS7 0x145C 850 #define BGE_SRS_LOC_NIC_CONS8 0x1460 851 #define BGE_SRS_LOC_NIC_CONS9 0x1464 852 #define BGE_SRS_LOC_NIC_CONS10 0x1468 853 #define BGE_SRS_LOC_NIC_CONS11 0x146C 854 #define BGE_SRS_LOC_NIC_CONS12 0x1470 855 #define BGE_SRS_LOC_NIC_CONS13 0x1474 856 #define BGE_SRS_LOC_NIC_CONS14 0x1478 857 #define BGE_SRS_LOC_NIC_CONS15 0x147C 858 859 /* Send BD Ring Selector Mode register */ 860 #define BGE_SRSMODE_RESET 0x00000001 861 #define BGE_SRSMODE_ENABLE 0x00000002 862 #define BGE_SRSMODE_ATTN 0x00000004 863 864 /* Send BD Ring Selector Status register */ 865 #define BGE_SRSSTAT_ERROR 0x00000004 866 867 /* Send BD Ring Selector HW Diagnostics register */ 868 #define BGE_SRSHWDIAG_STATE 0x0000000F 869 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 870 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 871 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 872 873 /* 874 * Send BD Initiator Selector Control registers 875 */ 876 #define BGE_SBDI_MODE 0x1800 877 #define BGE_SBDI_STATUS 0x1804 878 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 879 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 880 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 881 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 882 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 883 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 884 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 885 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 886 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 887 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 888 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 889 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 890 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 891 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 892 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 893 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 894 895 /* Send BD Initiator Mode register */ 896 #define BGE_SBDIMODE_RESET 0x00000001 897 #define BGE_SBDIMODE_ENABLE 0x00000002 898 #define BGE_SBDIMODE_ATTN 0x00000004 899 900 /* Send BD Initiator Status register */ 901 #define BGE_SBDISTAT_ERROR 0x00000004 902 903 /* 904 * Send BD Completion Control registers 905 */ 906 #define BGE_SBDC_MODE 0x1C00 907 #define BGE_SBDC_STATUS 0x1C04 908 909 /* Send BD Completion Control Mode register */ 910 #define BGE_SBDCMODE_RESET 0x00000001 911 #define BGE_SBDCMODE_ENABLE 0x00000002 912 #define BGE_SBDCMODE_ATTN 0x00000004 913 914 /* Send BD Completion Control Status register */ 915 #define BGE_SBDCSTAT_ATTN 0x00000004 916 917 /* 918 * Receive List Placement Control registers 919 */ 920 #define BGE_RXLP_MODE 0x2000 921 #define BGE_RXLP_STATUS 0x2004 922 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 923 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 924 #define BGE_RXLP_CFG 0x2010 925 #define BGE_RXLP_STATS_CTL 0x2014 926 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 927 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 928 #define BGE_RXLP_HEAD0 0x2100 929 #define BGE_RXLP_TAIL0 0x2104 930 #define BGE_RXLP_COUNT0 0x2108 931 #define BGE_RXLP_HEAD1 0x2110 932 #define BGE_RXLP_TAIL1 0x2114 933 #define BGE_RXLP_COUNT1 0x2118 934 #define BGE_RXLP_HEAD2 0x2120 935 #define BGE_RXLP_TAIL2 0x2124 936 #define BGE_RXLP_COUNT2 0x2128 937 #define BGE_RXLP_HEAD3 0x2130 938 #define BGE_RXLP_TAIL3 0x2134 939 #define BGE_RXLP_COUNT3 0x2138 940 #define BGE_RXLP_HEAD4 0x2140 941 #define BGE_RXLP_TAIL4 0x2144 942 #define BGE_RXLP_COUNT4 0x2148 943 #define BGE_RXLP_HEAD5 0x2150 944 #define BGE_RXLP_TAIL5 0x2154 945 #define BGE_RXLP_COUNT5 0x2158 946 #define BGE_RXLP_HEAD6 0x2160 947 #define BGE_RXLP_TAIL6 0x2164 948 #define BGE_RXLP_COUNT6 0x2168 949 #define BGE_RXLP_HEAD7 0x2170 950 #define BGE_RXLP_TAIL7 0x2174 951 #define BGE_RXLP_COUNT7 0x2178 952 #define BGE_RXLP_HEAD8 0x2180 953 #define BGE_RXLP_TAIL8 0x2184 954 #define BGE_RXLP_COUNT8 0x2188 955 #define BGE_RXLP_HEAD9 0x2190 956 #define BGE_RXLP_TAIL9 0x2194 957 #define BGE_RXLP_COUNT9 0x2198 958 #define BGE_RXLP_HEAD10 0x21A0 959 #define BGE_RXLP_TAIL10 0x21A4 960 #define BGE_RXLP_COUNT10 0x21A8 961 #define BGE_RXLP_HEAD11 0x21B0 962 #define BGE_RXLP_TAIL11 0x21B4 963 #define BGE_RXLP_COUNT11 0x21B8 964 #define BGE_RXLP_HEAD12 0x21C0 965 #define BGE_RXLP_TAIL12 0x21C4 966 #define BGE_RXLP_COUNT12 0x21C8 967 #define BGE_RXLP_HEAD13 0x21D0 968 #define BGE_RXLP_TAIL13 0x21D4 969 #define BGE_RXLP_COUNT13 0x21D8 970 #define BGE_RXLP_HEAD14 0x21E0 971 #define BGE_RXLP_TAIL14 0x21E4 972 #define BGE_RXLP_COUNT14 0x21E8 973 #define BGE_RXLP_HEAD15 0x21F0 974 #define BGE_RXLP_TAIL15 0x21F4 975 #define BGE_RXLP_COUNT15 0x21F8 976 #define BGE_RXLP_LOCSTAT_COS0 0x2200 977 #define BGE_RXLP_LOCSTAT_COS1 0x2204 978 #define BGE_RXLP_LOCSTAT_COS2 0x2208 979 #define BGE_RXLP_LOCSTAT_COS3 0x220C 980 #define BGE_RXLP_LOCSTAT_COS4 0x2210 981 #define BGE_RXLP_LOCSTAT_COS5 0x2214 982 #define BGE_RXLP_LOCSTAT_COS6 0x2218 983 #define BGE_RXLP_LOCSTAT_COS7 0x221C 984 #define BGE_RXLP_LOCSTAT_COS8 0x2220 985 #define BGE_RXLP_LOCSTAT_COS9 0x2224 986 #define BGE_RXLP_LOCSTAT_COS10 0x2228 987 #define BGE_RXLP_LOCSTAT_COS11 0x222C 988 #define BGE_RXLP_LOCSTAT_COS12 0x2230 989 #define BGE_RXLP_LOCSTAT_COS13 0x2234 990 #define BGE_RXLP_LOCSTAT_COS14 0x2238 991 #define BGE_RXLP_LOCSTAT_COS15 0x223C 992 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 993 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 994 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 995 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 996 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 997 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 998 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 999 1000 1001 /* Receive List Placement mode register */ 1002 #define BGE_RXLPMODE_RESET 0x00000001 1003 #define BGE_RXLPMODE_ENABLE 0x00000002 1004 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1005 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1006 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1007 1008 /* Receive List Placement Status register */ 1009 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1010 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1011 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1012 1013 /* 1014 * Receive Data and Receive BD Initiator Control Registers 1015 */ 1016 #define BGE_RDBDI_MODE 0x2400 1017 #define BGE_RDBDI_STATUS 0x2404 1018 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1019 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1020 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1021 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1022 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1023 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1024 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1025 #define BGE_RX_STD_RCB_NICADDR 0x245C 1026 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1027 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1028 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1029 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1030 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1031 #define BGE_RDBDI_STD_RX_CONS 0x2474 1032 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1033 #define BGE_RDBDI_RETURN_PROD0 0x2480 1034 #define BGE_RDBDI_RETURN_PROD1 0x2484 1035 #define BGE_RDBDI_RETURN_PROD2 0x2488 1036 #define BGE_RDBDI_RETURN_PROD3 0x248C 1037 #define BGE_RDBDI_RETURN_PROD4 0x2490 1038 #define BGE_RDBDI_RETURN_PROD5 0x2494 1039 #define BGE_RDBDI_RETURN_PROD6 0x2498 1040 #define BGE_RDBDI_RETURN_PROD7 0x249C 1041 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1042 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1043 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1044 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1045 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1046 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1047 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1048 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1049 #define BGE_RDBDI_HWDIAG 0x24C0 1050 1051 1052 /* Receive Data and Receive BD Initiator Mode register */ 1053 #define BGE_RDBDIMODE_RESET 0x00000001 1054 #define BGE_RDBDIMODE_ENABLE 0x00000002 1055 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1056 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1057 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1058 1059 /* Receive Data and Receive BD Initiator Status register */ 1060 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1061 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1062 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1063 1064 1065 /* 1066 * Receive Data Completion Control registers 1067 */ 1068 #define BGE_RDC_MODE 0x2800 1069 1070 /* Receive Data Completion Mode register */ 1071 #define BGE_RDCMODE_RESET 0x00000001 1072 #define BGE_RDCMODE_ENABLE 0x00000002 1073 #define BGE_RDCMODE_ATTN 0x00000004 1074 1075 /* 1076 * Receive BD Initiator Control registers 1077 */ 1078 #define BGE_RBDI_MODE 0x2C00 1079 #define BGE_RBDI_STATUS 0x2C04 1080 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1081 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1082 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1083 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1084 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1085 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1086 1087 /* Receive BD Initiator Mode register */ 1088 #define BGE_RBDIMODE_RESET 0x00000001 1089 #define BGE_RBDIMODE_ENABLE 0x00000002 1090 #define BGE_RBDIMODE_ATTN 0x00000004 1091 1092 /* Receive BD Initiator Status register */ 1093 #define BGE_RBDISTAT_ATTN 0x00000004 1094 1095 /* 1096 * Receive BD Completion Control registers 1097 */ 1098 #define BGE_RBDC_MODE 0x3000 1099 #define BGE_RBDC_STATUS 0x3004 1100 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1101 #define BGE_RBDC_STD_BD_PROD 0x300C 1102 #define BGE_RBDC_MINI_BD_PROD 0x3010 1103 1104 /* Receive BD completion mode register */ 1105 #define BGE_RBDCMODE_RESET 0x00000001 1106 #define BGE_RBDCMODE_ENABLE 0x00000002 1107 #define BGE_RBDCMODE_ATTN 0x00000004 1108 1109 /* Receive BD completion status register */ 1110 #define BGE_RBDCSTAT_ERROR 0x00000004 1111 1112 /* 1113 * Receive List Selector Control registers 1114 */ 1115 #define BGE_RXLS_MODE 0x3400 1116 #define BGE_RXLS_STATUS 0x3404 1117 1118 /* Receive List Selector Mode register */ 1119 #define BGE_RXLSMODE_RESET 0x00000001 1120 #define BGE_RXLSMODE_ENABLE 0x00000002 1121 #define BGE_RXLSMODE_ATTN 0x00000004 1122 1123 /* Receive List Selector Status register */ 1124 #define BGE_RXLSSTAT_ERROR 0x00000004 1125 1126 /* 1127 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1128 */ 1129 #define BGE_MBCF_MODE 0x3800 1130 #define BGE_MBCF_STATUS 0x3804 1131 1132 /* Mbuf Cluster Free mode register */ 1133 #define BGE_MBCFMODE_RESET 0x00000001 1134 #define BGE_MBCFMODE_ENABLE 0x00000002 1135 #define BGE_MBCFMODE_ATTN 0x00000004 1136 1137 /* Mbuf Cluster Free status register */ 1138 #define BGE_MBCFSTAT_ERROR 0x00000004 1139 1140 /* 1141 * Host Coalescing Control registers 1142 */ 1143 #define BGE_HCC_MODE 0x3C00 1144 #define BGE_HCC_STATUS 0x3C04 1145 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1146 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1147 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1148 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1149 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1150 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1151 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1152 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1153 #define BGE_HCC_STATS_TICKS 0x3C28 1154 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1155 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1156 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1157 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1158 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1159 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1160 #define BGE_FLOW_ATTN 0x3C48 1161 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1162 #define BGE_HCC_STD_BD_CONS 0x3C54 1163 #define BGE_HCC_MINI_BD_CONS 0x3C58 1164 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1165 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1166 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1167 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1168 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1169 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1170 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1171 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1172 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1173 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1174 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1175 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1176 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1177 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1178 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1179 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1180 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1181 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1182 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1183 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1184 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1185 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1186 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1187 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1188 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1189 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1190 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1191 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1192 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1193 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1194 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1195 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1196 1197 1198 /* Host coalescing mode register */ 1199 #define BGE_HCCMODE_RESET 0x00000001 1200 #define BGE_HCCMODE_ENABLE 0x00000002 1201 #define BGE_HCCMODE_ATTN 0x00000004 1202 #define BGE_HCCMODE_COAL_NOW 0x00000008 1203 #define BGE_HCCMODE_MSI_BITS 0x00000070 1204 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1205 1206 #define BGE_STATBLKSZ_FULL 0x00000000 1207 #define BGE_STATBLKSZ_64BYTE 0x00000080 1208 #define BGE_STATBLKSZ_32BYTE 0x00000100 1209 1210 /* Host coalescing status register */ 1211 #define BGE_HCCSTAT_ERROR 0x00000004 1212 1213 /* Flow attention register */ 1214 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1215 #define BGE_FLOWATTN_MEMARB 0x00000080 1216 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1217 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1218 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1219 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1220 #define BGE_FLOWATTN_RDBDI 0x00080000 1221 #define BGE_FLOWATTN_RXLS 0x00100000 1222 #define BGE_FLOWATTN_RXLP 0x00200000 1223 #define BGE_FLOWATTN_RBDC 0x00400000 1224 #define BGE_FLOWATTN_RBDI 0x00800000 1225 #define BGE_FLOWATTN_SDC 0x08000000 1226 #define BGE_FLOWATTN_SDI 0x10000000 1227 #define BGE_FLOWATTN_SRS 0x20000000 1228 #define BGE_FLOWATTN_SBDC 0x40000000 1229 #define BGE_FLOWATTN_SBDI 0x80000000 1230 1231 /* 1232 * Memory arbiter registers 1233 */ 1234 #define BGE_MARB_MODE 0x4000 1235 #define BGE_MARB_STATUS 0x4004 1236 #define BGE_MARB_TRAPADDR_HI 0x4008 1237 #define BGE_MARB_TRAPADDR_LO 0x400C 1238 1239 /* Memory arbiter mode register */ 1240 #define BGE_MARBMODE_RESET 0x00000001 1241 #define BGE_MARBMODE_ENABLE 0x00000002 1242 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1243 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1244 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1245 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1246 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1247 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1248 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1249 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1250 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1251 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1252 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1253 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1254 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1255 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1256 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1257 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1258 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1259 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1260 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1261 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1262 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1263 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1264 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1265 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1266 1267 /* Memory arbiter status register */ 1268 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1269 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1270 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1271 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1272 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1273 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1274 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1275 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1276 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1277 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1278 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1279 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1280 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1281 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1282 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1283 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1284 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1285 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1286 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1287 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1288 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1289 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1290 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1291 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1292 1293 /* 1294 * Buffer manager control registers 1295 */ 1296 #define BGE_BMAN_MODE 0x4400 1297 #define BGE_BMAN_STATUS 0x4404 1298 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1299 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1300 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1301 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1302 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1303 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1304 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1305 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1306 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1307 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1308 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1309 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1310 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1311 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1312 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1313 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1314 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1315 #define BGE_BMAN_HWDIAG_1 0x444C 1316 #define BGE_BMAN_HWDIAG_2 0x4450 1317 #define BGE_BMAN_HWDIAG_3 0x4454 1318 1319 /* Buffer manager mode register */ 1320 #define BGE_BMANMODE_RESET 0x00000001 1321 #define BGE_BMANMODE_ENABLE 0x00000002 1322 #define BGE_BMANMODE_ATTN 0x00000004 1323 #define BGE_BMANMODE_TESTMODE 0x00000008 1324 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1325 1326 /* Buffer manager status register */ 1327 #define BGE_BMANSTAT_ERRO 0x00000004 1328 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1329 1330 1331 /* 1332 * Read DMA Control registers 1333 */ 1334 #define BGE_RDMA_MODE 0x4800 1335 #define BGE_RDMA_STATUS 0x4804 1336 1337 /* Read DMA mode register */ 1338 #define BGE_RDMAMODE_RESET 0x00000001 1339 #define BGE_RDMAMODE_ENABLE 0x00000002 1340 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1341 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1342 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1343 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1344 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1345 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1346 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1347 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1348 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1349 1350 /* Read DMA status register */ 1351 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1352 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1353 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1354 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1355 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1356 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1357 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1358 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1359 1360 /* 1361 * Write DMA control registers 1362 */ 1363 #define BGE_WDMA_MODE 0x4C00 1364 #define BGE_WDMA_STATUS 0x4C04 1365 1366 /* Write DMA mode register */ 1367 #define BGE_WDMAMODE_RESET 0x00000001 1368 #define BGE_WDMAMODE_ENABLE 0x00000002 1369 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1370 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1371 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1372 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1373 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1374 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1375 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1376 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1377 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1378 1379 /* Write DMA status register */ 1380 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1381 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1382 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1383 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1384 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1385 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1386 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1387 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1388 1389 1390 /* 1391 * RX CPU registers 1392 */ 1393 #define BGE_RXCPU_MODE 0x5000 1394 #define BGE_RXCPU_STATUS 0x5004 1395 #define BGE_RXCPU_PC 0x501C 1396 1397 /* RX CPU mode register */ 1398 #define BGE_RXCPUMODE_RESET 0x00000001 1399 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1400 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1401 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1402 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1403 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1404 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1405 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1406 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1407 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1408 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1409 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1410 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1411 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1412 1413 /* RX CPU status register */ 1414 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1415 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1416 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1417 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1418 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1419 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1420 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1421 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1422 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1423 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1424 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1425 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1426 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1427 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1428 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1429 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1430 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1431 1432 1433 /* 1434 * TX CPU registers 1435 */ 1436 #define BGE_TXCPU_MODE 0x5400 1437 #define BGE_TXCPU_STATUS 0x5404 1438 #define BGE_TXCPU_PC 0x541C 1439 1440 /* TX CPU mode register */ 1441 #define BGE_TXCPUMODE_RESET 0x00000001 1442 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1443 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1444 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1445 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1446 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1447 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1448 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1449 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1450 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1451 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1452 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1453 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1454 1455 /* TX CPU status register */ 1456 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1457 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1458 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1459 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1460 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1461 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1462 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1463 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1464 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1465 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1466 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1467 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1468 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1469 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1470 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1471 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1472 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1473 1474 1475 /* 1476 * Low priority mailbox registers 1477 */ 1478 #define BGE_LPMBX_IRQ0_HI 0x5800 1479 #define BGE_LPMBX_IRQ0_LO 0x5804 1480 #define BGE_LPMBX_IRQ1_HI 0x5808 1481 #define BGE_LPMBX_IRQ1_LO 0x580C 1482 #define BGE_LPMBX_IRQ2_HI 0x5810 1483 #define BGE_LPMBX_IRQ2_LO 0x5814 1484 #define BGE_LPMBX_IRQ3_HI 0x5818 1485 #define BGE_LPMBX_IRQ3_LO 0x581C 1486 #define BGE_LPMBX_GEN0_HI 0x5820 1487 #define BGE_LPMBX_GEN0_LO 0x5824 1488 #define BGE_LPMBX_GEN1_HI 0x5828 1489 #define BGE_LPMBX_GEN1_LO 0x582C 1490 #define BGE_LPMBX_GEN2_HI 0x5830 1491 #define BGE_LPMBX_GEN2_LO 0x5834 1492 #define BGE_LPMBX_GEN3_HI 0x5828 1493 #define BGE_LPMBX_GEN3_LO 0x582C 1494 #define BGE_LPMBX_GEN4_HI 0x5840 1495 #define BGE_LPMBX_GEN4_LO 0x5844 1496 #define BGE_LPMBX_GEN5_HI 0x5848 1497 #define BGE_LPMBX_GEN5_LO 0x584C 1498 #define BGE_LPMBX_GEN6_HI 0x5850 1499 #define BGE_LPMBX_GEN6_LO 0x5854 1500 #define BGE_LPMBX_GEN7_HI 0x5858 1501 #define BGE_LPMBX_GEN7_LO 0x585C 1502 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1503 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1504 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1505 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1506 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1507 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1508 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1509 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1510 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1511 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1512 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1513 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1514 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1515 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1516 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1517 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1518 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1519 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1520 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1521 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1522 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1523 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1524 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1525 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1526 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1527 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1528 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1529 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1530 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1531 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1532 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1533 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1534 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1535 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1536 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1537 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1538 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1539 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1540 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1541 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1542 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1543 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1544 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1545 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1546 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1547 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1548 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1549 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1550 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1551 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1552 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1553 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1554 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1555 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1556 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1557 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1558 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1559 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1560 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1561 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1562 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1563 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1564 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1565 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1566 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1567 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1568 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1569 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1570 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1571 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1572 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1573 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1574 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1575 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1576 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1577 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1578 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1579 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1580 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1581 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1582 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1583 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1584 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1585 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1586 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1587 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1588 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1589 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1590 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1591 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1592 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1593 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1594 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1595 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1596 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1597 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1598 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1599 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1600 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1601 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1602 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1603 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1604 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1605 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1606 1607 /* 1608 * Flow throw Queue reset register 1609 */ 1610 #define BGE_FTQ_RESET 0x5C00 1611 1612 #define BGE_FTQRESET_DMAREAD 0x00000002 1613 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1614 #define BGE_FTQRESET_DMADONE 0x00000010 1615 #define BGE_FTQRESET_SBDC 0x00000020 1616 #define BGE_FTQRESET_SDI 0x00000040 1617 #define BGE_FTQRESET_WDMA 0x00000080 1618 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1619 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1620 #define BGE_FTQRESET_SDC 0x00000400 1621 #define BGE_FTQRESET_HCC 0x00000800 1622 #define BGE_FTQRESET_TXFIFO 0x00001000 1623 #define BGE_FTQRESET_MBC 0x00002000 1624 #define BGE_FTQRESET_RBDC 0x00004000 1625 #define BGE_FTQRESET_RXLP 0x00008000 1626 #define BGE_FTQRESET_RDBDI 0x00010000 1627 #define BGE_FTQRESET_RDC 0x00020000 1628 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1629 1630 /* 1631 * Message Signaled Interrupt registers 1632 */ 1633 #define BGE_MSI_MODE 0x6000 1634 #define BGE_MSI_STATUS 0x6004 1635 #define BGE_MSI_FIFOACCESS 0x6008 1636 1637 /* MSI mode register */ 1638 #define BGE_MSIMODE_RESET 0x00000001 1639 #define BGE_MSIMODE_ENABLE 0x00000002 1640 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1641 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1642 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1643 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1644 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1645 1646 /* MSI status register */ 1647 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1648 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1649 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1650 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1651 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1652 1653 1654 /* 1655 * DMA Completion registers 1656 */ 1657 #define BGE_DMAC_MODE 0x6400 1658 1659 /* DMA Completion mode register */ 1660 #define BGE_DMACMODE_RESET 0x00000001 1661 #define BGE_DMACMODE_ENABLE 0x00000002 1662 1663 1664 /* 1665 * General control registers. 1666 */ 1667 #define BGE_MODE_CTL 0x6800 1668 #define BGE_MISC_CFG 0x6804 1669 #define BGE_MISC_LOCAL_CTL 0x6808 1670 #define BGE_CPU_EVENT 0x6810 1671 #define BGE_EE_ADDR 0x6838 1672 #define BGE_EE_DATA 0x683C 1673 #define BGE_EE_CTL 0x6840 1674 #define BGE_MDI_CTL 0x6844 1675 #define BGE_EE_DELAY 0x6848 1676 #define BGE_FASTBOOT_PC 0x6894 1677 1678 /* Mode control register */ 1679 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1680 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1681 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1682 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1683 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1684 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1685 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1686 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1687 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1688 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1689 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1690 #define BGE_MODECTL_STACKUP 0x00010000 1691 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1692 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1693 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1694 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1695 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1696 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1697 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1698 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1699 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1700 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1701 1702 /* Misc. config register */ 1703 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1704 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1705 1706 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1707 1708 /* Misc. Local Control */ 1709 #define BGE_MLC_INTR_STATE 0x00000001 1710 #define BGE_MLC_INTR_CLR 0x00000002 1711 #define BGE_MLC_INTR_SET 0x00000004 1712 #define BGE_MLC_INTR_ONATTN 0x00000008 1713 #define BGE_MLC_MISCIO_IN0 0x00000100 1714 #define BGE_MLC_MISCIO_IN1 0x00000200 1715 #define BGE_MLC_MISCIO_IN2 0x00000400 1716 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1717 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1718 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1719 #define BGE_MLC_MISCIO_OUT0 0x00004000 1720 #define BGE_MLC_MISCIO_OUT1 0x00008000 1721 #define BGE_MLC_MISCIO_OUT2 0x00010000 1722 #define BGE_MLC_EXTRAM_ENB 0x00020000 1723 #define BGE_MLC_SRAM_SIZE 0x001C0000 1724 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1725 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1726 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1727 #define BGE_MLC_AUTO_EEPROM 0x01000000 1728 1729 #define BGE_SSRAMSIZE_256KB 0x00000000 1730 #define BGE_SSRAMSIZE_512KB 0x00040000 1731 #define BGE_SSRAMSIZE_1MB 0x00080000 1732 #define BGE_SSRAMSIZE_2MB 0x000C0000 1733 #define BGE_SSRAMSIZE_4MB 0x00100000 1734 #define BGE_SSRAMSIZE_8MB 0x00140000 1735 #define BGE_SSRAMSIZE_16M 0x00180000 1736 1737 /* EEPROM address register */ 1738 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1739 #define BGE_EEADDR_HALFCLK 0x01FF0000 1740 #define BGE_EEADDR_START 0x02000000 1741 #define BGE_EEADDR_DEVID 0x1C000000 1742 #define BGE_EEADDR_RESET 0x20000000 1743 #define BGE_EEADDR_DONE 0x40000000 1744 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1745 1746 #define BGE_EEDEVID(x) ((x & 7) << 26) 1747 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1748 #define BGE_HALFCLK_384SCL 0x60 1749 #define BGE_EE_READCMD \ 1750 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1751 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1752 #define BGE_EE_WRCMD \ 1753 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1754 BGE_EEADDR_START|BGE_EEADDR_DONE) 1755 1756 /* EEPROM Control register */ 1757 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1758 #define BGE_EECTL_CLKOUT 0x00000002 1759 #define BGE_EECTL_CLKIN 0x00000004 1760 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1761 #define BGE_EECTL_DATAOUT 0x00000010 1762 #define BGE_EECTL_DATAIN 0x00000020 1763 1764 /* MDI (MII/GMII) access register */ 1765 #define BGE_MDI_DATA 0x00000001 1766 #define BGE_MDI_DIR 0x00000002 1767 #define BGE_MDI_SEL 0x00000004 1768 #define BGE_MDI_CLK 0x00000008 1769 1770 #define BGE_MEMWIN_START 0x00008000 1771 #define BGE_MEMWIN_END 0x0000FFFF 1772 1773 1774 #define BGE_MEMWIN_READ(sc, x, val) \ 1775 do { \ 1776 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1777 (0xFFFF0000 & x), 4); \ 1778 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1779 } while(0) 1780 1781 #define BGE_MEMWIN_WRITE(sc, x, val) \ 1782 do { \ 1783 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1784 (0xFFFF0000 & x), 4); \ 1785 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1786 } while(0) 1787 1788 /* 1789 * This magic number is written to the firmware mailbox at 0xb50 1790 * before a software reset is issued. After the internal firmware 1791 * has completed its initialization it will write the opposite of 1792 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1793 * driver to synchronize with the firmware. 1794 */ 1795 #define BGE_MAGIC_NUMBER 0x4B657654 1796 1797 typedef struct { 1798 uint32_t bge_addr_hi; 1799 uint32_t bge_addr_lo; 1800 } bge_hostaddr; 1801 1802 #define BGE_HOSTADDR(x, y) \ 1803 do { \ 1804 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1805 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1806 } while(0) 1807 1808 #define BGE_ADDR_LO(y) \ 1809 ((uint64_t) (y) & 0xFFFFFFFF) 1810 #define BGE_ADDR_HI(y) \ 1811 ((uint64_t) (y) >> 32) 1812 1813 /* Ring control block structure */ 1814 struct bge_rcb { 1815 bge_hostaddr bge_hostaddr; 1816 uint32_t bge_maxlen_flags; 1817 uint32_t bge_nicaddr; 1818 }; 1819 1820 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1821 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1822 rcb + offsetof(struct bge_rcb, offset), val) 1823 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1824 1825 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1826 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1827 1828 struct bge_tx_bd { 1829 bge_hostaddr bge_addr; 1830 #if BYTE_ORDER == LITTLE_ENDIAN 1831 uint16_t bge_flags; 1832 uint16_t bge_len; 1833 uint16_t bge_vlan_tag; 1834 uint16_t bge_rsvd; 1835 #else 1836 uint16_t bge_len; 1837 uint16_t bge_flags; 1838 uint16_t bge_rsvd; 1839 uint16_t bge_vlan_tag; 1840 #endif 1841 }; 1842 1843 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1844 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1845 #define BGE_TXBDFLAG_END 0x0004 1846 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1847 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1848 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1849 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1850 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1851 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1852 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1853 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1854 #define BGE_TXBDFLAG_NO_CRC 0x8000 1855 1856 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1857 BGE_SEND_RING_1_TO_4 + \ 1858 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1859 1860 struct bge_rx_bd { 1861 bge_hostaddr bge_addr; 1862 #if BYTE_ORDER == LITTLE_ENDIAN 1863 uint16_t bge_len; 1864 uint16_t bge_idx; 1865 uint16_t bge_flags; 1866 uint16_t bge_type; 1867 uint16_t bge_tcp_udp_csum; 1868 uint16_t bge_ip_csum; 1869 uint16_t bge_vlan_tag; 1870 uint16_t bge_error_flag; 1871 #else 1872 uint16_t bge_idx; 1873 uint16_t bge_len; 1874 uint16_t bge_type; 1875 uint16_t bge_flags; 1876 uint16_t bge_ip_csum; 1877 uint16_t bge_tcp_udp_csum; 1878 uint16_t bge_error_flag; 1879 uint16_t bge_vlan_tag; 1880 #endif 1881 uint32_t bge_rsvd; 1882 uint32_t bge_opaque; 1883 }; 1884 1885 struct bge_extrx_bd { 1886 bge_hostaddr bge_addr1; 1887 bge_hostaddr bge_addr2; 1888 bge_hostaddr bge_addr3; 1889 #if BYTE_ORDER == LITTLE_ENDIAN 1890 uint16_t bge_len2; 1891 uint16_t bge_len1; 1892 uint16_t bge_rsvd1; 1893 uint16_t bge_len3; 1894 #else 1895 uint16_t bge_len1; 1896 uint16_t bge_len2; 1897 uint16_t bge_len3; 1898 uint16_t bge_rsvd1; 1899 #endif 1900 bge_hostaddr bge_addr0; 1901 #if BYTE_ORDER == LITTLE_ENDIAN 1902 uint16_t bge_len0; 1903 uint16_t bge_idx; 1904 uint16_t bge_flags; 1905 uint16_t bge_type; 1906 uint16_t bge_tcp_udp_csum; 1907 uint16_t bge_ip_csum; 1908 uint16_t bge_vlan_tag; 1909 uint16_t bge_error_flag; 1910 #else 1911 uint16_t bge_idx; 1912 uint16_t bge_len0; 1913 uint16_t bge_type; 1914 uint16_t bge_flags; 1915 uint16_t bge_ip_csum; 1916 uint16_t bge_tcp_udp_csum; 1917 uint16_t bge_error_flag; 1918 uint16_t bge_vlan_tag; 1919 #endif 1920 uint32_t bge_rsvd0; 1921 uint32_t bge_opaque; 1922 }; 1923 1924 #define BGE_RXBDFLAG_END 0x0004 1925 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1926 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1927 #define BGE_RXBDFLAG_ERROR 0x0400 1928 #define BGE_RXBDFLAG_MINI_RING 0x0800 1929 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1930 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1931 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1932 1933 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1934 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1935 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1936 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1937 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1938 #define BGE_RXERRFLAG_RUNT 0x0020 1939 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1940 #define BGE_RXERRFLAG_GIANT 0x0080 1941 1942 struct bge_sts_idx { 1943 #if BYTE_ORDER == LITTLE_ENDIAN 1944 uint16_t bge_rx_prod_idx; 1945 uint16_t bge_tx_cons_idx; 1946 #else 1947 uint16_t bge_tx_cons_idx; 1948 uint16_t bge_rx_prod_idx; 1949 #endif 1950 }; 1951 1952 struct bge_status_block { 1953 uint32_t bge_status; 1954 uint32_t bge_rsvd0; 1955 #if BYTE_ORDER == LITTLE_ENDIAN 1956 uint16_t bge_rx_jumbo_cons_idx; 1957 uint16_t bge_rx_std_cons_idx; 1958 uint16_t bge_rx_mini_cons_idx; 1959 uint16_t bge_rsvd1; 1960 #else 1961 uint16_t bge_rx_std_cons_idx; 1962 uint16_t bge_rx_jumbo_cons_idx; 1963 uint16_t bge_rsvd1; 1964 uint16_t bge_rx_mini_cons_idx; 1965 #endif 1966 struct bge_sts_idx bge_idx[16]; 1967 }; 1968 1969 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1970 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1971 1972 #define BGE_STATFLAG_UPDATED 0x00000001 1973 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1974 #define BGE_STATFLAG_ERROR 0x00000004 1975 1976 1977 /* 1978 * Broadcom Vendor ID 1979 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1980 * even though they're now manufactured by Broadcom) 1981 */ 1982 #define BCOM_VENDORID 0x14E4 1983 #define BCOM_DEVICEID_BCM5700 0x1644 1984 #define BCOM_DEVICEID_BCM5701 0x1645 1985 #define BCOM_DEVICEID_BCM5702 0x1646 1986 #define BCOM_DEVICEID_BCM5702X 0x16A6 1987 #define BCOM_DEVICEID_BCM5702_ALT 0x16C6 1988 #define BCOM_DEVICEID_BCM5703 0x1647 1989 #define BCOM_DEVICEID_BCM5703X 0x16A7 1990 #define BCOM_DEVICEID_BCM5703_ALT 0x16C7 1991 #define BCOM_DEVICEID_BCM5704C 0x1648 1992 #define BCOM_DEVICEID_BCM5704S 0x16A8 1993 #define BCOM_DEVICEID_BCM5704S_ALT 0x1649 1994 #define BCOM_DEVICEID_BCM5705 0x1653 1995 #define BCOM_DEVICEID_BCM5705K 0x1654 1996 #define BCOM_DEVICEID_BCM5705F 0x166E 1997 #define BCOM_DEVICEID_BCM5705M 0x165D 1998 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1999 #define BCOM_DEVICEID_BCM5714C 0x1668 2000 #define BCOM_DEVICEID_BCM5714S 0x1669 2001 #define BCOM_DEVICEID_BCM5715 0x1678 2002 #define BCOM_DEVICEID_BCM5715S 0x1679 2003 #define BCOM_DEVICEID_BCM5720 0x1658 2004 #define BCOM_DEVICEID_BCM5721 0x1659 2005 #define BCOM_DEVICEID_BCM5750 0x1676 2006 #define BCOM_DEVICEID_BCM5750M 0x167C 2007 #define BCOM_DEVICEID_BCM5751 0x1677 2008 #define BCOM_DEVICEID_BCM5751F 0x167E 2009 #define BCOM_DEVICEID_BCM5751M 0x167D 2010 #define BCOM_DEVICEID_BCM5752 0x1600 2011 #define BCOM_DEVICEID_BCM5752M 0x1601 2012 #define BCOM_DEVICEID_BCM5753 0x16F7 2013 #define BCOM_DEVICEID_BCM5753F 0x16FE 2014 #define BCOM_DEVICEID_BCM5753M 0x16FD 2015 #define BCOM_DEVICEID_BCM5754 0x167A 2016 #define BCOM_DEVICEID_BCM5754M 0x1672 2017 #define BCOM_DEVICEID_BCM5755 0x167B 2018 #define BCOM_DEVICEID_BCM5755M 0x1673 2019 #define BCOM_DEVICEID_BCM5780 0x166A 2020 #define BCOM_DEVICEID_BCM5780S 0x166B 2021 #define BCOM_DEVICEID_BCM5781 0x16DD 2022 #define BCOM_DEVICEID_BCM5782 0x1696 2023 #define BCOM_DEVICEID_BCM5786 0x169A 2024 #define BCOM_DEVICEID_BCM5787 0x169B 2025 #define BCOM_DEVICEID_BCM5787M 0x1693 2026 #define BCOM_DEVICEID_BCM5788 0x169C 2027 #define BCOM_DEVICEID_BCM5789 0x169D 2028 #define BCOM_DEVICEID_BCM5901 0x170D 2029 #define BCOM_DEVICEID_BCM5901A2 0x170E 2030 #define BCOM_DEVICEID_BCM5903M 0x16FF 2031 2032 /* 2033 * Alteon AceNIC PCI vendor/device ID. 2034 */ 2035 #define ALTEON_VENDORID 0x12AE 2036 #define ALTEON_DEVICEID_ACENIC 0x0001 2037 #define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2038 #define ALTEON_DEVICEID_BCM5700 0x0003 2039 #define ALTEON_DEVICEID_BCM5701 0x0004 2040 2041 /* 2042 * 3Com 3c996 PCI vendor/device ID. 2043 */ 2044 #define TC_VENDORID 0x10B7 2045 #define TC_DEVICEID_3C996 0x0003 2046 2047 /* 2048 * SysKonnect PCI vendor ID 2049 */ 2050 #define SK_VENDORID 0x1148 2051 #define SK_DEVICEID_ALTIMA 0x4400 2052 #define SK_SUBSYSID_9D21 0x4421 2053 #define SK_SUBSYSID_9D41 0x4441 2054 2055 /* 2056 * Altima PCI vendor/device ID. 2057 */ 2058 #define ALTIMA_VENDORID 0x173b 2059 #define ALTIMA_DEVICE_AC1000 0x03e8 2060 #define ALTIMA_DEVICE_AC1002 0x03e9 2061 #define ALTIMA_DEVICE_AC9100 0x03ea 2062 2063 /* 2064 * Dell PCI vendor ID 2065 */ 2066 2067 #define DELL_VENDORID 0x1028 2068 2069 /* 2070 * Apple PCI vendor ID. 2071 */ 2072 #define APPLE_VENDORID 0x106b 2073 #define APPLE_DEVICE_BCM5701 0x1645 2074 2075 /* 2076 * Offset of MAC address inside EEPROM. 2077 */ 2078 #define BGE_EE_MAC_OFFSET 0x7C 2079 #define BGE_EE_HWCFG_OFFSET 0xC8 2080 2081 #define BGE_HWCFG_VOLTAGE 0x00000003 2082 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2083 #define BGE_HWCFG_MEDIA 0x00000030 2084 #define BGE_HWCFG_ASF 0x00000080 2085 2086 #define BGE_VOLTAGE_1POINT3 0x00000000 2087 #define BGE_VOLTAGE_1POINT8 0x00000001 2088 2089 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2090 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2091 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2092 2093 #define BGE_MEDIA_UNSPEC 0x00000000 2094 #define BGE_MEDIA_COPPER 0x00000010 2095 #define BGE_MEDIA_FIBER 0x00000020 2096 2097 #define BGE_PCI_READ_CMD 0x06000000 2098 #define BGE_PCI_WRITE_CMD 0x70000000 2099 2100 #define BGE_TICKS_PER_SEC 1000000 2101 2102 /* 2103 * Ring size constants. 2104 */ 2105 #define BGE_EVENT_RING_CNT 256 2106 #define BGE_CMD_RING_CNT 64 2107 #define BGE_STD_RX_RING_CNT 512 2108 #define BGE_JUMBO_RX_RING_CNT 256 2109 #define BGE_MINI_RX_RING_CNT 1024 2110 #define BGE_RETURN_RING_CNT 1024 2111 2112 /* 5705 has smaller return ring size */ 2113 2114 #define BGE_RETURN_RING_CNT_5705 512 2115 2116 /* 2117 * Possible TX ring sizes. 2118 */ 2119 #define BGE_TX_RING_CNT_128 128 2120 #define BGE_TX_RING_BASE_128 0x3800 2121 2122 #define BGE_TX_RING_CNT_256 256 2123 #define BGE_TX_RING_BASE_256 0x3000 2124 2125 #define BGE_TX_RING_CNT_512 512 2126 #define BGE_TX_RING_BASE_512 0x2000 2127 2128 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2129 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2130 2131 /* 2132 * Tigon III statistics counters. 2133 */ 2134 /* Statistics maintained MAC Receive block. */ 2135 struct bge_rx_mac_stats { 2136 bge_hostaddr ifHCInOctets; 2137 bge_hostaddr Reserved1; 2138 bge_hostaddr etherStatsFragments; 2139 bge_hostaddr ifHCInUcastPkts; 2140 bge_hostaddr ifHCInMulticastPkts; 2141 bge_hostaddr ifHCInBroadcastPkts; 2142 bge_hostaddr dot3StatsFCSErrors; 2143 bge_hostaddr dot3StatsAlignmentErrors; 2144 bge_hostaddr xonPauseFramesReceived; 2145 bge_hostaddr xoffPauseFramesReceived; 2146 bge_hostaddr macControlFramesReceived; 2147 bge_hostaddr xoffStateEntered; 2148 bge_hostaddr dot3StatsFramesTooLong; 2149 bge_hostaddr etherStatsJabbers; 2150 bge_hostaddr etherStatsUndersizePkts; 2151 bge_hostaddr inRangeLengthError; 2152 bge_hostaddr outRangeLengthError; 2153 bge_hostaddr etherStatsPkts64Octets; 2154 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2155 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2156 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2157 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2158 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2159 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2160 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2161 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2162 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2163 }; 2164 2165 2166 /* Statistics maintained MAC Transmit block. */ 2167 struct bge_tx_mac_stats { 2168 bge_hostaddr ifHCOutOctets; 2169 bge_hostaddr Reserved2; 2170 bge_hostaddr etherStatsCollisions; 2171 bge_hostaddr outXonSent; 2172 bge_hostaddr outXoffSent; 2173 bge_hostaddr flowControlDone; 2174 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2175 bge_hostaddr dot3StatsSingleCollisionFrames; 2176 bge_hostaddr dot3StatsMultipleCollisionFrames; 2177 bge_hostaddr dot3StatsDeferredTransmissions; 2178 bge_hostaddr Reserved3; 2179 bge_hostaddr dot3StatsExcessiveCollisions; 2180 bge_hostaddr dot3StatsLateCollisions; 2181 bge_hostaddr dot3Collided2Times; 2182 bge_hostaddr dot3Collided3Times; 2183 bge_hostaddr dot3Collided4Times; 2184 bge_hostaddr dot3Collided5Times; 2185 bge_hostaddr dot3Collided6Times; 2186 bge_hostaddr dot3Collided7Times; 2187 bge_hostaddr dot3Collided8Times; 2188 bge_hostaddr dot3Collided9Times; 2189 bge_hostaddr dot3Collided10Times; 2190 bge_hostaddr dot3Collided11Times; 2191 bge_hostaddr dot3Collided12Times; 2192 bge_hostaddr dot3Collided13Times; 2193 bge_hostaddr dot3Collided14Times; 2194 bge_hostaddr dot3Collided15Times; 2195 bge_hostaddr ifHCOutUcastPkts; 2196 bge_hostaddr ifHCOutMulticastPkts; 2197 bge_hostaddr ifHCOutBroadcastPkts; 2198 bge_hostaddr dot3StatsCarrierSenseErrors; 2199 bge_hostaddr ifOutDiscards; 2200 bge_hostaddr ifOutErrors; 2201 }; 2202 2203 /* Stats counters access through registers */ 2204 struct bge_mac_stats_regs { 2205 uint32_t ifHCOutOctets; 2206 uint32_t Reserved0; 2207 uint32_t etherStatsCollisions; 2208 uint32_t outXonSent; 2209 uint32_t outXoffSent; 2210 uint32_t Reserved1; 2211 uint32_t dot3StatsInternalMacTransmitErrors; 2212 uint32_t dot3StatsSingleCollisionFrames; 2213 uint32_t dot3StatsMultipleCollisionFrames; 2214 uint32_t dot3StatsDeferredTransmissions; 2215 uint32_t Reserved2; 2216 uint32_t dot3StatsExcessiveCollisions; 2217 uint32_t dot3StatsLateCollisions; 2218 uint32_t Reserved3[14]; 2219 uint32_t ifHCOutUcastPkts; 2220 uint32_t ifHCOutMulticastPkts; 2221 uint32_t ifHCOutBroadcastPkts; 2222 uint32_t Reserved4[2]; 2223 uint32_t ifHCInOctets; 2224 uint32_t Reserved5; 2225 uint32_t etherStatsFragments; 2226 uint32_t ifHCInUcastPkts; 2227 uint32_t ifHCInMulticastPkts; 2228 uint32_t ifHCInBroadcastPkts; 2229 uint32_t dot3StatsFCSErrors; 2230 uint32_t dot3StatsAlignmentErrors; 2231 uint32_t xonPauseFramesReceived; 2232 uint32_t xoffPauseFramesReceived; 2233 uint32_t macControlFramesReceived; 2234 uint32_t xoffStateEntered; 2235 uint32_t dot3StatsFramesTooLong; 2236 uint32_t etherStatsJabbers; 2237 uint32_t etherStatsUndersizePkts; 2238 }; 2239 2240 struct bge_stats { 2241 uint8_t Reserved0[256]; 2242 2243 /* Statistics maintained by Receive MAC. */ 2244 struct bge_rx_mac_stats rxstats; 2245 2246 bge_hostaddr Unused1[37]; 2247 2248 /* Statistics maintained by Transmit MAC. */ 2249 struct bge_tx_mac_stats txstats; 2250 2251 bge_hostaddr Unused2[31]; 2252 2253 /* Statistics maintained by Receive List Placement. */ 2254 bge_hostaddr COSIfHCInPkts[16]; 2255 bge_hostaddr COSFramesDroppedDueToFilters; 2256 bge_hostaddr nicDmaWriteQueueFull; 2257 bge_hostaddr nicDmaWriteHighPriQueueFull; 2258 bge_hostaddr nicNoMoreRxBDs; 2259 bge_hostaddr ifInDiscards; 2260 bge_hostaddr ifInErrors; 2261 bge_hostaddr nicRecvThresholdHit; 2262 2263 bge_hostaddr Unused3[9]; 2264 2265 /* Statistics maintained by Send Data Initiator. */ 2266 bge_hostaddr COSIfHCOutPkts[16]; 2267 bge_hostaddr nicDmaReadQueueFull; 2268 bge_hostaddr nicDmaReadHighPriQueueFull; 2269 bge_hostaddr nicSendDataCompQueueFull; 2270 2271 /* Statistics maintained by Host Coalescing. */ 2272 bge_hostaddr nicRingSetSendProdIndex; 2273 bge_hostaddr nicRingStatusUpdate; 2274 bge_hostaddr nicInterrupts; 2275 bge_hostaddr nicAvoidedInterrupts; 2276 bge_hostaddr nicSendThresholdHit; 2277 2278 uint8_t Reserved4[320]; 2279 }; 2280 2281 /* 2282 * Tigon general information block. This resides in host memory 2283 * and contains the status counters, ring control blocks and 2284 * producer pointers. 2285 */ 2286 2287 struct bge_gib { 2288 struct bge_stats bge_stats; 2289 struct bge_rcb bge_tx_rcb[16]; 2290 struct bge_rcb bge_std_rx_rcb; 2291 struct bge_rcb bge_jumbo_rx_rcb; 2292 struct bge_rcb bge_mini_rx_rcb; 2293 struct bge_rcb bge_return_rcb; 2294 }; 2295 2296 #define BGE_FRAMELEN 1518 2297 #define BGE_MAX_FRAMELEN 1536 2298 #define BGE_JUMBO_FRAMELEN 9018 2299 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2300 #define BGE_MIN_FRAMELEN 60 2301 2302 /* 2303 * Other utility macros. 2304 */ 2305 #define BGE_INC(x, y) (x) = (x + 1) % y 2306 2307 /* 2308 * Register access macros. The Tigon always uses memory mapped register 2309 * accesses and all registers must be accessed with 32 bit operations. 2310 */ 2311 2312 #define CSR_WRITE_4(sc, reg, val) \ 2313 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2314 2315 #define CSR_READ_4(sc, reg) \ 2316 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2317 2318 #define BGE_SETBIT(sc, reg, x) \ 2319 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2320 #define BGE_CLRBIT(sc, reg, x) \ 2321 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2322 2323 #define PCI_SETBIT(dev, reg, x, s) \ 2324 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2325 #define PCI_CLRBIT(dev, reg, x, s) \ 2326 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2327 2328 /* 2329 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2330 * values are tuneable. They control the actual amount of buffers 2331 * allocated for the standard, mini and jumbo receive rings. 2332 */ 2333 2334 #define BGE_SSLOTS 256 2335 #define BGE_MSLOTS 256 2336 #define BGE_JSLOTS 384 2337 2338 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2339 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2340 (BGE_JRAWLEN % sizeof(uint64_t)))) 2341 #define BGE_JPAGESZ PAGE_SIZE 2342 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2343 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2344 2345 #define BGE_NSEG_JUMBO 4 2346 #define BGE_NSEG_NEW 32 2347 2348 /* 2349 * Ring structures. Most of these reside in host memory and we tell 2350 * the NIC where they are via the ring control blocks. The exceptions 2351 * are the tx and command rings, which live in NIC memory and which 2352 * we access via the shared memory window. 2353 */ 2354 2355 struct bge_ring_data { 2356 struct bge_rx_bd *bge_rx_std_ring; 2357 bus_addr_t bge_rx_std_ring_paddr; 2358 struct bge_extrx_bd *bge_rx_jumbo_ring; 2359 bus_addr_t bge_rx_jumbo_ring_paddr; 2360 struct bge_rx_bd *bge_rx_return_ring; 2361 bus_addr_t bge_rx_return_ring_paddr; 2362 struct bge_tx_bd *bge_tx_ring; 2363 bus_addr_t bge_tx_ring_paddr; 2364 struct bge_status_block *bge_status_block; 2365 bus_addr_t bge_status_block_paddr; 2366 struct bge_stats *bge_stats; 2367 bus_addr_t bge_stats_paddr; 2368 struct bge_gib bge_info; 2369 }; 2370 2371 #define BGE_STD_RX_RING_SZ \ 2372 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2373 #define BGE_JUMBO_RX_RING_SZ \ 2374 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2375 #define BGE_TX_RING_SZ \ 2376 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2377 #define BGE_RX_RTN_RING_SZ(x) \ 2378 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2379 2380 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2381 2382 #define BGE_STATS_SZ sizeof (struct bge_stats) 2383 2384 /* 2385 * Mbuf pointers. We need these to keep track of the virtual addresses 2386 * of our mbuf chains since we can only convert from physical to virtual, 2387 * not the other way around. 2388 */ 2389 struct bge_chain_data { 2390 bus_dma_tag_t bge_parent_tag; 2391 bus_dma_tag_t bge_rx_std_ring_tag; 2392 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2393 bus_dma_tag_t bge_rx_return_ring_tag; 2394 bus_dma_tag_t bge_tx_ring_tag; 2395 bus_dma_tag_t bge_status_tag; 2396 bus_dma_tag_t bge_stats_tag; 2397 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2398 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2399 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2400 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2401 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2402 bus_dmamap_t bge_rx_std_ring_map; 2403 bus_dmamap_t bge_rx_jumbo_ring_map; 2404 bus_dmamap_t bge_tx_ring_map; 2405 bus_dmamap_t bge_rx_return_ring_map; 2406 bus_dmamap_t bge_status_map; 2407 bus_dmamap_t bge_stats_map; 2408 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2409 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2410 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2411 }; 2412 2413 struct bge_dmamap_arg { 2414 struct bge_softc *sc; 2415 bus_addr_t bge_busaddr; 2416 uint16_t bge_flags; 2417 int bge_idx; 2418 int bge_maxsegs; 2419 struct bge_tx_bd *bge_ring; 2420 }; 2421 2422 #define BGE_HWREV_TIGON 0x01 2423 #define BGE_HWREV_TIGON_II 0x02 2424 #define BGE_TIMEOUT 100000 2425 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2426 2427 struct bge_bcom_hack { 2428 int reg; 2429 int val; 2430 }; 2431 2432 #define ASF_ENABLE 1 2433 #define ASF_NEW_HANDSHAKE 2 2434 #define ASF_STACKUP 4 2435 2436 struct bge_softc { 2437 struct ifnet *bge_ifp; /* interface info */ 2438 device_t bge_dev; 2439 struct mtx bge_mtx; 2440 device_t bge_miibus; 2441 bus_space_handle_t bge_bhandle; 2442 bus_space_tag_t bge_btag; 2443 void *bge_intrhand; 2444 struct resource *bge_irq; 2445 struct resource *bge_res; 2446 struct ifmedia bge_ifmedia; /* TBI media info */ 2447 uint32_t bge_flags; 2448 #define BGE_FLAG_EXTRAM 0x00000001 /* External SSRAM (unused) */ 2449 #define BGE_FLAG_TBI 0x00000002 2450 #define BGE_FLAG_RX_ALIGNBUG 0x00000004 2451 #define BGE_FLAG_NO3LED 0x00000008 2452 #define BGE_FLAG_PCIX 0x00000010 2453 #define BGE_FLAG_PCIE 0x00000020 2454 #define BGE_FLAG_JUMBO 0x00000040 2455 #define BGE_FLAG_5700_FAMILY 0x00000100 2456 #define BGE_FLAG_5705_PLUS 0x00000200 2457 #define BGE_FLAG_5714_FAMILY 0x00000400 2458 #define BGE_FLAG_575X_PLUS 0x00000800 2459 #define BGE_FLAG_MSI 0x00001000 2460 uint32_t bge_chipid; 2461 uint8_t bge_asicrev; 2462 uint8_t bge_chiprev; 2463 uint8_t bge_asf_mode; 2464 uint8_t bge_asf_count; 2465 struct bge_ring_data bge_ldata; /* rings */ 2466 struct bge_chain_data bge_cdata; /* mbufs */ 2467 uint16_t bge_tx_saved_considx; 2468 uint16_t bge_rx_saved_considx; 2469 uint16_t bge_ev_saved_considx; 2470 uint16_t bge_return_ring_cnt; 2471 uint16_t bge_std; /* current std ring head */ 2472 uint16_t bge_jumbo; /* current jumo ring head */ 2473 uint32_t bge_stat_ticks; 2474 uint32_t bge_rx_coal_ticks; 2475 uint32_t bge_tx_coal_ticks; 2476 uint32_t bge_tx_prodidx; 2477 uint32_t bge_rx_max_coal_bds; 2478 uint32_t bge_tx_max_coal_bds; 2479 uint32_t bge_tx_buf_ratio; 2480 int bge_if_flags; 2481 int bge_txcnt; 2482 int bge_link; /* link state */ 2483 int bge_link_evt; /* pending link event */ 2484 int bge_timer; 2485 struct callout bge_stat_ch; 2486 uint32_t bge_rx_discards; 2487 uint32_t bge_tx_discards; 2488 uint32_t bge_tx_collisions; 2489 #ifdef DEVICE_POLLING 2490 int rxcycles; 2491 #endif /* DEVICE_POLLING */ 2492 }; 2493 2494 #define BGE_LOCK_INIT(_sc, _name) \ 2495 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2496 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2497 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2498 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2499 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2500