1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 2001 Wind River Systems 5 * Copyright (c) 1997, 1998, 1999, 2001 6 * Bill Paul <wpaul@windriver.com>. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Bill Paul. 19 * 4. Neither the name of the author nor the names of any co-contributors 20 * may be used to endorse or promote products derived from this software 21 * without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 33 * THE POSSIBILITY OF SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37 38 /* 39 * BCM570x memory map. The internal memory layout varies somewhat 40 * depending on whether or not we have external SSRAM attached. 41 * The BCM5700 can have up to 16MB of external memory. The BCM5701 42 * is apparently not designed to use external SSRAM. The mappings 43 * up to the first 4 send rings are the same for both internal and 44 * external memory configurations. Note that mini RX ring space is 45 * only available with external SSRAM configurations, which means 46 * the mini RX ring is not supported on the BCM5701. 47 * 48 * The NIC's memory can be accessed by the host in one of 3 ways: 49 * 50 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 51 * registers in PCI config space can be used to read any 32-bit 52 * address within the NIC's memory. 53 * 54 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 55 * space can be used in conjunction with the memory window in the 56 * device register space at offset 0x8000 to read any 32K chunk 57 * of NIC memory. 58 * 59 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 60 * set, the device I/O mapping consumes 32MB of host address space, 61 * allowing all of the registers and internal NIC memory to be 62 * accessed directly. NIC memory addresses are offset by 0x01000000. 63 * Flat mode consumes so much host address space that it is not 64 * recommended. 65 */ 66 #define BGE_PAGE_ZERO 0x00000000 67 #define BGE_PAGE_ZERO_END 0x000000FF 68 #define BGE_SEND_RING_RCB 0x00000100 69 #define BGE_SEND_RING_RCB_END 0x000001FF 70 #define BGE_RX_RETURN_RING_RCB 0x00000200 71 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 72 #define BGE_STATS_BLOCK 0x00000300 73 #define BGE_STATS_BLOCK_END 0x00000AFF 74 #define BGE_STATUS_BLOCK 0x00000B00 75 #define BGE_STATUS_BLOCK_END 0x00000B4F 76 #define BGE_SRAM_FW_MB 0x00000B50 77 #define BGE_SRAM_DATA_SIG 0x00000B54 78 #define BGE_SRAM_DATA_CFG 0x00000B58 79 #define BGE_SRAM_FW_CMD_MB 0x00000B78 80 #define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 81 #define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 82 #define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 83 #define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 84 #define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 85 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 86 #define BGE_UNMAPPED 0x00001000 87 #define BGE_UNMAPPED_END 0x00001FFF 88 #define BGE_DMA_DESCRIPTORS 0x00002000 89 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 90 #define BGE_SEND_RING_5717 0x00004000 91 #define BGE_SEND_RING_1_TO_4 0x00004000 92 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 93 94 /* Firmware interface */ 95 #define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */ 96 97 #define BGE_FW_CMD_DRV_ALIVE 0x00000001 98 #define BGE_FW_CMD_PAUSE 0x00000002 99 #define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 100 #define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 101 #define BGE_FW_CMD_LINK_UPDATE 0x0000000C 102 #define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 103 #define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 104 105 #define BGE_FW_HB_TIMEOUT_SEC 3 106 107 #define BGE_FW_DRV_STATE_START 0x00000001 108 #define BGE_FW_DRV_STATE_START_DONE 0x80000001 109 #define BGE_FW_DRV_STATE_UNLOAD 0x00000002 110 #define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 111 #define BGE_FW_DRV_STATE_WOL 0x00000003 112 #define BGE_FW_DRV_STATE_SUSPEND 0x00000004 113 114 /* Mappings for internal memory configuration */ 115 #define BGE_STD_RX_RINGS 0x00006000 116 #define BGE_STD_RX_RINGS_END 0x00006FFF 117 #define BGE_JUMBO_RX_RINGS 0x00007000 118 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 119 #define BGE_BUFFPOOL_1 0x00008000 120 #define BGE_BUFFPOOL_1_END 0x0000FFFF 121 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 122 #define BGE_BUFFPOOL_2_END 0x00017FFF 123 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 124 #define BGE_BUFFPOOL_3_END 0x0001FFFF 125 #define BGE_STD_RX_RINGS_5717 0x00040000 126 #define BGE_JUMBO_RX_RINGS_5717 0x00044400 127 128 /* Mappings for external SSRAM configurations */ 129 #define BGE_SEND_RING_5_TO_6 0x00006000 130 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 131 #define BGE_SEND_RING_7_TO_8 0x00007000 132 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 133 #define BGE_SEND_RING_9_TO_16 0x00008000 134 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 135 #define BGE_EXT_STD_RX_RINGS 0x0000C000 136 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 137 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 138 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 139 #define BGE_MINI_RX_RINGS 0x0000E000 140 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 141 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 142 #define BGE_AVAIL_REGION1_END 0x00017FFF 143 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 144 #define BGE_AVAIL_REGION2_END 0x0001FFFF 145 #define BGE_EXT_SSRAM 0x00020000 146 #define BGE_EXT_SSRAM_END 0x000FFFFF 147 148 149 /* 150 * BCM570x register offsets. These are memory mapped registers 151 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 152 * Each register must be accessed using 32 bit operations. 153 * 154 * All registers are accessed through a 32K shared memory block. 155 * The first group of registers are actually copies of the PCI 156 * configuration space registers. 157 */ 158 159 /* 160 * PCI registers defined in the PCI 2.2 spec. 161 */ 162 #define BGE_PCI_VID 0x00 163 #define BGE_PCI_DID 0x02 164 #define BGE_PCI_CMD 0x04 165 #define BGE_PCI_STS 0x06 166 #define BGE_PCI_REV 0x08 167 #define BGE_PCI_CLASS 0x09 168 #define BGE_PCI_CACHESZ 0x0C 169 #define BGE_PCI_LATTIMER 0x0D 170 #define BGE_PCI_HDRTYPE 0x0E 171 #define BGE_PCI_BIST 0x0F 172 #define BGE_PCI_BAR0 0x10 173 #define BGE_PCI_BAR1 0x14 174 #define BGE_PCI_SUBSYS 0x2C 175 #define BGE_PCI_SUBVID 0x2E 176 #define BGE_PCI_ROMBASE 0x30 177 #define BGE_PCI_CAPPTR 0x34 178 #define BGE_PCI_INTLINE 0x3C 179 #define BGE_PCI_INTPIN 0x3D 180 #define BGE_PCI_MINGNT 0x3E 181 #define BGE_PCI_MAXLAT 0x3F 182 #define BGE_PCI_PCIXCAP 0x40 183 #define BGE_PCI_NEXTPTR_PM 0x41 184 #define BGE_PCI_PCIX_CMD 0x42 185 #define BGE_PCI_PCIX_STS 0x44 186 #define BGE_PCI_PWRMGMT_CAPID 0x48 187 #define BGE_PCI_NEXTPTR_VPD 0x49 188 #define BGE_PCI_PWRMGMT_CAPS 0x4A 189 #define BGE_PCI_PWRMGMT_CMD 0x4C 190 #define BGE_PCI_PWRMGMT_STS 0x4D 191 #define BGE_PCI_PWRMGMT_DATA 0x4F 192 #define BGE_PCI_VPD_CAPID 0x50 193 #define BGE_PCI_NEXTPTR_MSI 0x51 194 #define BGE_PCI_VPD_ADDR 0x52 195 #define BGE_PCI_VPD_DATA 0x54 196 #define BGE_PCI_MSI_CAPID 0x58 197 #define BGE_PCI_NEXTPTR_NONE 0x59 198 #define BGE_PCI_MSI_CTL 0x5A 199 #define BGE_PCI_MSI_ADDR_HI 0x5C 200 #define BGE_PCI_MSI_ADDR_LO 0x60 201 #define BGE_PCI_MSI_DATA 0x64 202 203 /* 204 * PCI Express definitions 205 * According to 206 * PCI Express base specification, REV. 1.0a 207 */ 208 209 /* PCI Express device control, 16bits */ 210 #define BGE_PCIE_DEVCTL 0x08 211 #define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 212 #define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 213 #define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 214 #define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 215 #define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 216 #define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 217 #define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 218 219 /* PCI MSI. ??? */ 220 #define BGE_PCIE_CAPID_REG 0xD0 221 #define BGE_PCIE_CAPID 0x10 222 223 /* 224 * PCI registers specific to the BCM570x family. 225 */ 226 #define BGE_PCI_MISC_CTL 0x68 227 #define BGE_PCI_DMA_RW_CTL 0x6C 228 #define BGE_PCI_PCISTATE 0x70 229 #define BGE_PCI_CLKCTL 0x74 230 #define BGE_PCI_REG_BASEADDR 0x78 231 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 232 #define BGE_PCI_REG_DATA 0x80 233 #define BGE_PCI_MEMWIN_DATA 0x84 234 #define BGE_PCI_MODECTL 0x88 235 #define BGE_PCI_MISC_CFG 0x8C 236 #define BGE_PCI_MISC_LOCALCTL 0x90 237 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 238 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 239 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 240 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 241 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 242 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 243 #define BGE_PCI_ISR_MBX_HI 0xB0 244 #define BGE_PCI_ISR_MBX_LO 0xB4 245 #define BGE_PCI_PRODID_ASICREV 0xBC 246 #define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 247 #define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 248 249 /* PCI Misc. Host control register */ 250 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 251 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 252 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 253 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 254 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 255 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 256 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 257 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 258 #define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 259 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 260 #define BGE_PCIMISCCTL_ASICREV_SHIFT 16 261 262 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 263 264 #define BGE_INIT \ 265 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 266 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 267 268 #define BGE_CHIPID_TIGON_I 0x4000 269 #define BGE_CHIPID_TIGON_II 0x6000 270 #define BGE_CHIPID_BCM5700_A0 0x7000 271 #define BGE_CHIPID_BCM5700_A1 0x7001 272 #define BGE_CHIPID_BCM5700_B0 0x7100 273 #define BGE_CHIPID_BCM5700_B1 0x7101 274 #define BGE_CHIPID_BCM5700_B2 0x7102 275 #define BGE_CHIPID_BCM5700_B3 0x7103 276 #define BGE_CHIPID_BCM5700_ALTIMA 0x7104 277 #define BGE_CHIPID_BCM5700_C0 0x7200 278 #define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */ 279 #define BGE_CHIPID_BCM5701_B0 0x0100 280 #define BGE_CHIPID_BCM5701_B2 0x0102 281 #define BGE_CHIPID_BCM5701_B5 0x0105 282 #define BGE_CHIPID_BCM5703_A0 0x1000 283 #define BGE_CHIPID_BCM5703_A1 0x1001 284 #define BGE_CHIPID_BCM5703_A2 0x1002 285 #define BGE_CHIPID_BCM5703_A3 0x1003 286 #define BGE_CHIPID_BCM5703_B0 0x1100 287 #define BGE_CHIPID_BCM5704_A0 0x2000 288 #define BGE_CHIPID_BCM5704_A1 0x2001 289 #define BGE_CHIPID_BCM5704_A2 0x2002 290 #define BGE_CHIPID_BCM5704_A3 0x2003 291 #define BGE_CHIPID_BCM5704_B0 0x2100 292 #define BGE_CHIPID_BCM5705_A0 0x3000 293 #define BGE_CHIPID_BCM5705_A1 0x3001 294 #define BGE_CHIPID_BCM5705_A2 0x3002 295 #define BGE_CHIPID_BCM5705_A3 0x3003 296 #define BGE_CHIPID_BCM5750_A0 0x4000 297 #define BGE_CHIPID_BCM5750_A1 0x4001 298 #define BGE_CHIPID_BCM5750_A3 0x4000 299 #define BGE_CHIPID_BCM5750_B0 0x4100 300 #define BGE_CHIPID_BCM5750_B1 0x4101 301 #define BGE_CHIPID_BCM5750_C0 0x4200 302 #define BGE_CHIPID_BCM5750_C1 0x4201 303 #define BGE_CHIPID_BCM5750_C2 0x4202 304 #define BGE_CHIPID_BCM5714_A0 0x5000 305 #define BGE_CHIPID_BCM5752_A0 0x6000 306 #define BGE_CHIPID_BCM5752_A1 0x6001 307 #define BGE_CHIPID_BCM5752_A2 0x6002 308 #define BGE_CHIPID_BCM5714_B0 0x8000 309 #define BGE_CHIPID_BCM5714_B3 0x8003 310 #define BGE_CHIPID_BCM5715_A0 0x9000 311 #define BGE_CHIPID_BCM5715_A1 0x9001 312 #define BGE_CHIPID_BCM5715_A3 0x9003 313 #define BGE_CHIPID_BCM5755_A0 0xa000 314 #define BGE_CHIPID_BCM5755_A1 0xa001 315 #define BGE_CHIPID_BCM5755_A2 0xa002 316 #define BGE_CHIPID_BCM5722_A0 0xa200 317 #define BGE_CHIPID_BCM5754_A0 0xb000 318 #define BGE_CHIPID_BCM5754_A1 0xb001 319 #define BGE_CHIPID_BCM5754_A2 0xb002 320 #define BGE_CHIPID_BCM5761_A0 0x5761000 321 #define BGE_CHIPID_BCM5761_A1 0x5761100 322 #define BGE_CHIPID_BCM5784_A0 0x5784000 323 #define BGE_CHIPID_BCM5784_A1 0x5784100 324 #define BGE_CHIPID_BCM5787_A0 0xb000 325 #define BGE_CHIPID_BCM5787_A1 0xb001 326 #define BGE_CHIPID_BCM5787_A2 0xb002 327 #define BGE_CHIPID_BCM5906_A0 0xc000 328 #define BGE_CHIPID_BCM5906_A1 0xc001 329 #define BGE_CHIPID_BCM5906_A2 0xc002 330 #define BGE_CHIPID_BCM57780_A0 0x57780000 331 #define BGE_CHIPID_BCM57780_A1 0x57780001 332 #define BGE_CHIPID_BCM5717_A0 0x05717000 333 #define BGE_CHIPID_BCM5717_B0 0x05717100 334 #define BGE_CHIPID_BCM5717_C0 0x05717200 335 #define BGE_CHIPID_BCM5719_A0 0x05719000 336 #define BGE_CHIPID_BCM5720_A0 0x05720000 337 #define BGE_CHIPID_BCM5762_A0 0x05762000 338 #define BGE_CHIPID_BCM57765_A0 0x57785000 339 #define BGE_CHIPID_BCM57765_B0 0x57785100 340 341 /* shorthand one */ 342 #define BGE_ASICREV(x) ((x) >> 12) 343 #define BGE_ASICREV_BCM5701 0x00 344 #define BGE_ASICREV_BCM5703 0x01 345 #define BGE_ASICREV_BCM5704 0x02 346 #define BGE_ASICREV_BCM5705 0x03 347 #define BGE_ASICREV_BCM5750 0x04 348 #define BGE_ASICREV_BCM5714_A0 0x05 349 #define BGE_ASICREV_BCM5752 0x06 350 #define BGE_ASICREV_BCM5700 0x07 351 #define BGE_ASICREV_BCM5780 0x08 352 #define BGE_ASICREV_BCM5714 0x09 353 #define BGE_ASICREV_BCM5755 0x0a 354 #define BGE_ASICREV_BCM5754 0x0b 355 #define BGE_ASICREV_BCM5787 0x0b 356 #define BGE_ASICREV_BCM5906 0x0c 357 /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 358 #define BGE_ASICREV_USE_PRODID_REG 0x0f 359 /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 360 #define BGE_ASICREV_BCM5717 0x5717 361 #define BGE_ASICREV_BCM5719 0x5719 362 #define BGE_ASICREV_BCM5720 0x5720 363 #define BGE_ASICREV_BCM5761 0x5761 364 #define BGE_ASICREV_BCM5762 0x5762 365 #define BGE_ASICREV_BCM5784 0x5784 366 #define BGE_ASICREV_BCM5785 0x5785 367 #define BGE_ASICREV_BCM57765 0x57785 368 #define BGE_ASICREV_BCM57766 0x57766 369 #define BGE_ASICREV_BCM57780 0x57780 370 371 /* chip revisions */ 372 #define BGE_CHIPREV(x) ((x) >> 8) 373 #define BGE_CHIPREV_5700_AX 0x70 374 #define BGE_CHIPREV_5700_BX 0x71 375 #define BGE_CHIPREV_5700_CX 0x72 376 #define BGE_CHIPREV_5701_AX 0x00 377 #define BGE_CHIPREV_5703_AX 0x10 378 #define BGE_CHIPREV_5704_AX 0x20 379 #define BGE_CHIPREV_5704_BX 0x21 380 #define BGE_CHIPREV_5750_AX 0x40 381 #define BGE_CHIPREV_5750_BX 0x41 382 /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */ 383 #define BGE_CHIPREV_5717_AX 0x57170 384 #define BGE_CHIPREV_5717_BX 0x57171 385 #define BGE_CHIPREV_5761_AX 0x57611 386 #define BGE_CHIPREV_57765_AX 0x577850 387 #define BGE_CHIPREV_5784_AX 0x57841 388 389 /* PCI DMA Read/Write Control register */ 390 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 391 #define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 392 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 393 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 394 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 395 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 396 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 397 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 398 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 399 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 400 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 401 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 402 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 403 404 #define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 405 #define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 406 #define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 407 #define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 408 409 #define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 410 #define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 411 412 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 413 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 414 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 415 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 416 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 417 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 418 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 419 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 420 421 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 422 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 423 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 424 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 425 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 426 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 427 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 428 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 429 430 /* 431 * PCI state register -- note, this register is read only 432 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 433 * register is set. 434 */ 435 #define BGE_PCISTATE_FORCE_RESET 0x00000001 436 #define BGE_PCISTATE_INTR_STATE 0x00000002 437 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 438 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */ 439 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 440 #define BGE_PCISTATE_ROM_ENABLE 0x00000020 441 #define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 442 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 443 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 444 #define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 445 #define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 446 #define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 447 #define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 448 449 /* 450 * PCI Clock Control register -- note, this register is read only 451 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 452 * register is set. 453 */ 454 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 455 #define BGE_PCICLOCKCTL_M66EN 0x00000080 456 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 457 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 458 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 459 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 460 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 461 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 462 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 463 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 464 465 466 #ifndef PCIM_CMD_MWIEN 467 #define PCIM_CMD_MWIEN 0x0010 468 #endif 469 #ifndef PCIM_CMD_INTxDIS 470 #define PCIM_CMD_INTxDIS 0x0400 471 #endif 472 473 /* BAR0 (MAC) Register Definitions */ 474 475 /* 476 * High priority mailbox registers 477 * Each mailbox is 64-bits wide, though we only use the 478 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 479 * first. The NIC will load the mailbox after the lower 32 bit word 480 * has been updated. 481 */ 482 #define BGE_MBX_IRQ0_HI 0x0200 483 #define BGE_MBX_IRQ0_LO 0x0204 484 #define BGE_MBX_IRQ1_HI 0x0208 485 #define BGE_MBX_IRQ1_LO 0x020C 486 #define BGE_MBX_IRQ2_HI 0x0210 487 #define BGE_MBX_IRQ2_LO 0x0214 488 #define BGE_MBX_IRQ3_HI 0x0218 489 #define BGE_MBX_IRQ3_LO 0x021C 490 #define BGE_MBX_GEN0_HI 0x0220 491 #define BGE_MBX_GEN0_LO 0x0224 492 #define BGE_MBX_GEN1_HI 0x0228 493 #define BGE_MBX_GEN1_LO 0x022C 494 #define BGE_MBX_GEN2_HI 0x0230 495 #define BGE_MBX_GEN2_LO 0x0234 496 #define BGE_MBX_GEN3_HI 0x0228 497 #define BGE_MBX_GEN3_LO 0x022C 498 #define BGE_MBX_GEN4_HI 0x0240 499 #define BGE_MBX_GEN4_LO 0x0244 500 #define BGE_MBX_GEN5_HI 0x0248 501 #define BGE_MBX_GEN5_LO 0x024C 502 #define BGE_MBX_GEN6_HI 0x0250 503 #define BGE_MBX_GEN6_LO 0x0254 504 #define BGE_MBX_GEN7_HI 0x0258 505 #define BGE_MBX_GEN7_LO 0x025C 506 #define BGE_MBX_RELOAD_STATS_HI 0x0260 507 #define BGE_MBX_RELOAD_STATS_LO 0x0264 508 #define BGE_MBX_RX_STD_PROD_HI 0x0268 509 #define BGE_MBX_RX_STD_PROD_LO 0x026C 510 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 511 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 512 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 513 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 514 #define BGE_MBX_RX_CONS0_HI 0x0280 515 #define BGE_MBX_RX_CONS0_LO 0x0284 516 #define BGE_MBX_RX_CONS1_HI 0x0288 517 #define BGE_MBX_RX_CONS1_LO 0x028C 518 #define BGE_MBX_RX_CONS2_HI 0x0290 519 #define BGE_MBX_RX_CONS2_LO 0x0294 520 #define BGE_MBX_RX_CONS3_HI 0x0298 521 #define BGE_MBX_RX_CONS3_LO 0x029C 522 #define BGE_MBX_RX_CONS4_HI 0x02A0 523 #define BGE_MBX_RX_CONS4_LO 0x02A4 524 #define BGE_MBX_RX_CONS5_HI 0x02A8 525 #define BGE_MBX_RX_CONS5_LO 0x02AC 526 #define BGE_MBX_RX_CONS6_HI 0x02B0 527 #define BGE_MBX_RX_CONS6_LO 0x02B4 528 #define BGE_MBX_RX_CONS7_HI 0x02B8 529 #define BGE_MBX_RX_CONS7_LO 0x02BC 530 #define BGE_MBX_RX_CONS8_HI 0x02C0 531 #define BGE_MBX_RX_CONS8_LO 0x02C4 532 #define BGE_MBX_RX_CONS9_HI 0x02C8 533 #define BGE_MBX_RX_CONS9_LO 0x02CC 534 #define BGE_MBX_RX_CONS10_HI 0x02D0 535 #define BGE_MBX_RX_CONS10_LO 0x02D4 536 #define BGE_MBX_RX_CONS11_HI 0x02D8 537 #define BGE_MBX_RX_CONS11_LO 0x02DC 538 #define BGE_MBX_RX_CONS12_HI 0x02E0 539 #define BGE_MBX_RX_CONS12_LO 0x02E4 540 #define BGE_MBX_RX_CONS13_HI 0x02E8 541 #define BGE_MBX_RX_CONS13_LO 0x02EC 542 #define BGE_MBX_RX_CONS14_HI 0x02F0 543 #define BGE_MBX_RX_CONS14_LO 0x02F4 544 #define BGE_MBX_RX_CONS15_HI 0x02F8 545 #define BGE_MBX_RX_CONS15_LO 0x02FC 546 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 547 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 548 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 549 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 550 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 551 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 552 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 553 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 554 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 555 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 556 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 557 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 558 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 559 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 560 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 561 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 562 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 563 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 564 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 565 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 566 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 567 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 568 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 569 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 570 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 571 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 572 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 573 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 574 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 575 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 576 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 577 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 578 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 579 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 580 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 581 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 582 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 583 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 584 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 585 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 586 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 587 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 588 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 589 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 590 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 591 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 592 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 593 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 594 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 595 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 596 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 597 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 598 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 599 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 600 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 601 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 602 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 603 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 604 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 605 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 606 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 607 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 608 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 609 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 610 611 #define BGE_TX_RINGS_MAX 4 612 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 613 #define BGE_RX_RINGS_MAX 16 614 #define BGE_RX_RINGS_MAX_5717 17 615 616 /* Ethernet MAC control registers */ 617 #define BGE_MAC_MODE 0x0400 618 #define BGE_MAC_STS 0x0404 619 #define BGE_MAC_EVT_ENB 0x0408 620 #define BGE_MAC_LED_CTL 0x040C 621 #define BGE_MAC_ADDR1_LO 0x0410 622 #define BGE_MAC_ADDR1_HI 0x0414 623 #define BGE_MAC_ADDR2_LO 0x0418 624 #define BGE_MAC_ADDR2_HI 0x041C 625 #define BGE_MAC_ADDR3_LO 0x0420 626 #define BGE_MAC_ADDR3_HI 0x0424 627 #define BGE_MAC_ADDR4_LO 0x0428 628 #define BGE_MAC_ADDR4_HI 0x042C 629 #define BGE_WOL_PATPTR 0x0430 630 #define BGE_WOL_PATCFG 0x0434 631 #define BGE_TX_RANDOM_BACKOFF 0x0438 632 #define BGE_RX_MTU 0x043C 633 #define BGE_GBIT_PCS_TEST 0x0440 634 #define BGE_TX_TBI_AUTONEG 0x0444 635 #define BGE_RX_TBI_AUTONEG 0x0448 636 #define BGE_MI_COMM 0x044C 637 #define BGE_MI_STS 0x0450 638 #define BGE_MI_MODE 0x0454 639 #define BGE_AUTOPOLL_STS 0x0458 640 #define BGE_TX_MODE 0x045C 641 #define BGE_TX_STS 0x0460 642 #define BGE_TX_LENGTHS 0x0464 643 #define BGE_RX_MODE 0x0468 644 #define BGE_RX_STS 0x046C 645 #define BGE_MAR0 0x0470 646 #define BGE_MAR1 0x0474 647 #define BGE_MAR2 0x0478 648 #define BGE_MAR3 0x047C 649 #define BGE_RX_BD_RULES_CTL0 0x0480 650 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 651 #define BGE_RX_BD_RULES_CTL1 0x0488 652 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 653 #define BGE_RX_BD_RULES_CTL2 0x0490 654 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 655 #define BGE_RX_BD_RULES_CTL3 0x0498 656 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 657 #define BGE_RX_BD_RULES_CTL4 0x04A0 658 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 659 #define BGE_RX_BD_RULES_CTL5 0x04A8 660 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 661 #define BGE_RX_BD_RULES_CTL6 0x04B0 662 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 663 #define BGE_RX_BD_RULES_CTL7 0x04B8 664 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 665 #define BGE_RX_BD_RULES_CTL8 0x04C0 666 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 667 #define BGE_RX_BD_RULES_CTL9 0x04C8 668 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 669 #define BGE_RX_BD_RULES_CTL10 0x04D0 670 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 671 #define BGE_RX_BD_RULES_CTL11 0x04D8 672 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 673 #define BGE_RX_BD_RULES_CTL12 0x04E0 674 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 675 #define BGE_RX_BD_RULES_CTL13 0x04E8 676 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 677 #define BGE_RX_BD_RULES_CTL14 0x04F0 678 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 679 #define BGE_RX_BD_RULES_CTL15 0x04F8 680 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 681 #define BGE_RX_RULES_CFG 0x0500 682 #define BGE_MAX_RX_FRAME_LOWAT 0x0504 683 #define BGE_SERDES_CFG 0x0590 684 #define BGE_SERDES_STS 0x0594 685 #define BGE_SGDIG_CFG 0x05B0 686 #define BGE_SGDIG_STS 0x05B4 687 #define BGE_TX_MAC_STATS_OCTETS 0x0800 688 #define BGE_TX_MAC_STATS_RESERVE_0 0x0804 689 #define BGE_TX_MAC_STATS_COLLS 0x0808 690 #define BGE_TX_MAC_STATS_XON_SENT 0x080C 691 #define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 692 #define BGE_TX_MAC_STATS_RESERVE_1 0x0814 693 #define BGE_TX_MAC_STATS_ERRORS 0x0818 694 #define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 695 #define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 696 #define BGE_TX_MAC_STATS_DEFERRED 0x0824 697 #define BGE_TX_MAC_STATS_RESERVE_2 0x0828 698 #define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 699 #define BGE_TX_MAC_STATS_LATE_COLL 0x0830 700 #define BGE_TX_MAC_STATS_RESERVE_3 0x0834 701 #define BGE_TX_MAC_STATS_RESERVE_4 0x0838 702 #define BGE_TX_MAC_STATS_RESERVE_5 0x083C 703 #define BGE_TX_MAC_STATS_RESERVE_6 0x0840 704 #define BGE_TX_MAC_STATS_RESERVE_7 0x0844 705 #define BGE_TX_MAC_STATS_RESERVE_8 0x0848 706 #define BGE_TX_MAC_STATS_RESERVE_9 0x084C 707 #define BGE_TX_MAC_STATS_RESERVE_10 0x0850 708 #define BGE_TX_MAC_STATS_RESERVE_11 0x0854 709 #define BGE_TX_MAC_STATS_RESERVE_12 0x0858 710 #define BGE_TX_MAC_STATS_RESERVE_13 0x085C 711 #define BGE_TX_MAC_STATS_RESERVE_14 0x0860 712 #define BGE_TX_MAC_STATS_RESERVE_15 0x0864 713 #define BGE_TX_MAC_STATS_RESERVE_16 0x0868 714 #define BGE_TX_MAC_STATS_UCAST 0x086C 715 #define BGE_TX_MAC_STATS_MCAST 0x0870 716 #define BGE_TX_MAC_STATS_BCAST 0x0874 717 #define BGE_TX_MAC_STATS_RESERVE_17 0x0878 718 #define BGE_TX_MAC_STATS_RESERVE_18 0x087C 719 #define BGE_RX_MAC_STATS_OCTESTS 0x0880 720 #define BGE_RX_MAC_STATS_RESERVE_0 0x0884 721 #define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 722 #define BGE_RX_MAC_STATS_UCAST 0x088C 723 #define BGE_RX_MAC_STATS_MCAST 0x0890 724 #define BGE_RX_MAC_STATS_BCAST 0x0894 725 #define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 726 #define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 727 #define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 728 #define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 729 #define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 730 #define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 731 #define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 732 #define BGE_RX_MAC_STATS_JABBERS 0x08B4 733 #define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 734 735 /* Ethernet MAC Mode register */ 736 #define BGE_MACMODE_RESET 0x00000001 737 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 738 #define BGE_MACMODE_PORTMODE 0x0000000C 739 #define BGE_MACMODE_LOOPBACK 0x00000010 740 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 741 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 742 #define BGE_MACMODE_MAX_DEFER 0x00000200 743 #define BGE_MACMODE_LINK_POLARITY 0x00000400 744 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 745 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 746 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 747 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 748 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 749 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 750 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 751 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 752 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 753 #define BGE_MACMODE_MIP_ENB 0x00100000 754 #define BGE_MACMODE_TXDMA_ENB 0x00200000 755 #define BGE_MACMODE_RXDMA_ENB 0x00400000 756 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 757 #define BGE_MACMODE_APE_RX_EN 0x08000000 758 #define BGE_MACMODE_APE_TX_EN 0x10000000 759 760 #define BGE_PORTMODE_NONE 0x00000000 761 #define BGE_PORTMODE_MII 0x00000004 762 #define BGE_PORTMODE_GMII 0x00000008 763 #define BGE_PORTMODE_TBI 0x0000000C 764 765 /* MAC Status register */ 766 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 767 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 768 #define BGE_MACSTAT_RX_CFG 0x00000004 769 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 770 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 771 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 772 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 773 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 774 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 775 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 776 #define BGE_MACSTAT_ODI_ERROR 0x02000000 777 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 778 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 779 780 /* MAC Event Enable Register */ 781 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 782 #define BGE_EVTENB_LINK_CHANGED 0x00001000 783 #define BGE_EVTENB_MI_COMPLETE 0x00400000 784 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 785 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 786 #define BGE_EVTENB_ODI_ERROR 0x02000000 787 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 788 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 789 790 /* LED Control Register */ 791 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 792 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 793 #define BGE_LEDCTL_100MBPS_LED 0x00000004 794 #define BGE_LEDCTL_10MBPS_LED 0x00000008 795 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 796 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 797 #define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 798 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 799 #define BGE_LEDCTL_100MBPS_STS 0x00000100 800 #define BGE_LEDCTL_10MBPS_STS 0x00000200 801 #define BGE_LEDCTL_TRAFLED_STS 0x00000400 802 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 803 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 804 805 /* TX backoff seed register */ 806 #define BGE_TX_BACKOFF_SEED_MASK 0x3FF 807 808 /* Autopoll status register */ 809 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 810 811 /* Transmit MAC mode register */ 812 #define BGE_TXMODE_RESET 0x00000001 813 #define BGE_TXMODE_ENABLE 0x00000002 814 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 815 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 816 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 817 #define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 818 #define BGE_TXMODE_JMB_FRM_LEN 0x00400000 819 #define BGE_TXMODE_CNT_DN_MODE 0x00800000 820 821 /* Transmit MAC status register */ 822 #define BGE_TXSTAT_RX_XOFFED 0x00000001 823 #define BGE_TXSTAT_SENT_XOFF 0x00000002 824 #define BGE_TXSTAT_SENT_XON 0x00000004 825 #define BGE_TXSTAT_LINK_UP 0x00000008 826 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 827 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 828 829 /* Transmit MAC lengths register */ 830 #define BGE_TXLEN_SLOTTIME 0x000000FF 831 #define BGE_TXLEN_IPG 0x00000F00 832 #define BGE_TXLEN_CRS 0x00003000 833 #define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 834 #define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 835 836 /* Receive MAC mode register */ 837 #define BGE_RXMODE_RESET 0x00000001 838 #define BGE_RXMODE_ENABLE 0x00000002 839 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 840 #define BGE_RXMODE_RX_GIANTS 0x00000020 841 #define BGE_RXMODE_RX_RUNTS 0x00000040 842 #define BGE_RXMODE_8022_LENCHECK 0x00000080 843 #define BGE_RXMODE_RX_PROMISC 0x00000100 844 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 845 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 846 #define BGE_RXMODE_IPV6_ENABLE 0x01000000 847 #define BGE_RXMODE_IPV4_FRAG_FIX 0x02000000 848 849 /* Receive MAC status register */ 850 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 851 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 852 #define BGE_RXSTAT_RCVD_XON 0x00000004 853 854 /* Receive Rules Control register */ 855 #define BGE_RXRULECTL_OFFSET 0x000000FF 856 #define BGE_RXRULECTL_CLASS 0x00001F00 857 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 858 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 859 #define BGE_RXRULECTL_MAP 0x01000000 860 #define BGE_RXRULECTL_DISCARD 0x02000000 861 #define BGE_RXRULECTL_MASK 0x04000000 862 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 863 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 864 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 865 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 866 867 /* Receive Rules Mask register */ 868 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 869 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 870 871 /* SERDES configuration register */ 872 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 873 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 874 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 875 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 876 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 877 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 878 #define BGE_SERDESCFG_TXMODE 0x00001000 879 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 880 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 881 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 882 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 883 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 884 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 885 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 886 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 887 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 888 889 /* SERDES status register */ 890 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 891 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 892 893 /* SGDIG config (not documented) */ 894 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 895 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 896 #define BGE_SGDIGCFG_SEND 0x40000000 897 #define BGE_SGDIGCFG_AUTO 0x80000000 898 899 /* SGDIG status (not documented) */ 900 #define BGE_SGDIGSTS_DONE 0x00000002 901 #define BGE_SGDIGSTS_IS_SERDES 0x00000100 902 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 903 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 904 905 906 /* MI communication register */ 907 #define BGE_MICOMM_DATA 0x0000FFFF 908 #define BGE_MICOMM_REG 0x001F0000 909 #define BGE_MICOMM_PHY 0x03E00000 910 #define BGE_MICOMM_CMD 0x0C000000 911 #define BGE_MICOMM_READFAIL 0x10000000 912 #define BGE_MICOMM_BUSY 0x20000000 913 914 #define BGE_MIREG(x) ((x & 0x1F) << 16) 915 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 916 #define BGE_MICMD_WRITE 0x04000000 917 #define BGE_MICMD_READ 0x08000000 918 919 /* MI status register */ 920 #define BGE_MISTS_LINK 0x00000001 921 #define BGE_MISTS_10MBPS 0x00000002 922 923 #define BGE_MIMODE_CLK_10MHZ 0x00000001 924 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 925 #define BGE_MIMODE_AUTOPOLL 0x00000010 926 #define BGE_MIMODE_CLKCNT 0x001F0000 927 #define BGE_MIMODE_500KHZ_CONST 0x00008000 928 #define BGE_MIMODE_BASE 0x000C0000 929 930 931 /* 932 * Send data initiator control registers. 933 */ 934 #define BGE_SDI_MODE 0x0C00 935 #define BGE_SDI_STATUS 0x0C04 936 #define BGE_SDI_STATS_CTL 0x0C08 937 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 938 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 939 #define BGE_ISO_PKT_TX 0x0C20 940 #define BGE_LOCSTATS_COS0 0x0C80 941 #define BGE_LOCSTATS_COS1 0x0C84 942 #define BGE_LOCSTATS_COS2 0x0C88 943 #define BGE_LOCSTATS_COS3 0x0C8C 944 #define BGE_LOCSTATS_COS4 0x0C90 945 #define BGE_LOCSTATS_COS5 0x0C84 946 #define BGE_LOCSTATS_COS6 0x0C98 947 #define BGE_LOCSTATS_COS7 0x0C9C 948 #define BGE_LOCSTATS_COS8 0x0CA0 949 #define BGE_LOCSTATS_COS9 0x0CA4 950 #define BGE_LOCSTATS_COS10 0x0CA8 951 #define BGE_LOCSTATS_COS11 0x0CAC 952 #define BGE_LOCSTATS_COS12 0x0CB0 953 #define BGE_LOCSTATS_COS13 0x0CB4 954 #define BGE_LOCSTATS_COS14 0x0CB8 955 #define BGE_LOCSTATS_COS15 0x0CBC 956 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 957 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 958 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 959 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 960 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 961 #define BGE_LOCSTATS_IRQS 0x0CD4 962 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 963 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 964 965 /* Send Data Initiator mode register */ 966 #define BGE_SDIMODE_RESET 0x00000001 967 #define BGE_SDIMODE_ENABLE 0x00000002 968 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 969 #define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 970 971 /* Send Data Initiator stats register */ 972 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 973 974 /* Send Data Initiator stats control register */ 975 #define BGE_SDISTATSCTL_ENABLE 0x00000001 976 #define BGE_SDISTATSCTL_FASTER 0x00000002 977 #define BGE_SDISTATSCTL_CLEAR 0x00000004 978 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 979 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 980 981 /* 982 * Send Data Completion Control registers 983 */ 984 #define BGE_SDC_MODE 0x1000 985 #define BGE_SDC_STATUS 0x1004 986 987 /* Send Data completion mode register */ 988 #define BGE_SDCMODE_RESET 0x00000001 989 #define BGE_SDCMODE_ENABLE 0x00000002 990 #define BGE_SDCMODE_ATTN 0x00000004 991 #define BGE_SDCMODE_CDELAY 0x00000010 992 993 /* Send Data completion status register */ 994 #define BGE_SDCSTAT_ATTN 0x00000004 995 996 /* 997 * Send BD Ring Selector Control registers 998 */ 999 #define BGE_SRS_MODE 0x1400 1000 #define BGE_SRS_STATUS 0x1404 1001 #define BGE_SRS_HWDIAG 0x1408 1002 #define BGE_SRS_LOC_NIC_CONS0 0x1440 1003 #define BGE_SRS_LOC_NIC_CONS1 0x1444 1004 #define BGE_SRS_LOC_NIC_CONS2 0x1448 1005 #define BGE_SRS_LOC_NIC_CONS3 0x144C 1006 #define BGE_SRS_LOC_NIC_CONS4 0x1450 1007 #define BGE_SRS_LOC_NIC_CONS5 0x1454 1008 #define BGE_SRS_LOC_NIC_CONS6 0x1458 1009 #define BGE_SRS_LOC_NIC_CONS7 0x145C 1010 #define BGE_SRS_LOC_NIC_CONS8 0x1460 1011 #define BGE_SRS_LOC_NIC_CONS9 0x1464 1012 #define BGE_SRS_LOC_NIC_CONS10 0x1468 1013 #define BGE_SRS_LOC_NIC_CONS11 0x146C 1014 #define BGE_SRS_LOC_NIC_CONS12 0x1470 1015 #define BGE_SRS_LOC_NIC_CONS13 0x1474 1016 #define BGE_SRS_LOC_NIC_CONS14 0x1478 1017 #define BGE_SRS_LOC_NIC_CONS15 0x147C 1018 1019 /* Send BD Ring Selector Mode register */ 1020 #define BGE_SRSMODE_RESET 0x00000001 1021 #define BGE_SRSMODE_ENABLE 0x00000002 1022 #define BGE_SRSMODE_ATTN 0x00000004 1023 1024 /* Send BD Ring Selector Status register */ 1025 #define BGE_SRSSTAT_ERROR 0x00000004 1026 1027 /* Send BD Ring Selector HW Diagnostics register */ 1028 #define BGE_SRSHWDIAG_STATE 0x0000000F 1029 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1030 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1031 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1032 1033 /* 1034 * Send BD Initiator Selector Control registers 1035 */ 1036 #define BGE_SBDI_MODE 0x1800 1037 #define BGE_SBDI_STATUS 0x1804 1038 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 1039 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 1040 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 1041 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 1042 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 1043 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 1044 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 1045 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 1046 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 1047 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 1048 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 1049 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 1050 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 1051 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 1052 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 1053 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 1054 1055 /* Send BD Initiator Mode register */ 1056 #define BGE_SBDIMODE_RESET 0x00000001 1057 #define BGE_SBDIMODE_ENABLE 0x00000002 1058 #define BGE_SBDIMODE_ATTN 0x00000004 1059 1060 /* Send BD Initiator Status register */ 1061 #define BGE_SBDISTAT_ERROR 0x00000004 1062 1063 /* 1064 * Send BD Completion Control registers 1065 */ 1066 #define BGE_SBDC_MODE 0x1C00 1067 #define BGE_SBDC_STATUS 0x1C04 1068 1069 /* Send BD Completion Control Mode register */ 1070 #define BGE_SBDCMODE_RESET 0x00000001 1071 #define BGE_SBDCMODE_ENABLE 0x00000002 1072 #define BGE_SBDCMODE_ATTN 0x00000004 1073 1074 /* Send BD Completion Control Status register */ 1075 #define BGE_SBDCSTAT_ATTN 0x00000004 1076 1077 /* 1078 * Receive List Placement Control registers 1079 */ 1080 #define BGE_RXLP_MODE 0x2000 1081 #define BGE_RXLP_STATUS 0x2004 1082 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 1083 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1084 #define BGE_RXLP_CFG 0x2010 1085 #define BGE_RXLP_STATS_CTL 0x2014 1086 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1087 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1088 #define BGE_RXLP_HEAD0 0x2100 1089 #define BGE_RXLP_TAIL0 0x2104 1090 #define BGE_RXLP_COUNT0 0x2108 1091 #define BGE_RXLP_HEAD1 0x2110 1092 #define BGE_RXLP_TAIL1 0x2114 1093 #define BGE_RXLP_COUNT1 0x2118 1094 #define BGE_RXLP_HEAD2 0x2120 1095 #define BGE_RXLP_TAIL2 0x2124 1096 #define BGE_RXLP_COUNT2 0x2128 1097 #define BGE_RXLP_HEAD3 0x2130 1098 #define BGE_RXLP_TAIL3 0x2134 1099 #define BGE_RXLP_COUNT3 0x2138 1100 #define BGE_RXLP_HEAD4 0x2140 1101 #define BGE_RXLP_TAIL4 0x2144 1102 #define BGE_RXLP_COUNT4 0x2148 1103 #define BGE_RXLP_HEAD5 0x2150 1104 #define BGE_RXLP_TAIL5 0x2154 1105 #define BGE_RXLP_COUNT5 0x2158 1106 #define BGE_RXLP_HEAD6 0x2160 1107 #define BGE_RXLP_TAIL6 0x2164 1108 #define BGE_RXLP_COUNT6 0x2168 1109 #define BGE_RXLP_HEAD7 0x2170 1110 #define BGE_RXLP_TAIL7 0x2174 1111 #define BGE_RXLP_COUNT7 0x2178 1112 #define BGE_RXLP_HEAD8 0x2180 1113 #define BGE_RXLP_TAIL8 0x2184 1114 #define BGE_RXLP_COUNT8 0x2188 1115 #define BGE_RXLP_HEAD9 0x2190 1116 #define BGE_RXLP_TAIL9 0x2194 1117 #define BGE_RXLP_COUNT9 0x2198 1118 #define BGE_RXLP_HEAD10 0x21A0 1119 #define BGE_RXLP_TAIL10 0x21A4 1120 #define BGE_RXLP_COUNT10 0x21A8 1121 #define BGE_RXLP_HEAD11 0x21B0 1122 #define BGE_RXLP_TAIL11 0x21B4 1123 #define BGE_RXLP_COUNT11 0x21B8 1124 #define BGE_RXLP_HEAD12 0x21C0 1125 #define BGE_RXLP_TAIL12 0x21C4 1126 #define BGE_RXLP_COUNT12 0x21C8 1127 #define BGE_RXLP_HEAD13 0x21D0 1128 #define BGE_RXLP_TAIL13 0x21D4 1129 #define BGE_RXLP_COUNT13 0x21D8 1130 #define BGE_RXLP_HEAD14 0x21E0 1131 #define BGE_RXLP_TAIL14 0x21E4 1132 #define BGE_RXLP_COUNT14 0x21E8 1133 #define BGE_RXLP_HEAD15 0x21F0 1134 #define BGE_RXLP_TAIL15 0x21F4 1135 #define BGE_RXLP_COUNT15 0x21F8 1136 #define BGE_RXLP_LOCSTAT_COS0 0x2200 1137 #define BGE_RXLP_LOCSTAT_COS1 0x2204 1138 #define BGE_RXLP_LOCSTAT_COS2 0x2208 1139 #define BGE_RXLP_LOCSTAT_COS3 0x220C 1140 #define BGE_RXLP_LOCSTAT_COS4 0x2210 1141 #define BGE_RXLP_LOCSTAT_COS5 0x2214 1142 #define BGE_RXLP_LOCSTAT_COS6 0x2218 1143 #define BGE_RXLP_LOCSTAT_COS7 0x221C 1144 #define BGE_RXLP_LOCSTAT_COS8 0x2220 1145 #define BGE_RXLP_LOCSTAT_COS9 0x2224 1146 #define BGE_RXLP_LOCSTAT_COS10 0x2228 1147 #define BGE_RXLP_LOCSTAT_COS11 0x222C 1148 #define BGE_RXLP_LOCSTAT_COS12 0x2230 1149 #define BGE_RXLP_LOCSTAT_COS13 0x2234 1150 #define BGE_RXLP_LOCSTAT_COS14 0x2238 1151 #define BGE_RXLP_LOCSTAT_COS15 0x223C 1152 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1153 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1154 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1155 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1156 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1157 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1158 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1159 1160 1161 /* Receive List Placement mode register */ 1162 #define BGE_RXLPMODE_RESET 0x00000001 1163 #define BGE_RXLPMODE_ENABLE 0x00000002 1164 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1165 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1166 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1167 1168 /* Receive List Placement Status register */ 1169 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1170 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1171 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1172 1173 /* 1174 * Receive Data and Receive BD Initiator Control Registers 1175 */ 1176 #define BGE_RDBDI_MODE 0x2400 1177 #define BGE_RDBDI_STATUS 0x2404 1178 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1179 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1180 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1181 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1182 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 1183 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 1184 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1185 #define BGE_RX_STD_RCB_NICADDR 0x245C 1186 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1187 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1188 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1189 #define BGE_RX_MINI_RCB_NICADDR 0x246C 1190 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1191 #define BGE_RDBDI_STD_RX_CONS 0x2474 1192 #define BGE_RDBDI_MINI_RX_CONS 0x2478 1193 #define BGE_RDBDI_RETURN_PROD0 0x2480 1194 #define BGE_RDBDI_RETURN_PROD1 0x2484 1195 #define BGE_RDBDI_RETURN_PROD2 0x2488 1196 #define BGE_RDBDI_RETURN_PROD3 0x248C 1197 #define BGE_RDBDI_RETURN_PROD4 0x2490 1198 #define BGE_RDBDI_RETURN_PROD5 0x2494 1199 #define BGE_RDBDI_RETURN_PROD6 0x2498 1200 #define BGE_RDBDI_RETURN_PROD7 0x249C 1201 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1202 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1203 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1204 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1205 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1206 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1207 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1208 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1209 #define BGE_RDBDI_HWDIAG 0x24C0 1210 1211 1212 /* Receive Data and Receive BD Initiator Mode register */ 1213 #define BGE_RDBDIMODE_RESET 0x00000001 1214 #define BGE_RDBDIMODE_ENABLE 0x00000002 1215 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1216 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1217 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1218 1219 /* Receive Data and Receive BD Initiator Status register */ 1220 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1221 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1222 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1223 1224 1225 /* 1226 * Receive Data Completion Control registers 1227 */ 1228 #define BGE_RDC_MODE 0x2800 1229 1230 /* Receive Data Completion Mode register */ 1231 #define BGE_RDCMODE_RESET 0x00000001 1232 #define BGE_RDCMODE_ENABLE 0x00000002 1233 #define BGE_RDCMODE_ATTN 0x00000004 1234 1235 /* 1236 * Receive BD Initiator Control registers 1237 */ 1238 #define BGE_RBDI_MODE 0x2C00 1239 #define BGE_RBDI_STATUS 0x2C04 1240 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1241 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1242 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1243 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1244 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1245 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1246 1247 #define BGE_STD_REPLENISH_LWM 0x2D00 1248 #define BGE_JMB_REPLENISH_LWM 0x2D04 1249 1250 /* Receive BD Initiator Mode register */ 1251 #define BGE_RBDIMODE_RESET 0x00000001 1252 #define BGE_RBDIMODE_ENABLE 0x00000002 1253 #define BGE_RBDIMODE_ATTN 0x00000004 1254 1255 /* Receive BD Initiator Status register */ 1256 #define BGE_RBDISTAT_ATTN 0x00000004 1257 1258 /* 1259 * Receive BD Completion Control registers 1260 */ 1261 #define BGE_RBDC_MODE 0x3000 1262 #define BGE_RBDC_STATUS 0x3004 1263 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1264 #define BGE_RBDC_STD_BD_PROD 0x300C 1265 #define BGE_RBDC_MINI_BD_PROD 0x3010 1266 1267 /* Receive BD completion mode register */ 1268 #define BGE_RBDCMODE_RESET 0x00000001 1269 #define BGE_RBDCMODE_ENABLE 0x00000002 1270 #define BGE_RBDCMODE_ATTN 0x00000004 1271 1272 /* Receive BD completion status register */ 1273 #define BGE_RBDCSTAT_ERROR 0x00000004 1274 1275 /* 1276 * Receive List Selector Control registers 1277 */ 1278 #define BGE_RXLS_MODE 0x3400 1279 #define BGE_RXLS_STATUS 0x3404 1280 1281 /* Receive List Selector Mode register */ 1282 #define BGE_RXLSMODE_RESET 0x00000001 1283 #define BGE_RXLSMODE_ENABLE 0x00000002 1284 #define BGE_RXLSMODE_ATTN 0x00000004 1285 1286 /* Receive List Selector Status register */ 1287 #define BGE_RXLSSTAT_ERROR 0x00000004 1288 1289 #define BGE_CPMU_CTRL 0x3600 1290 #define BGE_CPMU_LSPD_10MB_CLK 0x3604 1291 #define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1292 #define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1293 #define BGE_CPMU_HST_ACC 0x361C 1294 #define BGE_CPMU_CLCK_ORIDE 0x3624 1295 #define BGE_CPMU_CLCK_STAT 0x3630 1296 #define BGE_CPMU_MUTEX_REQ 0x365C 1297 #define BGE_CPMU_MUTEX_GNT 0x3660 1298 #define BGE_CPMU_PHY_STRAP 0x3664 1299 #define BGE_CPMU_PADRNG_CTL 0x3668 1300 1301 /* Central Power Management Unit (CPMU) register */ 1302 #define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1303 #define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1304 #define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1305 #define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1306 1307 /* Link Speed 10MB/No Link Power Mode Clock Policy register */ 1308 #define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1309 #define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1310 1311 /* Link Speed 1000MB Power Mode Clock Policy register */ 1312 #define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1313 #define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1314 #define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1315 1316 /* Link Aware Power Mode Clock Policy register */ 1317 #define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1318 #define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1319 1320 #define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1321 #define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1322 1323 /* Clock Speed Override Policy register */ 1324 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1325 1326 /* CPMU Clock Status register */ 1327 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1328 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1329 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1330 #define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1331 1332 /* CPMU Mutex Request register */ 1333 #define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1334 #define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1335 1336 /* CPMU GPHY Strap register */ 1337 #define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1338 1339 /* CPMU Padring Control register */ 1340 #define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1341 1342 /* 1343 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1344 */ 1345 #define BGE_MBCF_MODE 0x3800 1346 #define BGE_MBCF_STATUS 0x3804 1347 1348 /* Mbuf Cluster Free mode register */ 1349 #define BGE_MBCFMODE_RESET 0x00000001 1350 #define BGE_MBCFMODE_ENABLE 0x00000002 1351 #define BGE_MBCFMODE_ATTN 0x00000004 1352 1353 /* Mbuf Cluster Free status register */ 1354 #define BGE_MBCFSTAT_ERROR 0x00000004 1355 1356 /* 1357 * Host Coalescing Control registers 1358 */ 1359 #define BGE_HCC_MODE 0x3C00 1360 #define BGE_HCC_STATUS 0x3C04 1361 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1362 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1363 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1364 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1365 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1366 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1367 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1368 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1369 #define BGE_HCC_STATS_TICKS 0x3C28 1370 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1371 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1372 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1373 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1374 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1375 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1376 #define BGE_FLOW_ATTN 0x3C48 1377 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1378 #define BGE_HCC_STD_BD_CONS 0x3C54 1379 #define BGE_HCC_MINI_BD_CONS 0x3C58 1380 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1381 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1382 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1383 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1384 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1385 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1386 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1387 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1388 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1389 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1390 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1391 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1392 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1393 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1394 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1395 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1396 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1397 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1398 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1399 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1400 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1401 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1402 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1403 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1404 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1405 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1406 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1407 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1408 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1409 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1410 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1411 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1412 1413 1414 /* Host coalescing mode register */ 1415 #define BGE_HCCMODE_RESET 0x00000001 1416 #define BGE_HCCMODE_ENABLE 0x00000002 1417 #define BGE_HCCMODE_ATTN 0x00000004 1418 #define BGE_HCCMODE_COAL_NOW 0x00000008 1419 #define BGE_HCCMODE_MSI_BITS 0x00000070 1420 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1421 1422 #define BGE_STATBLKSZ_FULL 0x00000000 1423 #define BGE_STATBLKSZ_64BYTE 0x00000080 1424 #define BGE_STATBLKSZ_32BYTE 0x00000100 1425 1426 /* Host coalescing status register */ 1427 #define BGE_HCCSTAT_ERROR 0x00000004 1428 1429 /* Flow attention register */ 1430 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1431 #define BGE_FLOWATTN_MEMARB 0x00000080 1432 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1433 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1434 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1435 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1436 #define BGE_FLOWATTN_RDBDI 0x00080000 1437 #define BGE_FLOWATTN_RXLS 0x00100000 1438 #define BGE_FLOWATTN_RXLP 0x00200000 1439 #define BGE_FLOWATTN_RBDC 0x00400000 1440 #define BGE_FLOWATTN_RBDI 0x00800000 1441 #define BGE_FLOWATTN_SDC 0x08000000 1442 #define BGE_FLOWATTN_SDI 0x10000000 1443 #define BGE_FLOWATTN_SRS 0x20000000 1444 #define BGE_FLOWATTN_SBDC 0x40000000 1445 #define BGE_FLOWATTN_SBDI 0x80000000 1446 1447 /* 1448 * Memory arbiter registers 1449 */ 1450 #define BGE_MARB_MODE 0x4000 1451 #define BGE_MARB_STATUS 0x4004 1452 #define BGE_MARB_TRAPADDR_HI 0x4008 1453 #define BGE_MARB_TRAPADDR_LO 0x400C 1454 1455 /* Memory arbiter mode register */ 1456 #define BGE_MARBMODE_RESET 0x00000001 1457 #define BGE_MARBMODE_ENABLE 0x00000002 1458 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1459 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1460 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1461 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1462 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1463 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1464 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1465 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1466 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1467 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1468 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1469 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1470 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1471 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1472 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1473 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1474 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1475 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1476 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1477 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1478 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1479 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1480 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1481 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1482 1483 /* Memory arbiter status register */ 1484 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1485 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1486 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1487 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1488 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1489 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1490 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1491 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1492 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1493 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1494 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1495 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1496 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1497 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1498 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1499 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1500 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1501 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1502 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1503 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1504 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1505 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1506 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1507 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1508 1509 /* 1510 * Buffer manager control registers 1511 */ 1512 #define BGE_BMAN_MODE 0x4400 1513 #define BGE_BMAN_STATUS 0x4404 1514 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1515 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1516 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1517 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1518 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1519 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1520 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1521 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1522 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1523 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1524 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1525 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1526 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1527 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1528 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1529 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1530 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1531 #define BGE_BMAN_HWDIAG_1 0x444C 1532 #define BGE_BMAN_HWDIAG_2 0x4450 1533 #define BGE_BMAN_HWDIAG_3 0x4454 1534 1535 /* Buffer manager mode register */ 1536 #define BGE_BMANMODE_RESET 0x00000001 1537 #define BGE_BMANMODE_ENABLE 0x00000002 1538 #define BGE_BMANMODE_ATTN 0x00000004 1539 #define BGE_BMANMODE_TESTMODE 0x00000008 1540 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1541 #define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1542 1543 /* Buffer manager status register */ 1544 #define BGE_BMANSTAT_ERRO 0x00000004 1545 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1546 1547 1548 /* 1549 * Read DMA Control registers 1550 */ 1551 #define BGE_RDMA_MODE 0x4800 1552 #define BGE_RDMA_STATUS 0x4804 1553 #define BGE_RDMA_RSRVCTRL_REG2 0x4890 1554 #define BGE_RDMA_LSO_CRPTEN_CTRL_REG2 0x48A0 1555 #define BGE_RDMA_RSRVCTRL 0x4900 1556 #define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1557 1558 /* Read DMA mode register */ 1559 #define BGE_RDMAMODE_RESET 0x00000001 1560 #define BGE_RDMAMODE_ENABLE 0x00000002 1561 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1562 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1563 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1564 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1565 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1566 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1567 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1568 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1569 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1570 #define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1571 #define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1572 #define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1573 #define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1574 #define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1575 #define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1576 #define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1577 #define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1578 #define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1579 1580 /* Read DMA status register */ 1581 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1582 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1583 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1584 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1585 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1586 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1587 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1588 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1589 1590 /* Read DMA Reserved Control register */ 1591 #define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1592 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1593 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1594 #define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1595 #define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1596 #define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1597 #define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1598 1599 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1600 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1601 #define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1602 #define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1603 #define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1604 1605 /* BD Read DMA Mode register */ 1606 #define BGE_RDMA_BD_MODE 0x4A00 1607 /* BD Read DMA Mode status register */ 1608 #define BGE_RDMA_BD_STATUS 0x4A04 1609 1610 #define BGE_RDMA_BD_MODE_RESET 0x00000001 1611 #define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1612 1613 /* Non-LSO Read DMA Mode register */ 1614 #define BGE_RDMA_NON_LSO_MODE 0x4B00 1615 /* Non-LSO Read DMA Mode status register */ 1616 #define BGE_RDMA_NON_LSO_STATUS 0x4B04 1617 1618 #define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1619 #define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1620 1621 #define BGE_RDMA_LENGTH 0x4BE0 1622 #define BGE_NUM_RDMA_CHANNELS 4 1623 1624 /* 1625 * Write DMA control registers 1626 */ 1627 #define BGE_WDMA_MODE 0x4C00 1628 #define BGE_WDMA_STATUS 0x4C04 1629 1630 /* Write DMA mode register */ 1631 #define BGE_WDMAMODE_RESET 0x00000001 1632 #define BGE_WDMAMODE_ENABLE 0x00000002 1633 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1634 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1635 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1636 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1637 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1638 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1639 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1640 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1641 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1642 #define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1643 #define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1644 1645 /* Write DMA status register */ 1646 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1647 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1648 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1649 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1650 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1651 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1652 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1653 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1654 1655 1656 /* 1657 * RX CPU registers 1658 */ 1659 #define BGE_RXCPU_MODE 0x5000 1660 #define BGE_RXCPU_STATUS 0x5004 1661 #define BGE_RXCPU_PC 0x501C 1662 1663 /* RX CPU mode register */ 1664 #define BGE_RXCPUMODE_RESET 0x00000001 1665 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1666 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1667 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1668 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1669 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1670 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1671 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1672 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1673 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1674 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1675 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1676 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1677 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1678 1679 /* RX CPU status register */ 1680 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1681 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1682 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1683 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1684 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1685 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1686 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1687 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1688 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1689 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1690 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1691 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1692 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1693 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1694 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1695 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1696 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1697 1698 /* 1699 * V? CPU registers 1700 */ 1701 #define BGE_VCPU_STATUS 0x5100 1702 #define BGE_VCPU_EXT_CTRL 0x6890 1703 1704 #define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1705 #define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1706 1707 #define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1708 #define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1709 1710 /* 1711 * TX CPU registers 1712 */ 1713 #define BGE_TXCPU_MODE 0x5400 1714 #define BGE_TXCPU_STATUS 0x5404 1715 #define BGE_TXCPU_PC 0x541C 1716 1717 /* TX CPU mode register */ 1718 #define BGE_TXCPUMODE_RESET 0x00000001 1719 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1720 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1721 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1722 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1723 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1724 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1725 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1726 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1727 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1728 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1729 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1730 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1731 1732 /* TX CPU status register */ 1733 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1734 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1735 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1736 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1737 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1738 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1739 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1740 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1741 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1742 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1743 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1744 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1745 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1746 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1747 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1748 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1749 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1750 1751 1752 /* 1753 * Low priority mailbox registers 1754 */ 1755 #define BGE_LPMBX_IRQ0_HI 0x5800 1756 #define BGE_LPMBX_IRQ0_LO 0x5804 1757 #define BGE_LPMBX_IRQ1_HI 0x5808 1758 #define BGE_LPMBX_IRQ1_LO 0x580C 1759 #define BGE_LPMBX_IRQ2_HI 0x5810 1760 #define BGE_LPMBX_IRQ2_LO 0x5814 1761 #define BGE_LPMBX_IRQ3_HI 0x5818 1762 #define BGE_LPMBX_IRQ3_LO 0x581C 1763 #define BGE_LPMBX_GEN0_HI 0x5820 1764 #define BGE_LPMBX_GEN0_LO 0x5824 1765 #define BGE_LPMBX_GEN1_HI 0x5828 1766 #define BGE_LPMBX_GEN1_LO 0x582C 1767 #define BGE_LPMBX_GEN2_HI 0x5830 1768 #define BGE_LPMBX_GEN2_LO 0x5834 1769 #define BGE_LPMBX_GEN3_HI 0x5828 1770 #define BGE_LPMBX_GEN3_LO 0x582C 1771 #define BGE_LPMBX_GEN4_HI 0x5840 1772 #define BGE_LPMBX_GEN4_LO 0x5844 1773 #define BGE_LPMBX_GEN5_HI 0x5848 1774 #define BGE_LPMBX_GEN5_LO 0x584C 1775 #define BGE_LPMBX_GEN6_HI 0x5850 1776 #define BGE_LPMBX_GEN6_LO 0x5854 1777 #define BGE_LPMBX_GEN7_HI 0x5858 1778 #define BGE_LPMBX_GEN7_LO 0x585C 1779 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1780 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1781 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1782 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1783 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1784 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1785 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1786 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1787 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1788 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1789 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1790 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1791 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1792 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1793 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1794 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1795 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1796 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1797 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1798 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1799 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1800 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1801 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1802 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1803 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1804 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1805 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1806 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1807 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1808 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1809 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1810 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1811 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1812 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1813 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1814 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1815 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1816 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1817 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1818 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1819 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1820 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1821 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1822 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1823 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1824 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1825 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1826 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1827 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1828 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1829 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1830 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1831 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1832 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1833 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1834 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1835 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1836 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1837 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1838 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1839 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1840 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1841 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1842 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1843 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1844 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1845 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1846 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1847 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1848 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1849 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1850 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1851 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1852 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1853 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1854 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1855 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1856 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1857 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1858 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1859 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1860 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1861 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1862 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1863 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1864 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1865 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1866 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1867 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1868 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1869 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1870 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1871 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1872 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1873 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1874 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1875 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1876 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1877 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1878 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1879 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1880 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1881 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1882 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1883 1884 /* 1885 * Flow throw Queue reset register 1886 */ 1887 #define BGE_FTQ_RESET 0x5C00 1888 1889 #define BGE_FTQRESET_DMAREAD 0x00000002 1890 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1891 #define BGE_FTQRESET_DMADONE 0x00000010 1892 #define BGE_FTQRESET_SBDC 0x00000020 1893 #define BGE_FTQRESET_SDI 0x00000040 1894 #define BGE_FTQRESET_WDMA 0x00000080 1895 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1896 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1897 #define BGE_FTQRESET_SDC 0x00000400 1898 #define BGE_FTQRESET_HCC 0x00000800 1899 #define BGE_FTQRESET_TXFIFO 0x00001000 1900 #define BGE_FTQRESET_MBC 0x00002000 1901 #define BGE_FTQRESET_RBDC 0x00004000 1902 #define BGE_FTQRESET_RXLP 0x00008000 1903 #define BGE_FTQRESET_RDBDI 0x00010000 1904 #define BGE_FTQRESET_RDC 0x00020000 1905 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1906 1907 /* 1908 * Message Signaled Interrupt registers 1909 */ 1910 #define BGE_MSI_MODE 0x6000 1911 #define BGE_MSI_STATUS 0x6004 1912 #define BGE_MSI_FIFOACCESS 0x6008 1913 1914 /* MSI mode register */ 1915 #define BGE_MSIMODE_RESET 0x00000001 1916 #define BGE_MSIMODE_ENABLE 0x00000002 1917 #define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1918 #define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1919 1920 /* MSI status register */ 1921 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1922 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1923 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1924 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1925 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1926 1927 1928 /* 1929 * DMA Completion registers 1930 */ 1931 #define BGE_DMAC_MODE 0x6400 1932 1933 /* DMA Completion mode register */ 1934 #define BGE_DMACMODE_RESET 0x00000001 1935 #define BGE_DMACMODE_ENABLE 0x00000002 1936 1937 1938 /* 1939 * General control registers. 1940 */ 1941 #define BGE_MODE_CTL 0x6800 1942 #define BGE_MISC_CFG 0x6804 1943 #define BGE_MISC_LOCAL_CTL 0x6808 1944 #define BGE_RX_CPU_EVENT 0x6810 1945 #define BGE_TX_CPU_EVENT 0x6820 1946 #define BGE_EE_ADDR 0x6838 1947 #define BGE_EE_DATA 0x683C 1948 #define BGE_EE_CTL 0x6840 1949 #define BGE_MDI_CTL 0x6844 1950 #define BGE_EE_DELAY 0x6848 1951 #define BGE_FASTBOOT_PC 0x6894 1952 1953 #define BGE_RX_CPU_DRV_EVENT 0x00004000 1954 1955 /* 1956 * NVRAM Control registers 1957 */ 1958 #define BGE_NVRAM_CMD 0x7000 1959 #define BGE_NVRAM_STAT 0x7004 1960 #define BGE_NVRAM_WRDATA 0x7008 1961 #define BGE_NVRAM_ADDR 0x700c 1962 #define BGE_NVRAM_RDDATA 0x7010 1963 #define BGE_NVRAM_CFG1 0x7014 1964 #define BGE_NVRAM_CFG2 0x7018 1965 #define BGE_NVRAM_CFG3 0x701c 1966 #define BGE_NVRAM_SWARB 0x7020 1967 #define BGE_NVRAM_ACCESS 0x7024 1968 #define BGE_NVRAM_WRITE1 0x7028 1969 1970 #define BGE_NVRAMCMD_RESET 0x00000001 1971 #define BGE_NVRAMCMD_DONE 0x00000008 1972 #define BGE_NVRAMCMD_START 0x00000010 1973 #define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */ 1974 #define BGE_NVRAMCMD_ERASE 0x00000040 1975 #define BGE_NVRAMCMD_FIRST 0x00000080 1976 #define BGE_NVRAMCMD_LAST 0x00000100 1977 1978 #define BGE_NVRAM_READCMD \ 1979 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1980 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE) 1981 #define BGE_NVRAM_WRITECMD \ 1982 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \ 1983 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR) 1984 1985 #define BGE_NVRAMSWARB_SET0 0x00000001 1986 #define BGE_NVRAMSWARB_SET1 0x00000002 1987 #define BGE_NVRAMSWARB_SET2 0x00000003 1988 #define BGE_NVRAMSWARB_SET3 0x00000004 1989 #define BGE_NVRAMSWARB_CLR0 0x00000010 1990 #define BGE_NVRAMSWARB_CLR1 0x00000020 1991 #define BGE_NVRAMSWARB_CLR2 0x00000040 1992 #define BGE_NVRAMSWARB_CLR3 0x00000080 1993 #define BGE_NVRAMSWARB_GNT0 0x00000100 1994 #define BGE_NVRAMSWARB_GNT1 0x00000200 1995 #define BGE_NVRAMSWARB_GNT2 0x00000400 1996 #define BGE_NVRAMSWARB_GNT3 0x00000800 1997 #define BGE_NVRAMSWARB_REQ0 0x00001000 1998 #define BGE_NVRAMSWARB_REQ1 0x00002000 1999 #define BGE_NVRAMSWARB_REQ2 0x00004000 2000 #define BGE_NVRAMSWARB_REQ3 0x00008000 2001 2002 #define BGE_NVRAMACC_ENABLE 0x00000001 2003 #define BGE_NVRAMACC_WRENABLE 0x00000002 2004 2005 /* Mode control register */ 2006 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 2007 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2008 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2009 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2010 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2011 #define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2012 #define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2013 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2014 #define BGE_MODECTL_NO_RX_CRC 0x00000400 2015 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 2016 #define BGE_MODECTL_NO_TX_INTR 0x00002000 2017 #define BGE_MODECTL_NO_RX_INTR 0x00004000 2018 #define BGE_MODECTL_FORCE_PCI32 0x00008000 2019 #define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2020 #define BGE_MODECTL_STACKUP 0x00010000 2021 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2022 #define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2023 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2024 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2025 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2026 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2027 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2028 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2029 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2030 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2031 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2032 2033 /* Misc. config register */ 2034 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2035 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2036 #define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2037 #define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2038 #define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2039 #define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2040 #define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2041 #define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2042 #define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 2043 2044 #define BGE_32BITTIME_66MHZ (0x41 << 1) 2045 2046 /* Misc. Local Control */ 2047 #define BGE_MLC_INTR_STATE 0x00000001 2048 #define BGE_MLC_INTR_CLR 0x00000002 2049 #define BGE_MLC_INTR_SET 0x00000004 2050 #define BGE_MLC_INTR_ONATTN 0x00000008 2051 #define BGE_MLC_MISCIO_IN0 0x00000100 2052 #define BGE_MLC_MISCIO_IN1 0x00000200 2053 #define BGE_MLC_MISCIO_IN2 0x00000400 2054 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 2055 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 2056 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 2057 #define BGE_MLC_MISCIO_OUT0 0x00004000 2058 #define BGE_MLC_MISCIO_OUT1 0x00008000 2059 #define BGE_MLC_MISCIO_OUT2 0x00010000 2060 #define BGE_MLC_EXTRAM_ENB 0x00020000 2061 #define BGE_MLC_SRAM_SIZE 0x001C0000 2062 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 2063 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 2064 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2065 #define BGE_MLC_AUTO_EEPROM 0x01000000 2066 2067 #define BGE_SSRAMSIZE_256KB 0x00000000 2068 #define BGE_SSRAMSIZE_512KB 0x00040000 2069 #define BGE_SSRAMSIZE_1MB 0x00080000 2070 #define BGE_SSRAMSIZE_2MB 0x000C0000 2071 #define BGE_SSRAMSIZE_4MB 0x00100000 2072 #define BGE_SSRAMSIZE_8MB 0x00140000 2073 #define BGE_SSRAMSIZE_16M 0x00180000 2074 2075 /* EEPROM address register */ 2076 #define BGE_EEADDR_ADDRESS 0x0000FFFC 2077 #define BGE_EEADDR_HALFCLK 0x01FF0000 2078 #define BGE_EEADDR_START 0x02000000 2079 #define BGE_EEADDR_DEVID 0x1C000000 2080 #define BGE_EEADDR_RESET 0x20000000 2081 #define BGE_EEADDR_DONE 0x40000000 2082 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 2083 2084 #define BGE_EEDEVID(x) ((x & 7) << 26) 2085 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2086 #define BGE_HALFCLK_384SCL 0x60 2087 #define BGE_EE_READCMD \ 2088 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2089 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 2090 #define BGE_EE_WRCMD \ 2091 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 2092 BGE_EEADDR_START|BGE_EEADDR_DONE) 2093 2094 /* EEPROM Control register */ 2095 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2096 #define BGE_EECTL_CLKOUT 0x00000002 2097 #define BGE_EECTL_CLKIN 0x00000004 2098 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2099 #define BGE_EECTL_DATAOUT 0x00000010 2100 #define BGE_EECTL_DATAIN 0x00000020 2101 2102 /* MDI (MII/GMII) access register */ 2103 #define BGE_MDI_DATA 0x00000001 2104 #define BGE_MDI_DIR 0x00000002 2105 #define BGE_MDI_SEL 0x00000004 2106 #define BGE_MDI_CLK 0x00000008 2107 2108 #define BGE_MEMWIN_START 0x00008000 2109 #define BGE_MEMWIN_END 0x0000FFFF 2110 2111 /* BAR1 (APE) Register Definitions */ 2112 2113 #define BGE_APE_GPIO_MSG 0x0008 2114 #define BGE_APE_EVENT 0x000C 2115 #define BGE_APE_LOCK_REQ 0x002C 2116 #define BGE_APE_LOCK_GRANT 0x004C 2117 2118 #define BGE_APE_GPIO_MSG_SHIFT 4 2119 2120 #define BGE_APE_EVENT_1 0x00000001 2121 2122 #define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2123 2124 #define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2125 2126 /* APE Shared Memory block (writable by APE only) */ 2127 #define BGE_APE_SEG_SIG 0x4000 2128 #define BGE_APE_FW_STATUS 0x400C 2129 #define BGE_APE_FW_FEATURES 0x4010 2130 #define BGE_APE_FW_BEHAVIOR 0x4014 2131 #define BGE_APE_FW_VERSION 0x4018 2132 #define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2133 #define BGE_APE_FW_HEARTBEAT 0x4028 2134 #define BGE_APE_FW_ERROR_FLAGS 0x4074 2135 2136 #define BGE_APE_SEG_SIG_MAGIC 0x41504521 2137 2138 #define BGE_APE_FW_STATUS_READY 0x00000100 2139 2140 #define BGE_APE_FW_FEATURE_DASH 0x00000001 2141 #define BGE_APE_FW_FEATURE_NCSI 0x00000002 2142 2143 #define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2144 #define BGE_APE_FW_VERSION_MAJSFT 24 2145 #define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2146 #define BGE_APE_FW_VERSION_MINSFT 16 2147 #define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2148 #define BGE_APE_FW_VERSION_REVSFT 8 2149 #define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2150 2151 /* Host Shared Memory block (writable by host only) */ 2152 #define BGE_APE_HOST_SEG_SIG 0x4200 2153 #define BGE_APE_HOST_SEG_LEN 0x4204 2154 #define BGE_APE_HOST_INIT_COUNT 0x4208 2155 #define BGE_APE_HOST_DRIVER_ID 0x420C 2156 #define BGE_APE_HOST_BEHAVIOR 0x4210 2157 #define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2158 #define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2159 #define BGE_APE_HOST_DRVR_STATE 0x421C 2160 #define BGE_APE_HOST_WOL_SPEED 0x4224 2161 2162 #define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2163 2164 #define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2165 2166 #define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2167 #define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2168 (BGE_APE_HOST_DRIVER_ID_FBSD | \ 2169 ((maj) & 0xffd) << 16 | ((min) & 0xff) << 8) 2170 2171 #define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2172 2173 #define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2174 #define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2175 2176 #define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2177 #define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2178 #define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2179 #define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2180 2181 #define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2182 2183 #define BGE_APE_EVENT_STATUS 0x4300 2184 2185 #define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2186 #define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2187 #define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2188 #define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2189 #define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2190 #define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2191 #define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2192 2193 #define BGE_APE_DEBUG_LOG 0x4E00 2194 #define BGE_APE_DEBUG_LOG_LEN 0x0100 2195 2196 #define BGE_APE_PER_LOCK_REQ 0x8400 2197 #define BGE_APE_PER_LOCK_GRANT 0x8420 2198 2199 #define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2200 #define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2201 #define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2202 #define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2203 2204 #define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2205 #define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2206 #define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2207 #define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2208 2209 /* APE Mutex Resources */ 2210 #define BGE_APE_LOCK_PHY0 0 2211 #define BGE_APE_LOCK_GRC 1 2212 #define BGE_APE_LOCK_PHY1 2 2213 #define BGE_APE_LOCK_PHY2 3 2214 #define BGE_APE_LOCK_MEM 4 2215 #define BGE_APE_LOCK_PHY3 5 2216 #define BGE_APE_LOCK_GPIO 7 2217 2218 #define BGE_MEMWIN_READ(sc, x, val) \ 2219 do { \ 2220 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2221 (0xFFFF0000 & x), 4); \ 2222 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2223 } while(0) 2224 2225 #define BGE_MEMWIN_WRITE(sc, x, val) \ 2226 do { \ 2227 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2228 (0xFFFF0000 & x), 4); \ 2229 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2230 } while(0) 2231 2232 /* 2233 * This magic number is written to the firmware mailbox at 0xb50 2234 * before a software reset is issued. After the internal firmware 2235 * has completed its initialization it will write the opposite of 2236 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2237 * allowing the driver to synchronize with the firmware. 2238 */ 2239 #define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2240 2241 typedef struct { 2242 uint32_t bge_addr_hi; 2243 uint32_t bge_addr_lo; 2244 } bge_hostaddr; 2245 2246 #define BGE_HOSTADDR(x, y) \ 2247 do { \ 2248 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2249 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2250 } while(0) 2251 2252 #define BGE_ADDR_LO(y) \ 2253 ((uint64_t) (y) & 0xFFFFFFFF) 2254 #define BGE_ADDR_HI(y) \ 2255 ((uint64_t) (y) >> 32) 2256 2257 /* Ring control block structure */ 2258 struct bge_rcb { 2259 bge_hostaddr bge_hostaddr; 2260 uint32_t bge_maxlen_flags; 2261 uint32_t bge_nicaddr; 2262 }; 2263 2264 #define RCB_WRITE_4(sc, rcb, offset, val) \ 2265 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2266 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 2267 2268 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2269 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 2270 2271 struct bge_tx_bd { 2272 bge_hostaddr bge_addr; 2273 #if BYTE_ORDER == LITTLE_ENDIAN 2274 uint16_t bge_flags; 2275 uint16_t bge_len; 2276 uint16_t bge_vlan_tag; 2277 uint16_t bge_mss; 2278 #else 2279 uint16_t bge_len; 2280 uint16_t bge_flags; 2281 uint16_t bge_mss; 2282 uint16_t bge_vlan_tag; 2283 #endif 2284 }; 2285 2286 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2287 #define BGE_TXBDFLAG_IP_CSUM 0x0002 2288 #define BGE_TXBDFLAG_END 0x0004 2289 #define BGE_TXBDFLAG_IP_FRAG 0x0008 2290 #define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */ 2291 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2292 #define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */ 2293 #define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */ 2294 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 2295 #define BGE_TXBDFLAG_COAL_NOW 0x0080 2296 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2297 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2298 #define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */ 2299 #define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */ 2300 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2301 #define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */ 2302 #define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */ 2303 #define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */ 2304 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2305 #define BGE_TXBDFLAG_NO_CRC 0x8000 2306 2307 #define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */ 2308 /* Bits [1:0] of the MSS header length. */ 2309 #define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */ 2310 2311 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 2312 BGE_SEND_RING_1_TO_4 + \ 2313 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2314 2315 struct bge_rx_bd { 2316 bge_hostaddr bge_addr; 2317 #if BYTE_ORDER == LITTLE_ENDIAN 2318 uint16_t bge_len; 2319 uint16_t bge_idx; 2320 uint16_t bge_flags; 2321 uint16_t bge_type; 2322 uint16_t bge_tcp_udp_csum; 2323 uint16_t bge_ip_csum; 2324 uint16_t bge_vlan_tag; 2325 uint16_t bge_error_flag; 2326 #else 2327 uint16_t bge_idx; 2328 uint16_t bge_len; 2329 uint16_t bge_type; 2330 uint16_t bge_flags; 2331 uint16_t bge_ip_csum; 2332 uint16_t bge_tcp_udp_csum; 2333 uint16_t bge_error_flag; 2334 uint16_t bge_vlan_tag; 2335 #endif 2336 uint32_t bge_rsvd; 2337 uint32_t bge_opaque; 2338 }; 2339 2340 struct bge_extrx_bd { 2341 bge_hostaddr bge_addr1; 2342 bge_hostaddr bge_addr2; 2343 bge_hostaddr bge_addr3; 2344 #if BYTE_ORDER == LITTLE_ENDIAN 2345 uint16_t bge_len2; 2346 uint16_t bge_len1; 2347 uint16_t bge_rsvd1; 2348 uint16_t bge_len3; 2349 #else 2350 uint16_t bge_len1; 2351 uint16_t bge_len2; 2352 uint16_t bge_len3; 2353 uint16_t bge_rsvd1; 2354 #endif 2355 bge_hostaddr bge_addr0; 2356 #if BYTE_ORDER == LITTLE_ENDIAN 2357 uint16_t bge_len0; 2358 uint16_t bge_idx; 2359 uint16_t bge_flags; 2360 uint16_t bge_type; 2361 uint16_t bge_tcp_udp_csum; 2362 uint16_t bge_ip_csum; 2363 uint16_t bge_vlan_tag; 2364 uint16_t bge_error_flag; 2365 #else 2366 uint16_t bge_idx; 2367 uint16_t bge_len0; 2368 uint16_t bge_type; 2369 uint16_t bge_flags; 2370 uint16_t bge_ip_csum; 2371 uint16_t bge_tcp_udp_csum; 2372 uint16_t bge_error_flag; 2373 uint16_t bge_vlan_tag; 2374 #endif 2375 uint32_t bge_rsvd0; 2376 uint32_t bge_opaque; 2377 }; 2378 2379 #define BGE_RXBDFLAG_END 0x0004 2380 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 2381 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 2382 #define BGE_RXBDFLAG_ERROR 0x0400 2383 #define BGE_RXBDFLAG_MINI_RING 0x0800 2384 #define BGE_RXBDFLAG_IP_CSUM 0x1000 2385 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2386 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2387 #define BGE_RXBDFLAG_IPV6 0x8000 2388 2389 #define BGE_RXERRFLAG_BAD_CRC 0x0001 2390 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 2391 #define BGE_RXERRFLAG_LINK_LOST 0x0004 2392 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2393 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 2394 #define BGE_RXERRFLAG_RUNT 0x0020 2395 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2396 #define BGE_RXERRFLAG_GIANT 0x0080 2397 #define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */ 2398 2399 struct bge_sts_idx { 2400 #if BYTE_ORDER == LITTLE_ENDIAN 2401 uint16_t bge_rx_prod_idx; 2402 uint16_t bge_tx_cons_idx; 2403 #else 2404 uint16_t bge_tx_cons_idx; 2405 uint16_t bge_rx_prod_idx; 2406 #endif 2407 }; 2408 2409 struct bge_status_block { 2410 uint32_t bge_status; 2411 uint32_t bge_status_tag; 2412 #if BYTE_ORDER == LITTLE_ENDIAN 2413 uint16_t bge_rx_jumbo_cons_idx; 2414 uint16_t bge_rx_std_cons_idx; 2415 uint16_t bge_rx_mini_cons_idx; 2416 uint16_t bge_rsvd1; 2417 #else 2418 uint16_t bge_rx_std_cons_idx; 2419 uint16_t bge_rx_jumbo_cons_idx; 2420 uint16_t bge_rsvd1; 2421 uint16_t bge_rx_mini_cons_idx; 2422 #endif 2423 struct bge_sts_idx bge_idx[16]; 2424 }; 2425 2426 #define BGE_STATFLAG_UPDATED 0x00000001 2427 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2428 #define BGE_STATFLAG_ERROR 0x00000004 2429 2430 2431 /* 2432 * Broadcom Vendor ID 2433 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2434 * even though they're now manufactured by Broadcom) 2435 */ 2436 #define BCOM_VENDORID 0x14E4 2437 #define BCOM_DEVICEID_BCM5700 0x1644 2438 #define BCOM_DEVICEID_BCM5701 0x1645 2439 #define BCOM_DEVICEID_BCM5702 0x1646 2440 #define BCOM_DEVICEID_BCM5702X 0x16A6 2441 #define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2442 #define BCOM_DEVICEID_BCM5703 0x1647 2443 #define BCOM_DEVICEID_BCM5703X 0x16A7 2444 #define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2445 #define BCOM_DEVICEID_BCM5704C 0x1648 2446 #define BCOM_DEVICEID_BCM5704S 0x16A8 2447 #define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2448 #define BCOM_DEVICEID_BCM5705 0x1653 2449 #define BCOM_DEVICEID_BCM5705K 0x1654 2450 #define BCOM_DEVICEID_BCM5705F 0x166E 2451 #define BCOM_DEVICEID_BCM5705M 0x165D 2452 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2453 #define BCOM_DEVICEID_BCM5714C 0x1668 2454 #define BCOM_DEVICEID_BCM5714S 0x1669 2455 #define BCOM_DEVICEID_BCM5715 0x1678 2456 #define BCOM_DEVICEID_BCM5715S 0x1679 2457 #define BCOM_DEVICEID_BCM5717 0x1655 2458 #define BCOM_DEVICEID_BCM5717C 0x1665 2459 #define BCOM_DEVICEID_BCM5718 0x1656 2460 #define BCOM_DEVICEID_BCM5719 0x1657 2461 #define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */ 2462 #define BCOM_DEVICEID_BCM5720 0x165F 2463 #define BCOM_DEVICEID_BCM5721 0x1659 2464 #define BCOM_DEVICEID_BCM5722 0x165A 2465 #define BCOM_DEVICEID_BCM5723 0x165B 2466 #define BCOM_DEVICEID_BCM5725 0x1643 2467 #define BCOM_DEVICEID_BCM5727 0x16F3 2468 #define BCOM_DEVICEID_BCM5750 0x1676 2469 #define BCOM_DEVICEID_BCM5750M 0x167C 2470 #define BCOM_DEVICEID_BCM5751 0x1677 2471 #define BCOM_DEVICEID_BCM5751F 0x167E 2472 #define BCOM_DEVICEID_BCM5751M 0x167D 2473 #define BCOM_DEVICEID_BCM5752 0x1600 2474 #define BCOM_DEVICEID_BCM5752M 0x1601 2475 #define BCOM_DEVICEID_BCM5753 0x16F7 2476 #define BCOM_DEVICEID_BCM5753F 0x16FE 2477 #define BCOM_DEVICEID_BCM5753M 0x16FD 2478 #define BCOM_DEVICEID_BCM5754 0x167A 2479 #define BCOM_DEVICEID_BCM5754M 0x1672 2480 #define BCOM_DEVICEID_BCM5755 0x167B 2481 #define BCOM_DEVICEID_BCM5755M 0x1673 2482 #define BCOM_DEVICEID_BCM5756 0x1674 2483 #define BCOM_DEVICEID_BCM5761 0x1681 2484 #define BCOM_DEVICEID_BCM5761E 0x1680 2485 #define BCOM_DEVICEID_BCM5761S 0x1688 2486 #define BCOM_DEVICEID_BCM5761SE 0x1689 2487 #define BCOM_DEVICEID_BCM5762 0x1687 2488 #define BCOM_DEVICEID_BCM5764 0x1684 2489 #define BCOM_DEVICEID_BCM5780 0x166A 2490 #define BCOM_DEVICEID_BCM5780S 0x166B 2491 #define BCOM_DEVICEID_BCM5781 0x16DD 2492 #define BCOM_DEVICEID_BCM5782 0x1696 2493 #define BCOM_DEVICEID_BCM5784 0x1698 2494 #define BCOM_DEVICEID_BCM5785F 0x16a0 2495 #define BCOM_DEVICEID_BCM5785G 0x1699 2496 #define BCOM_DEVICEID_BCM5786 0x169A 2497 #define BCOM_DEVICEID_BCM5787 0x169B 2498 #define BCOM_DEVICEID_BCM5787M 0x1693 2499 #define BCOM_DEVICEID_BCM5787F 0x167f 2500 #define BCOM_DEVICEID_BCM5788 0x169C 2501 #define BCOM_DEVICEID_BCM5789 0x169D 2502 #define BCOM_DEVICEID_BCM5901 0x170D 2503 #define BCOM_DEVICEID_BCM5901A2 0x170E 2504 #define BCOM_DEVICEID_BCM5903M 0x16FF 2505 #define BCOM_DEVICEID_BCM5906 0x1712 2506 #define BCOM_DEVICEID_BCM5906M 0x1713 2507 #define BCOM_DEVICEID_BCM57760 0x1690 2508 #define BCOM_DEVICEID_BCM57761 0x16B0 2509 #define BCOM_DEVICEID_BCM57762 0x1682 2510 #define BCOM_DEVICEID_BCM57764 0x1642 2511 #define BCOM_DEVICEID_BCM57765 0x16B4 2512 #define BCOM_DEVICEID_BCM57766 0x1686 2513 #define BCOM_DEVICEID_BCM57767 0x1683 2514 #define BCOM_DEVICEID_BCM57780 0x1692 2515 #define BCOM_DEVICEID_BCM57781 0x16B1 2516 #define BCOM_DEVICEID_BCM57782 0x16B7 2517 #define BCOM_DEVICEID_BCM57785 0x16B5 2518 #define BCOM_DEVICEID_BCM57786 0x16B3 2519 #define BCOM_DEVICEID_BCM57787 0x1641 2520 #define BCOM_DEVICEID_BCM57788 0x1691 2521 #define BCOM_DEVICEID_BCM57790 0x1694 2522 #define BCOM_DEVICEID_BCM57791 0x16B2 2523 #define BCOM_DEVICEID_BCM57795 0x16B6 2524 2525 /* 2526 * Alteon AceNIC PCI vendor/device ID. 2527 */ 2528 #define ALTEON_VENDORID 0x12AE 2529 #define ALTEON_DEVICEID_ACENIC 0x0001 2530 #define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2531 #define ALTEON_DEVICEID_BCM5700 0x0003 2532 #define ALTEON_DEVICEID_BCM5701 0x0004 2533 2534 /* 2535 * 3Com 3c996 PCI vendor/device ID. 2536 */ 2537 #define TC_VENDORID 0x10B7 2538 #define TC_DEVICEID_3C996 0x0003 2539 2540 /* 2541 * SysKonnect PCI vendor ID 2542 */ 2543 #define SK_VENDORID 0x1148 2544 #define SK_DEVICEID_ALTIMA 0x4400 2545 #define SK_SUBSYSID_9D21 0x4421 2546 #define SK_SUBSYSID_9D41 0x4441 2547 2548 /* 2549 * Altima PCI vendor/device ID. 2550 */ 2551 #define ALTIMA_VENDORID 0x173b 2552 #define ALTIMA_DEVICE_AC1000 0x03e8 2553 #define ALTIMA_DEVICE_AC1002 0x03e9 2554 #define ALTIMA_DEVICE_AC9100 0x03ea 2555 2556 /* 2557 * Dell PCI vendor ID 2558 */ 2559 2560 #define DELL_VENDORID 0x1028 2561 2562 /* 2563 * Apple PCI vendor ID. 2564 */ 2565 #define APPLE_VENDORID 0x106b 2566 #define APPLE_DEVICE_BCM5701 0x1645 2567 2568 /* 2569 * Sun PCI vendor ID 2570 */ 2571 #define SUN_VENDORID 0x108e 2572 2573 /* 2574 * Fujitsu vendor/device IDs 2575 */ 2576 #define FJTSU_VENDORID 0x10cf 2577 #define FJTSU_DEVICEID_PW008GE5 0x11a1 2578 #define FJTSU_DEVICEID_PW008GE4 0x11a2 2579 #define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */ 2580 2581 /* 2582 * Offset of MAC address inside EEPROM. 2583 */ 2584 #define BGE_EE_MAC_OFFSET 0x7C 2585 #define BGE_EE_MAC_OFFSET_5906 0x10 2586 #define BGE_EE_HWCFG_OFFSET 0xC8 2587 2588 #define BGE_HWCFG_VOLTAGE 0x00000003 2589 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2590 #define BGE_HWCFG_MEDIA 0x00000030 2591 #define BGE_HWCFG_ASF 0x00000080 2592 2593 #define BGE_VOLTAGE_1POINT3 0x00000000 2594 #define BGE_VOLTAGE_1POINT8 0x00000001 2595 2596 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2597 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2598 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2599 2600 #define BGE_MEDIA_UNSPEC 0x00000000 2601 #define BGE_MEDIA_COPPER 0x00000010 2602 #define BGE_MEDIA_FIBER 0x00000020 2603 2604 #define BGE_TICKS_PER_SEC 1000000 2605 2606 /* 2607 * Ring size constants. 2608 */ 2609 #define BGE_EVENT_RING_CNT 256 2610 #define BGE_CMD_RING_CNT 64 2611 #define BGE_STD_RX_RING_CNT 512 2612 #define BGE_JUMBO_RX_RING_CNT 256 2613 #define BGE_MINI_RX_RING_CNT 1024 2614 #define BGE_RETURN_RING_CNT 1024 2615 2616 /* 5705 has smaller return ring size */ 2617 2618 #define BGE_RETURN_RING_CNT_5705 512 2619 2620 /* 2621 * Possible TX ring sizes. 2622 */ 2623 #define BGE_TX_RING_CNT_128 128 2624 #define BGE_TX_RING_BASE_128 0x3800 2625 2626 #define BGE_TX_RING_CNT_256 256 2627 #define BGE_TX_RING_BASE_256 0x3000 2628 2629 #define BGE_TX_RING_CNT_512 512 2630 #define BGE_TX_RING_BASE_512 0x2000 2631 2632 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2633 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2634 2635 /* 2636 * Tigon III statistics counters. 2637 */ 2638 /* Statistics maintained MAC Receive block. */ 2639 struct bge_rx_mac_stats { 2640 bge_hostaddr ifHCInOctets; 2641 bge_hostaddr Reserved1; 2642 bge_hostaddr etherStatsFragments; 2643 bge_hostaddr ifHCInUcastPkts; 2644 bge_hostaddr ifHCInMulticastPkts; 2645 bge_hostaddr ifHCInBroadcastPkts; 2646 bge_hostaddr dot3StatsFCSErrors; 2647 bge_hostaddr dot3StatsAlignmentErrors; 2648 bge_hostaddr xonPauseFramesReceived; 2649 bge_hostaddr xoffPauseFramesReceived; 2650 bge_hostaddr macControlFramesReceived; 2651 bge_hostaddr xoffStateEntered; 2652 bge_hostaddr dot3StatsFramesTooLong; 2653 bge_hostaddr etherStatsJabbers; 2654 bge_hostaddr etherStatsUndersizePkts; 2655 bge_hostaddr inRangeLengthError; 2656 bge_hostaddr outRangeLengthError; 2657 bge_hostaddr etherStatsPkts64Octets; 2658 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2659 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2660 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2661 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2662 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2663 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2664 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2665 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2666 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2667 }; 2668 2669 2670 /* Statistics maintained MAC Transmit block. */ 2671 struct bge_tx_mac_stats { 2672 bge_hostaddr ifHCOutOctets; 2673 bge_hostaddr Reserved2; 2674 bge_hostaddr etherStatsCollisions; 2675 bge_hostaddr outXonSent; 2676 bge_hostaddr outXoffSent; 2677 bge_hostaddr flowControlDone; 2678 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2679 bge_hostaddr dot3StatsSingleCollisionFrames; 2680 bge_hostaddr dot3StatsMultipleCollisionFrames; 2681 bge_hostaddr dot3StatsDeferredTransmissions; 2682 bge_hostaddr Reserved3; 2683 bge_hostaddr dot3StatsExcessiveCollisions; 2684 bge_hostaddr dot3StatsLateCollisions; 2685 bge_hostaddr dot3Collided2Times; 2686 bge_hostaddr dot3Collided3Times; 2687 bge_hostaddr dot3Collided4Times; 2688 bge_hostaddr dot3Collided5Times; 2689 bge_hostaddr dot3Collided6Times; 2690 bge_hostaddr dot3Collided7Times; 2691 bge_hostaddr dot3Collided8Times; 2692 bge_hostaddr dot3Collided9Times; 2693 bge_hostaddr dot3Collided10Times; 2694 bge_hostaddr dot3Collided11Times; 2695 bge_hostaddr dot3Collided12Times; 2696 bge_hostaddr dot3Collided13Times; 2697 bge_hostaddr dot3Collided14Times; 2698 bge_hostaddr dot3Collided15Times; 2699 bge_hostaddr ifHCOutUcastPkts; 2700 bge_hostaddr ifHCOutMulticastPkts; 2701 bge_hostaddr ifHCOutBroadcastPkts; 2702 bge_hostaddr dot3StatsCarrierSenseErrors; 2703 bge_hostaddr ifOutDiscards; 2704 bge_hostaddr ifOutErrors; 2705 }; 2706 2707 /* Stats counters access through registers */ 2708 struct bge_mac_stats { 2709 /* TX MAC statistics */ 2710 uint64_t ifHCOutOctets; 2711 uint64_t Reserved0; 2712 uint64_t etherStatsCollisions; 2713 uint64_t outXonSent; 2714 uint64_t outXoffSent; 2715 uint64_t Reserved1; 2716 uint64_t dot3StatsInternalMacTransmitErrors; 2717 uint64_t dot3StatsSingleCollisionFrames; 2718 uint64_t dot3StatsMultipleCollisionFrames; 2719 uint64_t dot3StatsDeferredTransmissions; 2720 uint64_t Reserved2; 2721 uint64_t dot3StatsExcessiveCollisions; 2722 uint64_t dot3StatsLateCollisions; 2723 uint64_t Reserved3[14]; 2724 uint64_t ifHCOutUcastPkts; 2725 uint64_t ifHCOutMulticastPkts; 2726 uint64_t ifHCOutBroadcastPkts; 2727 uint64_t Reserved4[2]; 2728 /* RX MAC statistics */ 2729 uint64_t ifHCInOctets; 2730 uint64_t Reserved5; 2731 uint64_t etherStatsFragments; 2732 uint64_t ifHCInUcastPkts; 2733 uint64_t ifHCInMulticastPkts; 2734 uint64_t ifHCInBroadcastPkts; 2735 uint64_t dot3StatsFCSErrors; 2736 uint64_t dot3StatsAlignmentErrors; 2737 uint64_t xonPauseFramesReceived; 2738 uint64_t xoffPauseFramesReceived; 2739 uint64_t macControlFramesReceived; 2740 uint64_t xoffStateEntered; 2741 uint64_t dot3StatsFramesTooLong; 2742 uint64_t etherStatsJabbers; 2743 uint64_t etherStatsUndersizePkts; 2744 /* Receive List Placement control */ 2745 uint64_t FramesDroppedDueToFilters; 2746 uint64_t DmaWriteQueueFull; 2747 uint64_t DmaWriteHighPriQueueFull; 2748 uint64_t NoMoreRxBDs; 2749 uint64_t InputDiscards; 2750 uint64_t InputErrors; 2751 uint64_t RecvThresholdHit; 2752 }; 2753 2754 struct bge_stats { 2755 uint8_t Reserved0[256]; 2756 2757 /* Statistics maintained by Receive MAC. */ 2758 struct bge_rx_mac_stats rxstats; 2759 2760 bge_hostaddr Unused1[37]; 2761 2762 /* Statistics maintained by Transmit MAC. */ 2763 struct bge_tx_mac_stats txstats; 2764 2765 bge_hostaddr Unused2[31]; 2766 2767 /* Statistics maintained by Receive List Placement. */ 2768 bge_hostaddr COSIfHCInPkts[16]; 2769 bge_hostaddr COSFramesDroppedDueToFilters; 2770 bge_hostaddr nicDmaWriteQueueFull; 2771 bge_hostaddr nicDmaWriteHighPriQueueFull; 2772 bge_hostaddr nicNoMoreRxBDs; 2773 bge_hostaddr ifInDiscards; 2774 bge_hostaddr ifInErrors; 2775 bge_hostaddr nicRecvThresholdHit; 2776 2777 bge_hostaddr Unused3[9]; 2778 2779 /* Statistics maintained by Send Data Initiator. */ 2780 bge_hostaddr COSIfHCOutPkts[16]; 2781 bge_hostaddr nicDmaReadQueueFull; 2782 bge_hostaddr nicDmaReadHighPriQueueFull; 2783 bge_hostaddr nicSendDataCompQueueFull; 2784 2785 /* Statistics maintained by Host Coalescing. */ 2786 bge_hostaddr nicRingSetSendProdIndex; 2787 bge_hostaddr nicRingStatusUpdate; 2788 bge_hostaddr nicInterrupts; 2789 bge_hostaddr nicAvoidedInterrupts; 2790 bge_hostaddr nicSendThresholdHit; 2791 2792 uint8_t Reserved4[320]; 2793 }; 2794 2795 /* 2796 * Tigon general information block. This resides in host memory 2797 * and contains the status counters, ring control blocks and 2798 * producer pointers. 2799 */ 2800 2801 struct bge_gib { 2802 struct bge_stats bge_stats; 2803 struct bge_rcb bge_tx_rcb[16]; 2804 struct bge_rcb bge_std_rx_rcb; 2805 struct bge_rcb bge_jumbo_rx_rcb; 2806 struct bge_rcb bge_mini_rx_rcb; 2807 struct bge_rcb bge_return_rcb; 2808 }; 2809 2810 #define BGE_FRAMELEN 1518 2811 #define BGE_MAX_FRAMELEN 1536 2812 #define BGE_JUMBO_FRAMELEN 9018 2813 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2814 #define BGE_MIN_FRAMELEN 60 2815 2816 /* 2817 * Other utility macros. 2818 */ 2819 #define BGE_INC(x, y) (x) = (x + 1) % y 2820 2821 /* 2822 * BAR0 MAC register access macros. The Tigon always uses memory mapped register 2823 * accesses and all registers must be accessed with 32 bit operations. 2824 */ 2825 2826 #define CSR_WRITE_4(sc, reg, val) \ 2827 bus_write_4(sc->bge_res, reg, val) 2828 2829 #define CSR_READ_4(sc, reg) \ 2830 bus_read_4(sc->bge_res, reg) 2831 2832 #define BGE_SETBIT(sc, reg, x) \ 2833 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2834 #define BGE_CLRBIT(sc, reg, x) \ 2835 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2836 2837 /* BAR2 APE register access macros. */ 2838 #define APE_WRITE_4(sc, reg, val) \ 2839 bus_write_4(sc->bge_res2, reg, val) 2840 2841 #define APE_READ_4(sc, reg) \ 2842 bus_read_4(sc->bge_res2, reg) 2843 2844 #define APE_SETBIT(sc, reg, x) \ 2845 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) | (x))) 2846 #define APE_CLRBIT(sc, reg, x) \ 2847 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2848 2849 #define PCI_SETBIT(dev, reg, x, s) \ 2850 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2851 #define PCI_CLRBIT(dev, reg, x, s) \ 2852 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2853 2854 /* 2855 * Memory management stuff. 2856 */ 2857 2858 #define BGE_NSEG_JUMBO 4 2859 #define BGE_NSEG_NEW 35 2860 #define BGE_TSOSEG_SZ 4096 2861 2862 /* Maximum DMA address for controllers that have 40bit DMA address bug. */ 2863 #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2864 #define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2865 #else 2866 #define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2867 #endif 2868 2869 /* 2870 * Ring structures. Most of these reside in host memory and we tell 2871 * the NIC where they are via the ring control blocks. The exceptions 2872 * are the tx and command rings, which live in NIC memory and which 2873 * we access via the shared memory window. 2874 */ 2875 2876 struct bge_ring_data { 2877 struct bge_rx_bd *bge_rx_std_ring; 2878 bus_addr_t bge_rx_std_ring_paddr; 2879 struct bge_extrx_bd *bge_rx_jumbo_ring; 2880 bus_addr_t bge_rx_jumbo_ring_paddr; 2881 struct bge_rx_bd *bge_rx_return_ring; 2882 bus_addr_t bge_rx_return_ring_paddr; 2883 struct bge_tx_bd *bge_tx_ring; 2884 bus_addr_t bge_tx_ring_paddr; 2885 struct bge_status_block *bge_status_block; 2886 bus_addr_t bge_status_block_paddr; 2887 struct bge_stats *bge_stats; 2888 bus_addr_t bge_stats_paddr; 2889 struct bge_gib bge_info; 2890 }; 2891 2892 #define BGE_STD_RX_RING_SZ \ 2893 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2894 #define BGE_JUMBO_RX_RING_SZ \ 2895 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2896 #define BGE_TX_RING_SZ \ 2897 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2898 #define BGE_RX_RTN_RING_SZ(x) \ 2899 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2900 2901 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2902 2903 #define BGE_STATS_SZ sizeof (struct bge_stats) 2904 2905 /* 2906 * Mbuf pointers. We need these to keep track of the virtual addresses 2907 * of our mbuf chains since we can only convert from physical to virtual, 2908 * not the other way around. 2909 */ 2910 struct bge_chain_data { 2911 bus_dma_tag_t bge_parent_tag; 2912 bus_dma_tag_t bge_buffer_tag; 2913 bus_dma_tag_t bge_rx_std_ring_tag; 2914 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2915 bus_dma_tag_t bge_rx_return_ring_tag; 2916 bus_dma_tag_t bge_tx_ring_tag; 2917 bus_dma_tag_t bge_status_tag; 2918 bus_dma_tag_t bge_stats_tag; 2919 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */ 2920 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */ 2921 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */ 2922 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2923 bus_dmamap_t bge_rx_std_sparemap; 2924 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2925 bus_dmamap_t bge_rx_jumbo_sparemap; 2926 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2927 bus_dmamap_t bge_rx_std_ring_map; 2928 bus_dmamap_t bge_rx_jumbo_ring_map; 2929 bus_dmamap_t bge_tx_ring_map; 2930 bus_dmamap_t bge_rx_return_ring_map; 2931 bus_dmamap_t bge_status_map; 2932 bus_dmamap_t bge_stats_map; 2933 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2934 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2935 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2936 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2937 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2938 }; 2939 2940 struct bge_dmamap_arg { 2941 bus_addr_t bge_busaddr; 2942 }; 2943 2944 #define BGE_HWREV_TIGON 0x01 2945 #define BGE_HWREV_TIGON_II 0x02 2946 #define BGE_TIMEOUT 100000 2947 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2948 #define BGE_TX_TIMEOUT 5 2949 2950 struct bge_bcom_hack { 2951 int reg; 2952 int val; 2953 }; 2954 2955 #define ASF_ENABLE 1 2956 #define ASF_NEW_HANDSHAKE 2 2957 #define ASF_STACKUP 4 2958 2959 struct bge_softc { 2960 struct ifnet *bge_ifp; /* interface info */ 2961 device_t bge_dev; 2962 struct mtx bge_mtx; 2963 device_t bge_miibus; 2964 void *bge_intrhand; 2965 struct resource *bge_irq; 2966 struct resource *bge_res; /* MAC mapped I/O */ 2967 struct resource *bge_res2; /* APE mapped I/O */ 2968 struct ifmedia bge_ifmedia; /* TBI media info */ 2969 int bge_expcap; 2970 int bge_expmrq; 2971 int bge_msicap; 2972 int bge_pcixcap; 2973 uint32_t bge_flags; 2974 #define BGE_FLAG_TBI 0x00000001 2975 #define BGE_FLAG_JUMBO 0x00000002 2976 #define BGE_FLAG_JUMBO_STD 0x00000004 2977 #define BGE_FLAG_EADDR 0x00000008 2978 #define BGE_FLAG_MII_SERDES 0x00000010 2979 #define BGE_FLAG_CPMU_PRESENT 0x00000020 2980 #define BGE_FLAG_TAGGED_STATUS 0x00000040 2981 #define BGE_FLAG_APE 0x00000080 2982 #define BGE_FLAG_MSI 0x00000100 2983 #define BGE_FLAG_PCIX 0x00000200 2984 #define BGE_FLAG_PCIE 0x00000400 2985 #define BGE_FLAG_TSO 0x00000800 2986 #define BGE_FLAG_TSO3 0x00001000 2987 #define BGE_FLAG_JUMBO_FRAME 0x00002000 2988 #define BGE_FLAG_5700_FAMILY 0x00010000 2989 #define BGE_FLAG_5705_PLUS 0x00020000 2990 #define BGE_FLAG_5714_FAMILY 0x00040000 2991 #define BGE_FLAG_575X_PLUS 0x00080000 2992 #define BGE_FLAG_5755_PLUS 0x00100000 2993 #define BGE_FLAG_5788 0x00200000 2994 #define BGE_FLAG_5717_PLUS 0x00400000 2995 #define BGE_FLAG_57765_PLUS 0x00800000 2996 #define BGE_FLAG_40BIT_BUG 0x01000000 2997 #define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2998 #define BGE_FLAG_RX_ALIGNBUG 0x04000000 2999 #define BGE_FLAG_SHORT_DMA_BUG 0x08000000 3000 #define BGE_FLAG_4K_RDMA_BUG 0x10000000 3001 #define BGE_FLAG_MBOX_REORDER 0x20000000 3002 #define BGE_FLAG_RDMA_BUG 0x40000000 3003 uint32_t bge_mfw_flags; /* Management F/W flags */ 3004 #define BGE_MFW_ON_RXCPU 0x00000001 3005 #define BGE_MFW_ON_APE 0x00000002 3006 #define BGE_MFW_TYPE_NCSI 0x00000004 3007 #define BGE_MFW_TYPE_DASH 0x00000008 3008 int bge_phy_ape_lock; 3009 int bge_func_addr; 3010 int bge_phy_addr; 3011 uint32_t bge_phy_flags; 3012 #define BGE_PHY_NO_WIRESPEED 0x00000001 3013 #define BGE_PHY_ADC_BUG 0x00000002 3014 #define BGE_PHY_5704_A0_BUG 0x00000004 3015 #define BGE_PHY_JITTER_BUG 0x00000008 3016 #define BGE_PHY_BER_BUG 0x00000010 3017 #define BGE_PHY_ADJUST_TRIM 0x00000020 3018 #define BGE_PHY_CRC_BUG 0x00000040 3019 #define BGE_PHY_NO_3LED 0x00000080 3020 uint32_t bge_chipid; 3021 uint32_t bge_asicrev; 3022 uint32_t bge_chiprev; 3023 uint8_t bge_asf_mode; 3024 uint8_t bge_asf_count; 3025 uint16_t bge_mps; 3026 struct bge_ring_data bge_ldata; /* rings */ 3027 struct bge_chain_data bge_cdata; /* mbufs */ 3028 uint16_t bge_tx_saved_considx; 3029 uint16_t bge_rx_saved_considx; 3030 uint16_t bge_ev_saved_considx; 3031 uint16_t bge_return_ring_cnt; 3032 uint16_t bge_std; /* current std ring head */ 3033 uint16_t bge_jumbo; /* current jumo ring head */ 3034 uint32_t bge_stat_ticks; 3035 uint32_t bge_rx_coal_ticks; 3036 uint32_t bge_tx_coal_ticks; 3037 uint32_t bge_tx_prodidx; 3038 uint32_t bge_rx_max_coal_bds; 3039 uint32_t bge_tx_max_coal_bds; 3040 uint32_t bge_mi_mode; 3041 int bge_if_flags; 3042 int bge_txcnt; 3043 int bge_link; /* link state */ 3044 int bge_link_evt; /* pending link event */ 3045 int bge_timer; 3046 int bge_forced_collapse; 3047 int bge_forced_udpcsum; 3048 int bge_msi; 3049 int bge_csum_features; 3050 struct callout bge_stat_ch; 3051 uint32_t bge_rx_discards; 3052 uint32_t bge_rx_inerrs; 3053 uint32_t bge_rx_nobds; 3054 uint32_t bge_tx_discards; 3055 uint32_t bge_tx_collisions; 3056 #ifdef DEVICE_POLLING 3057 int rxcycles; 3058 #endif /* DEVICE_POLLING */ 3059 struct bge_mac_stats bge_mac_stats; 3060 struct task bge_intr_task; 3061 struct taskqueue *bge_tq; 3062 }; 3063 3064 #define BGE_LOCK_INIT(_sc, _name) \ 3065 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 3066 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 3067 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 3068 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 3069 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 3070