xref: /freebsd/sys/dev/bge/if_bgereg.h (revision 78007886c995898a9494648343e5236bca1cbba3)
1 /*-
2  * Copyright (c) 2001 Wind River Systems
3  * Copyright (c) 1997, 1998, 1999, 2001
4  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. All advertising materials mentioning features or use of this software
15  *    must display the following acknowledgement:
16  *	This product includes software developed by Bill Paul.
17  * 4. Neither the name of the author nor the names of any co-contributors
18  *    may be used to endorse or promote products derived from this software
19  *    without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31  * THE POSSIBILITY OF SUCH DAMAGE.
32  *
33  * $FreeBSD$
34  */
35 
36 /*
37  * BCM570x memory map. The internal memory layout varies somewhat
38  * depending on whether or not we have external SSRAM attached.
39  * The BCM5700 can have up to 16MB of external memory. The BCM5701
40  * is apparently not designed to use external SSRAM. The mappings
41  * up to the first 4 send rings are the same for both internal and
42  * external memory configurations. Note that mini RX ring space is
43  * only available with external SSRAM configurations, which means
44  * the mini RX ring is not supported on the BCM5701.
45  *
46  * The NIC's memory can be accessed by the host in one of 3 ways:
47  *
48  * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49  *    registers in PCI config space can be used to read any 32-bit
50  *    address within the NIC's memory.
51  *
52  * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53  *    space can be used in conjunction with the memory window in the
54  *    device register space at offset 0x8000 to read any 32K chunk
55  *    of NIC memory.
56  *
57  * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58  *    set, the device I/O mapping consumes 32MB of host address space,
59  *    allowing all of the registers and internal NIC memory to be
60  *    accessed directly. NIC memory addresses are offset by 0x01000000.
61  *    Flat mode consumes so much host address space that it is not
62  *    recommended.
63  */
64 #define	BGE_PAGE_ZERO			0x00000000
65 #define	BGE_PAGE_ZERO_END		0x000000FF
66 #define	BGE_SEND_RING_RCB		0x00000100
67 #define	BGE_SEND_RING_RCB_END		0x000001FF
68 #define	BGE_RX_RETURN_RING_RCB		0x00000200
69 #define	BGE_RX_RETURN_RING_RCB_END	0x000002FF
70 #define	BGE_STATS_BLOCK			0x00000300
71 #define	BGE_STATS_BLOCK_END		0x00000AFF
72 #define	BGE_STATUS_BLOCK		0x00000B00
73 #define	BGE_STATUS_BLOCK_END		0x00000B4F
74 #define	BGE_SOFTWARE_GENCOMM		0x00000B50
75 #define	BGE_SOFTWARE_GENCOMM_SIG	0x00000B54
76 #define	BGE_SOFTWARE_GENCOMM_NICCFG	0x00000B58
77 #define	BGE_SOFTWARE_GENCOMM_FW		0x00000B78
78 #define	BGE_SOFTWARE_GENNCOMM_FW_LEN	0x00000B7C
79 #define	BGE_SOFTWARE_GENNCOMM_FW_DATA	0x00000B80
80 #define	BGE_SOFTWARE_GENCOMM_END	0x00000FFF
81 #define	BGE_UNMAPPED			0x00001000
82 #define	BGE_UNMAPPED_END		0x00001FFF
83 #define	BGE_DMA_DESCRIPTORS		0x00002000
84 #define	BGE_DMA_DESCRIPTORS_END		0x00003FFF
85 #define	BGE_SEND_RING_1_TO_4		0x00004000
86 #define	BGE_SEND_RING_1_TO_4_END	0x00005FFF
87 
88 /* Firmware interface */
89 #define	BGE_FW_DRV_ALIVE		0x00000001
90 #define	BGE_FW_PAUSE			0x00000002
91 
92 /* Mappings for internal memory configuration */
93 #define	BGE_STD_RX_RINGS		0x00006000
94 #define	BGE_STD_RX_RINGS_END		0x00006FFF
95 #define	BGE_JUMBO_RX_RINGS		0x00007000
96 #define	BGE_JUMBO_RX_RINGS_END		0x00007FFF
97 #define	BGE_BUFFPOOL_1			0x00008000
98 #define	BGE_BUFFPOOL_1_END		0x0000FFFF
99 #define	BGE_BUFFPOOL_2			0x00010000 /* or expansion ROM */
100 #define	BGE_BUFFPOOL_2_END		0x00017FFF
101 #define	BGE_BUFFPOOL_3			0x00018000 /* or expansion ROM */
102 #define	BGE_BUFFPOOL_3_END		0x0001FFFF
103 
104 /* Mappings for external SSRAM configurations */
105 #define	BGE_SEND_RING_5_TO_6		0x00006000
106 #define	BGE_SEND_RING_5_TO_6_END	0x00006FFF
107 #define	BGE_SEND_RING_7_TO_8		0x00007000
108 #define	BGE_SEND_RING_7_TO_8_END	0x00007FFF
109 #define	BGE_SEND_RING_9_TO_16		0x00008000
110 #define	BGE_SEND_RING_9_TO_16_END	0x0000BFFF
111 #define	BGE_EXT_STD_RX_RINGS		0x0000C000
112 #define	BGE_EXT_STD_RX_RINGS_END	0x0000CFFF
113 #define	BGE_EXT_JUMBO_RX_RINGS		0x0000D000
114 #define	BGE_EXT_JUMBO_RX_RINGS_END	0x0000DFFF
115 #define	BGE_MINI_RX_RINGS		0x0000E000
116 #define	BGE_MINI_RX_RINGS_END		0x0000FFFF
117 #define	BGE_AVAIL_REGION1		0x00010000 /* or expansion ROM */
118 #define	BGE_AVAIL_REGION1_END		0x00017FFF
119 #define	BGE_AVAIL_REGION2		0x00018000 /* or expansion ROM */
120 #define	BGE_AVAIL_REGION2_END		0x0001FFFF
121 #define	BGE_EXT_SSRAM			0x00020000
122 #define	BGE_EXT_SSRAM_END		0x000FFFFF
123 
124 
125 /*
126  * BCM570x register offsets. These are memory mapped registers
127  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
128  * Each register must be accessed using 32 bit operations.
129  *
130  * All registers are accessed through a 32K shared memory block.
131  * The first group of registers are actually copies of the PCI
132  * configuration space registers.
133  */
134 
135 /*
136  * PCI registers defined in the PCI 2.2 spec.
137  */
138 #define	BGE_PCI_VID			0x00
139 #define	BGE_PCI_DID			0x02
140 #define	BGE_PCI_CMD			0x04
141 #define	BGE_PCI_STS			0x06
142 #define	BGE_PCI_REV			0x08
143 #define	BGE_PCI_CLASS			0x09
144 #define	BGE_PCI_CACHESZ			0x0C
145 #define	BGE_PCI_LATTIMER		0x0D
146 #define	BGE_PCI_HDRTYPE			0x0E
147 #define	BGE_PCI_BIST			0x0F
148 #define	BGE_PCI_BAR0			0x10
149 #define	BGE_PCI_BAR1			0x14
150 #define	BGE_PCI_SUBSYS			0x2C
151 #define	BGE_PCI_SUBVID			0x2E
152 #define	BGE_PCI_ROMBASE			0x30
153 #define	BGE_PCI_CAPPTR			0x34
154 #define	BGE_PCI_INTLINE			0x3C
155 #define	BGE_PCI_INTPIN			0x3D
156 #define	BGE_PCI_MINGNT			0x3E
157 #define	BGE_PCI_MAXLAT			0x3F
158 #define	BGE_PCI_PCIXCAP			0x40
159 #define	BGE_PCI_NEXTPTR_PM		0x41
160 #define	BGE_PCI_PCIX_CMD		0x42
161 #define	BGE_PCI_PCIX_STS		0x44
162 #define	BGE_PCI_PWRMGMT_CAPID		0x48
163 #define	BGE_PCI_NEXTPTR_VPD		0x49
164 #define	BGE_PCI_PWRMGMT_CAPS		0x4A
165 #define	BGE_PCI_PWRMGMT_CMD		0x4C
166 #define	BGE_PCI_PWRMGMT_STS		0x4D
167 #define	BGE_PCI_PWRMGMT_DATA		0x4F
168 #define	BGE_PCI_VPD_CAPID		0x50
169 #define	BGE_PCI_NEXTPTR_MSI		0x51
170 #define	BGE_PCI_VPD_ADDR		0x52
171 #define	BGE_PCI_VPD_DATA		0x54
172 #define	BGE_PCI_MSI_CAPID		0x58
173 #define	BGE_PCI_NEXTPTR_NONE		0x59
174 #define	BGE_PCI_MSI_CTL			0x5A
175 #define	BGE_PCI_MSI_ADDR_HI		0x5C
176 #define	BGE_PCI_MSI_ADDR_LO		0x60
177 #define	BGE_PCI_MSI_DATA		0x64
178 
179 /* PCI MSI. ??? */
180 #define	BGE_PCIE_CAPID_REG		0xD0
181 #define	BGE_PCIE_CAPID			0x10
182 
183 /*
184  * PCI registers specific to the BCM570x family.
185  */
186 #define	BGE_PCI_MISC_CTL		0x68
187 #define	BGE_PCI_DMA_RW_CTL		0x6C
188 #define	BGE_PCI_PCISTATE		0x70
189 #define	BGE_PCI_CLKCTL			0x74
190 #define	BGE_PCI_REG_BASEADDR		0x78
191 #define	BGE_PCI_MEMWIN_BASEADDR		0x7C
192 #define	BGE_PCI_REG_DATA		0x80
193 #define	BGE_PCI_MEMWIN_DATA		0x84
194 #define	BGE_PCI_MODECTL			0x88
195 #define	BGE_PCI_MISC_CFG		0x8C
196 #define	BGE_PCI_MISC_LOCALCTL		0x90
197 #define	BGE_PCI_UNDI_RX_STD_PRODIDX_HI	0x98
198 #define	BGE_PCI_UNDI_RX_STD_PRODIDX_LO	0x9C
199 #define	BGE_PCI_UNDI_RX_RTN_CONSIDX_HI	0xA0
200 #define	BGE_PCI_UNDI_RX_RTN_CONSIDX_LO	0xA4
201 #define	BGE_PCI_UNDI_TX_BD_PRODIDX_HI	0xA8
202 #define	BGE_PCI_UNDI_TX_BD_PRODIDX_LO	0xAC
203 #define	BGE_PCI_ISR_MBX_HI		0xB0
204 #define	BGE_PCI_ISR_MBX_LO		0xB4
205 
206 /* PCI Misc. Host control register */
207 #define	BGE_PCIMISCCTL_CLEAR_INTA	0x00000001
208 #define	BGE_PCIMISCCTL_MASK_PCI_INTR	0x00000002
209 #define	BGE_PCIMISCCTL_ENDIAN_BYTESWAP	0x00000004
210 #define	BGE_PCIMISCCTL_ENDIAN_WORDSWAP	0x00000008
211 #define	BGE_PCIMISCCTL_PCISTATE_RW	0x00000010
212 #define	BGE_PCIMISCCTL_CLOCKCTL_RW	0x00000020
213 #define	BGE_PCIMISCCTL_REG_WORDSWAP	0x00000040
214 #define	BGE_PCIMISCCTL_INDIRECT_ACCESS	0x00000080
215 #define	BGE_PCIMISCCTL_ASICREV		0xFFFF0000
216 
217 #define	BGE_HIF_SWAP_OPTIONS	(BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
218 #if BYTE_ORDER == LITTLE_ENDIAN
219 #define	BGE_DMA_SWAP_OPTIONS \
220 	BGE_MODECTL_WORDSWAP_NONFRAME| \
221 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
222 #else
223 #define	BGE_DMA_SWAP_OPTIONS \
224 	BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
225 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
226 #endif
227 
228 #define	BGE_INIT \
229 	(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
230 	 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
231 
232 #define	BGE_CHIPID_TIGON_I		0x40000000
233 #define	BGE_CHIPID_TIGON_II		0x60000000
234 #define	BGE_CHIPID_BCM5700_A0		0x70000000
235 #define	BGE_CHIPID_BCM5700_A1		0x70010000
236 #define	BGE_CHIPID_BCM5700_B0		0x71000000
237 #define	BGE_CHIPID_BCM5700_B1		0x71010000
238 #define	BGE_CHIPID_BCM5700_B2		0x71020000
239 #define	BGE_CHIPID_BCM5700_B3		0x71030000
240 #define	BGE_CHIPID_BCM5700_ALTIMA	0x71040000
241 #define	BGE_CHIPID_BCM5700_C0		0x72000000
242 #define	BGE_CHIPID_BCM5701_A0		0x00000000	/* grrrr */
243 #define	BGE_CHIPID_BCM5701_B0		0x01000000
244 #define	BGE_CHIPID_BCM5701_B2		0x01020000
245 #define	BGE_CHIPID_BCM5701_B5		0x01050000
246 #define	BGE_CHIPID_BCM5703_A0		0x10000000
247 #define	BGE_CHIPID_BCM5703_A1		0x10010000
248 #define	BGE_CHIPID_BCM5703_A2		0x10020000
249 #define	BGE_CHIPID_BCM5703_A3		0x10030000
250 #define	BGE_CHIPID_BCM5703_B0		0x11000000
251 #define	BGE_CHIPID_BCM5704_A0		0x20000000
252 #define	BGE_CHIPID_BCM5704_A1		0x20010000
253 #define	BGE_CHIPID_BCM5704_A2		0x20020000
254 #define	BGE_CHIPID_BCM5704_A3		0x20030000
255 #define	BGE_CHIPID_BCM5704_B0		0x21000000
256 #define	BGE_CHIPID_BCM5705_A0		0x30000000
257 #define	BGE_CHIPID_BCM5705_A1		0x30010000
258 #define	BGE_CHIPID_BCM5705_A2		0x30020000
259 #define	BGE_CHIPID_BCM5705_A3		0x30030000
260 #define	BGE_CHIPID_BCM5750_A0		0x40000000
261 #define	BGE_CHIPID_BCM5750_A1		0x40010000
262 #define	BGE_CHIPID_BCM5750_A3		0x40030000
263 #define	BGE_CHIPID_BCM5750_B0		0x41000000
264 #define	BGE_CHIPID_BCM5750_B1		0x41010000
265 #define	BGE_CHIPID_BCM5750_C0		0x42000000
266 #define	BGE_CHIPID_BCM5750_C1		0x42010000
267 #define	BGE_CHIPID_BCM5750_C2		0x42020000
268 #define	BGE_CHIPID_BCM5714_A0		0x50000000
269 #define	BGE_CHIPID_BCM5752_A0		0x60000000
270 #define	BGE_CHIPID_BCM5752_A1		0x60010000
271 #define	BGE_CHIPID_BCM5752_A2		0x60020000
272 #define	BGE_CHIPID_BCM5714_B0		0x80000000
273 #define	BGE_CHIPID_BCM5714_B3		0x80030000
274 #define	BGE_CHIPID_BCM5715_A0		0x90000000
275 #define	BGE_CHIPID_BCM5715_A1		0x90010000
276 #define	BGE_CHIPID_BCM5715_A3		0x90030000
277 #define	BGE_CHIPID_BCM5755_A0		0xa0000000
278 #define	BGE_CHIPID_BCM5755_A1		0xa0010000
279 #define	BGE_CHIPID_BCM5755_A2		0xa0020000
280 #define	BGE_CHIPID_BCM5754_A0		0xb0000000
281 #define	BGE_CHIPID_BCM5754_A1		0xb0010000
282 #define	BGE_CHIPID_BCM5754_A2		0xb0020000
283 #define	BGE_CHIPID_BCM5787_A0		0xb0000000
284 #define	BGE_CHIPID_BCM5787_A1		0xb0010000
285 #define	BGE_CHIPID_BCM5787_A2		0xb0020000
286 
287 /* shorthand one */
288 #define	BGE_ASICREV(x)			((x) >> 28)
289 #define	BGE_ASICREV_BCM5701		0x00
290 #define	BGE_ASICREV_BCM5703		0x01
291 #define	BGE_ASICREV_BCM5704		0x02
292 #define	BGE_ASICREV_BCM5705		0x03
293 #define	BGE_ASICREV_BCM5750		0x04
294 #define	BGE_ASICREV_BCM5714_A0		0x05
295 #define	BGE_ASICREV_BCM5752		0x06
296 #define	BGE_ASICREV_BCM5700		0x07
297 #define	BGE_ASICREV_BCM5780		0x08
298 #define	BGE_ASICREV_BCM5714		0x09
299 #define	BGE_ASICREV_BCM5755		0x0a
300 #define	BGE_ASICREV_BCM5754		0x0b
301 #define	BGE_ASICREV_BCM5787		0x0b
302 
303 /* chip revisions */
304 #define	BGE_CHIPREV(x)			((x) >> 24)
305 #define	BGE_CHIPREV_5700_AX		0x70
306 #define	BGE_CHIPREV_5700_BX		0x71
307 #define	BGE_CHIPREV_5700_CX		0x72
308 #define	BGE_CHIPREV_5701_AX		0x00
309 #define	BGE_CHIPREV_5703_AX		0x10
310 #define	BGE_CHIPREV_5704_AX		0x20
311 #define	BGE_CHIPREV_5704_BX		0x21
312 #define	BGE_CHIPREV_5750_AX		0x40
313 #define	BGE_CHIPREV_5750_BX		0x41
314 
315 /* PCI DMA Read/Write Control register */
316 #define	BGE_PCIDMARWCTL_MINDMA		0x000000FF
317 #define	BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
318 #define	BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
319 #define	BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x00004000
320 #define	BGE_PCIDMARWCTL_RD_WAT		0x00070000
321 #define	BGE_PCIDMARWCTL_WR_WAT		0x00380000
322 #define	BGE_PCIDMARWCTL_USE_MRM		0x00400000
323 #define	BGE_PCIDMARWCTL_ASRT_ALL_BE	0x00800000
324 #define	BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD	0x0F000000
325 #define	BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD	0xF0000000
326 
327 #define	BGE_PCIDMARWCTL_RD_WAT_SHIFT(x)	((x) << 16)
328 #define	BGE_PCIDMARWCTL_WR_WAT_SHIFT(x)	((x) << 19)
329 #define	BGE_PCIDMARWCTL_RD_CMD_SHIFT(x)	((x) << 24)
330 #define	BGE_PCIDMARWCTL_WR_CMD_SHIFT(x)	((x) << 28)
331 
332 #define	BGE_PCI_READ_BNDRY_DISABLE	0x00000000
333 #define	BGE_PCI_READ_BNDRY_16BYTES	0x00000100
334 #define	BGE_PCI_READ_BNDRY_32BYTES	0x00000200
335 #define	BGE_PCI_READ_BNDRY_64BYTES	0x00000300
336 #define	BGE_PCI_READ_BNDRY_128BYTES	0x00000400
337 #define	BGE_PCI_READ_BNDRY_256BYTES	0x00000500
338 #define	BGE_PCI_READ_BNDRY_512BYTES	0x00000600
339 #define	BGE_PCI_READ_BNDRY_1024BYTES	0x00000700
340 
341 #define	BGE_PCI_WRITE_BNDRY_DISABLE	0x00000000
342 #define	BGE_PCI_WRITE_BNDRY_16BYTES	0x00000800
343 #define	BGE_PCI_WRITE_BNDRY_32BYTES	0x00001000
344 #define	BGE_PCI_WRITE_BNDRY_64BYTES	0x00001800
345 #define	BGE_PCI_WRITE_BNDRY_128BYTES	0x00002000
346 #define	BGE_PCI_WRITE_BNDRY_256BYTES	0x00002800
347 #define	BGE_PCI_WRITE_BNDRY_512BYTES	0x00003000
348 #define	BGE_PCI_WRITE_BNDRY_1024BYTES	0x00003800
349 
350 /*
351  * PCI state register -- note, this register is read only
352  * unless the PCISTATE_WR bit of the PCI Misc. Host Control
353  * register is set.
354  */
355 #define	BGE_PCISTATE_FORCE_RESET	0x00000001
356 #define	BGE_PCISTATE_INTR_STATE		0x00000002
357 #define	BGE_PCISTATE_PCI_BUSMODE	0x00000004 /* 1 = PCI, 0 = PCI-X */
358 #define	BGE_PCISTATE_PCI_BUSSPEED	0x00000008 /* 1 = 66/133, 0 = 33/66 */
359 #define	BGE_PCISTATE_32BIT_BUS		0x00000010 /* 1 = 32bit, 0 = 64bit */
360 #define	BGE_PCISTATE_WANT_EXPROM	0x00000020
361 #define	BGE_PCISTATE_EXPROM_RETRY	0x00000040
362 #define	BGE_PCISTATE_FLATVIEW_MODE	0x00000100
363 #define	BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
364 
365 /*
366  * PCI Clock Control register -- note, this register is read only
367  * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
368  * register is set.
369  */
370 #define	BGE_PCICLOCKCTL_DETECTED_SPEED	0x0000000F
371 #define	BGE_PCICLOCKCTL_M66EN		0x00000080
372 #define	BGE_PCICLOCKCTL_LOWPWR_CLKMODE	0x00000200
373 #define	BGE_PCICLOCKCTL_RXCPU_CLK_DIS	0x00000400
374 #define	BGE_PCICLOCKCTL_TXCPU_CLK_DIS	0x00000800
375 #define	BGE_PCICLOCKCTL_ALTCLK		0x00001000
376 #define	BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
377 #define	BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
378 #define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000
379 #define	BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
380 
381 
382 #ifndef PCIM_CMD_MWIEN
383 #define	PCIM_CMD_MWIEN			0x0010
384 #endif
385 
386 /*
387  * High priority mailbox registers
388  * Each mailbox is 64-bits wide, though we only use the
389  * lower 32 bits. To write a 64-bit value, write the upper 32 bits
390  * first. The NIC will load the mailbox after the lower 32 bit word
391  * has been updated.
392  */
393 #define	BGE_MBX_IRQ0_HI			0x0200
394 #define	BGE_MBX_IRQ0_LO			0x0204
395 #define	BGE_MBX_IRQ1_HI			0x0208
396 #define	BGE_MBX_IRQ1_LO			0x020C
397 #define	BGE_MBX_IRQ2_HI			0x0210
398 #define	BGE_MBX_IRQ2_LO			0x0214
399 #define	BGE_MBX_IRQ3_HI			0x0218
400 #define	BGE_MBX_IRQ3_LO			0x021C
401 #define	BGE_MBX_GEN0_HI			0x0220
402 #define	BGE_MBX_GEN0_LO			0x0224
403 #define	BGE_MBX_GEN1_HI			0x0228
404 #define	BGE_MBX_GEN1_LO			0x022C
405 #define	BGE_MBX_GEN2_HI			0x0230
406 #define	BGE_MBX_GEN2_LO			0x0234
407 #define	BGE_MBX_GEN3_HI			0x0228
408 #define	BGE_MBX_GEN3_LO			0x022C
409 #define	BGE_MBX_GEN4_HI			0x0240
410 #define	BGE_MBX_GEN4_LO			0x0244
411 #define	BGE_MBX_GEN5_HI			0x0248
412 #define	BGE_MBX_GEN5_LO			0x024C
413 #define	BGE_MBX_GEN6_HI			0x0250
414 #define	BGE_MBX_GEN6_LO			0x0254
415 #define	BGE_MBX_GEN7_HI			0x0258
416 #define	BGE_MBX_GEN7_LO			0x025C
417 #define	BGE_MBX_RELOAD_STATS_HI		0x0260
418 #define	BGE_MBX_RELOAD_STATS_LO		0x0264
419 #define	BGE_MBX_RX_STD_PROD_HI		0x0268
420 #define	BGE_MBX_RX_STD_PROD_LO		0x026C
421 #define	BGE_MBX_RX_JUMBO_PROD_HI	0x0270
422 #define	BGE_MBX_RX_JUMBO_PROD_LO	0x0274
423 #define	BGE_MBX_RX_MINI_PROD_HI		0x0278
424 #define	BGE_MBX_RX_MINI_PROD_LO		0x027C
425 #define	BGE_MBX_RX_CONS0_HI		0x0280
426 #define	BGE_MBX_RX_CONS0_LO		0x0284
427 #define	BGE_MBX_RX_CONS1_HI		0x0288
428 #define	BGE_MBX_RX_CONS1_LO		0x028C
429 #define	BGE_MBX_RX_CONS2_HI		0x0290
430 #define	BGE_MBX_RX_CONS2_LO		0x0294
431 #define	BGE_MBX_RX_CONS3_HI		0x0298
432 #define	BGE_MBX_RX_CONS3_LO		0x029C
433 #define	BGE_MBX_RX_CONS4_HI		0x02A0
434 #define	BGE_MBX_RX_CONS4_LO		0x02A4
435 #define	BGE_MBX_RX_CONS5_HI		0x02A8
436 #define	BGE_MBX_RX_CONS5_LO		0x02AC
437 #define	BGE_MBX_RX_CONS6_HI		0x02B0
438 #define	BGE_MBX_RX_CONS6_LO		0x02B4
439 #define	BGE_MBX_RX_CONS7_HI		0x02B8
440 #define	BGE_MBX_RX_CONS7_LO		0x02BC
441 #define	BGE_MBX_RX_CONS8_HI		0x02C0
442 #define	BGE_MBX_RX_CONS8_LO		0x02C4
443 #define	BGE_MBX_RX_CONS9_HI		0x02C8
444 #define	BGE_MBX_RX_CONS9_LO		0x02CC
445 #define	BGE_MBX_RX_CONS10_HI		0x02D0
446 #define	BGE_MBX_RX_CONS10_LO		0x02D4
447 #define	BGE_MBX_RX_CONS11_HI		0x02D8
448 #define	BGE_MBX_RX_CONS11_LO		0x02DC
449 #define	BGE_MBX_RX_CONS12_HI		0x02E0
450 #define	BGE_MBX_RX_CONS12_LO		0x02E4
451 #define	BGE_MBX_RX_CONS13_HI		0x02E8
452 #define	BGE_MBX_RX_CONS13_LO		0x02EC
453 #define	BGE_MBX_RX_CONS14_HI		0x02F0
454 #define	BGE_MBX_RX_CONS14_LO		0x02F4
455 #define	BGE_MBX_RX_CONS15_HI		0x02F8
456 #define	BGE_MBX_RX_CONS15_LO		0x02FC
457 #define	BGE_MBX_TX_HOST_PROD0_HI	0x0300
458 #define	BGE_MBX_TX_HOST_PROD0_LO	0x0304
459 #define	BGE_MBX_TX_HOST_PROD1_HI	0x0308
460 #define	BGE_MBX_TX_HOST_PROD1_LO	0x030C
461 #define	BGE_MBX_TX_HOST_PROD2_HI	0x0310
462 #define	BGE_MBX_TX_HOST_PROD2_LO	0x0314
463 #define	BGE_MBX_TX_HOST_PROD3_HI	0x0318
464 #define	BGE_MBX_TX_HOST_PROD3_LO	0x031C
465 #define	BGE_MBX_TX_HOST_PROD4_HI	0x0320
466 #define	BGE_MBX_TX_HOST_PROD4_LO	0x0324
467 #define	BGE_MBX_TX_HOST_PROD5_HI	0x0328
468 #define	BGE_MBX_TX_HOST_PROD5_LO	0x032C
469 #define	BGE_MBX_TX_HOST_PROD6_HI	0x0330
470 #define	BGE_MBX_TX_HOST_PROD6_LO	0x0334
471 #define	BGE_MBX_TX_HOST_PROD7_HI	0x0338
472 #define	BGE_MBX_TX_HOST_PROD7_LO	0x033C
473 #define	BGE_MBX_TX_HOST_PROD8_HI	0x0340
474 #define	BGE_MBX_TX_HOST_PROD8_LO	0x0344
475 #define	BGE_MBX_TX_HOST_PROD9_HI	0x0348
476 #define	BGE_MBX_TX_HOST_PROD9_LO	0x034C
477 #define	BGE_MBX_TX_HOST_PROD10_HI	0x0350
478 #define	BGE_MBX_TX_HOST_PROD10_LO	0x0354
479 #define	BGE_MBX_TX_HOST_PROD11_HI	0x0358
480 #define	BGE_MBX_TX_HOST_PROD11_LO	0x035C
481 #define	BGE_MBX_TX_HOST_PROD12_HI	0x0360
482 #define	BGE_MBX_TX_HOST_PROD12_LO	0x0364
483 #define	BGE_MBX_TX_HOST_PROD13_HI	0x0368
484 #define	BGE_MBX_TX_HOST_PROD13_LO	0x036C
485 #define	BGE_MBX_TX_HOST_PROD14_HI	0x0370
486 #define	BGE_MBX_TX_HOST_PROD14_LO	0x0374
487 #define	BGE_MBX_TX_HOST_PROD15_HI	0x0378
488 #define	BGE_MBX_TX_HOST_PROD15_LO	0x037C
489 #define	BGE_MBX_TX_NIC_PROD0_HI		0x0380
490 #define	BGE_MBX_TX_NIC_PROD0_LO		0x0384
491 #define	BGE_MBX_TX_NIC_PROD1_HI		0x0388
492 #define	BGE_MBX_TX_NIC_PROD1_LO		0x038C
493 #define	BGE_MBX_TX_NIC_PROD2_HI		0x0390
494 #define	BGE_MBX_TX_NIC_PROD2_LO		0x0394
495 #define	BGE_MBX_TX_NIC_PROD3_HI		0x0398
496 #define	BGE_MBX_TX_NIC_PROD3_LO		0x039C
497 #define	BGE_MBX_TX_NIC_PROD4_HI		0x03A0
498 #define	BGE_MBX_TX_NIC_PROD4_LO		0x03A4
499 #define	BGE_MBX_TX_NIC_PROD5_HI		0x03A8
500 #define	BGE_MBX_TX_NIC_PROD5_LO		0x03AC
501 #define	BGE_MBX_TX_NIC_PROD6_HI		0x03B0
502 #define	BGE_MBX_TX_NIC_PROD6_LO		0x03B4
503 #define	BGE_MBX_TX_NIC_PROD7_HI		0x03B8
504 #define	BGE_MBX_TX_NIC_PROD7_LO		0x03BC
505 #define	BGE_MBX_TX_NIC_PROD8_HI		0x03C0
506 #define	BGE_MBX_TX_NIC_PROD8_LO		0x03C4
507 #define	BGE_MBX_TX_NIC_PROD9_HI		0x03C8
508 #define	BGE_MBX_TX_NIC_PROD9_LO		0x03CC
509 #define	BGE_MBX_TX_NIC_PROD10_HI	0x03D0
510 #define	BGE_MBX_TX_NIC_PROD10_LO	0x03D4
511 #define	BGE_MBX_TX_NIC_PROD11_HI	0x03D8
512 #define	BGE_MBX_TX_NIC_PROD11_LO	0x03DC
513 #define	BGE_MBX_TX_NIC_PROD12_HI	0x03E0
514 #define	BGE_MBX_TX_NIC_PROD12_LO	0x03E4
515 #define	BGE_MBX_TX_NIC_PROD13_HI	0x03E8
516 #define	BGE_MBX_TX_NIC_PROD13_LO	0x03EC
517 #define	BGE_MBX_TX_NIC_PROD14_HI	0x03F0
518 #define	BGE_MBX_TX_NIC_PROD14_LO	0x03F4
519 #define	BGE_MBX_TX_NIC_PROD15_HI	0x03F8
520 #define	BGE_MBX_TX_NIC_PROD15_LO	0x03FC
521 
522 #define	BGE_TX_RINGS_MAX		4
523 #define	BGE_TX_RINGS_EXTSSRAM_MAX	16
524 #define	BGE_RX_RINGS_MAX		16
525 
526 /* Ethernet MAC control registers */
527 #define	BGE_MAC_MODE			0x0400
528 #define	BGE_MAC_STS			0x0404
529 #define	BGE_MAC_EVT_ENB			0x0408
530 #define	BGE_MAC_LED_CTL			0x040C
531 #define	BGE_MAC_ADDR1_LO		0x0410
532 #define	BGE_MAC_ADDR1_HI		0x0414
533 #define	BGE_MAC_ADDR2_LO		0x0418
534 #define	BGE_MAC_ADDR2_HI		0x041C
535 #define	BGE_MAC_ADDR3_LO		0x0420
536 #define	BGE_MAC_ADDR3_HI		0x0424
537 #define	BGE_MAC_ADDR4_LO		0x0428
538 #define	BGE_MAC_ADDR4_HI		0x042C
539 #define	BGE_WOL_PATPTR			0x0430
540 #define	BGE_WOL_PATCFG			0x0434
541 #define	BGE_TX_RANDOM_BACKOFF		0x0438
542 #define	BGE_RX_MTU			0x043C
543 #define	BGE_GBIT_PCS_TEST		0x0440
544 #define	BGE_TX_TBI_AUTONEG		0x0444
545 #define	BGE_RX_TBI_AUTONEG		0x0448
546 #define	BGE_MI_COMM			0x044C
547 #define	BGE_MI_STS			0x0450
548 #define	BGE_MI_MODE			0x0454
549 #define	BGE_AUTOPOLL_STS		0x0458
550 #define	BGE_TX_MODE			0x045C
551 #define	BGE_TX_STS			0x0460
552 #define	BGE_TX_LENGTHS			0x0464
553 #define	BGE_RX_MODE			0x0468
554 #define	BGE_RX_STS			0x046C
555 #define	BGE_MAR0			0x0470
556 #define	BGE_MAR1			0x0474
557 #define	BGE_MAR2			0x0478
558 #define	BGE_MAR3			0x047C
559 #define	BGE_RX_BD_RULES_CTL0		0x0480
560 #define	BGE_RX_BD_RULES_MASKVAL0	0x0484
561 #define	BGE_RX_BD_RULES_CTL1		0x0488
562 #define	BGE_RX_BD_RULES_MASKVAL1	0x048C
563 #define	BGE_RX_BD_RULES_CTL2		0x0490
564 #define	BGE_RX_BD_RULES_MASKVAL2	0x0494
565 #define	BGE_RX_BD_RULES_CTL3		0x0498
566 #define	BGE_RX_BD_RULES_MASKVAL3	0x049C
567 #define	BGE_RX_BD_RULES_CTL4		0x04A0
568 #define	BGE_RX_BD_RULES_MASKVAL4	0x04A4
569 #define	BGE_RX_BD_RULES_CTL5		0x04A8
570 #define	BGE_RX_BD_RULES_MASKVAL5	0x04AC
571 #define	BGE_RX_BD_RULES_CTL6		0x04B0
572 #define	BGE_RX_BD_RULES_MASKVAL6	0x04B4
573 #define	BGE_RX_BD_RULES_CTL7		0x04B8
574 #define	BGE_RX_BD_RULES_MASKVAL7	0x04BC
575 #define	BGE_RX_BD_RULES_CTL8		0x04C0
576 #define	BGE_RX_BD_RULES_MASKVAL8	0x04C4
577 #define	BGE_RX_BD_RULES_CTL9		0x04C8
578 #define	BGE_RX_BD_RULES_MASKVAL9	0x04CC
579 #define	BGE_RX_BD_RULES_CTL10		0x04D0
580 #define	BGE_RX_BD_RULES_MASKVAL10	0x04D4
581 #define	BGE_RX_BD_RULES_CTL11		0x04D8
582 #define	BGE_RX_BD_RULES_MASKVAL11	0x04DC
583 #define	BGE_RX_BD_RULES_CTL12		0x04E0
584 #define	BGE_RX_BD_RULES_MASKVAL12	0x04E4
585 #define	BGE_RX_BD_RULES_CTL13		0x04E8
586 #define	BGE_RX_BD_RULES_MASKVAL13	0x04EC
587 #define	BGE_RX_BD_RULES_CTL14		0x04F0
588 #define	BGE_RX_BD_RULES_MASKVAL14	0x04F4
589 #define	BGE_RX_BD_RULES_CTL15		0x04F8
590 #define	BGE_RX_BD_RULES_MASKVAL15	0x04FC
591 #define	BGE_RX_RULES_CFG		0x0500
592 #define	BGE_SERDES_CFG			0x0590
593 #define	BGE_SERDES_STS			0x0594
594 #define	BGE_SGDIG_CFG			0x05B0
595 #define	BGE_SGDIG_STS			0x05B4
596 #define	BGE_MAC_STATS			0x0800
597 
598 /* Ethernet MAC Mode register */
599 #define	BGE_MACMODE_RESET		0x00000001
600 #define	BGE_MACMODE_HALF_DUPLEX		0x00000002
601 #define	BGE_MACMODE_PORTMODE		0x0000000C
602 #define	BGE_MACMODE_LOOPBACK		0x00000010
603 #define	BGE_MACMODE_RX_TAGGEDPKT	0x00000080
604 #define	BGE_MACMODE_TX_BURST_ENB	0x00000100
605 #define	BGE_MACMODE_MAX_DEFER		0x00000200
606 #define	BGE_MACMODE_LINK_POLARITY	0x00000400
607 #define	BGE_MACMODE_RX_STATS_ENB	0x00000800
608 #define	BGE_MACMODE_RX_STATS_CLEAR	0x00001000
609 #define	BGE_MACMODE_RX_STATS_FLUSH	0x00002000
610 #define	BGE_MACMODE_TX_STATS_ENB	0x00004000
611 #define	BGE_MACMODE_TX_STATS_CLEAR	0x00008000
612 #define	BGE_MACMODE_TX_STATS_FLUSH	0x00010000
613 #define	BGE_MACMODE_TBI_SEND_CFGS	0x00020000
614 #define	BGE_MACMODE_MAGIC_PKT_ENB	0x00040000
615 #define	BGE_MACMODE_ACPI_PWRON_ENB	0x00080000
616 #define	BGE_MACMODE_MIP_ENB		0x00100000
617 #define	BGE_MACMODE_TXDMA_ENB		0x00200000
618 #define	BGE_MACMODE_RXDMA_ENB		0x00400000
619 #define	BGE_MACMODE_FRMHDR_DMA_ENB	0x00800000
620 
621 #define	BGE_PORTMODE_NONE		0x00000000
622 #define	BGE_PORTMODE_MII		0x00000004
623 #define	BGE_PORTMODE_GMII		0x00000008
624 #define	BGE_PORTMODE_TBI		0x0000000C
625 
626 /* MAC Status register */
627 #define	BGE_MACSTAT_TBI_PCS_SYNCHED	0x00000001
628 #define	BGE_MACSTAT_TBI_SIGNAL_DETECT	0x00000002
629 #define	BGE_MACSTAT_RX_CFG		0x00000004
630 #define	BGE_MACSTAT_CFG_CHANGED		0x00000008
631 #define	BGE_MACSTAT_SYNC_CHANGED	0x00000010
632 #define	BGE_MACSTAT_PORT_DECODE_ERROR	0x00000400
633 #define	BGE_MACSTAT_LINK_CHANGED	0x00001000
634 #define	BGE_MACSTAT_MI_COMPLETE		0x00400000
635 #define	BGE_MACSTAT_MI_INTERRUPT	0x00800000
636 #define	BGE_MACSTAT_AUTOPOLL_ERROR	0x01000000
637 #define	BGE_MACSTAT_ODI_ERROR		0x02000000
638 #define	BGE_MACSTAT_RXSTAT_OFLOW	0x04000000
639 #define	BGE_MACSTAT_TXSTAT_OFLOW	0x08000000
640 
641 /* MAC Event Enable Register */
642 #define	BGE_EVTENB_PORT_DECODE_ERROR	0x00000400
643 #define	BGE_EVTENB_LINK_CHANGED		0x00001000
644 #define	BGE_EVTENB_MI_COMPLETE		0x00400000
645 #define	BGE_EVTENB_MI_INTERRUPT		0x00800000
646 #define	BGE_EVTENB_AUTOPOLL_ERROR	0x01000000
647 #define	BGE_EVTENB_ODI_ERROR		0x02000000
648 #define	BGE_EVTENB_RXSTAT_OFLOW		0x04000000
649 #define	BGE_EVTENB_TXSTAT_OFLOW		0x08000000
650 
651 /* LED Control Register */
652 #define	BGE_LEDCTL_LINKLED_OVERRIDE	0x00000001
653 #define	BGE_LEDCTL_1000MBPS_LED		0x00000002
654 #define	BGE_LEDCTL_100MBPS_LED		0x00000004
655 #define	BGE_LEDCTL_10MBPS_LED		0x00000008
656 #define	BGE_LEDCTL_TRAFLED_OVERRIDE	0x00000010
657 #define	BGE_LEDCTL_TRAFLED_BLINK	0x00000020
658 #define	BGE_LEDCTL_TREFLED_BLINK_2	0x00000040
659 #define	BGE_LEDCTL_1000MBPS_STS		0x00000080
660 #define	BGE_LEDCTL_100MBPS_STS		0x00000100
661 #define	BGE_LEDCTL_10MBPS_STS		0x00000200
662 #define	BGE_LEDCTL_TRADLED_STS		0x00000400
663 #define	BGE_LEDCTL_BLINKPERIOD		0x7FF80000
664 #define	BGE_LEDCTL_BLINKPERIOD_OVERRIDE	0x80000000
665 
666 /* TX backoff seed register */
667 #define	BGE_TX_BACKOFF_SEED_MASK	0x3F
668 
669 /* Autopoll status register */
670 #define	BGE_AUTOPOLLSTS_ERROR		0x00000001
671 
672 /* Transmit MAC mode register */
673 #define	BGE_TXMODE_RESET		0x00000001
674 #define	BGE_TXMODE_ENABLE		0x00000002
675 #define	BGE_TXMODE_FLOWCTL_ENABLE	0x00000010
676 #define	BGE_TXMODE_BIGBACKOFF_ENABLE	0x00000020
677 #define	BGE_TXMODE_LONGPAUSE_ENABLE	0x00000040
678 
679 /* Transmit MAC status register */
680 #define	BGE_TXSTAT_RX_XOFFED		0x00000001
681 #define	BGE_TXSTAT_SENT_XOFF		0x00000002
682 #define	BGE_TXSTAT_SENT_XON		0x00000004
683 #define	BGE_TXSTAT_LINK_UP		0x00000008
684 #define	BGE_TXSTAT_ODI_UFLOW		0x00000010
685 #define	BGE_TXSTAT_ODI_OFLOW		0x00000020
686 
687 /* Transmit MAC lengths register */
688 #define	BGE_TXLEN_SLOTTIME		0x000000FF
689 #define	BGE_TXLEN_IPG			0x00000F00
690 #define	BGE_TXLEN_CRS			0x00003000
691 
692 /* Receive MAC mode register */
693 #define	BGE_RXMODE_RESET		0x00000001
694 #define	BGE_RXMODE_ENABLE		0x00000002
695 #define	BGE_RXMODE_FLOWCTL_ENABLE	0x00000004
696 #define	BGE_RXMODE_RX_GIANTS		0x00000020
697 #define	BGE_RXMODE_RX_RUNTS		0x00000040
698 #define	BGE_RXMODE_8022_LENCHECK	0x00000080
699 #define	BGE_RXMODE_RX_PROMISC		0x00000100
700 #define	BGE_RXMODE_RX_NO_CRC_CHECK	0x00000200
701 #define	BGE_RXMODE_RX_KEEP_VLAN_DIAG	0x00000400
702 
703 /* Receive MAC status register */
704 #define	BGE_RXSTAT_REMOTE_XOFFED	0x00000001
705 #define	BGE_RXSTAT_RCVD_XOFF		0x00000002
706 #define	BGE_RXSTAT_RCVD_XON		0x00000004
707 
708 /* Receive Rules Control register */
709 #define	BGE_RXRULECTL_OFFSET		0x000000FF
710 #define	BGE_RXRULECTL_CLASS		0x00001F00
711 #define	BGE_RXRULECTL_HDRTYPE		0x0000E000
712 #define	BGE_RXRULECTL_COMPARE_OP	0x00030000
713 #define	BGE_RXRULECTL_MAP		0x01000000
714 #define	BGE_RXRULECTL_DISCARD		0x02000000
715 #define	BGE_RXRULECTL_MASK		0x04000000
716 #define	BGE_RXRULECTL_ACTIVATE_PROC3	0x08000000
717 #define	BGE_RXRULECTL_ACTIVATE_PROC2	0x10000000
718 #define	BGE_RXRULECTL_ACTIVATE_PROC1	0x20000000
719 #define	BGE_RXRULECTL_ANDWITHNEXT	0x40000000
720 
721 /* Receive Rules Mask register */
722 #define	BGE_RXRULEMASK_VALUE		0x0000FFFF
723 #define	BGE_RXRULEMASK_MASKVAL		0xFFFF0000
724 
725 /* SERDES configuration register */
726 #define	BGE_SERDESCFG_RXR		0x00000007 /* phase interpolator */
727 #define	BGE_SERDESCFG_RXG		0x00000018 /* rx gain setting */
728 #define	BGE_SERDESCFG_RXEDGESEL		0x00000040 /* rising/falling egde */
729 #define	BGE_SERDESCFG_TX_BIAS		0x00000380 /* TXDAC bias setting */
730 #define	BGE_SERDESCFG_IBMAX		0x00000400 /* bias current +25% */
731 #define	BGE_SERDESCFG_IBMIN		0x00000800 /* bias current -25% */
732 #define	BGE_SERDESCFG_TXMODE		0x00001000
733 #define	BGE_SERDESCFG_TXEDGESEL		0x00002000 /* rising/falling edge */
734 #define	BGE_SERDESCFG_MODE		0x00004000 /* TXCP/TXCN disabled */
735 #define	BGE_SERDESCFG_PLLTEST		0x00008000 /* PLL test mode */
736 #define	BGE_SERDESCFG_CDET		0x00010000 /* comma detect enable */
737 #define	BGE_SERDESCFG_TBILOOP		0x00020000 /* local loopback */
738 #define	BGE_SERDESCFG_REMLOOP		0x00040000 /* remote loopback */
739 #define	BGE_SERDESCFG_INVPHASE		0x00080000 /* Reverse 125Mhz clock */
740 #define	BGE_SERDESCFG_12REGCTL		0x00300000 /* 1.2v regulator ctl */
741 #define	BGE_SERDESCFG_REGCTL		0x00C00000 /* regulator ctl (2.5v) */
742 
743 /* SERDES status register */
744 #define	BGE_SERDESSTS_RXSTAT		0x0000000F /* receive status bits */
745 #define	BGE_SERDESSTS_CDET		0x00000010 /* comma code detected */
746 
747 /* SGDIG config (not documented) */
748 #define	BGE_SGDIGCFG_PAUSE_CAP		0x00000800
749 #define	BGE_SGDIGCFG_ASYM_PAUSE		0x00001000
750 #define	BGE_SGDIGCFG_SEND		0x40000000
751 #define	BGE_SGDIGCFG_AUTO		0x80000000
752 
753 /* SGDIG status (not documented) */
754 #define	BGE_SGDIGSTS_PAUSE_CAP		0x00080000
755 #define	BGE_SGDIGSTS_ASYM_PAUSE		0x00100000
756 #define	BGE_SGDIGSTS_DONE		0x00000002
757 
758 
759 /* MI communication register */
760 #define	BGE_MICOMM_DATA			0x0000FFFF
761 #define	BGE_MICOMM_REG			0x001F0000
762 #define	BGE_MICOMM_PHY			0x03E00000
763 #define	BGE_MICOMM_CMD			0x0C000000
764 #define	BGE_MICOMM_READFAIL		0x10000000
765 #define	BGE_MICOMM_BUSY			0x20000000
766 
767 #define	BGE_MIREG(x)	((x & 0x1F) << 16)
768 #define	BGE_MIPHY(x)	((x & 0x1F) << 21)
769 #define	BGE_MICMD_WRITE			0x04000000
770 #define	BGE_MICMD_READ			0x08000000
771 
772 /* MI status register */
773 #define	BGE_MISTS_LINK			0x00000001
774 #define	BGE_MISTS_10MBPS		0x00000002
775 
776 #define	BGE_MIMODE_SHORTPREAMBLE	0x00000002
777 #define	BGE_MIMODE_AUTOPOLL		0x00000010
778 #define	BGE_MIMODE_CLKCNT		0x001F0000
779 
780 
781 /*
782  * Send data initiator control registers.
783  */
784 #define	BGE_SDI_MODE			0x0C00
785 #define	BGE_SDI_STATUS			0x0C04
786 #define	BGE_SDI_STATS_CTL		0x0C08
787 #define	BGE_SDI_STATS_ENABLE_MASK	0x0C0C
788 #define	BGE_SDI_STATS_INCREMENT_MASK	0x0C10
789 #define	BGE_LOCSTATS_COS0		0x0C80
790 #define	BGE_LOCSTATS_COS1		0x0C84
791 #define	BGE_LOCSTATS_COS2		0x0C88
792 #define	BGE_LOCSTATS_COS3		0x0C8C
793 #define	BGE_LOCSTATS_COS4		0x0C90
794 #define	BGE_LOCSTATS_COS5		0x0C84
795 #define	BGE_LOCSTATS_COS6		0x0C98
796 #define	BGE_LOCSTATS_COS7		0x0C9C
797 #define	BGE_LOCSTATS_COS8		0x0CA0
798 #define	BGE_LOCSTATS_COS9		0x0CA4
799 #define	BGE_LOCSTATS_COS10		0x0CA8
800 #define	BGE_LOCSTATS_COS11		0x0CAC
801 #define	BGE_LOCSTATS_COS12		0x0CB0
802 #define	BGE_LOCSTATS_COS13		0x0CB4
803 #define	BGE_LOCSTATS_COS14		0x0CB8
804 #define	BGE_LOCSTATS_COS15		0x0CBC
805 #define	BGE_LOCSTATS_DMA_RQ_FULL	0x0CC0
806 #define	BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL	0x0CC4
807 #define	BGE_LOCSTATS_SDC_QUEUE_FULL	0x0CC8
808 #define	BGE_LOCSTATS_NIC_SENDPROD_SET	0x0CCC
809 #define	BGE_LOCSTATS_STATS_UPDATED	0x0CD0
810 #define	BGE_LOCSTATS_IRQS		0x0CD4
811 #define	BGE_LOCSTATS_AVOIDED_IRQS	0x0CD8
812 #define	BGE_LOCSTATS_TX_THRESH_HIT	0x0CDC
813 
814 /* Send Data Initiator mode register */
815 #define	BGE_SDIMODE_RESET		0x00000001
816 #define	BGE_SDIMODE_ENABLE		0x00000002
817 #define	BGE_SDIMODE_STATS_OFLOW_ATTN	0x00000004
818 
819 /* Send Data Initiator stats register */
820 #define	BGE_SDISTAT_STATS_OFLOW_ATTN	0x00000004
821 
822 /* Send Data Initiator stats control register */
823 #define	BGE_SDISTATSCTL_ENABLE		0x00000001
824 #define	BGE_SDISTATSCTL_FASTER		0x00000002
825 #define	BGE_SDISTATSCTL_CLEAR		0x00000004
826 #define	BGE_SDISTATSCTL_FORCEFLUSH	0x00000008
827 #define	BGE_SDISTATSCTL_FORCEZERO	0x00000010
828 
829 /*
830  * Send Data Completion Control registers
831  */
832 #define	BGE_SDC_MODE			0x1000
833 #define	BGE_SDC_STATUS			0x1004
834 
835 /* Send Data completion mode register */
836 #define	BGE_SDCMODE_RESET		0x00000001
837 #define	BGE_SDCMODE_ENABLE		0x00000002
838 #define	BGE_SDCMODE_ATTN		0x00000004
839 
840 /* Send Data completion status register */
841 #define	BGE_SDCSTAT_ATTN		0x00000004
842 
843 /*
844  * Send BD Ring Selector Control registers
845  */
846 #define	BGE_SRS_MODE			0x1400
847 #define	BGE_SRS_STATUS			0x1404
848 #define	BGE_SRS_HWDIAG			0x1408
849 #define	BGE_SRS_LOC_NIC_CONS0		0x1440
850 #define	BGE_SRS_LOC_NIC_CONS1		0x1444
851 #define	BGE_SRS_LOC_NIC_CONS2		0x1448
852 #define	BGE_SRS_LOC_NIC_CONS3		0x144C
853 #define	BGE_SRS_LOC_NIC_CONS4		0x1450
854 #define	BGE_SRS_LOC_NIC_CONS5		0x1454
855 #define	BGE_SRS_LOC_NIC_CONS6		0x1458
856 #define	BGE_SRS_LOC_NIC_CONS7		0x145C
857 #define	BGE_SRS_LOC_NIC_CONS8		0x1460
858 #define	BGE_SRS_LOC_NIC_CONS9		0x1464
859 #define	BGE_SRS_LOC_NIC_CONS10		0x1468
860 #define	BGE_SRS_LOC_NIC_CONS11		0x146C
861 #define	BGE_SRS_LOC_NIC_CONS12		0x1470
862 #define	BGE_SRS_LOC_NIC_CONS13		0x1474
863 #define	BGE_SRS_LOC_NIC_CONS14		0x1478
864 #define	BGE_SRS_LOC_NIC_CONS15		0x147C
865 
866 /* Send BD Ring Selector Mode register */
867 #define	BGE_SRSMODE_RESET		0x00000001
868 #define	BGE_SRSMODE_ENABLE		0x00000002
869 #define	BGE_SRSMODE_ATTN		0x00000004
870 
871 /* Send BD Ring Selector Status register */
872 #define	BGE_SRSSTAT_ERROR		0x00000004
873 
874 /* Send BD Ring Selector HW Diagnostics register */
875 #define	BGE_SRSHWDIAG_STATE		0x0000000F
876 #define	BGE_SRSHWDIAG_CURRINGNUM	0x000000F0
877 #define	BGE_SRSHWDIAG_STAGEDRINGNUM	0x00000F00
878 #define	BGE_SRSHWDIAG_RINGNUM_IN_MBX	0x0000F000
879 
880 /*
881  * Send BD Initiator Selector Control registers
882  */
883 #define	BGE_SBDI_MODE			0x1800
884 #define	BGE_SBDI_STATUS			0x1804
885 #define	BGE_SBDI_LOC_NIC_PROD0		0x1808
886 #define	BGE_SBDI_LOC_NIC_PROD1		0x180C
887 #define	BGE_SBDI_LOC_NIC_PROD2		0x1810
888 #define	BGE_SBDI_LOC_NIC_PROD3		0x1814
889 #define	BGE_SBDI_LOC_NIC_PROD4		0x1818
890 #define	BGE_SBDI_LOC_NIC_PROD5		0x181C
891 #define	BGE_SBDI_LOC_NIC_PROD6		0x1820
892 #define	BGE_SBDI_LOC_NIC_PROD7		0x1824
893 #define	BGE_SBDI_LOC_NIC_PROD8		0x1828
894 #define	BGE_SBDI_LOC_NIC_PROD9		0x182C
895 #define	BGE_SBDI_LOC_NIC_PROD10		0x1830
896 #define	BGE_SBDI_LOC_NIC_PROD11		0x1834
897 #define	BGE_SBDI_LOC_NIC_PROD12		0x1838
898 #define	BGE_SBDI_LOC_NIC_PROD13		0x183C
899 #define	BGE_SBDI_LOC_NIC_PROD14		0x1840
900 #define	BGE_SBDI_LOC_NIC_PROD15		0x1844
901 
902 /* Send BD Initiator Mode register */
903 #define	BGE_SBDIMODE_RESET		0x00000001
904 #define	BGE_SBDIMODE_ENABLE		0x00000002
905 #define	BGE_SBDIMODE_ATTN		0x00000004
906 
907 /* Send BD Initiator Status register */
908 #define	BGE_SBDISTAT_ERROR		0x00000004
909 
910 /*
911  * Send BD Completion Control registers
912  */
913 #define	BGE_SBDC_MODE			0x1C00
914 #define	BGE_SBDC_STATUS			0x1C04
915 
916 /* Send BD Completion Control Mode register */
917 #define	BGE_SBDCMODE_RESET		0x00000001
918 #define	BGE_SBDCMODE_ENABLE		0x00000002
919 #define	BGE_SBDCMODE_ATTN		0x00000004
920 
921 /* Send BD Completion Control Status register */
922 #define	BGE_SBDCSTAT_ATTN		0x00000004
923 
924 /*
925  * Receive List Placement Control registers
926  */
927 #define	BGE_RXLP_MODE			0x2000
928 #define	BGE_RXLP_STATUS			0x2004
929 #define	BGE_RXLP_SEL_LIST_LOCK		0x2008
930 #define	BGE_RXLP_SEL_NON_EMPTY_BITS	0x200C
931 #define	BGE_RXLP_CFG			0x2010
932 #define	BGE_RXLP_STATS_CTL		0x2014
933 #define	BGE_RXLP_STATS_ENABLE_MASK	0x2018
934 #define	BGE_RXLP_STATS_INCREMENT_MASK	0x201C
935 #define	BGE_RXLP_HEAD0			0x2100
936 #define	BGE_RXLP_TAIL0			0x2104
937 #define	BGE_RXLP_COUNT0			0x2108
938 #define	BGE_RXLP_HEAD1			0x2110
939 #define	BGE_RXLP_TAIL1			0x2114
940 #define	BGE_RXLP_COUNT1			0x2118
941 #define	BGE_RXLP_HEAD2			0x2120
942 #define	BGE_RXLP_TAIL2			0x2124
943 #define	BGE_RXLP_COUNT2			0x2128
944 #define	BGE_RXLP_HEAD3			0x2130
945 #define	BGE_RXLP_TAIL3			0x2134
946 #define	BGE_RXLP_COUNT3			0x2138
947 #define	BGE_RXLP_HEAD4			0x2140
948 #define	BGE_RXLP_TAIL4			0x2144
949 #define	BGE_RXLP_COUNT4			0x2148
950 #define	BGE_RXLP_HEAD5			0x2150
951 #define	BGE_RXLP_TAIL5			0x2154
952 #define	BGE_RXLP_COUNT5			0x2158
953 #define	BGE_RXLP_HEAD6			0x2160
954 #define	BGE_RXLP_TAIL6			0x2164
955 #define	BGE_RXLP_COUNT6			0x2168
956 #define	BGE_RXLP_HEAD7			0x2170
957 #define	BGE_RXLP_TAIL7			0x2174
958 #define	BGE_RXLP_COUNT7			0x2178
959 #define	BGE_RXLP_HEAD8			0x2180
960 #define	BGE_RXLP_TAIL8			0x2184
961 #define	BGE_RXLP_COUNT8			0x2188
962 #define	BGE_RXLP_HEAD9			0x2190
963 #define	BGE_RXLP_TAIL9			0x2194
964 #define	BGE_RXLP_COUNT9			0x2198
965 #define	BGE_RXLP_HEAD10			0x21A0
966 #define	BGE_RXLP_TAIL10			0x21A4
967 #define	BGE_RXLP_COUNT10		0x21A8
968 #define	BGE_RXLP_HEAD11			0x21B0
969 #define	BGE_RXLP_TAIL11			0x21B4
970 #define	BGE_RXLP_COUNT11		0x21B8
971 #define	BGE_RXLP_HEAD12			0x21C0
972 #define	BGE_RXLP_TAIL12			0x21C4
973 #define	BGE_RXLP_COUNT12		0x21C8
974 #define	BGE_RXLP_HEAD13			0x21D0
975 #define	BGE_RXLP_TAIL13			0x21D4
976 #define	BGE_RXLP_COUNT13		0x21D8
977 #define	BGE_RXLP_HEAD14			0x21E0
978 #define	BGE_RXLP_TAIL14			0x21E4
979 #define	BGE_RXLP_COUNT14		0x21E8
980 #define	BGE_RXLP_HEAD15			0x21F0
981 #define	BGE_RXLP_TAIL15			0x21F4
982 #define	BGE_RXLP_COUNT15		0x21F8
983 #define	BGE_RXLP_LOCSTAT_COS0		0x2200
984 #define	BGE_RXLP_LOCSTAT_COS1		0x2204
985 #define	BGE_RXLP_LOCSTAT_COS2		0x2208
986 #define	BGE_RXLP_LOCSTAT_COS3		0x220C
987 #define	BGE_RXLP_LOCSTAT_COS4		0x2210
988 #define	BGE_RXLP_LOCSTAT_COS5		0x2214
989 #define	BGE_RXLP_LOCSTAT_COS6		0x2218
990 #define	BGE_RXLP_LOCSTAT_COS7		0x221C
991 #define	BGE_RXLP_LOCSTAT_COS8		0x2220
992 #define	BGE_RXLP_LOCSTAT_COS9		0x2224
993 #define	BGE_RXLP_LOCSTAT_COS10		0x2228
994 #define	BGE_RXLP_LOCSTAT_COS11		0x222C
995 #define	BGE_RXLP_LOCSTAT_COS12		0x2230
996 #define	BGE_RXLP_LOCSTAT_COS13		0x2234
997 #define	BGE_RXLP_LOCSTAT_COS14		0x2238
998 #define	BGE_RXLP_LOCSTAT_COS15		0x223C
999 #define	BGE_RXLP_LOCSTAT_FILTDROP	0x2240
1000 #define	BGE_RXLP_LOCSTAT_DMA_WRQ_FULL	0x2244
1001 #define	BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL	0x2248
1002 #define	BGE_RXLP_LOCSTAT_OUT_OF_BDS	0x224C
1003 #define	BGE_RXLP_LOCSTAT_IFIN_DROPS	0x2250
1004 #define	BGE_RXLP_LOCSTAT_IFIN_ERRORS	0x2254
1005 #define	BGE_RXLP_LOCSTAT_RXTHRESH_HIT	0x2258
1006 
1007 
1008 /* Receive List Placement mode register */
1009 #define	BGE_RXLPMODE_RESET		0x00000001
1010 #define	BGE_RXLPMODE_ENABLE		0x00000002
1011 #define	BGE_RXLPMODE_CLASS0_ATTN	0x00000004
1012 #define	BGE_RXLPMODE_MAPOUTRANGE_ATTN	0x00000008
1013 #define	BGE_RXLPMODE_STATSOFLOW_ATTN	0x00000010
1014 
1015 /* Receive List Placement Status register */
1016 #define	BGE_RXLPSTAT_CLASS0_ATTN	0x00000004
1017 #define	BGE_RXLPSTAT_MAPOUTRANGE_ATTN	0x00000008
1018 #define	BGE_RXLPSTAT_STATSOFLOW_ATTN	0x00000010
1019 
1020 /*
1021  * Receive Data and Receive BD Initiator Control Registers
1022  */
1023 #define	BGE_RDBDI_MODE			0x2400
1024 #define	BGE_RDBDI_STATUS		0x2404
1025 #define	BGE_RX_JUMBO_RCB_HADDR_HI	0x2440
1026 #define	BGE_RX_JUMBO_RCB_HADDR_LO	0x2444
1027 #define	BGE_RX_JUMBO_RCB_MAXLEN_FLAGS	0x2448
1028 #define	BGE_RX_JUMBO_RCB_NICADDR	0x244C
1029 #define	BGE_RX_STD_RCB_HADDR_HI		0x2450
1030 #define	BGE_RX_STD_RCB_HADDR_LO		0x2454
1031 #define	BGE_RX_STD_RCB_MAXLEN_FLAGS	0x2458
1032 #define	BGE_RX_STD_RCB_NICADDR		0x245C
1033 #define	BGE_RX_MINI_RCB_HADDR_HI	0x2460
1034 #define	BGE_RX_MINI_RCB_HADDR_LO	0x2464
1035 #define	BGE_RX_MINI_RCB_MAXLEN_FLAGS	0x2468
1036 #define	BGE_RX_MINI_RCB_NICADDR		0x246C
1037 #define	BGE_RDBDI_JUMBO_RX_CONS		0x2470
1038 #define	BGE_RDBDI_STD_RX_CONS		0x2474
1039 #define	BGE_RDBDI_MINI_RX_CONS		0x2478
1040 #define	BGE_RDBDI_RETURN_PROD0		0x2480
1041 #define	BGE_RDBDI_RETURN_PROD1		0x2484
1042 #define	BGE_RDBDI_RETURN_PROD2		0x2488
1043 #define	BGE_RDBDI_RETURN_PROD3		0x248C
1044 #define	BGE_RDBDI_RETURN_PROD4		0x2490
1045 #define	BGE_RDBDI_RETURN_PROD5		0x2494
1046 #define	BGE_RDBDI_RETURN_PROD6		0x2498
1047 #define	BGE_RDBDI_RETURN_PROD7		0x249C
1048 #define	BGE_RDBDI_RETURN_PROD8		0x24A0
1049 #define	BGE_RDBDI_RETURN_PROD9		0x24A4
1050 #define	BGE_RDBDI_RETURN_PROD10		0x24A8
1051 #define	BGE_RDBDI_RETURN_PROD11		0x24AC
1052 #define	BGE_RDBDI_RETURN_PROD12		0x24B0
1053 #define	BGE_RDBDI_RETURN_PROD13		0x24B4
1054 #define	BGE_RDBDI_RETURN_PROD14		0x24B8
1055 #define	BGE_RDBDI_RETURN_PROD15		0x24BC
1056 #define	BGE_RDBDI_HWDIAG		0x24C0
1057 
1058 
1059 /* Receive Data and Receive BD Initiator Mode register */
1060 #define	BGE_RDBDIMODE_RESET		0x00000001
1061 #define	BGE_RDBDIMODE_ENABLE		0x00000002
1062 #define	BGE_RDBDIMODE_JUMBO_ATTN	0x00000004
1063 #define	BGE_RDBDIMODE_GIANT_ATTN	0x00000008
1064 #define	BGE_RDBDIMODE_BADRINGSZ_ATTN	0x00000010
1065 
1066 /* Receive Data and Receive BD Initiator Status register */
1067 #define	BGE_RDBDISTAT_JUMBO_ATTN	0x00000004
1068 #define	BGE_RDBDISTAT_GIANT_ATTN	0x00000008
1069 #define	BGE_RDBDISTAT_BADRINGSZ_ATTN	0x00000010
1070 
1071 
1072 /*
1073  * Receive Data Completion Control registers
1074  */
1075 #define	BGE_RDC_MODE			0x2800
1076 
1077 /* Receive Data Completion Mode register */
1078 #define	BGE_RDCMODE_RESET		0x00000001
1079 #define	BGE_RDCMODE_ENABLE		0x00000002
1080 #define	BGE_RDCMODE_ATTN		0x00000004
1081 
1082 /*
1083  * Receive BD Initiator Control registers
1084  */
1085 #define	BGE_RBDI_MODE			0x2C00
1086 #define	BGE_RBDI_STATUS			0x2C04
1087 #define	BGE_RBDI_NIC_JUMBO_BD_PROD	0x2C08
1088 #define	BGE_RBDI_NIC_STD_BD_PROD	0x2C0C
1089 #define	BGE_RBDI_NIC_MINI_BD_PROD	0x2C10
1090 #define	BGE_RBDI_MINI_REPL_THRESH	0x2C14
1091 #define	BGE_RBDI_STD_REPL_THRESH	0x2C18
1092 #define	BGE_RBDI_JUMBO_REPL_THRESH	0x2C1C
1093 
1094 /* Receive BD Initiator Mode register */
1095 #define	BGE_RBDIMODE_RESET		0x00000001
1096 #define	BGE_RBDIMODE_ENABLE		0x00000002
1097 #define	BGE_RBDIMODE_ATTN		0x00000004
1098 
1099 /* Receive BD Initiator Status register */
1100 #define	BGE_RBDISTAT_ATTN		0x00000004
1101 
1102 /*
1103  * Receive BD Completion Control registers
1104  */
1105 #define	BGE_RBDC_MODE			0x3000
1106 #define	BGE_RBDC_STATUS			0x3004
1107 #define	BGE_RBDC_JUMBO_BD_PROD		0x3008
1108 #define	BGE_RBDC_STD_BD_PROD		0x300C
1109 #define	BGE_RBDC_MINI_BD_PROD		0x3010
1110 
1111 /* Receive BD completion mode register */
1112 #define	BGE_RBDCMODE_RESET		0x00000001
1113 #define	BGE_RBDCMODE_ENABLE		0x00000002
1114 #define	BGE_RBDCMODE_ATTN		0x00000004
1115 
1116 /* Receive BD completion status register */
1117 #define	BGE_RBDCSTAT_ERROR		0x00000004
1118 
1119 /*
1120  * Receive List Selector Control registers
1121  */
1122 #define	BGE_RXLS_MODE			0x3400
1123 #define	BGE_RXLS_STATUS			0x3404
1124 
1125 /* Receive List Selector Mode register */
1126 #define	BGE_RXLSMODE_RESET		0x00000001
1127 #define	BGE_RXLSMODE_ENABLE		0x00000002
1128 #define	BGE_RXLSMODE_ATTN		0x00000004
1129 
1130 /* Receive List Selector Status register */
1131 #define	BGE_RXLSSTAT_ERROR		0x00000004
1132 
1133 /*
1134  * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1135  */
1136 #define	BGE_MBCF_MODE			0x3800
1137 #define	BGE_MBCF_STATUS			0x3804
1138 
1139 /* Mbuf Cluster Free mode register */
1140 #define	BGE_MBCFMODE_RESET		0x00000001
1141 #define	BGE_MBCFMODE_ENABLE		0x00000002
1142 #define	BGE_MBCFMODE_ATTN		0x00000004
1143 
1144 /* Mbuf Cluster Free status register */
1145 #define	BGE_MBCFSTAT_ERROR		0x00000004
1146 
1147 /*
1148  * Host Coalescing Control registers
1149  */
1150 #define	BGE_HCC_MODE			0x3C00
1151 #define	BGE_HCC_STATUS			0x3C04
1152 #define	BGE_HCC_RX_COAL_TICKS		0x3C08
1153 #define	BGE_HCC_TX_COAL_TICKS		0x3C0C
1154 #define	BGE_HCC_RX_MAX_COAL_BDS		0x3C10
1155 #define	BGE_HCC_TX_MAX_COAL_BDS		0x3C14
1156 #define	BGE_HCC_RX_COAL_TICKS_INT	0x3C18 /* ticks during interrupt */
1157 #define	BGE_HCC_TX_COAL_TICKS_INT	0x3C1C /* ticks during interrupt */
1158 #define	BGE_HCC_RX_MAX_COAL_BDS_INT	0x3C20 /* BDs during interrupt */
1159 #define	BGE_HCC_TX_MAX_COAL_BDS_INT	0x3C24 /* BDs during interrupt */
1160 #define	BGE_HCC_STATS_TICKS		0x3C28
1161 #define	BGE_HCC_STATS_ADDR_HI		0x3C30
1162 #define	BGE_HCC_STATS_ADDR_LO		0x3C34
1163 #define	BGE_HCC_STATUSBLK_ADDR_HI	0x3C38
1164 #define	BGE_HCC_STATUSBLK_ADDR_LO	0x3C3C
1165 #define	BGE_HCC_STATS_BASEADDR		0x3C40 /* address in NIC memory */
1166 #define	BGE_HCC_STATUSBLK_BASEADDR	0x3C44 /* address in NIC memory */
1167 #define	BGE_FLOW_ATTN			0x3C48
1168 #define	BGE_HCC_JUMBO_BD_CONS		0x3C50
1169 #define	BGE_HCC_STD_BD_CONS		0x3C54
1170 #define	BGE_HCC_MINI_BD_CONS		0x3C58
1171 #define	BGE_HCC_RX_RETURN_PROD0		0x3C80
1172 #define	BGE_HCC_RX_RETURN_PROD1		0x3C84
1173 #define	BGE_HCC_RX_RETURN_PROD2		0x3C88
1174 #define	BGE_HCC_RX_RETURN_PROD3		0x3C8C
1175 #define	BGE_HCC_RX_RETURN_PROD4		0x3C90
1176 #define	BGE_HCC_RX_RETURN_PROD5		0x3C94
1177 #define	BGE_HCC_RX_RETURN_PROD6		0x3C98
1178 #define	BGE_HCC_RX_RETURN_PROD7		0x3C9C
1179 #define	BGE_HCC_RX_RETURN_PROD8		0x3CA0
1180 #define	BGE_HCC_RX_RETURN_PROD9		0x3CA4
1181 #define	BGE_HCC_RX_RETURN_PROD10	0x3CA8
1182 #define	BGE_HCC_RX_RETURN_PROD11	0x3CAC
1183 #define	BGE_HCC_RX_RETURN_PROD12	0x3CB0
1184 #define	BGE_HCC_RX_RETURN_PROD13	0x3CB4
1185 #define	BGE_HCC_RX_RETURN_PROD14	0x3CB8
1186 #define	BGE_HCC_RX_RETURN_PROD15	0x3CBC
1187 #define	BGE_HCC_TX_BD_CONS0		0x3CC0
1188 #define	BGE_HCC_TX_BD_CONS1		0x3CC4
1189 #define	BGE_HCC_TX_BD_CONS2		0x3CC8
1190 #define	BGE_HCC_TX_BD_CONS3		0x3CCC
1191 #define	BGE_HCC_TX_BD_CONS4		0x3CD0
1192 #define	BGE_HCC_TX_BD_CONS5		0x3CD4
1193 #define	BGE_HCC_TX_BD_CONS6		0x3CD8
1194 #define	BGE_HCC_TX_BD_CONS7		0x3CDC
1195 #define	BGE_HCC_TX_BD_CONS8		0x3CE0
1196 #define	BGE_HCC_TX_BD_CONS9		0x3CE4
1197 #define	BGE_HCC_TX_BD_CONS10		0x3CE8
1198 #define	BGE_HCC_TX_BD_CONS11		0x3CEC
1199 #define	BGE_HCC_TX_BD_CONS12		0x3CF0
1200 #define	BGE_HCC_TX_BD_CONS13		0x3CF4
1201 #define	BGE_HCC_TX_BD_CONS14		0x3CF8
1202 #define	BGE_HCC_TX_BD_CONS15		0x3CFC
1203 
1204 
1205 /* Host coalescing mode register */
1206 #define	BGE_HCCMODE_RESET		0x00000001
1207 #define	BGE_HCCMODE_ENABLE		0x00000002
1208 #define	BGE_HCCMODE_ATTN		0x00000004
1209 #define	BGE_HCCMODE_COAL_NOW		0x00000008
1210 #define	BGE_HCCMODE_MSI_BITS		0x00000070
1211 #define	BGE_HCCMODE_STATBLK_SIZE	0x00000180
1212 
1213 #define	BGE_STATBLKSZ_FULL		0x00000000
1214 #define	BGE_STATBLKSZ_64BYTE		0x00000080
1215 #define	BGE_STATBLKSZ_32BYTE		0x00000100
1216 
1217 /* Host coalescing status register */
1218 #define	BGE_HCCSTAT_ERROR		0x00000004
1219 
1220 /* Flow attention register */
1221 #define	BGE_FLOWATTN_MB_LOWAT		0x00000040
1222 #define	BGE_FLOWATTN_MEMARB		0x00000080
1223 #define	BGE_FLOWATTN_HOSTCOAL		0x00008000
1224 #define	BGE_FLOWATTN_DMADONE_DISCARD	0x00010000
1225 #define	BGE_FLOWATTN_RCB_INVAL		0x00020000
1226 #define	BGE_FLOWATTN_RXDATA_CORRUPT	0x00040000
1227 #define	BGE_FLOWATTN_RDBDI		0x00080000
1228 #define	BGE_FLOWATTN_RXLS		0x00100000
1229 #define	BGE_FLOWATTN_RXLP		0x00200000
1230 #define	BGE_FLOWATTN_RBDC		0x00400000
1231 #define	BGE_FLOWATTN_RBDI		0x00800000
1232 #define	BGE_FLOWATTN_SDC		0x08000000
1233 #define	BGE_FLOWATTN_SDI		0x10000000
1234 #define	BGE_FLOWATTN_SRS		0x20000000
1235 #define	BGE_FLOWATTN_SBDC		0x40000000
1236 #define	BGE_FLOWATTN_SBDI		0x80000000
1237 
1238 /*
1239  * Memory arbiter registers
1240  */
1241 #define	BGE_MARB_MODE			0x4000
1242 #define	BGE_MARB_STATUS			0x4004
1243 #define	BGE_MARB_TRAPADDR_HI		0x4008
1244 #define	BGE_MARB_TRAPADDR_LO		0x400C
1245 
1246 /* Memory arbiter mode register */
1247 #define	BGE_MARBMODE_RESET		0x00000001
1248 #define	BGE_MARBMODE_ENABLE		0x00000002
1249 #define	BGE_MARBMODE_TX_ADDR_TRAP	0x00000004
1250 #define	BGE_MARBMODE_RX_ADDR_TRAP	0x00000008
1251 #define	BGE_MARBMODE_DMAW1_TRAP		0x00000010
1252 #define	BGE_MARBMODE_DMAR1_TRAP		0x00000020
1253 #define	BGE_MARBMODE_RXRISC_TRAP	0x00000040
1254 #define	BGE_MARBMODE_TXRISC_TRAP	0x00000080
1255 #define	BGE_MARBMODE_PCI_TRAP		0x00000100
1256 #define	BGE_MARBMODE_DMAR2_TRAP		0x00000200
1257 #define	BGE_MARBMODE_RXQ_TRAP		0x00000400
1258 #define	BGE_MARBMODE_RXDI1_TRAP		0x00000800
1259 #define	BGE_MARBMODE_RXDI2_TRAP		0x00001000
1260 #define	BGE_MARBMODE_DC_GRPMEM_TRAP	0x00002000
1261 #define	BGE_MARBMODE_HCOAL_TRAP		0x00004000
1262 #define	BGE_MARBMODE_MBUF_TRAP		0x00008000
1263 #define	BGE_MARBMODE_TXDI_TRAP		0x00010000
1264 #define	BGE_MARBMODE_SDC_DMAC_TRAP	0x00020000
1265 #define	BGE_MARBMODE_TXBD_TRAP		0x00040000
1266 #define	BGE_MARBMODE_BUFFMAN_TRAP	0x00080000
1267 #define	BGE_MARBMODE_DMAW2_TRAP		0x00100000
1268 #define	BGE_MARBMODE_XTSSRAM_ROFLO_TRAP	0x00200000
1269 #define	BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1270 #define	BGE_MARBMODE_XTSSRAM_WOFLO_TRAP	0x00800000
1271 #define	BGE_MARBMODE_XTSSRAM_WUFLO_TRAP	0x01000000
1272 #define	BGE_MARBMODE_XTSSRAM_PERR_TRAP	0x02000000
1273 
1274 /* Memory arbiter status register */
1275 #define	BGE_MARBSTAT_TX_ADDR_TRAP	0x00000004
1276 #define	BGE_MARBSTAT_RX_ADDR_TRAP	0x00000008
1277 #define	BGE_MARBSTAT_DMAW1_TRAP		0x00000010
1278 #define	BGE_MARBSTAT_DMAR1_TRAP		0x00000020
1279 #define	BGE_MARBSTAT_RXRISC_TRAP	0x00000040
1280 #define	BGE_MARBSTAT_TXRISC_TRAP	0x00000080
1281 #define	BGE_MARBSTAT_PCI_TRAP		0x00000100
1282 #define	BGE_MARBSTAT_DMAR2_TRAP		0x00000200
1283 #define	BGE_MARBSTAT_RXQ_TRAP		0x00000400
1284 #define	BGE_MARBSTAT_RXDI1_TRAP		0x00000800
1285 #define	BGE_MARBSTAT_RXDI2_TRAP		0x00001000
1286 #define	BGE_MARBSTAT_DC_GRPMEM_TRAP	0x00002000
1287 #define	BGE_MARBSTAT_HCOAL_TRAP		0x00004000
1288 #define	BGE_MARBSTAT_MBUF_TRAP		0x00008000
1289 #define	BGE_MARBSTAT_TXDI_TRAP		0x00010000
1290 #define	BGE_MARBSTAT_SDC_DMAC_TRAP	0x00020000
1291 #define	BGE_MARBSTAT_TXBD_TRAP		0x00040000
1292 #define	BGE_MARBSTAT_BUFFMAN_TRAP	0x00080000
1293 #define	BGE_MARBSTAT_DMAW2_TRAP		0x00100000
1294 #define	BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP	0x00200000
1295 #define	BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1296 #define	BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP	0x00800000
1297 #define	BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP	0x01000000
1298 #define	BGE_MARBSTAT_XTSSRAM_PERR_TRAP	0x02000000
1299 
1300 /*
1301  * Buffer manager control registers
1302  */
1303 #define	BGE_BMAN_MODE			0x4400
1304 #define	BGE_BMAN_STATUS			0x4404
1305 #define	BGE_BMAN_MBUFPOOL_BASEADDR	0x4408
1306 #define	BGE_BMAN_MBUFPOOL_LEN		0x440C
1307 #define	BGE_BMAN_MBUFPOOL_READDMA_LOWAT	0x4410
1308 #define	BGE_BMAN_MBUFPOOL_MACRX_LOWAT	0x4414
1309 #define	BGE_BMAN_MBUFPOOL_HIWAT		0x4418
1310 #define	BGE_BMAN_RXCPU_MBALLOC_REQ	0x441C
1311 #define	BGE_BMAN_RXCPU_MBALLOC_RESP	0x4420
1312 #define	BGE_BMAN_TXCPU_MBALLOC_REQ	0x4424
1313 #define	BGE_BMAN_TXCPU_MBALLOC_RESP	0x4428
1314 #define	BGE_BMAN_DMA_DESCPOOL_BASEADDR	0x442C
1315 #define	BGE_BMAN_DMA_DESCPOOL_LEN	0x4430
1316 #define	BGE_BMAN_DMA_DESCPOOL_LOWAT	0x4434
1317 #define	BGE_BMAN_DMA_DESCPOOL_HIWAT	0x4438
1318 #define	BGE_BMAN_RXCPU_DMAALLOC_REQ	0x443C
1319 #define	BGE_BMAN_RXCPU_DMAALLOC_RESP	0x4440
1320 #define	BGE_BMAN_TXCPU_DMAALLOC_REQ	0x4444
1321 #define	BGE_BMAN_TXCPU_DMALLLOC_RESP	0x4448
1322 #define	BGE_BMAN_HWDIAG_1		0x444C
1323 #define	BGE_BMAN_HWDIAG_2		0x4450
1324 #define	BGE_BMAN_HWDIAG_3		0x4454
1325 
1326 /* Buffer manager mode register */
1327 #define	BGE_BMANMODE_RESET		0x00000001
1328 #define	BGE_BMANMODE_ENABLE		0x00000002
1329 #define	BGE_BMANMODE_ATTN		0x00000004
1330 #define	BGE_BMANMODE_TESTMODE		0x00000008
1331 #define	BGE_BMANMODE_LOMBUF_ATTN	0x00000010
1332 
1333 /* Buffer manager status register */
1334 #define	BGE_BMANSTAT_ERRO		0x00000004
1335 #define	BGE_BMANSTAT_LOWMBUF_ERROR	0x00000010
1336 
1337 
1338 /*
1339  * Read DMA Control registers
1340  */
1341 #define	BGE_RDMA_MODE			0x4800
1342 #define	BGE_RDMA_STATUS			0x4804
1343 
1344 /* Read DMA mode register */
1345 #define	BGE_RDMAMODE_RESET		0x00000001
1346 #define	BGE_RDMAMODE_ENABLE		0x00000002
1347 #define	BGE_RDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
1348 #define	BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
1349 #define	BGE_RDMAMODE_PCI_PERR_ATTN	0x00000010
1350 #define	BGE_RDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
1351 #define	BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
1352 #define	BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
1353 #define	BGE_RDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
1354 #define	BGE_RDMAMODE_LOCWRITE_TOOBIG	0x00000200
1355 #define	BGE_RDMAMODE_ALL_ATTNS		0x000003FC
1356 
1357 /* Read DMA status register */
1358 #define	BGE_RDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
1359 #define	BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
1360 #define	BGE_RDMASTAT_PCI_PERR_ATTN	0x00000010
1361 #define	BGE_RDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
1362 #define	BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
1363 #define	BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
1364 #define	BGE_RDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
1365 #define	BGE_RDMASTAT_LOCWRITE_TOOBIG	0x00000200
1366 
1367 /*
1368  * Write DMA control registers
1369  */
1370 #define	BGE_WDMA_MODE			0x4C00
1371 #define	BGE_WDMA_STATUS			0x4C04
1372 
1373 /* Write DMA mode register */
1374 #define	BGE_WDMAMODE_RESET		0x00000001
1375 #define	BGE_WDMAMODE_ENABLE		0x00000002
1376 #define	BGE_WDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
1377 #define	BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
1378 #define	BGE_WDMAMODE_PCI_PERR_ATTN	0x00000010
1379 #define	BGE_WDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
1380 #define	BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
1381 #define	BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
1382 #define	BGE_WDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
1383 #define	BGE_WDMAMODE_LOCREAD_TOOBIG	0x00000200
1384 #define	BGE_WDMAMODE_ALL_ATTNS		0x000003FC
1385 
1386 /* Write DMA status register */
1387 #define	BGE_WDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
1388 #define	BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
1389 #define	BGE_WDMASTAT_PCI_PERR_ATTN	0x00000010
1390 #define	BGE_WDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
1391 #define	BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
1392 #define	BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
1393 #define	BGE_WDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
1394 #define	BGE_WDMASTAT_LOCREAD_TOOBIG	0x00000200
1395 
1396 
1397 /*
1398  * RX CPU registers
1399  */
1400 #define	BGE_RXCPU_MODE			0x5000
1401 #define	BGE_RXCPU_STATUS		0x5004
1402 #define	BGE_RXCPU_PC			0x501C
1403 
1404 /* RX CPU mode register */
1405 #define	BGE_RXCPUMODE_RESET		0x00000001
1406 #define	BGE_RXCPUMODE_SINGLESTEP	0x00000002
1407 #define	BGE_RXCPUMODE_P0_DATAHLT_ENB	0x00000004
1408 #define	BGE_RXCPUMODE_P0_INSTRHLT_ENB	0x00000008
1409 #define	BGE_RXCPUMODE_WR_POSTBUF_ENB	0x00000010
1410 #define	BGE_RXCPUMODE_DATACACHE_ENB	0x00000020
1411 #define	BGE_RXCPUMODE_ROMFAIL		0x00000040
1412 #define	BGE_RXCPUMODE_WATCHDOG_ENB	0x00000080
1413 #define	BGE_RXCPUMODE_INSTRCACHE_PRF	0x00000100
1414 #define	BGE_RXCPUMODE_INSTRCACHE_FLUSH	0x00000200
1415 #define	BGE_RXCPUMODE_HALTCPU		0x00000400
1416 #define	BGE_RXCPUMODE_INVDATAHLT_ENB	0x00000800
1417 #define	BGE_RXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
1418 #define	BGE_RXCPUMODE_RADDRTRAPHLT_ENB	0x00002000
1419 
1420 /* RX CPU status register */
1421 #define	BGE_RXCPUSTAT_HW_BREAKPOINT	0x00000001
1422 #define	BGE_RXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
1423 #define	BGE_RXCPUSTAT_INVALID_INSTR	0x00000004
1424 #define	BGE_RXCPUSTAT_P0_DATAREF	0x00000008
1425 #define	BGE_RXCPUSTAT_P0_INSTRREF	0x00000010
1426 #define	BGE_RXCPUSTAT_INVALID_DATAACC	0x00000020
1427 #define	BGE_RXCPUSTAT_INVALID_INSTRFTCH	0x00000040
1428 #define	BGE_RXCPUSTAT_BAD_MEMALIGN	0x00000080
1429 #define	BGE_RXCPUSTAT_MADDR_TRAP	0x00000100
1430 #define	BGE_RXCPUSTAT_REGADDR_TRAP	0x00000200
1431 #define	BGE_RXCPUSTAT_DATAACC_STALL	0x00001000
1432 #define	BGE_RXCPUSTAT_INSTRFETCH_STALL	0x00002000
1433 #define	BGE_RXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
1434 #define	BGE_RXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
1435 #define	BGE_RXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
1436 #define	BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
1437 #define	BGE_RXCPUSTAT_BLOCKING_READ	0x80000000
1438 
1439 
1440 /*
1441  * TX CPU registers
1442  */
1443 #define	BGE_TXCPU_MODE			0x5400
1444 #define	BGE_TXCPU_STATUS		0x5404
1445 #define	BGE_TXCPU_PC			0x541C
1446 
1447 /* TX CPU mode register */
1448 #define	BGE_TXCPUMODE_RESET		0x00000001
1449 #define	BGE_TXCPUMODE_SINGLESTEP	0x00000002
1450 #define	BGE_TXCPUMODE_P0_DATAHLT_ENB	0x00000004
1451 #define	BGE_TXCPUMODE_P0_INSTRHLT_ENB	0x00000008
1452 #define	BGE_TXCPUMODE_WR_POSTBUF_ENB	0x00000010
1453 #define	BGE_TXCPUMODE_DATACACHE_ENB	0x00000020
1454 #define	BGE_TXCPUMODE_ROMFAIL		0x00000040
1455 #define	BGE_TXCPUMODE_WATCHDOG_ENB	0x00000080
1456 #define	BGE_TXCPUMODE_INSTRCACHE_PRF	0x00000100
1457 #define	BGE_TXCPUMODE_INSTRCACHE_FLUSH	0x00000200
1458 #define	BGE_TXCPUMODE_HALTCPU		0x00000400
1459 #define	BGE_TXCPUMODE_INVDATAHLT_ENB	0x00000800
1460 #define	BGE_TXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
1461 
1462 /* TX CPU status register */
1463 #define	BGE_TXCPUSTAT_HW_BREAKPOINT	0x00000001
1464 #define	BGE_TXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
1465 #define	BGE_TXCPUSTAT_INVALID_INSTR	0x00000004
1466 #define	BGE_TXCPUSTAT_P0_DATAREF	0x00000008
1467 #define	BGE_TXCPUSTAT_P0_INSTRREF	0x00000010
1468 #define	BGE_TXCPUSTAT_INVALID_DATAACC	0x00000020
1469 #define	BGE_TXCPUSTAT_INVALID_INSTRFTCH	0x00000040
1470 #define	BGE_TXCPUSTAT_BAD_MEMALIGN	0x00000080
1471 #define	BGE_TXCPUSTAT_MADDR_TRAP	0x00000100
1472 #define	BGE_TXCPUSTAT_REGADDR_TRAP	0x00000200
1473 #define	BGE_TXCPUSTAT_DATAACC_STALL	0x00001000
1474 #define	BGE_TXCPUSTAT_INSTRFETCH_STALL	0x00002000
1475 #define	BGE_TXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
1476 #define	BGE_TXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
1477 #define	BGE_TXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
1478 #define	BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
1479 #define	BGE_TXCPUSTAT_BLOCKING_READ	0x80000000
1480 
1481 
1482 /*
1483  * Low priority mailbox registers
1484  */
1485 #define	BGE_LPMBX_IRQ0_HI		0x5800
1486 #define	BGE_LPMBX_IRQ0_LO		0x5804
1487 #define	BGE_LPMBX_IRQ1_HI		0x5808
1488 #define	BGE_LPMBX_IRQ1_LO		0x580C
1489 #define	BGE_LPMBX_IRQ2_HI		0x5810
1490 #define	BGE_LPMBX_IRQ2_LO		0x5814
1491 #define	BGE_LPMBX_IRQ3_HI		0x5818
1492 #define	BGE_LPMBX_IRQ3_LO		0x581C
1493 #define	BGE_LPMBX_GEN0_HI		0x5820
1494 #define	BGE_LPMBX_GEN0_LO		0x5824
1495 #define	BGE_LPMBX_GEN1_HI		0x5828
1496 #define	BGE_LPMBX_GEN1_LO		0x582C
1497 #define	BGE_LPMBX_GEN2_HI		0x5830
1498 #define	BGE_LPMBX_GEN2_LO		0x5834
1499 #define	BGE_LPMBX_GEN3_HI		0x5828
1500 #define	BGE_LPMBX_GEN3_LO		0x582C
1501 #define	BGE_LPMBX_GEN4_HI		0x5840
1502 #define	BGE_LPMBX_GEN4_LO		0x5844
1503 #define	BGE_LPMBX_GEN5_HI		0x5848
1504 #define	BGE_LPMBX_GEN5_LO		0x584C
1505 #define	BGE_LPMBX_GEN6_HI		0x5850
1506 #define	BGE_LPMBX_GEN6_LO		0x5854
1507 #define	BGE_LPMBX_GEN7_HI		0x5858
1508 #define	BGE_LPMBX_GEN7_LO		0x585C
1509 #define	BGE_LPMBX_RELOAD_STATS_HI	0x5860
1510 #define	BGE_LPMBX_RELOAD_STATS_LO	0x5864
1511 #define	BGE_LPMBX_RX_STD_PROD_HI	0x5868
1512 #define	BGE_LPMBX_RX_STD_PROD_LO	0x586C
1513 #define	BGE_LPMBX_RX_JUMBO_PROD_HI	0x5870
1514 #define	BGE_LPMBX_RX_JUMBO_PROD_LO	0x5874
1515 #define	BGE_LPMBX_RX_MINI_PROD_HI	0x5878
1516 #define	BGE_LPMBX_RX_MINI_PROD_LO	0x587C
1517 #define	BGE_LPMBX_RX_CONS0_HI		0x5880
1518 #define	BGE_LPMBX_RX_CONS0_LO		0x5884
1519 #define	BGE_LPMBX_RX_CONS1_HI		0x5888
1520 #define	BGE_LPMBX_RX_CONS1_LO		0x588C
1521 #define	BGE_LPMBX_RX_CONS2_HI		0x5890
1522 #define	BGE_LPMBX_RX_CONS2_LO		0x5894
1523 #define	BGE_LPMBX_RX_CONS3_HI		0x5898
1524 #define	BGE_LPMBX_RX_CONS3_LO		0x589C
1525 #define	BGE_LPMBX_RX_CONS4_HI		0x58A0
1526 #define	BGE_LPMBX_RX_CONS4_LO		0x58A4
1527 #define	BGE_LPMBX_RX_CONS5_HI		0x58A8
1528 #define	BGE_LPMBX_RX_CONS5_LO		0x58AC
1529 #define	BGE_LPMBX_RX_CONS6_HI		0x58B0
1530 #define	BGE_LPMBX_RX_CONS6_LO		0x58B4
1531 #define	BGE_LPMBX_RX_CONS7_HI		0x58B8
1532 #define	BGE_LPMBX_RX_CONS7_LO		0x58BC
1533 #define	BGE_LPMBX_RX_CONS8_HI		0x58C0
1534 #define	BGE_LPMBX_RX_CONS8_LO		0x58C4
1535 #define	BGE_LPMBX_RX_CONS9_HI		0x58C8
1536 #define	BGE_LPMBX_RX_CONS9_LO		0x58CC
1537 #define	BGE_LPMBX_RX_CONS10_HI		0x58D0
1538 #define	BGE_LPMBX_RX_CONS10_LO		0x58D4
1539 #define	BGE_LPMBX_RX_CONS11_HI		0x58D8
1540 #define	BGE_LPMBX_RX_CONS11_LO		0x58DC
1541 #define	BGE_LPMBX_RX_CONS12_HI		0x58E0
1542 #define	BGE_LPMBX_RX_CONS12_LO		0x58E4
1543 #define	BGE_LPMBX_RX_CONS13_HI		0x58E8
1544 #define	BGE_LPMBX_RX_CONS13_LO		0x58EC
1545 #define	BGE_LPMBX_RX_CONS14_HI		0x58F0
1546 #define	BGE_LPMBX_RX_CONS14_LO		0x58F4
1547 #define	BGE_LPMBX_RX_CONS15_HI		0x58F8
1548 #define	BGE_LPMBX_RX_CONS15_LO		0x58FC
1549 #define	BGE_LPMBX_TX_HOST_PROD0_HI	0x5900
1550 #define	BGE_LPMBX_TX_HOST_PROD0_LO	0x5904
1551 #define	BGE_LPMBX_TX_HOST_PROD1_HI	0x5908
1552 #define	BGE_LPMBX_TX_HOST_PROD1_LO	0x590C
1553 #define	BGE_LPMBX_TX_HOST_PROD2_HI	0x5910
1554 #define	BGE_LPMBX_TX_HOST_PROD2_LO	0x5914
1555 #define	BGE_LPMBX_TX_HOST_PROD3_HI	0x5918
1556 #define	BGE_LPMBX_TX_HOST_PROD3_LO	0x591C
1557 #define	BGE_LPMBX_TX_HOST_PROD4_HI	0x5920
1558 #define	BGE_LPMBX_TX_HOST_PROD4_LO	0x5924
1559 #define	BGE_LPMBX_TX_HOST_PROD5_HI	0x5928
1560 #define	BGE_LPMBX_TX_HOST_PROD5_LO	0x592C
1561 #define	BGE_LPMBX_TX_HOST_PROD6_HI	0x5930
1562 #define	BGE_LPMBX_TX_HOST_PROD6_LO	0x5934
1563 #define	BGE_LPMBX_TX_HOST_PROD7_HI	0x5938
1564 #define	BGE_LPMBX_TX_HOST_PROD7_LO	0x593C
1565 #define	BGE_LPMBX_TX_HOST_PROD8_HI	0x5940
1566 #define	BGE_LPMBX_TX_HOST_PROD8_LO	0x5944
1567 #define	BGE_LPMBX_TX_HOST_PROD9_HI	0x5948
1568 #define	BGE_LPMBX_TX_HOST_PROD9_LO	0x594C
1569 #define	BGE_LPMBX_TX_HOST_PROD10_HI	0x5950
1570 #define	BGE_LPMBX_TX_HOST_PROD10_LO	0x5954
1571 #define	BGE_LPMBX_TX_HOST_PROD11_HI	0x5958
1572 #define	BGE_LPMBX_TX_HOST_PROD11_LO	0x595C
1573 #define	BGE_LPMBX_TX_HOST_PROD12_HI	0x5960
1574 #define	BGE_LPMBX_TX_HOST_PROD12_LO	0x5964
1575 #define	BGE_LPMBX_TX_HOST_PROD13_HI	0x5968
1576 #define	BGE_LPMBX_TX_HOST_PROD13_LO	0x596C
1577 #define	BGE_LPMBX_TX_HOST_PROD14_HI	0x5970
1578 #define	BGE_LPMBX_TX_HOST_PROD14_LO	0x5974
1579 #define	BGE_LPMBX_TX_HOST_PROD15_HI	0x5978
1580 #define	BGE_LPMBX_TX_HOST_PROD15_LO	0x597C
1581 #define	BGE_LPMBX_TX_NIC_PROD0_HI	0x5980
1582 #define	BGE_LPMBX_TX_NIC_PROD0_LO	0x5984
1583 #define	BGE_LPMBX_TX_NIC_PROD1_HI	0x5988
1584 #define	BGE_LPMBX_TX_NIC_PROD1_LO	0x598C
1585 #define	BGE_LPMBX_TX_NIC_PROD2_HI	0x5990
1586 #define	BGE_LPMBX_TX_NIC_PROD2_LO	0x5994
1587 #define	BGE_LPMBX_TX_NIC_PROD3_HI	0x5998
1588 #define	BGE_LPMBX_TX_NIC_PROD3_LO	0x599C
1589 #define	BGE_LPMBX_TX_NIC_PROD4_HI	0x59A0
1590 #define	BGE_LPMBX_TX_NIC_PROD4_LO	0x59A4
1591 #define	BGE_LPMBX_TX_NIC_PROD5_HI	0x59A8
1592 #define	BGE_LPMBX_TX_NIC_PROD5_LO	0x59AC
1593 #define	BGE_LPMBX_TX_NIC_PROD6_HI	0x59B0
1594 #define	BGE_LPMBX_TX_NIC_PROD6_LO	0x59B4
1595 #define	BGE_LPMBX_TX_NIC_PROD7_HI	0x59B8
1596 #define	BGE_LPMBX_TX_NIC_PROD7_LO	0x59BC
1597 #define	BGE_LPMBX_TX_NIC_PROD8_HI	0x59C0
1598 #define	BGE_LPMBX_TX_NIC_PROD8_LO	0x59C4
1599 #define	BGE_LPMBX_TX_NIC_PROD9_HI	0x59C8
1600 #define	BGE_LPMBX_TX_NIC_PROD9_LO	0x59CC
1601 #define	BGE_LPMBX_TX_NIC_PROD10_HI	0x59D0
1602 #define	BGE_LPMBX_TX_NIC_PROD10_LO	0x59D4
1603 #define	BGE_LPMBX_TX_NIC_PROD11_HI	0x59D8
1604 #define	BGE_LPMBX_TX_NIC_PROD11_LO	0x59DC
1605 #define	BGE_LPMBX_TX_NIC_PROD12_HI	0x59E0
1606 #define	BGE_LPMBX_TX_NIC_PROD12_LO	0x59E4
1607 #define	BGE_LPMBX_TX_NIC_PROD13_HI	0x59E8
1608 #define	BGE_LPMBX_TX_NIC_PROD13_LO	0x59EC
1609 #define	BGE_LPMBX_TX_NIC_PROD14_HI	0x59F0
1610 #define	BGE_LPMBX_TX_NIC_PROD14_LO	0x59F4
1611 #define	BGE_LPMBX_TX_NIC_PROD15_HI	0x59F8
1612 #define	BGE_LPMBX_TX_NIC_PROD15_LO	0x59FC
1613 
1614 /*
1615  * Flow throw Queue reset register
1616  */
1617 #define	BGE_FTQ_RESET			0x5C00
1618 
1619 #define	BGE_FTQRESET_DMAREAD		0x00000002
1620 #define	BGE_FTQRESET_DMAHIPRIO_RD	0x00000004
1621 #define	BGE_FTQRESET_DMADONE		0x00000010
1622 #define	BGE_FTQRESET_SBDC		0x00000020
1623 #define	BGE_FTQRESET_SDI		0x00000040
1624 #define	BGE_FTQRESET_WDMA		0x00000080
1625 #define	BGE_FTQRESET_DMAHIPRIO_WR	0x00000100
1626 #define	BGE_FTQRESET_TYPE1_SOFTWARE	0x00000200
1627 #define	BGE_FTQRESET_SDC		0x00000400
1628 #define	BGE_FTQRESET_HCC		0x00000800
1629 #define	BGE_FTQRESET_TXFIFO		0x00001000
1630 #define	BGE_FTQRESET_MBC		0x00002000
1631 #define	BGE_FTQRESET_RBDC		0x00004000
1632 #define	BGE_FTQRESET_RXLP		0x00008000
1633 #define	BGE_FTQRESET_RDBDI		0x00010000
1634 #define	BGE_FTQRESET_RDC		0x00020000
1635 #define	BGE_FTQRESET_TYPE2_SOFTWARE	0x00040000
1636 
1637 /*
1638  * Message Signaled Interrupt registers
1639  */
1640 #define	BGE_MSI_MODE			0x6000
1641 #define	BGE_MSI_STATUS			0x6004
1642 #define	BGE_MSI_FIFOACCESS		0x6008
1643 
1644 /* MSI mode register */
1645 #define	BGE_MSIMODE_RESET		0x00000001
1646 #define	BGE_MSIMODE_ENABLE		0x00000002
1647 #define	BGE_MSIMODE_PCI_TGT_ABRT_ATTN	0x00000004
1648 #define	BGE_MSIMODE_PCI_MSTR_ABRT_ATTN	0x00000008
1649 #define	BGE_MSIMODE_PCI_PERR_ATTN	0x00000010
1650 #define	BGE_MSIMODE_MSI_FIFOUFLOW_ATTN	0x00000020
1651 #define	BGE_MSIMODE_MSI_FIFOOFLOW_ATTN	0x00000040
1652 
1653 /* MSI status register */
1654 #define	BGE_MSISTAT_PCI_TGT_ABRT_ATTN	0x00000004
1655 #define	BGE_MSISTAT_PCI_MSTR_ABRT_ATTN	0x00000008
1656 #define	BGE_MSISTAT_PCI_PERR_ATTN	0x00000010
1657 #define	BGE_MSISTAT_MSI_FIFOUFLOW_ATTN	0x00000020
1658 #define	BGE_MSISTAT_MSI_FIFOOFLOW_ATTN	0x00000040
1659 
1660 
1661 /*
1662  * DMA Completion registers
1663  */
1664 #define	BGE_DMAC_MODE			0x6400
1665 
1666 /* DMA Completion mode register */
1667 #define	BGE_DMACMODE_RESET		0x00000001
1668 #define	BGE_DMACMODE_ENABLE		0x00000002
1669 
1670 
1671 /*
1672  * General control registers.
1673  */
1674 #define	BGE_MODE_CTL			0x6800
1675 #define	BGE_MISC_CFG			0x6804
1676 #define	BGE_MISC_LOCAL_CTL		0x6808
1677 #define	BGE_CPU_EVENT			0x6810
1678 #define	BGE_EE_ADDR			0x6838
1679 #define	BGE_EE_DATA			0x683C
1680 #define	BGE_EE_CTL			0x6840
1681 #define	BGE_MDI_CTL			0x6844
1682 #define	BGE_EE_DELAY			0x6848
1683 #define	BGE_FASTBOOT_PC			0x6894
1684 
1685 /* Mode control register */
1686 #define	BGE_MODECTL_INT_SNDCOAL_ONLY	0x00000001
1687 #define	BGE_MODECTL_BYTESWAP_NONFRAME	0x00000002
1688 #define	BGE_MODECTL_WORDSWAP_NONFRAME	0x00000004
1689 #define	BGE_MODECTL_BYTESWAP_DATA	0x00000010
1690 #define	BGE_MODECTL_WORDSWAP_DATA	0x00000020
1691 #define	BGE_MODECTL_NO_FRAME_CRACKING	0x00000200
1692 #define	BGE_MODECTL_NO_RX_CRC		0x00000400
1693 #define	BGE_MODECTL_RX_BADFRAMES	0x00000800
1694 #define	BGE_MODECTL_NO_TX_INTR		0x00002000
1695 #define	BGE_MODECTL_NO_RX_INTR		0x00004000
1696 #define	BGE_MODECTL_FORCE_PCI32		0x00008000
1697 #define	BGE_MODECTL_STACKUP		0x00010000
1698 #define	BGE_MODECTL_HOST_SEND_BDS	0x00020000
1699 #define	BGE_MODECTL_TX_NO_PHDR_CSUM	0x00100000
1700 #define	BGE_MODECTL_RX_NO_PHDR_CSUM	0x00800000
1701 #define	BGE_MODECTL_TX_ATTN_INTR	0x01000000
1702 #define	BGE_MODECTL_RX_ATTN_INTR	0x02000000
1703 #define	BGE_MODECTL_MAC_ATTN_INTR	0x04000000
1704 #define	BGE_MODECTL_DMA_ATTN_INTR	0x08000000
1705 #define	BGE_MODECTL_FLOWCTL_ATTN_INTR	0x10000000
1706 #define	BGE_MODECTL_4X_SENDRING_SZ	0x20000000
1707 #define	BGE_MODECTL_FW_PROCESS_MCASTS	0x40000000
1708 
1709 /* Misc. config register */
1710 #define	BGE_MISCCFG_RESET_CORE_CLOCKS	0x00000001
1711 #define	BGE_MISCCFG_TIMER_PRESCALER	0x000000FE
1712 
1713 #define	BGE_32BITTIME_66MHZ		(0x41 << 1)
1714 
1715 /* Misc. Local Control */
1716 #define	BGE_MLC_INTR_STATE		0x00000001
1717 #define	BGE_MLC_INTR_CLR		0x00000002
1718 #define	BGE_MLC_INTR_SET		0x00000004
1719 #define	BGE_MLC_INTR_ONATTN		0x00000008
1720 #define	BGE_MLC_MISCIO_IN0		0x00000100
1721 #define	BGE_MLC_MISCIO_IN1		0x00000200
1722 #define	BGE_MLC_MISCIO_IN2		0x00000400
1723 #define	BGE_MLC_MISCIO_OUTEN0		0x00000800
1724 #define	BGE_MLC_MISCIO_OUTEN1		0x00001000
1725 #define	BGE_MLC_MISCIO_OUTEN2		0x00002000
1726 #define	BGE_MLC_MISCIO_OUT0		0x00004000
1727 #define	BGE_MLC_MISCIO_OUT1		0x00008000
1728 #define	BGE_MLC_MISCIO_OUT2		0x00010000
1729 #define	BGE_MLC_EXTRAM_ENB		0x00020000
1730 #define	BGE_MLC_SRAM_SIZE		0x001C0000
1731 #define	BGE_MLC_BANK_SEL		0x00200000 /* 0 = 2 banks, 1 == 1 */
1732 #define	BGE_MLC_SSRAM_TYPE		0x00400000 /* 1 = ZBT, 0 = standard */
1733 #define	BGE_MLC_SSRAM_CYC_DESEL		0x00800000
1734 #define	BGE_MLC_AUTO_EEPROM		0x01000000
1735 
1736 #define	BGE_SSRAMSIZE_256KB		0x00000000
1737 #define	BGE_SSRAMSIZE_512KB		0x00040000
1738 #define	BGE_SSRAMSIZE_1MB		0x00080000
1739 #define	BGE_SSRAMSIZE_2MB		0x000C0000
1740 #define	BGE_SSRAMSIZE_4MB		0x00100000
1741 #define	BGE_SSRAMSIZE_8MB		0x00140000
1742 #define	BGE_SSRAMSIZE_16M		0x00180000
1743 
1744 /* EEPROM address register */
1745 #define	BGE_EEADDR_ADDRESS		0x0000FFFC
1746 #define	BGE_EEADDR_HALFCLK		0x01FF0000
1747 #define	BGE_EEADDR_START		0x02000000
1748 #define	BGE_EEADDR_DEVID		0x1C000000
1749 #define	BGE_EEADDR_RESET		0x20000000
1750 #define	BGE_EEADDR_DONE			0x40000000
1751 #define	BGE_EEADDR_RW			0x80000000 /* 1 = rd, 0 = wr */
1752 
1753 #define	BGE_EEDEVID(x)			((x & 7) << 26)
1754 #define	BGE_EEHALFCLK(x)		((x & 0x1FF) << 16)
1755 #define	BGE_HALFCLK_384SCL		0x60
1756 #define	BGE_EE_READCMD \
1757 	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
1758 	BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
1759 #define	BGE_EE_WRCMD \
1760 	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
1761 	BGE_EEADDR_START|BGE_EEADDR_DONE)
1762 
1763 /* EEPROM Control register */
1764 #define	BGE_EECTL_CLKOUT_TRISTATE	0x00000001
1765 #define	BGE_EECTL_CLKOUT		0x00000002
1766 #define	BGE_EECTL_CLKIN			0x00000004
1767 #define	BGE_EECTL_DATAOUT_TRISTATE	0x00000008
1768 #define	BGE_EECTL_DATAOUT		0x00000010
1769 #define	BGE_EECTL_DATAIN		0x00000020
1770 
1771 /* MDI (MII/GMII) access register */
1772 #define	BGE_MDI_DATA			0x00000001
1773 #define	BGE_MDI_DIR			0x00000002
1774 #define	BGE_MDI_SEL			0x00000004
1775 #define	BGE_MDI_CLK			0x00000008
1776 
1777 #define	BGE_MEMWIN_START		0x00008000
1778 #define	BGE_MEMWIN_END			0x0000FFFF
1779 
1780 
1781 #define	BGE_MEMWIN_READ(sc, x, val)					\
1782 	do {								\
1783 		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
1784 		    (0xFFFF0000 & x), 4);				\
1785 		val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF));	\
1786 	} while(0)
1787 
1788 #define	BGE_MEMWIN_WRITE(sc, x, val)					\
1789 	do {								\
1790 		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
1791 		    (0xFFFF0000 & x), 4);				\
1792 		CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val);	\
1793 	} while(0)
1794 
1795 /*
1796  * This magic number is written to the firmware mailbox at 0xb50
1797  * before a software reset is issued.  After the internal firmware
1798  * has completed its initialization it will write the opposite of
1799  * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
1800  * driver to synchronize with the firmware.
1801  */
1802 #define	BGE_MAGIC_NUMBER                0x4B657654
1803 
1804 typedef struct {
1805 	uint32_t		bge_addr_hi;
1806 	uint32_t		bge_addr_lo;
1807 } bge_hostaddr;
1808 
1809 #define	BGE_HOSTADDR(x, y)						\
1810 	do {								\
1811 		(x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff);	\
1812 		(x).bge_addr_hi = ((uint64_t) (y) >> 32);		\
1813 	} while(0)
1814 
1815 #define	BGE_ADDR_LO(y)	\
1816 	((uint64_t) (y) & 0xFFFFFFFF)
1817 #define	BGE_ADDR_HI(y)	\
1818 	((uint64_t) (y) >> 32)
1819 
1820 /* Ring control block structure */
1821 struct bge_rcb {
1822 	bge_hostaddr		bge_hostaddr;
1823 	uint32_t		bge_maxlen_flags;
1824 	uint32_t		bge_nicaddr;
1825 };
1826 
1827 #define	RCB_WRITE_4(sc, rcb, offset, val) \
1828 	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \
1829 			  rcb + offsetof(struct bge_rcb, offset), val)
1830 #define	BGE_RCB_MAXLEN_FLAGS(maxlen, flags)	((maxlen) << 16 | (flags))
1831 
1832 #define	BGE_RCB_FLAG_USE_EXT_RX_BD	0x0001
1833 #define	BGE_RCB_FLAG_RING_DISABLED	0x0002
1834 
1835 struct bge_tx_bd {
1836 	bge_hostaddr		bge_addr;
1837 #if BYTE_ORDER == LITTLE_ENDIAN
1838 	uint16_t		bge_flags;
1839 	uint16_t		bge_len;
1840 	uint16_t		bge_vlan_tag;
1841 	uint16_t		bge_rsvd;
1842 #else
1843 	uint16_t		bge_len;
1844 	uint16_t		bge_flags;
1845 	uint16_t		bge_rsvd;
1846 	uint16_t		bge_vlan_tag;
1847 #endif
1848 };
1849 
1850 #define	BGE_TXBDFLAG_TCP_UDP_CSUM	0x0001
1851 #define	BGE_TXBDFLAG_IP_CSUM		0x0002
1852 #define	BGE_TXBDFLAG_END		0x0004
1853 #define	BGE_TXBDFLAG_IP_FRAG		0x0008
1854 #define	BGE_TXBDFLAG_IP_FRAG_END	0x0010
1855 #define	BGE_TXBDFLAG_VLAN_TAG		0x0040
1856 #define	BGE_TXBDFLAG_COAL_NOW		0x0080
1857 #define	BGE_TXBDFLAG_CPU_PRE_DMA	0x0100
1858 #define	BGE_TXBDFLAG_CPU_POST_DMA	0x0200
1859 #define	BGE_TXBDFLAG_INSERT_SRC_ADDR	0x1000
1860 #define	BGE_TXBDFLAG_CHOOSE_SRC_ADDR	0x6000
1861 #define	BGE_TXBDFLAG_NO_CRC		0x8000
1862 
1863 #define	BGE_NIC_TXRING_ADDR(ringno, size)	\
1864 	BGE_SEND_RING_1_TO_4 +			\
1865 	((ringno * sizeof(struct bge_tx_bd) * size) / 4)
1866 
1867 struct bge_rx_bd {
1868 	bge_hostaddr		bge_addr;
1869 #if BYTE_ORDER == LITTLE_ENDIAN
1870 	uint16_t		bge_len;
1871 	uint16_t		bge_idx;
1872 	uint16_t		bge_flags;
1873 	uint16_t		bge_type;
1874 	uint16_t		bge_tcp_udp_csum;
1875 	uint16_t		bge_ip_csum;
1876 	uint16_t		bge_vlan_tag;
1877 	uint16_t		bge_error_flag;
1878 #else
1879 	uint16_t		bge_idx;
1880 	uint16_t		bge_len;
1881 	uint16_t		bge_type;
1882 	uint16_t		bge_flags;
1883 	uint16_t		bge_ip_csum;
1884 	uint16_t		bge_tcp_udp_csum;
1885 	uint16_t		bge_error_flag;
1886 	uint16_t		bge_vlan_tag;
1887 #endif
1888 	uint32_t		bge_rsvd;
1889 	uint32_t		bge_opaque;
1890 };
1891 
1892 struct bge_extrx_bd {
1893 	bge_hostaddr		bge_addr1;
1894 	bge_hostaddr		bge_addr2;
1895 	bge_hostaddr		bge_addr3;
1896 #if BYTE_ORDER == LITTLE_ENDIAN
1897 	uint16_t		bge_len2;
1898 	uint16_t		bge_len1;
1899 	uint16_t		bge_rsvd1;
1900 	uint16_t		bge_len3;
1901 #else
1902 	uint16_t		bge_len1;
1903 	uint16_t		bge_len2;
1904 	uint16_t		bge_len3;
1905 	uint16_t		bge_rsvd1;
1906 #endif
1907 	bge_hostaddr		bge_addr0;
1908 #if BYTE_ORDER == LITTLE_ENDIAN
1909 	uint16_t		bge_len0;
1910 	uint16_t		bge_idx;
1911 	uint16_t		bge_flags;
1912 	uint16_t		bge_type;
1913 	uint16_t		bge_tcp_udp_csum;
1914 	uint16_t		bge_ip_csum;
1915 	uint16_t		bge_vlan_tag;
1916 	uint16_t		bge_error_flag;
1917 #else
1918 	uint16_t		bge_idx;
1919 	uint16_t		bge_len0;
1920 	uint16_t		bge_type;
1921 	uint16_t		bge_flags;
1922 	uint16_t		bge_ip_csum;
1923 	uint16_t		bge_tcp_udp_csum;
1924 	uint16_t		bge_error_flag;
1925 	uint16_t		bge_vlan_tag;
1926 #endif
1927 	uint32_t		bge_rsvd0;
1928 	uint32_t		bge_opaque;
1929 };
1930 
1931 #define	BGE_RXBDFLAG_END		0x0004
1932 #define	BGE_RXBDFLAG_JUMBO_RING		0x0020
1933 #define	BGE_RXBDFLAG_VLAN_TAG		0x0040
1934 #define	BGE_RXBDFLAG_ERROR		0x0400
1935 #define	BGE_RXBDFLAG_MINI_RING		0x0800
1936 #define	BGE_RXBDFLAG_IP_CSUM		0x1000
1937 #define	BGE_RXBDFLAG_TCP_UDP_CSUM	0x2000
1938 #define	BGE_RXBDFLAG_TCP_UDP_IS_TCP	0x4000
1939 
1940 #define	BGE_RXERRFLAG_BAD_CRC		0x0001
1941 #define	BGE_RXERRFLAG_COLL_DETECT	0x0002
1942 #define	BGE_RXERRFLAG_LINK_LOST		0x0004
1943 #define	BGE_RXERRFLAG_PHY_DECODE_ERR	0x0008
1944 #define	BGE_RXERRFLAG_MAC_ABORT		0x0010
1945 #define	BGE_RXERRFLAG_RUNT		0x0020
1946 #define	BGE_RXERRFLAG_TRUNC_NO_RSRCS	0x0040
1947 #define	BGE_RXERRFLAG_GIANT		0x0080
1948 
1949 struct bge_sts_idx {
1950 #if BYTE_ORDER == LITTLE_ENDIAN
1951 	uint16_t		bge_rx_prod_idx;
1952 	uint16_t		bge_tx_cons_idx;
1953 #else
1954 	uint16_t		bge_tx_cons_idx;
1955 	uint16_t		bge_rx_prod_idx;
1956 #endif
1957 };
1958 
1959 struct bge_status_block {
1960 	uint32_t		bge_status;
1961 	uint32_t		bge_rsvd0;
1962 #if BYTE_ORDER == LITTLE_ENDIAN
1963 	uint16_t		bge_rx_jumbo_cons_idx;
1964 	uint16_t		bge_rx_std_cons_idx;
1965 	uint16_t		bge_rx_mini_cons_idx;
1966 	uint16_t		bge_rsvd1;
1967 #else
1968 	uint16_t		bge_rx_std_cons_idx;
1969 	uint16_t		bge_rx_jumbo_cons_idx;
1970 	uint16_t		bge_rsvd1;
1971 	uint16_t		bge_rx_mini_cons_idx;
1972 #endif
1973 	struct bge_sts_idx	bge_idx[16];
1974 };
1975 
1976 #define	BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx
1977 #define	BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx
1978 
1979 #define	BGE_STATFLAG_UPDATED		0x00000001
1980 #define	BGE_STATFLAG_LINKSTATE_CHANGED	0x00000002
1981 #define	BGE_STATFLAG_ERROR		0x00000004
1982 
1983 
1984 /*
1985  * Broadcom Vendor ID
1986  * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
1987  * even though they're now manufactured by Broadcom)
1988  */
1989 #define	BCOM_VENDORID			0x14E4
1990 #define	BCOM_DEVICEID_BCM5700		0x1644
1991 #define	BCOM_DEVICEID_BCM5701		0x1645
1992 #define	BCOM_DEVICEID_BCM5702		0x1646
1993 #define	BCOM_DEVICEID_BCM5702X		0x16A6
1994 #define	BCOM_DEVICEID_BCM5702_ALT	0x16C6
1995 #define	BCOM_DEVICEID_BCM5703		0x1647
1996 #define	BCOM_DEVICEID_BCM5703X		0x16A7
1997 #define	BCOM_DEVICEID_BCM5703_ALT	0x16C7
1998 #define	BCOM_DEVICEID_BCM5704C		0x1648
1999 #define	BCOM_DEVICEID_BCM5704S		0x16A8
2000 #define	BCOM_DEVICEID_BCM5704S_ALT	0x1649
2001 #define	BCOM_DEVICEID_BCM5705		0x1653
2002 #define	BCOM_DEVICEID_BCM5705K		0x1654
2003 #define	BCOM_DEVICEID_BCM5705F		0x166E
2004 #define	BCOM_DEVICEID_BCM5705M		0x165D
2005 #define	BCOM_DEVICEID_BCM5705M_ALT	0x165E
2006 #define	BCOM_DEVICEID_BCM5714C		0x1668
2007 #define	BCOM_DEVICEID_BCM5714S		0x1669
2008 #define	BCOM_DEVICEID_BCM5715		0x1678
2009 #define	BCOM_DEVICEID_BCM5715S		0x1679
2010 #define	BCOM_DEVICEID_BCM5720		0x1658
2011 #define	BCOM_DEVICEID_BCM5721		0x1659
2012 #define	BCOM_DEVICEID_BCM5750		0x1676
2013 #define	BCOM_DEVICEID_BCM5750M		0x167C
2014 #define	BCOM_DEVICEID_BCM5751		0x1677
2015 #define	BCOM_DEVICEID_BCM5751F		0x167E
2016 #define	BCOM_DEVICEID_BCM5751M		0x167D
2017 #define	BCOM_DEVICEID_BCM5752		0x1600
2018 #define	BCOM_DEVICEID_BCM5752M		0x1601
2019 #define	BCOM_DEVICEID_BCM5753		0x16F7
2020 #define	BCOM_DEVICEID_BCM5753F		0x16FE
2021 #define	BCOM_DEVICEID_BCM5753M		0x16FD
2022 #define	BCOM_DEVICEID_BCM5754		0x167A
2023 #define	BCOM_DEVICEID_BCM5754M		0x1672
2024 #define	BCOM_DEVICEID_BCM5755		0x167B
2025 #define	BCOM_DEVICEID_BCM5755M		0x1673
2026 #define	BCOM_DEVICEID_BCM5780		0x166A
2027 #define	BCOM_DEVICEID_BCM5780S		0x166B
2028 #define	BCOM_DEVICEID_BCM5781		0x16DD
2029 #define	BCOM_DEVICEID_BCM5782		0x1696
2030 #define	BCOM_DEVICEID_BCM5786		0x169A
2031 #define	BCOM_DEVICEID_BCM5787		0x169B
2032 #define	BCOM_DEVICEID_BCM5787M		0x1693
2033 #define	BCOM_DEVICEID_BCM5788		0x169C
2034 #define	BCOM_DEVICEID_BCM5789		0x169D
2035 #define	BCOM_DEVICEID_BCM5901		0x170D
2036 #define	BCOM_DEVICEID_BCM5901A2		0x170E
2037 #define	BCOM_DEVICEID_BCM5903M		0x16FF
2038 
2039 /*
2040  * Alteon AceNIC PCI vendor/device ID.
2041  */
2042 #define	ALTEON_VENDORID			0x12AE
2043 #define	ALTEON_DEVICEID_ACENIC		0x0001
2044 #define	ALTEON_DEVICEID_ACENIC_COPPER	0x0002
2045 #define	ALTEON_DEVICEID_BCM5700		0x0003
2046 #define	ALTEON_DEVICEID_BCM5701		0x0004
2047 
2048 /*
2049  * 3Com 3c996 PCI vendor/device ID.
2050  */
2051 #define	TC_VENDORID			0x10B7
2052 #define	TC_DEVICEID_3C996		0x0003
2053 
2054 /*
2055  * SysKonnect PCI vendor ID
2056  */
2057 #define	SK_VENDORID			0x1148
2058 #define	SK_DEVICEID_ALTIMA		0x4400
2059 #define	SK_SUBSYSID_9D21		0x4421
2060 #define	SK_SUBSYSID_9D41		0x4441
2061 
2062 /*
2063  * Altima PCI vendor/device ID.
2064  */
2065 #define	ALTIMA_VENDORID			0x173b
2066 #define	ALTIMA_DEVICE_AC1000		0x03e8
2067 #define	ALTIMA_DEVICE_AC1002		0x03e9
2068 #define	ALTIMA_DEVICE_AC9100		0x03ea
2069 
2070 /*
2071  * Dell PCI vendor ID
2072  */
2073 
2074 #define	DELL_VENDORID			0x1028
2075 
2076 /*
2077  * Apple PCI vendor ID.
2078  */
2079 #define	APPLE_VENDORID			0x106b
2080 #define	APPLE_DEVICE_BCM5701		0x1645
2081 
2082 /*
2083  * Offset of MAC address inside EEPROM.
2084  */
2085 #define	BGE_EE_MAC_OFFSET		0x7C
2086 #define	BGE_EE_HWCFG_OFFSET		0xC8
2087 
2088 #define	BGE_HWCFG_VOLTAGE		0x00000003
2089 #define	BGE_HWCFG_PHYLED_MODE		0x0000000C
2090 #define	BGE_HWCFG_MEDIA			0x00000030
2091 #define	BGE_HWCFG_ASF			0x00000080
2092 
2093 #define	BGE_VOLTAGE_1POINT3		0x00000000
2094 #define	BGE_VOLTAGE_1POINT8		0x00000001
2095 
2096 #define	BGE_PHYLEDMODE_UNSPEC		0x00000000
2097 #define	BGE_PHYLEDMODE_TRIPLELED	0x00000004
2098 #define	BGE_PHYLEDMODE_SINGLELED	0x00000008
2099 
2100 #define	BGE_MEDIA_UNSPEC		0x00000000
2101 #define	BGE_MEDIA_COPPER		0x00000010
2102 #define	BGE_MEDIA_FIBER			0x00000020
2103 
2104 #define	BGE_PCI_READ_CMD		0x06000000
2105 #define	BGE_PCI_WRITE_CMD		0x70000000
2106 
2107 #define	BGE_TICKS_PER_SEC		1000000
2108 
2109 /*
2110  * Ring size constants.
2111  */
2112 #define	BGE_EVENT_RING_CNT	256
2113 #define	BGE_CMD_RING_CNT	64
2114 #define	BGE_STD_RX_RING_CNT	512
2115 #define	BGE_JUMBO_RX_RING_CNT	256
2116 #define	BGE_MINI_RX_RING_CNT	1024
2117 #define	BGE_RETURN_RING_CNT	1024
2118 
2119 /* 5705 has smaller return ring size */
2120 
2121 #define	BGE_RETURN_RING_CNT_5705	512
2122 
2123 /*
2124  * Possible TX ring sizes.
2125  */
2126 #define	BGE_TX_RING_CNT_128	128
2127 #define	BGE_TX_RING_BASE_128	0x3800
2128 
2129 #define	BGE_TX_RING_CNT_256	256
2130 #define	BGE_TX_RING_BASE_256	0x3000
2131 
2132 #define	BGE_TX_RING_CNT_512	512
2133 #define	BGE_TX_RING_BASE_512	0x2000
2134 
2135 #define	BGE_TX_RING_CNT		BGE_TX_RING_CNT_512
2136 #define	BGE_TX_RING_BASE	BGE_TX_RING_BASE_512
2137 
2138 /*
2139  * Tigon III statistics counters.
2140  */
2141 /* Statistics maintained MAC Receive block. */
2142 struct bge_rx_mac_stats {
2143 	bge_hostaddr		ifHCInOctets;
2144 	bge_hostaddr		Reserved1;
2145 	bge_hostaddr		etherStatsFragments;
2146 	bge_hostaddr		ifHCInUcastPkts;
2147 	bge_hostaddr		ifHCInMulticastPkts;
2148 	bge_hostaddr		ifHCInBroadcastPkts;
2149 	bge_hostaddr		dot3StatsFCSErrors;
2150 	bge_hostaddr		dot3StatsAlignmentErrors;
2151 	bge_hostaddr		xonPauseFramesReceived;
2152 	bge_hostaddr		xoffPauseFramesReceived;
2153 	bge_hostaddr		macControlFramesReceived;
2154 	bge_hostaddr		xoffStateEntered;
2155 	bge_hostaddr		dot3StatsFramesTooLong;
2156 	bge_hostaddr		etherStatsJabbers;
2157 	bge_hostaddr		etherStatsUndersizePkts;
2158 	bge_hostaddr		inRangeLengthError;
2159 	bge_hostaddr		outRangeLengthError;
2160 	bge_hostaddr		etherStatsPkts64Octets;
2161 	bge_hostaddr		etherStatsPkts65Octetsto127Octets;
2162 	bge_hostaddr		etherStatsPkts128Octetsto255Octets;
2163 	bge_hostaddr		etherStatsPkts256Octetsto511Octets;
2164 	bge_hostaddr		etherStatsPkts512Octetsto1023Octets;
2165 	bge_hostaddr		etherStatsPkts1024Octetsto1522Octets;
2166 	bge_hostaddr		etherStatsPkts1523Octetsto2047Octets;
2167 	bge_hostaddr		etherStatsPkts2048Octetsto4095Octets;
2168 	bge_hostaddr		etherStatsPkts4096Octetsto8191Octets;
2169 	bge_hostaddr		etherStatsPkts8192Octetsto9022Octets;
2170 };
2171 
2172 
2173 /* Statistics maintained MAC Transmit block. */
2174 struct bge_tx_mac_stats {
2175 	bge_hostaddr		ifHCOutOctets;
2176 	bge_hostaddr		Reserved2;
2177 	bge_hostaddr		etherStatsCollisions;
2178 	bge_hostaddr		outXonSent;
2179 	bge_hostaddr		outXoffSent;
2180 	bge_hostaddr		flowControlDone;
2181 	bge_hostaddr		dot3StatsInternalMacTransmitErrors;
2182 	bge_hostaddr		dot3StatsSingleCollisionFrames;
2183 	bge_hostaddr		dot3StatsMultipleCollisionFrames;
2184 	bge_hostaddr		dot3StatsDeferredTransmissions;
2185 	bge_hostaddr		Reserved3;
2186 	bge_hostaddr		dot3StatsExcessiveCollisions;
2187 	bge_hostaddr		dot3StatsLateCollisions;
2188 	bge_hostaddr		dot3Collided2Times;
2189 	bge_hostaddr		dot3Collided3Times;
2190 	bge_hostaddr		dot3Collided4Times;
2191 	bge_hostaddr		dot3Collided5Times;
2192 	bge_hostaddr		dot3Collided6Times;
2193 	bge_hostaddr		dot3Collided7Times;
2194 	bge_hostaddr		dot3Collided8Times;
2195 	bge_hostaddr		dot3Collided9Times;
2196 	bge_hostaddr		dot3Collided10Times;
2197 	bge_hostaddr		dot3Collided11Times;
2198 	bge_hostaddr		dot3Collided12Times;
2199 	bge_hostaddr		dot3Collided13Times;
2200 	bge_hostaddr		dot3Collided14Times;
2201 	bge_hostaddr		dot3Collided15Times;
2202 	bge_hostaddr		ifHCOutUcastPkts;
2203 	bge_hostaddr		ifHCOutMulticastPkts;
2204 	bge_hostaddr		ifHCOutBroadcastPkts;
2205 	bge_hostaddr		dot3StatsCarrierSenseErrors;
2206 	bge_hostaddr		ifOutDiscards;
2207 	bge_hostaddr		ifOutErrors;
2208 };
2209 
2210 /* Stats counters access through registers */
2211 struct bge_mac_stats_regs {
2212 	uint32_t		ifHCOutOctets;
2213 	uint32_t		Reserved0;
2214 	uint32_t		etherStatsCollisions;
2215 	uint32_t		outXonSent;
2216 	uint32_t		outXoffSent;
2217 	uint32_t		Reserved1;
2218 	uint32_t		dot3StatsInternalMacTransmitErrors;
2219 	uint32_t		dot3StatsSingleCollisionFrames;
2220 	uint32_t		dot3StatsMultipleCollisionFrames;
2221 	uint32_t		dot3StatsDeferredTransmissions;
2222 	uint32_t		Reserved2;
2223 	uint32_t		dot3StatsExcessiveCollisions;
2224 	uint32_t		dot3StatsLateCollisions;
2225 	uint32_t		Reserved3[14];
2226 	uint32_t		ifHCOutUcastPkts;
2227 	uint32_t		ifHCOutMulticastPkts;
2228 	uint32_t		ifHCOutBroadcastPkts;
2229 	uint32_t		Reserved4[2];
2230 	uint32_t		ifHCInOctets;
2231 	uint32_t		Reserved5;
2232 	uint32_t		etherStatsFragments;
2233 	uint32_t		ifHCInUcastPkts;
2234 	uint32_t		ifHCInMulticastPkts;
2235 	uint32_t		ifHCInBroadcastPkts;
2236 	uint32_t		dot3StatsFCSErrors;
2237 	uint32_t		dot3StatsAlignmentErrors;
2238 	uint32_t		xonPauseFramesReceived;
2239 	uint32_t		xoffPauseFramesReceived;
2240 	uint32_t		macControlFramesReceived;
2241 	uint32_t		xoffStateEntered;
2242 	uint32_t		dot3StatsFramesTooLong;
2243 	uint32_t		etherStatsJabbers;
2244 	uint32_t		etherStatsUndersizePkts;
2245 };
2246 
2247 struct bge_stats {
2248 	uint8_t		Reserved0[256];
2249 
2250 	/* Statistics maintained by Receive MAC. */
2251 	struct bge_rx_mac_stats rxstats;
2252 
2253 	bge_hostaddr		Unused1[37];
2254 
2255 	/* Statistics maintained by Transmit MAC. */
2256 	struct bge_tx_mac_stats txstats;
2257 
2258 	bge_hostaddr		Unused2[31];
2259 
2260 	/* Statistics maintained by Receive List Placement. */
2261 	bge_hostaddr		COSIfHCInPkts[16];
2262 	bge_hostaddr		COSFramesDroppedDueToFilters;
2263 	bge_hostaddr		nicDmaWriteQueueFull;
2264 	bge_hostaddr		nicDmaWriteHighPriQueueFull;
2265 	bge_hostaddr		nicNoMoreRxBDs;
2266 	bge_hostaddr		ifInDiscards;
2267 	bge_hostaddr		ifInErrors;
2268 	bge_hostaddr		nicRecvThresholdHit;
2269 
2270 	bge_hostaddr		Unused3[9];
2271 
2272 	/* Statistics maintained by Send Data Initiator. */
2273 	bge_hostaddr		COSIfHCOutPkts[16];
2274 	bge_hostaddr		nicDmaReadQueueFull;
2275 	bge_hostaddr		nicDmaReadHighPriQueueFull;
2276 	bge_hostaddr		nicSendDataCompQueueFull;
2277 
2278 	/* Statistics maintained by Host Coalescing. */
2279 	bge_hostaddr		nicRingSetSendProdIndex;
2280 	bge_hostaddr		nicRingStatusUpdate;
2281 	bge_hostaddr		nicInterrupts;
2282 	bge_hostaddr		nicAvoidedInterrupts;
2283 	bge_hostaddr		nicSendThresholdHit;
2284 
2285 	uint8_t		Reserved4[320];
2286 };
2287 
2288 /*
2289  * Tigon general information block. This resides in host memory
2290  * and contains the status counters, ring control blocks and
2291  * producer pointers.
2292  */
2293 
2294 struct bge_gib {
2295 	struct bge_stats	bge_stats;
2296 	struct bge_rcb		bge_tx_rcb[16];
2297 	struct bge_rcb		bge_std_rx_rcb;
2298 	struct bge_rcb		bge_jumbo_rx_rcb;
2299 	struct bge_rcb		bge_mini_rx_rcb;
2300 	struct bge_rcb		bge_return_rcb;
2301 };
2302 
2303 #define	BGE_FRAMELEN		1518
2304 #define	BGE_MAX_FRAMELEN	1536
2305 #define	BGE_JUMBO_FRAMELEN	9018
2306 #define	BGE_JUMBO_MTU		(BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2307 #define	BGE_MIN_FRAMELEN		60
2308 
2309 /*
2310  * Other utility macros.
2311  */
2312 #define	BGE_INC(x, y)	(x) = (x + 1) % y
2313 
2314 /*
2315  * Register access macros. The Tigon always uses memory mapped register
2316  * accesses and all registers must be accessed with 32 bit operations.
2317  */
2318 
2319 #define	CSR_WRITE_4(sc, reg, val)	\
2320 	bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val)
2321 
2322 #define	CSR_READ_4(sc, reg)		\
2323 	bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
2324 
2325 #define	BGE_SETBIT(sc, reg, x)	\
2326 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2327 #define	BGE_CLRBIT(sc, reg, x)	\
2328 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2329 
2330 #define	PCI_SETBIT(dev, reg, x, s)	\
2331 	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2332 #define	PCI_CLRBIT(dev, reg, x, s)	\
2333 	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2334 
2335 /*
2336  * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS
2337  * values are tuneable. They control the actual amount of buffers
2338  * allocated for the standard, mini and jumbo receive rings.
2339  */
2340 
2341 #define	BGE_SSLOTS	256
2342 #define	BGE_MSLOTS	256
2343 #define	BGE_JSLOTS	384
2344 
2345 #define	BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN)
2346 #define	BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \
2347 	(BGE_JRAWLEN % sizeof(uint64_t))))
2348 #define	BGE_JPAGESZ PAGE_SIZE
2349 #define	BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ)
2350 #define	BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID)
2351 
2352 #define	BGE_NSEG_JUMBO	4
2353 #define	BGE_NSEG_NEW 32
2354 
2355 /*
2356  * Ring structures. Most of these reside in host memory and we tell
2357  * the NIC where they are via the ring control blocks. The exceptions
2358  * are the tx and command rings, which live in NIC memory and which
2359  * we access via the shared memory window.
2360  */
2361 
2362 struct bge_ring_data {
2363 	struct bge_rx_bd	*bge_rx_std_ring;
2364 	bus_addr_t		bge_rx_std_ring_paddr;
2365 	struct bge_extrx_bd	*bge_rx_jumbo_ring;
2366 	bus_addr_t		bge_rx_jumbo_ring_paddr;
2367 	struct bge_rx_bd	*bge_rx_return_ring;
2368 	bus_addr_t		bge_rx_return_ring_paddr;
2369 	struct bge_tx_bd	*bge_tx_ring;
2370 	bus_addr_t		bge_tx_ring_paddr;
2371 	struct bge_status_block	*bge_status_block;
2372 	bus_addr_t		bge_status_block_paddr;
2373 	struct bge_stats	*bge_stats;
2374 	bus_addr_t		bge_stats_paddr;
2375 	struct bge_gib		bge_info;
2376 };
2377 
2378 #define	BGE_STD_RX_RING_SZ	\
2379 	(sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2380 #define	BGE_JUMBO_RX_RING_SZ	\
2381 	(sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2382 #define	BGE_TX_RING_SZ		\
2383 	(sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2384 #define	BGE_RX_RTN_RING_SZ(x)	\
2385 	(sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2386 
2387 #define	BGE_STATUS_BLK_SZ	sizeof (struct bge_status_block)
2388 
2389 #define	BGE_STATS_SZ		sizeof (struct bge_stats)
2390 
2391 /*
2392  * Mbuf pointers. We need these to keep track of the virtual addresses
2393  * of our mbuf chains since we can only convert from physical to virtual,
2394  * not the other way around.
2395  */
2396 struct bge_chain_data {
2397 	bus_dma_tag_t		bge_parent_tag;
2398 	bus_dma_tag_t		bge_rx_std_ring_tag;
2399 	bus_dma_tag_t		bge_rx_jumbo_ring_tag;
2400 	bus_dma_tag_t		bge_rx_return_ring_tag;
2401 	bus_dma_tag_t		bge_tx_ring_tag;
2402 	bus_dma_tag_t		bge_status_tag;
2403 	bus_dma_tag_t		bge_stats_tag;
2404 	bus_dma_tag_t		bge_mtag;	/* mbuf mapping tag */
2405 	bus_dma_tag_t		bge_mtag_jumbo;	/* mbuf mapping tag */
2406 	bus_dmamap_t		bge_tx_dmamap[BGE_TX_RING_CNT];
2407 	bus_dmamap_t		bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2408 	bus_dmamap_t		bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2409 	bus_dmamap_t		bge_rx_std_ring_map;
2410 	bus_dmamap_t		bge_rx_jumbo_ring_map;
2411 	bus_dmamap_t		bge_tx_ring_map;
2412 	bus_dmamap_t		bge_rx_return_ring_map;
2413 	bus_dmamap_t		bge_status_map;
2414 	bus_dmamap_t		bge_stats_map;
2415 	struct mbuf		*bge_tx_chain[BGE_TX_RING_CNT];
2416 	struct mbuf		*bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2417 	struct mbuf		*bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2418 };
2419 
2420 struct bge_dmamap_arg {
2421 	struct bge_softc	*sc;
2422 	bus_addr_t		bge_busaddr;
2423 	uint16_t		bge_flags;
2424 	int			bge_idx;
2425 	int			bge_maxsegs;
2426 	struct bge_tx_bd	*bge_ring;
2427 };
2428 
2429 #define	BGE_HWREV_TIGON		0x01
2430 #define	BGE_HWREV_TIGON_II	0x02
2431 #define	BGE_TIMEOUT		100000
2432 #define	BGE_TXCONS_UNSET		0xFFFF	/* impossible value */
2433 
2434 struct bge_bcom_hack {
2435 	int			reg;
2436 	int			val;
2437 };
2438 
2439 #define	ASF_ENABLE		1
2440 #define	ASF_NEW_HANDSHAKE	2
2441 #define	ASF_STACKUP		4
2442 
2443 struct bge_softc {
2444 	struct ifnet		*bge_ifp;	/* interface info */
2445 	device_t		bge_dev;
2446 	struct mtx		bge_mtx;
2447 	device_t		bge_miibus;
2448 	bus_space_handle_t	bge_bhandle;
2449 	bus_space_tag_t		bge_btag;
2450 	void			*bge_intrhand;
2451 	struct resource		*bge_irq;
2452 	struct resource		*bge_res;
2453 	struct ifmedia		bge_ifmedia;	/* TBI media info */
2454 	uint32_t		bge_flags;
2455 #define	BGE_FLAG_TBI		0x00000001
2456 #define	BGE_FLAG_JUMBO		0x00000002
2457 #define	BGE_FLAG_MSI		0x00000100
2458 #define	BGE_FLAG_PCIX		0x00000200
2459 #define	BGE_FLAG_PCIE		0x00000400
2460 #define	BGE_FLAG_5700_FAMILY	0x00001000
2461 #define	BGE_FLAG_5705_PLUS	0x00002000
2462 #define	BGE_FLAG_5714_FAMILY	0x00004000
2463 #define	BGE_FLAG_575X_PLUS	0x00008000
2464 #define	BGE_FLAG_RX_ALIGNBUG	0x00100000
2465 #define	BGE_FLAG_NO_3LED	0x00200000
2466 #define	BGE_FLAG_ADC_BUG	0x00400000
2467 #define	BGE_FLAG_5704_A0_BUG	0x00800000
2468 #define	BGE_FLAG_JITTER_BUG	0x01000000
2469 #define	BGE_FLAG_BER_BUG	0x02000000
2470 #define	BGE_FLAG_ADJUST_TRIM	0x04000000
2471 #define	BGE_FLAG_CRC_BUG	0x08000000
2472 	uint32_t		bge_chipid;
2473 	uint8_t			bge_asicrev;
2474 	uint8_t			bge_chiprev;
2475 	uint8_t			bge_asf_mode;
2476 	uint8_t			bge_asf_count;
2477 	struct bge_ring_data	bge_ldata;	/* rings */
2478 	struct bge_chain_data	bge_cdata;	/* mbufs */
2479 	uint16_t		bge_tx_saved_considx;
2480 	uint16_t		bge_rx_saved_considx;
2481 	uint16_t		bge_ev_saved_considx;
2482 	uint16_t		bge_return_ring_cnt;
2483 	uint16_t		bge_std;	/* current std ring head */
2484 	uint16_t		bge_jumbo;	/* current jumo ring head */
2485 	uint32_t		bge_stat_ticks;
2486 	uint32_t		bge_rx_coal_ticks;
2487 	uint32_t		bge_tx_coal_ticks;
2488 	uint32_t		bge_tx_prodidx;
2489 	uint32_t		bge_rx_max_coal_bds;
2490 	uint32_t		bge_tx_max_coal_bds;
2491 	uint32_t		bge_tx_buf_ratio;
2492 	int			bge_if_flags;
2493 	int			bge_txcnt;
2494 	int			bge_link;	/* link state */
2495 	int			bge_link_evt;	/* pending link event */
2496 	int			bge_timer;
2497 	struct callout		bge_stat_ch;
2498 	uint32_t		bge_rx_discards;
2499 	uint32_t		bge_tx_discards;
2500 	uint32_t		bge_tx_collisions;
2501 #ifdef DEVICE_POLLING
2502 	int			rxcycles;
2503 #endif /* DEVICE_POLLING */
2504 };
2505 
2506 #define	BGE_LOCK_INIT(_sc, _name) \
2507 	mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2508 #define	BGE_LOCK(_sc)		mtx_lock(&(_sc)->bge_mtx)
2509 #define	BGE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2510 #define	BGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->bge_mtx)
2511 #define	BGE_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->bge_mtx)
2512