1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64 #define BGE_PAGE_ZERO 0x00000000 65 #define BGE_PAGE_ZERO_END 0x000000FF 66 #define BGE_SEND_RING_RCB 0x00000100 67 #define BGE_SEND_RING_RCB_END 0x000001FF 68 #define BGE_RX_RETURN_RING_RCB 0x00000200 69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70 #define BGE_STATS_BLOCK 0x00000300 71 #define BGE_STATS_BLOCK_END 0x00000AFF 72 #define BGE_STATUS_BLOCK 0x00000B00 73 #define BGE_STATUS_BLOCK_END 0x00000B4F 74 #define BGE_SOFTWARE_GENCOMM 0x00000B50 75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 78 #define BGE_UNMAPPED 0x00001000 79 #define BGE_UNMAPPED_END 0x00001FFF 80 #define BGE_DMA_DESCRIPTORS 0x00002000 81 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 82 #define BGE_SEND_RING_1_TO_4 0x00004000 83 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 84 85 /* Mappings for internal memory configuration */ 86 #define BGE_STD_RX_RINGS 0x00006000 87 #define BGE_STD_RX_RINGS_END 0x00006FFF 88 #define BGE_JUMBO_RX_RINGS 0x00007000 89 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 90 #define BGE_BUFFPOOL_1 0x00008000 91 #define BGE_BUFFPOOL_1_END 0x0000FFFF 92 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 93 #define BGE_BUFFPOOL_2_END 0x00017FFF 94 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 95 #define BGE_BUFFPOOL_3_END 0x0001FFFF 96 97 /* Mappings for external SSRAM configurations */ 98 #define BGE_SEND_RING_5_TO_6 0x00006000 99 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 100 #define BGE_SEND_RING_7_TO_8 0x00007000 101 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 102 #define BGE_SEND_RING_9_TO_16 0x00008000 103 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 104 #define BGE_EXT_STD_RX_RINGS 0x0000C000 105 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 106 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 107 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 108 #define BGE_MINI_RX_RINGS 0x0000E000 109 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 110 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 111 #define BGE_AVAIL_REGION1_END 0x00017FFF 112 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 113 #define BGE_AVAIL_REGION2_END 0x0001FFFF 114 #define BGE_EXT_SSRAM 0x00020000 115 #define BGE_EXT_SSRAM_END 0x000FFFFF 116 117 118 /* 119 * BCM570x register offsets. These are memory mapped registers 120 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 121 * Each register must be accessed using 32 bit operations. 122 * 123 * All registers are accessed through a 32K shared memory block. 124 * The first group of registers are actually copies of the PCI 125 * configuration space registers. 126 */ 127 128 /* 129 * PCI registers defined in the PCI 2.2 spec. 130 */ 131 #define BGE_PCI_VID 0x00 132 #define BGE_PCI_DID 0x02 133 #define BGE_PCI_CMD 0x04 134 #define BGE_PCI_STS 0x06 135 #define BGE_PCI_REV 0x08 136 #define BGE_PCI_CLASS 0x09 137 #define BGE_PCI_CACHESZ 0x0C 138 #define BGE_PCI_LATTIMER 0x0D 139 #define BGE_PCI_HDRTYPE 0x0E 140 #define BGE_PCI_BIST 0x0F 141 #define BGE_PCI_BAR0 0x10 142 #define BGE_PCI_BAR1 0x14 143 #define BGE_PCI_SUBSYS 0x2C 144 #define BGE_PCI_SUBVID 0x2E 145 #define BGE_PCI_ROMBASE 0x30 146 #define BGE_PCI_CAPPTR 0x34 147 #define BGE_PCI_INTLINE 0x3C 148 #define BGE_PCI_INTPIN 0x3D 149 #define BGE_PCI_MINGNT 0x3E 150 #define BGE_PCI_MAXLAT 0x3F 151 #define BGE_PCI_PCIXCAP 0x40 152 #define BGE_PCI_NEXTPTR_PM 0x41 153 #define BGE_PCI_PCIX_CMD 0x42 154 #define BGE_PCI_PCIX_STS 0x44 155 #define BGE_PCI_PWRMGMT_CAPID 0x48 156 #define BGE_PCI_NEXTPTR_VPD 0x49 157 #define BGE_PCI_PWRMGMT_CAPS 0x4A 158 #define BGE_PCI_PWRMGMT_CMD 0x4C 159 #define BGE_PCI_PWRMGMT_STS 0x4D 160 #define BGE_PCI_PWRMGMT_DATA 0x4F 161 #define BGE_PCI_VPD_CAPID 0x50 162 #define BGE_PCI_NEXTPTR_MSI 0x51 163 #define BGE_PCI_VPD_ADDR 0x52 164 #define BGE_PCI_VPD_DATA 0x54 165 #define BGE_PCI_MSI_CAPID 0x58 166 #define BGE_PCI_NEXTPTR_NONE 0x59 167 #define BGE_PCI_MSI_CTL 0x5A 168 #define BGE_PCI_MSI_ADDR_HI 0x5C 169 #define BGE_PCI_MSI_ADDR_LO 0x60 170 #define BGE_PCI_MSI_DATA 0x64 171 172 /* PCI MSI. ??? */ 173 #define BGE_PCIE_CAPID_REG 0xD0 174 #define BGE_PCIE_CAPID 0x10 175 176 /* 177 * PCI registers specific to the BCM570x family. 178 */ 179 #define BGE_PCI_MISC_CTL 0x68 180 #define BGE_PCI_DMA_RW_CTL 0x6C 181 #define BGE_PCI_PCISTATE 0x70 182 #define BGE_PCI_CLKCTL 0x74 183 #define BGE_PCI_REG_BASEADDR 0x78 184 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 185 #define BGE_PCI_REG_DATA 0x80 186 #define BGE_PCI_MEMWIN_DATA 0x84 187 #define BGE_PCI_MODECTL 0x88 188 #define BGE_PCI_MISC_CFG 0x8C 189 #define BGE_PCI_MISC_LOCALCTL 0x90 190 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 191 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 192 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 193 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 194 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 195 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 196 #define BGE_PCI_ISR_MBX_HI 0xB0 197 #define BGE_PCI_ISR_MBX_LO 0xB4 198 199 /* PCI Misc. Host control register */ 200 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 201 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 202 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209 210 #define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 211 #if BYTE_ORDER == LITTLE_ENDIAN 212 #define BGE_DMA_SWAP_OPTIONS \ 213 BGE_MODECTL_WORDSWAP_NONFRAME| \ 214 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 215 #else 216 #define BGE_DMA_SWAP_OPTIONS \ 217 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 218 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 219 #endif 220 221 #define BGE_INIT \ 222 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 223 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 224 225 #define BGE_CHIPID_TIGON_I 0x40000000 226 #define BGE_CHIPID_TIGON_II 0x60000000 227 #define BGE_CHIPID_BCM5700_B0 0x71000000 228 #define BGE_CHIPID_BCM5700_B1 0x71020000 229 #define BGE_CHIPID_BCM5700_B2 0x71030000 230 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 231 #define BGE_CHIPID_BCM5700_C0 0x72000000 232 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 233 #define BGE_CHIPID_BCM5701_B0 0x01000000 234 #define BGE_CHIPID_BCM5701_B2 0x01020000 235 #define BGE_CHIPID_BCM5701_B5 0x01050000 236 #define BGE_CHIPID_BCM5703_A0 0x10000000 237 #define BGE_CHIPID_BCM5703_A1 0x10010000 238 #define BGE_CHIPID_BCM5703_A2 0x10020000 239 #define BGE_CHIPID_BCM5704_A0 0x20000000 240 #define BGE_CHIPID_BCM5704_A1 0x20010000 241 #define BGE_CHIPID_BCM5704_A2 0x20020000 242 #define BGE_CHIPID_BCM5705_A0 0x30000000 243 #define BGE_CHIPID_BCM5705_A1 0x30010000 244 #define BGE_CHIPID_BCM5705_A2 0x30020000 245 #define BGE_CHIPID_BCM5705_A3 0x30030000 246 #define BGE_CHIPID_BCM5750_A0 0x40000000 247 #define BGE_CHIPID_BCM5750_A1 0x40010000 248 #define BGE_CHIPID_BCM5714_A0 0x50000000 249 250 /* shorthand one */ 251 #define BGE_ASICREV(x) ((x) >> 28) 252 #define BGE_ASICREV_BCM5700 0x07 253 #define BGE_ASICREV_BCM5701 0x00 254 #define BGE_ASICREV_BCM5703 0x01 255 #define BGE_ASICREV_BCM5704 0x02 256 #define BGE_ASICREV_BCM5705 0x03 257 #define BGE_ASICREV_BCM5750 0x04 258 #define BGE_ASICREV_BCM5714 0x05 259 #define BGE_ASICREV_BCM5752 0x06 260 261 /* chip revisions */ 262 #define BGE_CHIPREV(x) ((x) >> 24) 263 #define BGE_CHIPREV_5700_AX 0x70 264 #define BGE_CHIPREV_5700_BX 0x71 265 #define BGE_CHIPREV_5700_CX 0x72 266 #define BGE_CHIPREV_5701_AX 0x00 267 268 /* PCI DMA Read/Write Control register */ 269 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 270 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 271 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 272 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 273 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 274 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 275 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 276 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 277 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 278 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 279 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 280 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 281 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 282 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 283 284 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 285 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 286 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 287 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 288 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 289 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 290 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 291 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 292 293 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 294 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 295 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 296 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 297 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 298 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 299 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 300 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 301 302 /* 303 * PCI state register -- note, this register is read only 304 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 305 * register is set. 306 */ 307 #define BGE_PCISTATE_FORCE_RESET 0x00000001 308 #define BGE_PCISTATE_INTR_STATE 0x00000002 309 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 310 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 311 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 312 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 313 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 314 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 315 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 316 317 /* 318 * PCI Clock Control register -- note, this register is read only 319 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 320 * register is set. 321 */ 322 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 323 #define BGE_PCICLOCKCTL_M66EN 0x00000080 324 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 325 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 326 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 327 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 328 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 329 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 330 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 331 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 332 333 334 #ifndef PCIM_CMD_MWIEN 335 #define PCIM_CMD_MWIEN 0x0010 336 #endif 337 338 /* 339 * High priority mailbox registers 340 * Each mailbox is 64-bits wide, though we only use the 341 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 342 * first. The NIC will load the mailbox after the lower 32 bit word 343 * has been updated. 344 */ 345 #define BGE_MBX_IRQ0_HI 0x0200 346 #define BGE_MBX_IRQ0_LO 0x0204 347 #define BGE_MBX_IRQ1_HI 0x0208 348 #define BGE_MBX_IRQ1_LO 0x020C 349 #define BGE_MBX_IRQ2_HI 0x0210 350 #define BGE_MBX_IRQ2_LO 0x0214 351 #define BGE_MBX_IRQ3_HI 0x0218 352 #define BGE_MBX_IRQ3_LO 0x021C 353 #define BGE_MBX_GEN0_HI 0x0220 354 #define BGE_MBX_GEN0_LO 0x0224 355 #define BGE_MBX_GEN1_HI 0x0228 356 #define BGE_MBX_GEN1_LO 0x022C 357 #define BGE_MBX_GEN2_HI 0x0230 358 #define BGE_MBX_GEN2_LO 0x0234 359 #define BGE_MBX_GEN3_HI 0x0228 360 #define BGE_MBX_GEN3_LO 0x022C 361 #define BGE_MBX_GEN4_HI 0x0240 362 #define BGE_MBX_GEN4_LO 0x0244 363 #define BGE_MBX_GEN5_HI 0x0248 364 #define BGE_MBX_GEN5_LO 0x024C 365 #define BGE_MBX_GEN6_HI 0x0250 366 #define BGE_MBX_GEN6_LO 0x0254 367 #define BGE_MBX_GEN7_HI 0x0258 368 #define BGE_MBX_GEN7_LO 0x025C 369 #define BGE_MBX_RELOAD_STATS_HI 0x0260 370 #define BGE_MBX_RELOAD_STATS_LO 0x0264 371 #define BGE_MBX_RX_STD_PROD_HI 0x0268 372 #define BGE_MBX_RX_STD_PROD_LO 0x026C 373 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 374 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 375 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 376 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 377 #define BGE_MBX_RX_CONS0_HI 0x0280 378 #define BGE_MBX_RX_CONS0_LO 0x0284 379 #define BGE_MBX_RX_CONS1_HI 0x0288 380 #define BGE_MBX_RX_CONS1_LO 0x028C 381 #define BGE_MBX_RX_CONS2_HI 0x0290 382 #define BGE_MBX_RX_CONS2_LO 0x0294 383 #define BGE_MBX_RX_CONS3_HI 0x0298 384 #define BGE_MBX_RX_CONS3_LO 0x029C 385 #define BGE_MBX_RX_CONS4_HI 0x02A0 386 #define BGE_MBX_RX_CONS4_LO 0x02A4 387 #define BGE_MBX_RX_CONS5_HI 0x02A8 388 #define BGE_MBX_RX_CONS5_LO 0x02AC 389 #define BGE_MBX_RX_CONS6_HI 0x02B0 390 #define BGE_MBX_RX_CONS6_LO 0x02B4 391 #define BGE_MBX_RX_CONS7_HI 0x02B8 392 #define BGE_MBX_RX_CONS7_LO 0x02BC 393 #define BGE_MBX_RX_CONS8_HI 0x02C0 394 #define BGE_MBX_RX_CONS8_LO 0x02C4 395 #define BGE_MBX_RX_CONS9_HI 0x02C8 396 #define BGE_MBX_RX_CONS9_LO 0x02CC 397 #define BGE_MBX_RX_CONS10_HI 0x02D0 398 #define BGE_MBX_RX_CONS10_LO 0x02D4 399 #define BGE_MBX_RX_CONS11_HI 0x02D8 400 #define BGE_MBX_RX_CONS11_LO 0x02DC 401 #define BGE_MBX_RX_CONS12_HI 0x02E0 402 #define BGE_MBX_RX_CONS12_LO 0x02E4 403 #define BGE_MBX_RX_CONS13_HI 0x02E8 404 #define BGE_MBX_RX_CONS13_LO 0x02EC 405 #define BGE_MBX_RX_CONS14_HI 0x02F0 406 #define BGE_MBX_RX_CONS14_LO 0x02F4 407 #define BGE_MBX_RX_CONS15_HI 0x02F8 408 #define BGE_MBX_RX_CONS15_LO 0x02FC 409 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 410 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 411 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 412 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 413 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 414 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 415 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 416 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 417 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 418 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 419 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 420 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 421 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 422 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 423 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 424 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 425 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 426 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 427 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 428 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 429 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 430 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 431 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 432 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 433 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 434 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 435 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 436 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 437 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 438 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 439 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 440 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 441 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 442 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 443 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 444 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 445 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 446 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 447 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 448 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 449 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 450 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 451 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 452 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 453 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 454 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 455 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 456 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 457 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 458 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 459 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 460 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 461 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 462 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 463 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 464 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 465 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 466 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 467 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 468 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 469 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 470 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 471 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 472 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 473 474 #define BGE_TX_RINGS_MAX 4 475 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 476 #define BGE_RX_RINGS_MAX 16 477 478 /* Ethernet MAC control registers */ 479 #define BGE_MAC_MODE 0x0400 480 #define BGE_MAC_STS 0x0404 481 #define BGE_MAC_EVT_ENB 0x0408 482 #define BGE_MAC_LED_CTL 0x040C 483 #define BGE_MAC_ADDR1_LO 0x0410 484 #define BGE_MAC_ADDR1_HI 0x0414 485 #define BGE_MAC_ADDR2_LO 0x0418 486 #define BGE_MAC_ADDR2_HI 0x041C 487 #define BGE_MAC_ADDR3_LO 0x0420 488 #define BGE_MAC_ADDR3_HI 0x0424 489 #define BGE_MAC_ADDR4_LO 0x0428 490 #define BGE_MAC_ADDR4_HI 0x042C 491 #define BGE_WOL_PATPTR 0x0430 492 #define BGE_WOL_PATCFG 0x0434 493 #define BGE_TX_RANDOM_BACKOFF 0x0438 494 #define BGE_RX_MTU 0x043C 495 #define BGE_GBIT_PCS_TEST 0x0440 496 #define BGE_TX_TBI_AUTONEG 0x0444 497 #define BGE_RX_TBI_AUTONEG 0x0448 498 #define BGE_MI_COMM 0x044C 499 #define BGE_MI_STS 0x0450 500 #define BGE_MI_MODE 0x0454 501 #define BGE_AUTOPOLL_STS 0x0458 502 #define BGE_TX_MODE 0x045C 503 #define BGE_TX_STS 0x0460 504 #define BGE_TX_LENGTHS 0x0464 505 #define BGE_RX_MODE 0x0468 506 #define BGE_RX_STS 0x046C 507 #define BGE_MAR0 0x0470 508 #define BGE_MAR1 0x0474 509 #define BGE_MAR2 0x0478 510 #define BGE_MAR3 0x047C 511 #define BGE_RX_BD_RULES_CTL0 0x0480 512 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 513 #define BGE_RX_BD_RULES_CTL1 0x0488 514 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 515 #define BGE_RX_BD_RULES_CTL2 0x0490 516 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 517 #define BGE_RX_BD_RULES_CTL3 0x0498 518 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 519 #define BGE_RX_BD_RULES_CTL4 0x04A0 520 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 521 #define BGE_RX_BD_RULES_CTL5 0x04A8 522 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 523 #define BGE_RX_BD_RULES_CTL6 0x04B0 524 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 525 #define BGE_RX_BD_RULES_CTL7 0x04B8 526 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 527 #define BGE_RX_BD_RULES_CTL8 0x04C0 528 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 529 #define BGE_RX_BD_RULES_CTL9 0x04C8 530 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 531 #define BGE_RX_BD_RULES_CTL10 0x04D0 532 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 533 #define BGE_RX_BD_RULES_CTL11 0x04D8 534 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 535 #define BGE_RX_BD_RULES_CTL12 0x04E0 536 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 537 #define BGE_RX_BD_RULES_CTL13 0x04E8 538 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 539 #define BGE_RX_BD_RULES_CTL14 0x04F0 540 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 541 #define BGE_RX_BD_RULES_CTL15 0x04F8 542 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 543 #define BGE_RX_RULES_CFG 0x0500 544 #define BGE_SERDES_CFG 0x0590 545 #define BGE_SERDES_STS 0x0594 546 #define BGE_SGDIG_CFG 0x05B0 547 #define BGE_SGDIG_STS 0x05B4 548 #define BGE_RX_STATS 0x0800 549 #define BGE_TX_STATS 0x0880 550 551 /* Ethernet MAC Mode register */ 552 #define BGE_MACMODE_RESET 0x00000001 553 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 554 #define BGE_MACMODE_PORTMODE 0x0000000C 555 #define BGE_MACMODE_LOOPBACK 0x00000010 556 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 557 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 558 #define BGE_MACMODE_MAX_DEFER 0x00000200 559 #define BGE_MACMODE_LINK_POLARITY 0x00000400 560 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 561 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 562 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 563 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 564 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 565 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 566 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 567 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 568 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 569 #define BGE_MACMODE_MIP_ENB 0x00100000 570 #define BGE_MACMODE_TXDMA_ENB 0x00200000 571 #define BGE_MACMODE_RXDMA_ENB 0x00400000 572 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 573 574 #define BGE_PORTMODE_NONE 0x00000000 575 #define BGE_PORTMODE_MII 0x00000004 576 #define BGE_PORTMODE_GMII 0x00000008 577 #define BGE_PORTMODE_TBI 0x0000000C 578 579 /* MAC Status register */ 580 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 581 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 582 #define BGE_MACSTAT_RX_CFG 0x00000004 583 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 584 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 585 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 586 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 587 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 588 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 589 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 590 #define BGE_MACSTAT_ODI_ERROR 0x02000000 591 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 592 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 593 594 /* MAC Event Enable Register */ 595 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 596 #define BGE_EVTENB_LINK_CHANGED 0x00001000 597 #define BGE_EVTENB_MI_COMPLETE 0x00400000 598 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 599 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 600 #define BGE_EVTENB_ODI_ERROR 0x02000000 601 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 602 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 603 604 /* LED Control Register */ 605 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 606 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 607 #define BGE_LEDCTL_100MBPS_LED 0x00000004 608 #define BGE_LEDCTL_10MBPS_LED 0x00000008 609 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 610 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 611 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 612 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 613 #define BGE_LEDCTL_100MBPS_STS 0x00000100 614 #define BGE_LEDCTL_10MBPS_STS 0x00000200 615 #define BGE_LEDCTL_TRADLED_STS 0x00000400 616 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 617 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 618 619 /* TX backoff seed register */ 620 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 621 622 /* Autopoll status register */ 623 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 624 625 /* Transmit MAC mode register */ 626 #define BGE_TXMODE_RESET 0x00000001 627 #define BGE_TXMODE_ENABLE 0x00000002 628 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 629 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 630 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 631 632 /* Transmit MAC status register */ 633 #define BGE_TXSTAT_RX_XOFFED 0x00000001 634 #define BGE_TXSTAT_SENT_XOFF 0x00000002 635 #define BGE_TXSTAT_SENT_XON 0x00000004 636 #define BGE_TXSTAT_LINK_UP 0x00000008 637 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 638 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 639 640 /* Transmit MAC lengths register */ 641 #define BGE_TXLEN_SLOTTIME 0x000000FF 642 #define BGE_TXLEN_IPG 0x00000F00 643 #define BGE_TXLEN_CRS 0x00003000 644 645 /* Receive MAC mode register */ 646 #define BGE_RXMODE_RESET 0x00000001 647 #define BGE_RXMODE_ENABLE 0x00000002 648 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 649 #define BGE_RXMODE_RX_GIANTS 0x00000020 650 #define BGE_RXMODE_RX_RUNTS 0x00000040 651 #define BGE_RXMODE_8022_LENCHECK 0x00000080 652 #define BGE_RXMODE_RX_PROMISC 0x00000100 653 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 654 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 655 656 /* Receive MAC status register */ 657 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 658 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 659 #define BGE_RXSTAT_RCVD_XON 0x00000004 660 661 /* Receive Rules Control register */ 662 #define BGE_RXRULECTL_OFFSET 0x000000FF 663 #define BGE_RXRULECTL_CLASS 0x00001F00 664 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 665 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 666 #define BGE_RXRULECTL_MAP 0x01000000 667 #define BGE_RXRULECTL_DISCARD 0x02000000 668 #define BGE_RXRULECTL_MASK 0x04000000 669 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 670 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 671 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 672 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 673 674 /* Receive Rules Mask register */ 675 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 676 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 677 678 /* SERDES configuration register */ 679 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 680 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 681 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 682 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 683 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 684 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 685 #define BGE_SERDESCFG_TXMODE 0x00001000 686 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 687 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 688 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 689 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 690 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 691 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 692 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 693 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 694 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 695 696 /* SERDES status register */ 697 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 698 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 699 700 /* SGDIG config (not documented) */ 701 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 702 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 703 #define BGE_SGDIGCFG_SEND 0x40000000 704 #define BGE_SGDIGCFG_AUTO 0x80000000 705 706 /* SGDIG status (not documented) */ 707 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 708 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 709 #define BGE_SGDIGSTS_DONE 0x00000002 710 711 712 /* MI communication register */ 713 #define BGE_MICOMM_DATA 0x0000FFFF 714 #define BGE_MICOMM_REG 0x001F0000 715 #define BGE_MICOMM_PHY 0x03E00000 716 #define BGE_MICOMM_CMD 0x0C000000 717 #define BGE_MICOMM_READFAIL 0x10000000 718 #define BGE_MICOMM_BUSY 0x20000000 719 720 #define BGE_MIREG(x) ((x & 0x1F) << 16) 721 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 722 #define BGE_MICMD_WRITE 0x04000000 723 #define BGE_MICMD_READ 0x08000000 724 725 /* MI status register */ 726 #define BGE_MISTS_LINK 0x00000001 727 #define BGE_MISTS_10MBPS 0x00000002 728 729 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 730 #define BGE_MIMODE_AUTOPOLL 0x00000010 731 #define BGE_MIMODE_CLKCNT 0x001F0000 732 733 734 /* 735 * Send data initiator control registers. 736 */ 737 #define BGE_SDI_MODE 0x0C00 738 #define BGE_SDI_STATUS 0x0C04 739 #define BGE_SDI_STATS_CTL 0x0C08 740 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 741 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 742 #define BGE_LOCSTATS_COS0 0x0C80 743 #define BGE_LOCSTATS_COS1 0x0C84 744 #define BGE_LOCSTATS_COS2 0x0C88 745 #define BGE_LOCSTATS_COS3 0x0C8C 746 #define BGE_LOCSTATS_COS4 0x0C90 747 #define BGE_LOCSTATS_COS5 0x0C84 748 #define BGE_LOCSTATS_COS6 0x0C98 749 #define BGE_LOCSTATS_COS7 0x0C9C 750 #define BGE_LOCSTATS_COS8 0x0CA0 751 #define BGE_LOCSTATS_COS9 0x0CA4 752 #define BGE_LOCSTATS_COS10 0x0CA8 753 #define BGE_LOCSTATS_COS11 0x0CAC 754 #define BGE_LOCSTATS_COS12 0x0CB0 755 #define BGE_LOCSTATS_COS13 0x0CB4 756 #define BGE_LOCSTATS_COS14 0x0CB8 757 #define BGE_LOCSTATS_COS15 0x0CBC 758 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 759 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 760 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 761 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 762 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 763 #define BGE_LOCSTATS_IRQS 0x0CD4 764 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 765 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 766 767 /* Send Data Initiator mode register */ 768 #define BGE_SDIMODE_RESET 0x00000001 769 #define BGE_SDIMODE_ENABLE 0x00000002 770 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 771 772 /* Send Data Initiator stats register */ 773 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 774 775 /* Send Data Initiator stats control register */ 776 #define BGE_SDISTATSCTL_ENABLE 0x00000001 777 #define BGE_SDISTATSCTL_FASTER 0x00000002 778 #define BGE_SDISTATSCTL_CLEAR 0x00000004 779 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 780 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 781 782 /* 783 * Send Data Completion Control registers 784 */ 785 #define BGE_SDC_MODE 0x1000 786 #define BGE_SDC_STATUS 0x1004 787 788 /* Send Data completion mode register */ 789 #define BGE_SDCMODE_RESET 0x00000001 790 #define BGE_SDCMODE_ENABLE 0x00000002 791 #define BGE_SDCMODE_ATTN 0x00000004 792 793 /* Send Data completion status register */ 794 #define BGE_SDCSTAT_ATTN 0x00000004 795 796 /* 797 * Send BD Ring Selector Control registers 798 */ 799 #define BGE_SRS_MODE 0x1400 800 #define BGE_SRS_STATUS 0x1404 801 #define BGE_SRS_HWDIAG 0x1408 802 #define BGE_SRS_LOC_NIC_CONS0 0x1440 803 #define BGE_SRS_LOC_NIC_CONS1 0x1444 804 #define BGE_SRS_LOC_NIC_CONS2 0x1448 805 #define BGE_SRS_LOC_NIC_CONS3 0x144C 806 #define BGE_SRS_LOC_NIC_CONS4 0x1450 807 #define BGE_SRS_LOC_NIC_CONS5 0x1454 808 #define BGE_SRS_LOC_NIC_CONS6 0x1458 809 #define BGE_SRS_LOC_NIC_CONS7 0x145C 810 #define BGE_SRS_LOC_NIC_CONS8 0x1460 811 #define BGE_SRS_LOC_NIC_CONS9 0x1464 812 #define BGE_SRS_LOC_NIC_CONS10 0x1468 813 #define BGE_SRS_LOC_NIC_CONS11 0x146C 814 #define BGE_SRS_LOC_NIC_CONS12 0x1470 815 #define BGE_SRS_LOC_NIC_CONS13 0x1474 816 #define BGE_SRS_LOC_NIC_CONS14 0x1478 817 #define BGE_SRS_LOC_NIC_CONS15 0x147C 818 819 /* Send BD Ring Selector Mode register */ 820 #define BGE_SRSMODE_RESET 0x00000001 821 #define BGE_SRSMODE_ENABLE 0x00000002 822 #define BGE_SRSMODE_ATTN 0x00000004 823 824 /* Send BD Ring Selector Status register */ 825 #define BGE_SRSSTAT_ERROR 0x00000004 826 827 /* Send BD Ring Selector HW Diagnostics register */ 828 #define BGE_SRSHWDIAG_STATE 0x0000000F 829 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 830 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 831 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 832 833 /* 834 * Send BD Initiator Selector Control registers 835 */ 836 #define BGE_SBDI_MODE 0x1800 837 #define BGE_SBDI_STATUS 0x1804 838 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 839 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 840 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 841 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 842 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 843 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 844 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 845 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 846 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 847 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 848 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 849 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 850 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 851 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 852 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 853 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 854 855 /* Send BD Initiator Mode register */ 856 #define BGE_SBDIMODE_RESET 0x00000001 857 #define BGE_SBDIMODE_ENABLE 0x00000002 858 #define BGE_SBDIMODE_ATTN 0x00000004 859 860 /* Send BD Initiator Status register */ 861 #define BGE_SBDISTAT_ERROR 0x00000004 862 863 /* 864 * Send BD Completion Control registers 865 */ 866 #define BGE_SBDC_MODE 0x1C00 867 #define BGE_SBDC_STATUS 0x1C04 868 869 /* Send BD Completion Control Mode register */ 870 #define BGE_SBDCMODE_RESET 0x00000001 871 #define BGE_SBDCMODE_ENABLE 0x00000002 872 #define BGE_SBDCMODE_ATTN 0x00000004 873 874 /* Send BD Completion Control Status register */ 875 #define BGE_SBDCSTAT_ATTN 0x00000004 876 877 /* 878 * Receive List Placement Control registers 879 */ 880 #define BGE_RXLP_MODE 0x2000 881 #define BGE_RXLP_STATUS 0x2004 882 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 883 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 884 #define BGE_RXLP_CFG 0x2010 885 #define BGE_RXLP_STATS_CTL 0x2014 886 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 887 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 888 #define BGE_RXLP_HEAD0 0x2100 889 #define BGE_RXLP_TAIL0 0x2104 890 #define BGE_RXLP_COUNT0 0x2108 891 #define BGE_RXLP_HEAD1 0x2110 892 #define BGE_RXLP_TAIL1 0x2114 893 #define BGE_RXLP_COUNT1 0x2118 894 #define BGE_RXLP_HEAD2 0x2120 895 #define BGE_RXLP_TAIL2 0x2124 896 #define BGE_RXLP_COUNT2 0x2128 897 #define BGE_RXLP_HEAD3 0x2130 898 #define BGE_RXLP_TAIL3 0x2134 899 #define BGE_RXLP_COUNT3 0x2138 900 #define BGE_RXLP_HEAD4 0x2140 901 #define BGE_RXLP_TAIL4 0x2144 902 #define BGE_RXLP_COUNT4 0x2148 903 #define BGE_RXLP_HEAD5 0x2150 904 #define BGE_RXLP_TAIL5 0x2154 905 #define BGE_RXLP_COUNT5 0x2158 906 #define BGE_RXLP_HEAD6 0x2160 907 #define BGE_RXLP_TAIL6 0x2164 908 #define BGE_RXLP_COUNT6 0x2168 909 #define BGE_RXLP_HEAD7 0x2170 910 #define BGE_RXLP_TAIL7 0x2174 911 #define BGE_RXLP_COUNT7 0x2178 912 #define BGE_RXLP_HEAD8 0x2180 913 #define BGE_RXLP_TAIL8 0x2184 914 #define BGE_RXLP_COUNT8 0x2188 915 #define BGE_RXLP_HEAD9 0x2190 916 #define BGE_RXLP_TAIL9 0x2194 917 #define BGE_RXLP_COUNT9 0x2198 918 #define BGE_RXLP_HEAD10 0x21A0 919 #define BGE_RXLP_TAIL10 0x21A4 920 #define BGE_RXLP_COUNT10 0x21A8 921 #define BGE_RXLP_HEAD11 0x21B0 922 #define BGE_RXLP_TAIL11 0x21B4 923 #define BGE_RXLP_COUNT11 0x21B8 924 #define BGE_RXLP_HEAD12 0x21C0 925 #define BGE_RXLP_TAIL12 0x21C4 926 #define BGE_RXLP_COUNT12 0x21C8 927 #define BGE_RXLP_HEAD13 0x21D0 928 #define BGE_RXLP_TAIL13 0x21D4 929 #define BGE_RXLP_COUNT13 0x21D8 930 #define BGE_RXLP_HEAD14 0x21E0 931 #define BGE_RXLP_TAIL14 0x21E4 932 #define BGE_RXLP_COUNT14 0x21E8 933 #define BGE_RXLP_HEAD15 0x21F0 934 #define BGE_RXLP_TAIL15 0x21F4 935 #define BGE_RXLP_COUNT15 0x21F8 936 #define BGE_RXLP_LOCSTAT_COS0 0x2200 937 #define BGE_RXLP_LOCSTAT_COS1 0x2204 938 #define BGE_RXLP_LOCSTAT_COS2 0x2208 939 #define BGE_RXLP_LOCSTAT_COS3 0x220C 940 #define BGE_RXLP_LOCSTAT_COS4 0x2210 941 #define BGE_RXLP_LOCSTAT_COS5 0x2214 942 #define BGE_RXLP_LOCSTAT_COS6 0x2218 943 #define BGE_RXLP_LOCSTAT_COS7 0x221C 944 #define BGE_RXLP_LOCSTAT_COS8 0x2220 945 #define BGE_RXLP_LOCSTAT_COS9 0x2224 946 #define BGE_RXLP_LOCSTAT_COS10 0x2228 947 #define BGE_RXLP_LOCSTAT_COS11 0x222C 948 #define BGE_RXLP_LOCSTAT_COS12 0x2230 949 #define BGE_RXLP_LOCSTAT_COS13 0x2234 950 #define BGE_RXLP_LOCSTAT_COS14 0x2238 951 #define BGE_RXLP_LOCSTAT_COS15 0x223C 952 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 953 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 954 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 955 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 956 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 957 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 958 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 959 960 961 /* Receive List Placement mode register */ 962 #define BGE_RXLPMODE_RESET 0x00000001 963 #define BGE_RXLPMODE_ENABLE 0x00000002 964 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 965 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 966 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 967 968 /* Receive List Placement Status register */ 969 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 970 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 971 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 972 973 /* 974 * Receive Data and Receive BD Initiator Control Registers 975 */ 976 #define BGE_RDBDI_MODE 0x2400 977 #define BGE_RDBDI_STATUS 0x2404 978 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 979 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 980 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 981 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 982 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 983 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 984 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 985 #define BGE_RX_STD_RCB_NICADDR 0x245C 986 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 987 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 988 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 989 #define BGE_RX_MINI_RCB_NICADDR 0x246C 990 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 991 #define BGE_RDBDI_STD_RX_CONS 0x2474 992 #define BGE_RDBDI_MINI_RX_CONS 0x2478 993 #define BGE_RDBDI_RETURN_PROD0 0x2480 994 #define BGE_RDBDI_RETURN_PROD1 0x2484 995 #define BGE_RDBDI_RETURN_PROD2 0x2488 996 #define BGE_RDBDI_RETURN_PROD3 0x248C 997 #define BGE_RDBDI_RETURN_PROD4 0x2490 998 #define BGE_RDBDI_RETURN_PROD5 0x2494 999 #define BGE_RDBDI_RETURN_PROD6 0x2498 1000 #define BGE_RDBDI_RETURN_PROD7 0x249C 1001 #define BGE_RDBDI_RETURN_PROD8 0x24A0 1002 #define BGE_RDBDI_RETURN_PROD9 0x24A4 1003 #define BGE_RDBDI_RETURN_PROD10 0x24A8 1004 #define BGE_RDBDI_RETURN_PROD11 0x24AC 1005 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1006 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1007 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1008 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1009 #define BGE_RDBDI_HWDIAG 0x24C0 1010 1011 1012 /* Receive Data and Receive BD Initiator Mode register */ 1013 #define BGE_RDBDIMODE_RESET 0x00000001 1014 #define BGE_RDBDIMODE_ENABLE 0x00000002 1015 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1016 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1017 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1018 1019 /* Receive Data and Receive BD Initiator Status register */ 1020 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1021 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1022 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1023 1024 1025 /* 1026 * Receive Data Completion Control registers 1027 */ 1028 #define BGE_RDC_MODE 0x2800 1029 1030 /* Receive Data Completion Mode register */ 1031 #define BGE_RDCMODE_RESET 0x00000001 1032 #define BGE_RDCMODE_ENABLE 0x00000002 1033 #define BGE_RDCMODE_ATTN 0x00000004 1034 1035 /* 1036 * Receive BD Initiator Control registers 1037 */ 1038 #define BGE_RBDI_MODE 0x2C00 1039 #define BGE_RBDI_STATUS 0x2C04 1040 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1041 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1042 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1043 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1044 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1045 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1046 1047 /* Receive BD Initiator Mode register */ 1048 #define BGE_RBDIMODE_RESET 0x00000001 1049 #define BGE_RBDIMODE_ENABLE 0x00000002 1050 #define BGE_RBDIMODE_ATTN 0x00000004 1051 1052 /* Receive BD Initiator Status register */ 1053 #define BGE_RBDISTAT_ATTN 0x00000004 1054 1055 /* 1056 * Receive BD Completion Control registers 1057 */ 1058 #define BGE_RBDC_MODE 0x3000 1059 #define BGE_RBDC_STATUS 0x3004 1060 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1061 #define BGE_RBDC_STD_BD_PROD 0x300C 1062 #define BGE_RBDC_MINI_BD_PROD 0x3010 1063 1064 /* Receive BD completion mode register */ 1065 #define BGE_RBDCMODE_RESET 0x00000001 1066 #define BGE_RBDCMODE_ENABLE 0x00000002 1067 #define BGE_RBDCMODE_ATTN 0x00000004 1068 1069 /* Receive BD completion status register */ 1070 #define BGE_RBDCSTAT_ERROR 0x00000004 1071 1072 /* 1073 * Receive List Selector Control registers 1074 */ 1075 #define BGE_RXLS_MODE 0x3400 1076 #define BGE_RXLS_STATUS 0x3404 1077 1078 /* Receive List Selector Mode register */ 1079 #define BGE_RXLSMODE_RESET 0x00000001 1080 #define BGE_RXLSMODE_ENABLE 0x00000002 1081 #define BGE_RXLSMODE_ATTN 0x00000004 1082 1083 /* Receive List Selector Status register */ 1084 #define BGE_RXLSSTAT_ERROR 0x00000004 1085 1086 /* 1087 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1088 */ 1089 #define BGE_MBCF_MODE 0x3800 1090 #define BGE_MBCF_STATUS 0x3804 1091 1092 /* Mbuf Cluster Free mode register */ 1093 #define BGE_MBCFMODE_RESET 0x00000001 1094 #define BGE_MBCFMODE_ENABLE 0x00000002 1095 #define BGE_MBCFMODE_ATTN 0x00000004 1096 1097 /* Mbuf Cluster Free status register */ 1098 #define BGE_MBCFSTAT_ERROR 0x00000004 1099 1100 /* 1101 * Host Coalescing Control registers 1102 */ 1103 #define BGE_HCC_MODE 0x3C00 1104 #define BGE_HCC_STATUS 0x3C04 1105 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1106 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1107 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1108 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1109 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1110 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1111 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1112 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1113 #define BGE_HCC_STATS_TICKS 0x3C28 1114 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1115 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1116 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1117 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1118 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1119 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1120 #define BGE_FLOW_ATTN 0x3C48 1121 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1122 #define BGE_HCC_STD_BD_CONS 0x3C54 1123 #define BGE_HCC_MINI_BD_CONS 0x3C58 1124 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1125 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1126 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1127 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1128 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1129 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1130 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1131 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1132 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1133 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1134 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1135 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1136 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1137 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1138 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1139 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1140 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1141 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1142 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1143 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1144 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1145 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1146 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1147 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1148 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1149 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1150 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1151 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1152 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1153 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1154 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1155 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1156 1157 1158 /* Host coalescing mode register */ 1159 #define BGE_HCCMODE_RESET 0x00000001 1160 #define BGE_HCCMODE_ENABLE 0x00000002 1161 #define BGE_HCCMODE_ATTN 0x00000004 1162 #define BGE_HCCMODE_COAL_NOW 0x00000008 1163 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1164 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1165 1166 #define BGE_STATBLKSZ_FULL 0x00000000 1167 #define BGE_STATBLKSZ_64BYTE 0x00000080 1168 #define BGE_STATBLKSZ_32BYTE 0x00000100 1169 1170 /* Host coalescing status register */ 1171 #define BGE_HCCSTAT_ERROR 0x00000004 1172 1173 /* Flow attention register */ 1174 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1175 #define BGE_FLOWATTN_MEMARB 0x00000080 1176 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1177 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1178 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1179 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1180 #define BGE_FLOWATTN_RDBDI 0x00080000 1181 #define BGE_FLOWATTN_RXLS 0x00100000 1182 #define BGE_FLOWATTN_RXLP 0x00200000 1183 #define BGE_FLOWATTN_RBDC 0x00400000 1184 #define BGE_FLOWATTN_RBDI 0x00800000 1185 #define BGE_FLOWATTN_SDC 0x08000000 1186 #define BGE_FLOWATTN_SDI 0x10000000 1187 #define BGE_FLOWATTN_SRS 0x20000000 1188 #define BGE_FLOWATTN_SBDC 0x40000000 1189 #define BGE_FLOWATTN_SBDI 0x80000000 1190 1191 /* 1192 * Memory arbiter registers 1193 */ 1194 #define BGE_MARB_MODE 0x4000 1195 #define BGE_MARB_STATUS 0x4004 1196 #define BGE_MARB_TRAPADDR_HI 0x4008 1197 #define BGE_MARB_TRAPADDR_LO 0x400C 1198 1199 /* Memory arbiter mode register */ 1200 #define BGE_MARBMODE_RESET 0x00000001 1201 #define BGE_MARBMODE_ENABLE 0x00000002 1202 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1203 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1204 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1205 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1206 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1207 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1208 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1209 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1210 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1211 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1212 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1213 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1214 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1215 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1216 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1217 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1218 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1219 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1220 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1221 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1222 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1223 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1224 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1225 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1226 1227 /* Memory arbiter status register */ 1228 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1229 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1230 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1231 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1232 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1233 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1234 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1235 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1236 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1237 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1238 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1239 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1240 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1241 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1242 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1243 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1244 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1245 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1246 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1247 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1248 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1249 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1250 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1251 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1252 1253 /* 1254 * Buffer manager control registers 1255 */ 1256 #define BGE_BMAN_MODE 0x4400 1257 #define BGE_BMAN_STATUS 0x4404 1258 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1259 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1260 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1261 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1262 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1263 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1264 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1265 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1266 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1267 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1268 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1269 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1270 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1271 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1272 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1273 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1274 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1275 #define BGE_BMAN_HWDIAG_1 0x444C 1276 #define BGE_BMAN_HWDIAG_2 0x4450 1277 #define BGE_BMAN_HWDIAG_3 0x4454 1278 1279 /* Buffer manager mode register */ 1280 #define BGE_BMANMODE_RESET 0x00000001 1281 #define BGE_BMANMODE_ENABLE 0x00000002 1282 #define BGE_BMANMODE_ATTN 0x00000004 1283 #define BGE_BMANMODE_TESTMODE 0x00000008 1284 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1285 1286 /* Buffer manager status register */ 1287 #define BGE_BMANSTAT_ERRO 0x00000004 1288 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1289 1290 1291 /* 1292 * Read DMA Control registers 1293 */ 1294 #define BGE_RDMA_MODE 0x4800 1295 #define BGE_RDMA_STATUS 0x4804 1296 1297 /* Read DMA mode register */ 1298 #define BGE_RDMAMODE_RESET 0x00000001 1299 #define BGE_RDMAMODE_ENABLE 0x00000002 1300 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1301 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1302 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1303 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1304 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1305 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1306 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1307 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1308 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1309 1310 /* Read DMA status register */ 1311 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1312 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1313 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1314 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1315 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1316 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1317 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1318 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1319 1320 /* 1321 * Write DMA control registers 1322 */ 1323 #define BGE_WDMA_MODE 0x4C00 1324 #define BGE_WDMA_STATUS 0x4C04 1325 1326 /* Write DMA mode register */ 1327 #define BGE_WDMAMODE_RESET 0x00000001 1328 #define BGE_WDMAMODE_ENABLE 0x00000002 1329 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1330 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1331 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1332 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1333 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1334 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1335 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1336 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1337 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1338 1339 /* Write DMA status register */ 1340 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1341 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1342 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1343 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1344 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1345 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1346 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1347 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1348 1349 1350 /* 1351 * RX CPU registers 1352 */ 1353 #define BGE_RXCPU_MODE 0x5000 1354 #define BGE_RXCPU_STATUS 0x5004 1355 #define BGE_RXCPU_PC 0x501C 1356 1357 /* RX CPU mode register */ 1358 #define BGE_RXCPUMODE_RESET 0x00000001 1359 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1360 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1361 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1362 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1363 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1364 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1365 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1366 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1367 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1368 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1369 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1370 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1371 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1372 1373 /* RX CPU status register */ 1374 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1375 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1376 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1377 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1378 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1379 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1380 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1381 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1382 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1383 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1384 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1385 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1386 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1387 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1388 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1389 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1390 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1391 1392 1393 /* 1394 * TX CPU registers 1395 */ 1396 #define BGE_TXCPU_MODE 0x5400 1397 #define BGE_TXCPU_STATUS 0x5404 1398 #define BGE_TXCPU_PC 0x541C 1399 1400 /* TX CPU mode register */ 1401 #define BGE_TXCPUMODE_RESET 0x00000001 1402 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1403 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1404 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1405 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1406 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1407 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1408 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1409 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1410 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1411 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1412 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1413 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1414 1415 /* TX CPU status register */ 1416 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1417 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1418 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1419 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1420 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1421 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1422 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1423 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1424 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1425 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1426 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1427 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1428 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1429 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1430 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1431 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1432 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1433 1434 1435 /* 1436 * Low priority mailbox registers 1437 */ 1438 #define BGE_LPMBX_IRQ0_HI 0x5800 1439 #define BGE_LPMBX_IRQ0_LO 0x5804 1440 #define BGE_LPMBX_IRQ1_HI 0x5808 1441 #define BGE_LPMBX_IRQ1_LO 0x580C 1442 #define BGE_LPMBX_IRQ2_HI 0x5810 1443 #define BGE_LPMBX_IRQ2_LO 0x5814 1444 #define BGE_LPMBX_IRQ3_HI 0x5818 1445 #define BGE_LPMBX_IRQ3_LO 0x581C 1446 #define BGE_LPMBX_GEN0_HI 0x5820 1447 #define BGE_LPMBX_GEN0_LO 0x5824 1448 #define BGE_LPMBX_GEN1_HI 0x5828 1449 #define BGE_LPMBX_GEN1_LO 0x582C 1450 #define BGE_LPMBX_GEN2_HI 0x5830 1451 #define BGE_LPMBX_GEN2_LO 0x5834 1452 #define BGE_LPMBX_GEN3_HI 0x5828 1453 #define BGE_LPMBX_GEN3_LO 0x582C 1454 #define BGE_LPMBX_GEN4_HI 0x5840 1455 #define BGE_LPMBX_GEN4_LO 0x5844 1456 #define BGE_LPMBX_GEN5_HI 0x5848 1457 #define BGE_LPMBX_GEN5_LO 0x584C 1458 #define BGE_LPMBX_GEN6_HI 0x5850 1459 #define BGE_LPMBX_GEN6_LO 0x5854 1460 #define BGE_LPMBX_GEN7_HI 0x5858 1461 #define BGE_LPMBX_GEN7_LO 0x585C 1462 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1463 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1464 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1465 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1466 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1467 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1468 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1469 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1470 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1471 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1472 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1473 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1474 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1475 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1476 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1477 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1478 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1479 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1480 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1481 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1482 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1483 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1484 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1485 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1486 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1487 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1488 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1489 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1490 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1491 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1492 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1493 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1494 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1495 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1496 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1497 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1498 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1499 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1500 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1501 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1502 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1503 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1504 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1505 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1506 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1507 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1508 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1509 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1510 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1511 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1512 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1513 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1514 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1515 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1516 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1517 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1518 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1519 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1520 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1521 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1522 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1523 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1524 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1525 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1526 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1527 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1528 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1529 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1530 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1531 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1532 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1533 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1534 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1535 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1536 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1537 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1538 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1539 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1540 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1541 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1542 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1543 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1544 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1545 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1546 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1547 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1548 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1549 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1550 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1551 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1552 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1553 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1554 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1555 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1556 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1557 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1558 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1559 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1560 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1561 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1562 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1563 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1564 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1565 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1566 1567 /* 1568 * Flow throw Queue reset register 1569 */ 1570 #define BGE_FTQ_RESET 0x5C00 1571 1572 #define BGE_FTQRESET_DMAREAD 0x00000002 1573 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1574 #define BGE_FTQRESET_DMADONE 0x00000010 1575 #define BGE_FTQRESET_SBDC 0x00000020 1576 #define BGE_FTQRESET_SDI 0x00000040 1577 #define BGE_FTQRESET_WDMA 0x00000080 1578 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1579 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1580 #define BGE_FTQRESET_SDC 0x00000400 1581 #define BGE_FTQRESET_HCC 0x00000800 1582 #define BGE_FTQRESET_TXFIFO 0x00001000 1583 #define BGE_FTQRESET_MBC 0x00002000 1584 #define BGE_FTQRESET_RBDC 0x00004000 1585 #define BGE_FTQRESET_RXLP 0x00008000 1586 #define BGE_FTQRESET_RDBDI 0x00010000 1587 #define BGE_FTQRESET_RDC 0x00020000 1588 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1589 1590 /* 1591 * Message Signaled Interrupt registers 1592 */ 1593 #define BGE_MSI_MODE 0x6000 1594 #define BGE_MSI_STATUS 0x6004 1595 #define BGE_MSI_FIFOACCESS 0x6008 1596 1597 /* MSI mode register */ 1598 #define BGE_MSIMODE_RESET 0x00000001 1599 #define BGE_MSIMODE_ENABLE 0x00000002 1600 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1601 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1602 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1603 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1604 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1605 1606 /* MSI status register */ 1607 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1608 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1609 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1610 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1611 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1612 1613 1614 /* 1615 * DMA Completion registers 1616 */ 1617 #define BGE_DMAC_MODE 0x6400 1618 1619 /* DMA Completion mode register */ 1620 #define BGE_DMACMODE_RESET 0x00000001 1621 #define BGE_DMACMODE_ENABLE 0x00000002 1622 1623 1624 /* 1625 * General control registers. 1626 */ 1627 #define BGE_MODE_CTL 0x6800 1628 #define BGE_MISC_CFG 0x6804 1629 #define BGE_MISC_LOCAL_CTL 0x6808 1630 #define BGE_EE_ADDR 0x6838 1631 #define BGE_EE_DATA 0x683C 1632 #define BGE_EE_CTL 0x6840 1633 #define BGE_MDI_CTL 0x6844 1634 #define BGE_EE_DELAY 0x6848 1635 1636 /* Mode control register */ 1637 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1638 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1639 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1640 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1641 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1642 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1643 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1644 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1645 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1646 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1647 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1648 #define BGE_MODECTL_STACKUP 0x00010000 1649 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1650 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1651 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1652 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1653 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1654 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1655 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1656 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1657 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1658 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1659 1660 /* Misc. config register */ 1661 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1662 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1663 1664 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1665 1666 /* Misc. Local Control */ 1667 #define BGE_MLC_INTR_STATE 0x00000001 1668 #define BGE_MLC_INTR_CLR 0x00000002 1669 #define BGE_MLC_INTR_SET 0x00000004 1670 #define BGE_MLC_INTR_ONATTN 0x00000008 1671 #define BGE_MLC_MISCIO_IN0 0x00000100 1672 #define BGE_MLC_MISCIO_IN1 0x00000200 1673 #define BGE_MLC_MISCIO_IN2 0x00000400 1674 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1675 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1676 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1677 #define BGE_MLC_MISCIO_OUT0 0x00004000 1678 #define BGE_MLC_MISCIO_OUT1 0x00008000 1679 #define BGE_MLC_MISCIO_OUT2 0x00010000 1680 #define BGE_MLC_EXTRAM_ENB 0x00020000 1681 #define BGE_MLC_SRAM_SIZE 0x001C0000 1682 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1683 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1684 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1685 #define BGE_MLC_AUTO_EEPROM 0x01000000 1686 1687 #define BGE_SSRAMSIZE_256KB 0x00000000 1688 #define BGE_SSRAMSIZE_512KB 0x00040000 1689 #define BGE_SSRAMSIZE_1MB 0x00080000 1690 #define BGE_SSRAMSIZE_2MB 0x000C0000 1691 #define BGE_SSRAMSIZE_4MB 0x00100000 1692 #define BGE_SSRAMSIZE_8MB 0x00140000 1693 #define BGE_SSRAMSIZE_16M 0x00180000 1694 1695 /* EEPROM address register */ 1696 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1697 #define BGE_EEADDR_HALFCLK 0x01FF0000 1698 #define BGE_EEADDR_START 0x02000000 1699 #define BGE_EEADDR_DEVID 0x1C000000 1700 #define BGE_EEADDR_RESET 0x20000000 1701 #define BGE_EEADDR_DONE 0x40000000 1702 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1703 1704 #define BGE_EEDEVID(x) ((x & 7) << 26) 1705 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1706 #define BGE_HALFCLK_384SCL 0x60 1707 #define BGE_EE_READCMD \ 1708 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1709 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1710 #define BGE_EE_WRCMD \ 1711 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1712 BGE_EEADDR_START|BGE_EEADDR_DONE) 1713 1714 /* EEPROM Control register */ 1715 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1716 #define BGE_EECTL_CLKOUT 0x00000002 1717 #define BGE_EECTL_CLKIN 0x00000004 1718 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1719 #define BGE_EECTL_DATAOUT 0x00000010 1720 #define BGE_EECTL_DATAIN 0x00000020 1721 1722 /* MDI (MII/GMII) access register */ 1723 #define BGE_MDI_DATA 0x00000001 1724 #define BGE_MDI_DIR 0x00000002 1725 #define BGE_MDI_SEL 0x00000004 1726 #define BGE_MDI_CLK 0x00000008 1727 1728 #define BGE_MEMWIN_START 0x00008000 1729 #define BGE_MEMWIN_END 0x0000FFFF 1730 1731 1732 #define BGE_MEMWIN_READ(sc, x, val) \ 1733 do { \ 1734 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1735 (0xFFFF0000 & x), 4); \ 1736 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1737 } while(0) 1738 1739 #define BGE_MEMWIN_WRITE(sc, x, val) \ 1740 do { \ 1741 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1742 (0xFFFF0000 & x), 4); \ 1743 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1744 } while(0) 1745 1746 /* 1747 * This magic number is used to prevent PXE restart when we 1748 * issue a software reset. We write this magic number to the 1749 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1750 * code from running. 1751 */ 1752 #define BGE_MAGIC_NUMBER 0x4B657654 1753 1754 typedef struct { 1755 u_int32_t bge_addr_hi; 1756 u_int32_t bge_addr_lo; 1757 } bge_hostaddr; 1758 1759 #define BGE_HOSTADDR(x, y) \ 1760 do { \ 1761 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1762 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1763 } while(0) 1764 1765 #define BGE_ADDR_LO(y) \ 1766 ((u_int64_t) (y) & 0xFFFFFFFF) 1767 #define BGE_ADDR_HI(y) \ 1768 ((u_int64_t) (y) >> 32) 1769 1770 /* Ring control block structure */ 1771 struct bge_rcb { 1772 bge_hostaddr bge_hostaddr; 1773 u_int32_t bge_maxlen_flags; 1774 u_int32_t bge_nicaddr; 1775 }; 1776 1777 #define RCB_WRITE_4(sc, rcb, offset, val) \ 1778 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1779 rcb + offsetof(struct bge_rcb, offset), val) 1780 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1781 1782 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1783 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1784 1785 struct bge_tx_bd { 1786 bge_hostaddr bge_addr; 1787 #if BYTE_ORDER == LITTLE_ENDIAN 1788 u_int16_t bge_flags; 1789 u_int16_t bge_len; 1790 u_int16_t bge_vlan_tag; 1791 u_int16_t bge_rsvd; 1792 #else 1793 u_int16_t bge_len; 1794 u_int16_t bge_flags; 1795 u_int16_t bge_rsvd; 1796 u_int16_t bge_vlan_tag; 1797 #endif 1798 }; 1799 1800 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1801 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1802 #define BGE_TXBDFLAG_END 0x0004 1803 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1804 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1805 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1806 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1807 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1808 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1809 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1810 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1811 #define BGE_TXBDFLAG_NO_CRC 0x8000 1812 1813 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1814 BGE_SEND_RING_1_TO_4 + \ 1815 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1816 1817 struct bge_rx_bd { 1818 bge_hostaddr bge_addr; 1819 #if BYTE_ORDER == LITTLE_ENDIAN 1820 u_int16_t bge_len; 1821 u_int16_t bge_idx; 1822 u_int16_t bge_flags; 1823 u_int16_t bge_type; 1824 u_int16_t bge_tcp_udp_csum; 1825 u_int16_t bge_ip_csum; 1826 u_int16_t bge_vlan_tag; 1827 u_int16_t bge_error_flag; 1828 #else 1829 u_int16_t bge_idx; 1830 u_int16_t bge_len; 1831 u_int16_t bge_type; 1832 u_int16_t bge_flags; 1833 u_int16_t bge_ip_csum; 1834 u_int16_t bge_tcp_udp_csum; 1835 u_int16_t bge_error_flag; 1836 u_int16_t bge_vlan_tag; 1837 #endif 1838 u_int32_t bge_rsvd; 1839 u_int32_t bge_opaque; 1840 }; 1841 1842 struct bge_extrx_bd { 1843 bge_hostaddr bge_addr1; 1844 bge_hostaddr bge_addr2; 1845 bge_hostaddr bge_addr3; 1846 #if BYTE_ORDER == LITTLE_ENDIAN 1847 u_int16_t bge_len2; 1848 u_int16_t bge_len1; 1849 u_int16_t bge_rsvd1; 1850 u_int16_t bge_len3; 1851 #else 1852 u_int16_t bge_len1; 1853 u_int16_t bge_len2; 1854 u_int16_t bge_len3; 1855 u_int16_t bge_rsvd1; 1856 #endif 1857 bge_hostaddr bge_addr0; 1858 #if BYTE_ORDER == LITTLE_ENDIAN 1859 u_int16_t bge_len0; 1860 u_int16_t bge_idx; 1861 u_int16_t bge_flags; 1862 u_int16_t bge_type; 1863 u_int16_t bge_tcp_udp_csum; 1864 u_int16_t bge_ip_csum; 1865 u_int16_t bge_vlan_tag; 1866 u_int16_t bge_error_flag; 1867 #else 1868 u_int16_t bge_idx; 1869 u_int16_t bge_len0; 1870 u_int16_t bge_type; 1871 u_int16_t bge_flags; 1872 u_int16_t bge_ip_csum; 1873 u_int16_t bge_tcp_udp_csum; 1874 u_int16_t bge_error_flag; 1875 u_int16_t bge_vlan_tag; 1876 #endif 1877 u_int32_t bge_rsvd0; 1878 u_int32_t bge_opaque; 1879 }; 1880 1881 #define BGE_RXBDFLAG_END 0x0004 1882 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1883 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1884 #define BGE_RXBDFLAG_ERROR 0x0400 1885 #define BGE_RXBDFLAG_MINI_RING 0x0800 1886 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1887 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1888 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1889 1890 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1891 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1892 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1893 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1894 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1895 #define BGE_RXERRFLAG_RUNT 0x0020 1896 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1897 #define BGE_RXERRFLAG_GIANT 0x0080 1898 1899 struct bge_sts_idx { 1900 #if BYTE_ORDER == LITTLE_ENDIAN 1901 u_int16_t bge_rx_prod_idx; 1902 u_int16_t bge_tx_cons_idx; 1903 #else 1904 u_int16_t bge_tx_cons_idx; 1905 u_int16_t bge_rx_prod_idx; 1906 #endif 1907 }; 1908 1909 struct bge_status_block { 1910 u_int32_t bge_status; 1911 u_int32_t bge_rsvd0; 1912 #if BYTE_ORDER == LITTLE_ENDIAN 1913 u_int16_t bge_rx_jumbo_cons_idx; 1914 u_int16_t bge_rx_std_cons_idx; 1915 u_int16_t bge_rx_mini_cons_idx; 1916 u_int16_t bge_rsvd1; 1917 #else 1918 u_int16_t bge_rx_std_cons_idx; 1919 u_int16_t bge_rx_jumbo_cons_idx; 1920 u_int16_t bge_rsvd1; 1921 u_int16_t bge_rx_mini_cons_idx; 1922 #endif 1923 struct bge_sts_idx bge_idx[16]; 1924 }; 1925 1926 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1927 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1928 1929 #define BGE_STATFLAG_UPDATED 0x00000001 1930 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1931 #define BGE_STATFLAG_ERROR 0x00000004 1932 1933 1934 /* 1935 * Broadcom Vendor ID 1936 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1937 * even though they're now manufactured by Broadcom) 1938 */ 1939 #define BCOM_VENDORID 0x14E4 1940 #define BCOM_DEVICEID_BCM5700 0x1644 1941 #define BCOM_DEVICEID_BCM5701 0x1645 1942 #define BCOM_DEVICEID_BCM5702 0x16A6 1943 #define BCOM_DEVICEID_BCM5702X 0x16C6 1944 #define BCOM_DEVICEID_BCM5703 0x16A7 1945 #define BCOM_DEVICEID_BCM5703X 0x16C7 1946 #define BCOM_DEVICEID_BCM5704C 0x1648 1947 #define BCOM_DEVICEID_BCM5704S 0x16A8 1948 #define BCOM_DEVICEID_BCM5705 0x1653 1949 #define BCOM_DEVICEID_BCM5705K 0x1654 1950 #define BCOM_DEVICEID_BCM5721 0x1659 1951 #define BCOM_DEVICEID_BCM5705M 0x165D 1952 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1953 #define BCOM_DEVICEID_BCM5714C 0x1668 1954 #define BCOM_DEVICEID_BCM5750 0x1676 1955 #define BCOM_DEVICEID_BCM5750M 0x167C 1956 #define BCOM_DEVICEID_BCM5751 0x1677 1957 #define BCOM_DEVICEID_BCM5751M 0x167D 1958 #define BCOM_DEVICEID_BCM5752 0x1600 1959 #define BCOM_DEVICEID_BCM5782 0x1696 1960 #define BCOM_DEVICEID_BCM5788 0x169C 1961 #define BCOM_DEVICEID_BCM5789 0x169D 1962 #define BCOM_DEVICEID_BCM5901 0x170D 1963 #define BCOM_DEVICEID_BCM5901A2 0x170E 1964 1965 /* 1966 * Alteon AceNIC PCI vendor/device ID. 1967 */ 1968 #define ALT_VENDORID 0x12AE 1969 #define ALT_DEVICEID_ACENIC 0x0001 1970 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1971 #define ALT_DEVICEID_BCM5700 0x0003 1972 #define ALT_DEVICEID_BCM5701 0x0004 1973 1974 /* 1975 * 3Com 3c985 PCI vendor/device ID. 1976 */ 1977 #define TC_VENDORID 0x10B7 1978 #define TC_DEVICEID_3C985 0x0001 1979 #define TC_DEVICEID_3C996 0x0003 1980 1981 /* 1982 * SysKonnect PCI vendor ID 1983 */ 1984 #define SK_VENDORID 0x1148 1985 #define SK_DEVICEID_ALTIMA 0x4400 1986 #define SK_SUBSYSID_9D21 0x4421 1987 #define SK_SUBSYSID_9D41 0x4441 1988 1989 /* 1990 * Altima PCI vendor/device ID. 1991 */ 1992 #define ALTIMA_VENDORID 0x173b 1993 #define ALTIMA_DEVICE_AC1000 0x03e8 1994 #define ALTIMA_DEVICE_AC1002 0x03e9 1995 #define ALTIMA_DEVICE_AC9100 0x03ea 1996 1997 /* 1998 * Dell PCI vendor ID 1999 */ 2000 2001 #define DELL_VENDORID 0x1028 2002 2003 /* 2004 * Offset of MAC address inside EEPROM. 2005 */ 2006 #define BGE_EE_MAC_OFFSET 0x7C 2007 #define BGE_EE_HWCFG_OFFSET 0xC8 2008 2009 #define BGE_HWCFG_VOLTAGE 0x00000003 2010 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 2011 #define BGE_HWCFG_MEDIA 0x00000030 2012 2013 #define BGE_VOLTAGE_1POINT3 0x00000000 2014 #define BGE_VOLTAGE_1POINT8 0x00000001 2015 2016 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 2017 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2018 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 2019 2020 #define BGE_MEDIA_UNSPEC 0x00000000 2021 #define BGE_MEDIA_COPPER 0x00000010 2022 #define BGE_MEDIA_FIBER 0x00000020 2023 2024 #define BGE_PCI_READ_CMD 0x06000000 2025 #define BGE_PCI_WRITE_CMD 0x70000000 2026 2027 #define BGE_TICKS_PER_SEC 1000000 2028 2029 /* 2030 * Ring size constants. 2031 */ 2032 #define BGE_EVENT_RING_CNT 256 2033 #define BGE_CMD_RING_CNT 64 2034 #define BGE_STD_RX_RING_CNT 512 2035 #define BGE_JUMBO_RX_RING_CNT 256 2036 #define BGE_MINI_RX_RING_CNT 1024 2037 #define BGE_RETURN_RING_CNT 1024 2038 2039 /* 5705 has smaller return ring size */ 2040 2041 #define BGE_RETURN_RING_CNT_5705 512 2042 2043 /* 2044 * Possible TX ring sizes. 2045 */ 2046 #define BGE_TX_RING_CNT_128 128 2047 #define BGE_TX_RING_BASE_128 0x3800 2048 2049 #define BGE_TX_RING_CNT_256 256 2050 #define BGE_TX_RING_BASE_256 0x3000 2051 2052 #define BGE_TX_RING_CNT_512 512 2053 #define BGE_TX_RING_BASE_512 0x2000 2054 2055 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2056 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2057 2058 /* 2059 * Tigon III statistics counters. 2060 */ 2061 /* Statistics maintained MAC Receive block. */ 2062 struct bge_rx_mac_stats { 2063 bge_hostaddr ifHCInOctets; 2064 bge_hostaddr Reserved1; 2065 bge_hostaddr etherStatsFragments; 2066 bge_hostaddr ifHCInUcastPkts; 2067 bge_hostaddr ifHCInMulticastPkts; 2068 bge_hostaddr ifHCInBroadcastPkts; 2069 bge_hostaddr dot3StatsFCSErrors; 2070 bge_hostaddr dot3StatsAlignmentErrors; 2071 bge_hostaddr xonPauseFramesReceived; 2072 bge_hostaddr xoffPauseFramesReceived; 2073 bge_hostaddr macControlFramesReceived; 2074 bge_hostaddr xoffStateEntered; 2075 bge_hostaddr dot3StatsFramesTooLong; 2076 bge_hostaddr etherStatsJabbers; 2077 bge_hostaddr etherStatsUndersizePkts; 2078 bge_hostaddr inRangeLengthError; 2079 bge_hostaddr outRangeLengthError; 2080 bge_hostaddr etherStatsPkts64Octets; 2081 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2082 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2083 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2084 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2085 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2086 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2087 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2088 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2089 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2090 }; 2091 2092 2093 /* Statistics maintained MAC Transmit block. */ 2094 struct bge_tx_mac_stats { 2095 bge_hostaddr ifHCOutOctets; 2096 bge_hostaddr Reserved2; 2097 bge_hostaddr etherStatsCollisions; 2098 bge_hostaddr outXonSent; 2099 bge_hostaddr outXoffSent; 2100 bge_hostaddr flowControlDone; 2101 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2102 bge_hostaddr dot3StatsSingleCollisionFrames; 2103 bge_hostaddr dot3StatsMultipleCollisionFrames; 2104 bge_hostaddr dot3StatsDeferredTransmissions; 2105 bge_hostaddr Reserved3; 2106 bge_hostaddr dot3StatsExcessiveCollisions; 2107 bge_hostaddr dot3StatsLateCollisions; 2108 bge_hostaddr dot3Collided2Times; 2109 bge_hostaddr dot3Collided3Times; 2110 bge_hostaddr dot3Collided4Times; 2111 bge_hostaddr dot3Collided5Times; 2112 bge_hostaddr dot3Collided6Times; 2113 bge_hostaddr dot3Collided7Times; 2114 bge_hostaddr dot3Collided8Times; 2115 bge_hostaddr dot3Collided9Times; 2116 bge_hostaddr dot3Collided10Times; 2117 bge_hostaddr dot3Collided11Times; 2118 bge_hostaddr dot3Collided12Times; 2119 bge_hostaddr dot3Collided13Times; 2120 bge_hostaddr dot3Collided14Times; 2121 bge_hostaddr dot3Collided15Times; 2122 bge_hostaddr ifHCOutUcastPkts; 2123 bge_hostaddr ifHCOutMulticastPkts; 2124 bge_hostaddr ifHCOutBroadcastPkts; 2125 bge_hostaddr dot3StatsCarrierSenseErrors; 2126 bge_hostaddr ifOutDiscards; 2127 bge_hostaddr ifOutErrors; 2128 }; 2129 2130 /* Stats counters access through registers */ 2131 struct bge_mac_stats_regs { 2132 u_int32_t ifHCOutOctets; 2133 u_int32_t Reserved0; 2134 u_int32_t etherStatsCollisions; 2135 u_int32_t outXonSent; 2136 u_int32_t outXoffSent; 2137 u_int32_t Reserved1; 2138 u_int32_t dot3StatsInternalMacTransmitErrors; 2139 u_int32_t dot3StatsSingleCollisionFrames; 2140 u_int32_t dot3StatsMultipleCollisionFrames; 2141 u_int32_t dot3StatsDeferredTransmissions; 2142 u_int32_t Reserved2; 2143 u_int32_t dot3StatsExcessiveCollisions; 2144 u_int32_t dot3StatsLateCollisions; 2145 u_int32_t Reserved3[14]; 2146 u_int32_t ifHCOutUcastPkts; 2147 u_int32_t ifHCOutMulticastPkts; 2148 u_int32_t ifHCOutBroadcastPkts; 2149 u_int32_t Reserved4[2]; 2150 u_int32_t ifHCInOctets; 2151 u_int32_t Reserved5; 2152 u_int32_t etherStatsFragments; 2153 u_int32_t ifHCInUcastPkts; 2154 u_int32_t ifHCInMulticastPkts; 2155 u_int32_t ifHCInBroadcastPkts; 2156 u_int32_t dot3StatsFCSErrors; 2157 u_int32_t dot3StatsAlignmentErrors; 2158 u_int32_t xonPauseFramesReceived; 2159 u_int32_t xoffPauseFramesReceived; 2160 u_int32_t macControlFramesReceived; 2161 u_int32_t xoffStateEntered; 2162 u_int32_t dot3StatsFramesTooLong; 2163 u_int32_t etherStatsJabbers; 2164 u_int32_t etherStatsUndersizePkts; 2165 }; 2166 2167 struct bge_stats { 2168 u_int8_t Reserved0[256]; 2169 2170 /* Statistics maintained by Receive MAC. */ 2171 struct bge_rx_mac_stats rxstats; 2172 2173 bge_hostaddr Unused1[37]; 2174 2175 /* Statistics maintained by Transmit MAC. */ 2176 struct bge_tx_mac_stats txstats; 2177 2178 bge_hostaddr Unused2[31]; 2179 2180 /* Statistics maintained by Receive List Placement. */ 2181 bge_hostaddr COSIfHCInPkts[16]; 2182 bge_hostaddr COSFramesDroppedDueToFilters; 2183 bge_hostaddr nicDmaWriteQueueFull; 2184 bge_hostaddr nicDmaWriteHighPriQueueFull; 2185 bge_hostaddr nicNoMoreRxBDs; 2186 bge_hostaddr ifInDiscards; 2187 bge_hostaddr ifInErrors; 2188 bge_hostaddr nicRecvThresholdHit; 2189 2190 bge_hostaddr Unused3[9]; 2191 2192 /* Statistics maintained by Send Data Initiator. */ 2193 bge_hostaddr COSIfHCOutPkts[16]; 2194 bge_hostaddr nicDmaReadQueueFull; 2195 bge_hostaddr nicDmaReadHighPriQueueFull; 2196 bge_hostaddr nicSendDataCompQueueFull; 2197 2198 /* Statistics maintained by Host Coalescing. */ 2199 bge_hostaddr nicRingSetSendProdIndex; 2200 bge_hostaddr nicRingStatusUpdate; 2201 bge_hostaddr nicInterrupts; 2202 bge_hostaddr nicAvoidedInterrupts; 2203 bge_hostaddr nicSendThresholdHit; 2204 2205 u_int8_t Reserved4[320]; 2206 }; 2207 2208 /* 2209 * Tigon general information block. This resides in host memory 2210 * and contains the status counters, ring control blocks and 2211 * producer pointers. 2212 */ 2213 2214 struct bge_gib { 2215 struct bge_stats bge_stats; 2216 struct bge_rcb bge_tx_rcb[16]; 2217 struct bge_rcb bge_std_rx_rcb; 2218 struct bge_rcb bge_jumbo_rx_rcb; 2219 struct bge_rcb bge_mini_rx_rcb; 2220 struct bge_rcb bge_return_rcb; 2221 }; 2222 2223 #define BGE_FRAMELEN 1518 2224 #define BGE_MAX_FRAMELEN 1536 2225 #define BGE_JUMBO_FRAMELEN 9018 2226 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2227 #define BGE_MIN_FRAMELEN 60 2228 2229 /* 2230 * Other utility macros. 2231 */ 2232 #define BGE_INC(x, y) (x) = (x + 1) % y 2233 2234 /* 2235 * Vital product data and structures. 2236 */ 2237 #define BGE_VPD_FLAG 0x8000 2238 2239 /* VPD structures */ 2240 struct vpd_res { 2241 u_int8_t vr_id; 2242 u_int8_t vr_len; 2243 u_int8_t vr_pad; 2244 }; 2245 2246 struct vpd_key { 2247 char vk_key[2]; 2248 u_int8_t vk_len; 2249 }; 2250 2251 #define VPD_RES_ID 0x82 /* ID string */ 2252 #define VPD_RES_READ 0x90 /* start of read only area */ 2253 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2254 #define VPD_RES_END 0x78 /* end tag */ 2255 2256 2257 /* 2258 * Register access macros. The Tigon always uses memory mapped register 2259 * accesses and all registers must be accessed with 32 bit operations. 2260 */ 2261 2262 #define CSR_WRITE_4(sc, reg, val) \ 2263 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2264 2265 #define CSR_READ_4(sc, reg) \ 2266 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2267 2268 #define BGE_SETBIT(sc, reg, x) \ 2269 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2270 #define BGE_CLRBIT(sc, reg, x) \ 2271 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2272 2273 #define PCI_SETBIT(dev, reg, x, s) \ 2274 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2275 #define PCI_CLRBIT(dev, reg, x, s) \ 2276 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2277 2278 /* 2279 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2280 * values are tuneable. They control the actual amount of buffers 2281 * allocated for the standard, mini and jumbo receive rings. 2282 */ 2283 2284 #define BGE_SSLOTS 256 2285 #define BGE_MSLOTS 256 2286 #define BGE_JSLOTS 384 2287 2288 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2289 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2290 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2291 #define BGE_JPAGESZ PAGE_SIZE 2292 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2293 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2294 2295 #define BGE_NSEG_JUMBO 4 2296 #define BGE_NSEG_NEW 32 2297 2298 /* 2299 * Ring structures. Most of these reside in host memory and we tell 2300 * the NIC where they are via the ring control blocks. The exceptions 2301 * are the tx and command rings, which live in NIC memory and which 2302 * we access via the shared memory window. 2303 */ 2304 2305 struct bge_ring_data { 2306 struct bge_rx_bd *bge_rx_std_ring; 2307 bus_addr_t bge_rx_std_ring_paddr; 2308 struct bge_extrx_bd *bge_rx_jumbo_ring; 2309 bus_addr_t bge_rx_jumbo_ring_paddr; 2310 struct bge_rx_bd *bge_rx_return_ring; 2311 bus_addr_t bge_rx_return_ring_paddr; 2312 struct bge_tx_bd *bge_tx_ring; 2313 bus_addr_t bge_tx_ring_paddr; 2314 struct bge_status_block *bge_status_block; 2315 bus_addr_t bge_status_block_paddr; 2316 struct bge_stats *bge_stats; 2317 bus_addr_t bge_stats_paddr; 2318 struct bge_gib bge_info; 2319 }; 2320 2321 #define BGE_STD_RX_RING_SZ \ 2322 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2323 #define BGE_JUMBO_RX_RING_SZ \ 2324 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2325 #define BGE_TX_RING_SZ \ 2326 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2327 #define BGE_RX_RTN_RING_SZ(x) \ 2328 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2329 2330 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2331 2332 #define BGE_STATS_SZ sizeof (struct bge_stats) 2333 2334 /* 2335 * Mbuf pointers. We need these to keep track of the virtual addresses 2336 * of our mbuf chains since we can only convert from physical to virtual, 2337 * not the other way around. 2338 */ 2339 struct bge_chain_data { 2340 bus_dma_tag_t bge_parent_tag; 2341 bus_dma_tag_t bge_rx_std_ring_tag; 2342 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2343 bus_dma_tag_t bge_rx_return_ring_tag; 2344 bus_dma_tag_t bge_tx_ring_tag; 2345 bus_dma_tag_t bge_status_tag; 2346 bus_dma_tag_t bge_stats_tag; 2347 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2348 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2349 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2350 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2351 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2352 bus_dmamap_t bge_rx_std_ring_map; 2353 bus_dmamap_t bge_rx_jumbo_ring_map; 2354 bus_dmamap_t bge_tx_ring_map; 2355 bus_dmamap_t bge_rx_return_ring_map; 2356 bus_dmamap_t bge_status_map; 2357 bus_dmamap_t bge_stats_map; 2358 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2359 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2360 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2361 }; 2362 2363 struct bge_dmamap_arg { 2364 struct bge_softc *sc; 2365 bus_addr_t bge_busaddr; 2366 u_int16_t bge_flags; 2367 int bge_idx; 2368 int bge_maxsegs; 2369 struct bge_tx_bd *bge_ring; 2370 }; 2371 2372 struct bge_type { 2373 u_int16_t bge_vid; 2374 u_int16_t bge_did; 2375 char *bge_name; 2376 }; 2377 2378 #define BGE_HWREV_TIGON 0x01 2379 #define BGE_HWREV_TIGON_II 0x02 2380 #define BGE_TIMEOUT 100000 2381 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2382 2383 struct bge_bcom_hack { 2384 int reg; 2385 int val; 2386 }; 2387 2388 struct bge_softc { 2389 struct ifnet *bge_ifp; /* interface info */ 2390 device_t bge_dev; 2391 struct mtx bge_mtx; 2392 device_t bge_miibus; 2393 bus_space_handle_t bge_bhandle; 2394 bus_space_tag_t bge_btag; 2395 void *bge_intrhand; 2396 struct resource *bge_irq; 2397 struct resource *bge_res; 2398 struct ifmedia bge_ifmedia; /* TBI media info */ 2399 u_int8_t bge_extram; /* has external SSRAM */ 2400 u_int8_t bge_tbi; 2401 u_int8_t bge_rx_alignment_bug; 2402 u_int32_t bge_chipid; 2403 u_int8_t bge_asicrev; 2404 u_int8_t bge_chiprev; 2405 u_int8_t bge_no_3_led; 2406 u_int8_t bge_pcie; 2407 struct bge_ring_data bge_ldata; /* rings */ 2408 struct bge_chain_data bge_cdata; /* mbufs */ 2409 u_int16_t bge_tx_saved_considx; 2410 u_int16_t bge_rx_saved_considx; 2411 u_int16_t bge_ev_saved_considx; 2412 u_int16_t bge_return_ring_cnt; 2413 u_int16_t bge_std; /* current std ring head */ 2414 u_int16_t bge_jumbo; /* current jumo ring head */ 2415 u_int32_t bge_stat_ticks; 2416 u_int32_t bge_rx_coal_ticks; 2417 u_int32_t bge_tx_coal_ticks; 2418 u_int32_t bge_tx_prodidx; 2419 u_int32_t bge_rx_max_coal_bds; 2420 u_int32_t bge_tx_max_coal_bds; 2421 u_int32_t bge_tx_buf_ratio; 2422 int bge_if_flags; 2423 int bge_txcnt; 2424 int bge_link; /* link state */ 2425 int bge_link_evt; /* pending link event */ 2426 struct callout bge_stat_ch; 2427 char *bge_vpd_prodname; 2428 char *bge_vpd_readonly; 2429 u_long bge_rx_discards; 2430 u_long bge_tx_discards; 2431 u_long bge_tx_collisions; 2432 #ifdef DEVICE_POLLING 2433 int rxcycles; 2434 #endif /* DEVICE_POLLING */ 2435 }; 2436 2437 #define BGE_LOCK_INIT(_sc, _name) \ 2438 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2439 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2440 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2441 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2442 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2443