1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36 /* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64 #define BGE_PAGE_ZERO 0x00000000 65 #define BGE_PAGE_ZERO_END 0x000000FF 66 #define BGE_SEND_RING_RCB 0x00000100 67 #define BGE_SEND_RING_RCB_END 0x000001FF 68 #define BGE_RX_RETURN_RING_RCB 0x00000200 69 #define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70 #define BGE_STATS_BLOCK 0x00000300 71 #define BGE_STATS_BLOCK_END 0x00000AFF 72 #define BGE_STATUS_BLOCK 0x00000B00 73 #define BGE_STATUS_BLOCK_END 0x00000B4F 74 #define BGE_SOFTWARE_GENCOMM 0x00000B50 75 #define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76 #define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77 #define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 78 #define BGE_UNMAPPED 0x00001000 79 #define BGE_UNMAPPED_END 0x00001FFF 80 #define BGE_DMA_DESCRIPTORS 0x00002000 81 #define BGE_DMA_DESCRIPTORS_END 0x00003FFF 82 #define BGE_SEND_RING_1_TO_4 0x00004000 83 #define BGE_SEND_RING_1_TO_4_END 0x00005FFF 84 85 /* Mappings for internal memory configuration */ 86 #define BGE_STD_RX_RINGS 0x00006000 87 #define BGE_STD_RX_RINGS_END 0x00006FFF 88 #define BGE_JUMBO_RX_RINGS 0x00007000 89 #define BGE_JUMBO_RX_RINGS_END 0x00007FFF 90 #define BGE_BUFFPOOL_1 0x00008000 91 #define BGE_BUFFPOOL_1_END 0x0000FFFF 92 #define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 93 #define BGE_BUFFPOOL_2_END 0x00017FFF 94 #define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 95 #define BGE_BUFFPOOL_3_END 0x0001FFFF 96 97 /* Mappings for external SSRAM configurations */ 98 #define BGE_SEND_RING_5_TO_6 0x00006000 99 #define BGE_SEND_RING_5_TO_6_END 0x00006FFF 100 #define BGE_SEND_RING_7_TO_8 0x00007000 101 #define BGE_SEND_RING_7_TO_8_END 0x00007FFF 102 #define BGE_SEND_RING_9_TO_16 0x00008000 103 #define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 104 #define BGE_EXT_STD_RX_RINGS 0x0000C000 105 #define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 106 #define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 107 #define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 108 #define BGE_MINI_RX_RINGS 0x0000E000 109 #define BGE_MINI_RX_RINGS_END 0x0000FFFF 110 #define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 111 #define BGE_AVAIL_REGION1_END 0x00017FFF 112 #define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 113 #define BGE_AVAIL_REGION2_END 0x0001FFFF 114 #define BGE_EXT_SSRAM 0x00020000 115 #define BGE_EXT_SSRAM_END 0x000FFFFF 116 117 118 /* 119 * BCM570x register offsets. These are memory mapped registers 120 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 121 * Each register must be accessed using 32 bit operations. 122 * 123 * All registers are accessed through a 32K shared memory block. 124 * The first group of registers are actually copies of the PCI 125 * configuration space registers. 126 */ 127 128 /* 129 * PCI registers defined in the PCI 2.2 spec. 130 */ 131 #define BGE_PCI_VID 0x00 132 #define BGE_PCI_DID 0x02 133 #define BGE_PCI_CMD 0x04 134 #define BGE_PCI_STS 0x06 135 #define BGE_PCI_REV 0x08 136 #define BGE_PCI_CLASS 0x09 137 #define BGE_PCI_CACHESZ 0x0C 138 #define BGE_PCI_LATTIMER 0x0D 139 #define BGE_PCI_HDRTYPE 0x0E 140 #define BGE_PCI_BIST 0x0F 141 #define BGE_PCI_BAR0 0x10 142 #define BGE_PCI_BAR1 0x14 143 #define BGE_PCI_SUBSYS 0x2C 144 #define BGE_PCI_SUBVID 0x2E 145 #define BGE_PCI_ROMBASE 0x30 146 #define BGE_PCI_CAPPTR 0x34 147 #define BGE_PCI_INTLINE 0x3C 148 #define BGE_PCI_INTPIN 0x3D 149 #define BGE_PCI_MINGNT 0x3E 150 #define BGE_PCI_MAXLAT 0x3F 151 #define BGE_PCI_PCIXCAP 0x40 152 #define BGE_PCI_NEXTPTR_PM 0x41 153 #define BGE_PCI_PCIX_CMD 0x42 154 #define BGE_PCI_PCIX_STS 0x44 155 #define BGE_PCI_PWRMGMT_CAPID 0x48 156 #define BGE_PCI_NEXTPTR_VPD 0x49 157 #define BGE_PCI_PWRMGMT_CAPS 0x4A 158 #define BGE_PCI_PWRMGMT_CMD 0x4C 159 #define BGE_PCI_PWRMGMT_STS 0x4D 160 #define BGE_PCI_PWRMGMT_DATA 0x4F 161 #define BGE_PCI_VPD_CAPID 0x50 162 #define BGE_PCI_NEXTPTR_MSI 0x51 163 #define BGE_PCI_VPD_ADDR 0x52 164 #define BGE_PCI_VPD_DATA 0x54 165 #define BGE_PCI_MSI_CAPID 0x58 166 #define BGE_PCI_NEXTPTR_NONE 0x59 167 #define BGE_PCI_MSI_CTL 0x5A 168 #define BGE_PCI_MSI_ADDR_HI 0x5C 169 #define BGE_PCI_MSI_ADDR_LO 0x60 170 #define BGE_PCI_MSI_DATA 0x64 171 172 /* PCI MSI. ??? */ 173 #define BGE_PCIE_CAPID_REG 0xD0 174 #define BGE_PCIE_CAPID 0x10 175 176 /* 177 * PCI registers specific to the BCM570x family. 178 */ 179 #define BGE_PCI_MISC_CTL 0x68 180 #define BGE_PCI_DMA_RW_CTL 0x6C 181 #define BGE_PCI_PCISTATE 0x70 182 #define BGE_PCI_CLKCTL 0x74 183 #define BGE_PCI_REG_BASEADDR 0x78 184 #define BGE_PCI_MEMWIN_BASEADDR 0x7C 185 #define BGE_PCI_REG_DATA 0x80 186 #define BGE_PCI_MEMWIN_DATA 0x84 187 #define BGE_PCI_MODECTL 0x88 188 #define BGE_PCI_MISC_CFG 0x8C 189 #define BGE_PCI_MISC_LOCALCTL 0x90 190 #define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 191 #define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 192 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 193 #define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 194 #define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 195 #define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 196 #define BGE_PCI_ISR_MBX_HI 0xB0 197 #define BGE_PCI_ISR_MBX_LO 0xB4 198 199 /* PCI Misc. Host control register */ 200 #define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 201 #define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 202 #define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 203 #define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 204 #define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 205 #define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 206 #define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 207 #define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 208 #define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 209 210 #define BGE_BIGENDIAN_INIT \ 211 (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 212 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 213 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 214 215 #define BGE_LITTLEENDIAN_INIT \ 216 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 217 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 218 219 #define BGE_CHIPID_TIGON_I 0x40000000 220 #define BGE_CHIPID_TIGON_II 0x60000000 221 #define BGE_CHIPID_BCM5700_B0 0x71000000 222 #define BGE_CHIPID_BCM5700_B1 0x71020000 223 #define BGE_CHIPID_BCM5700_B2 0x71030000 224 #define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 225 #define BGE_CHIPID_BCM5700_C0 0x72000000 226 #define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr */ 227 #define BGE_CHIPID_BCM5701_B0 0x01000000 228 #define BGE_CHIPID_BCM5701_B2 0x01020000 229 #define BGE_CHIPID_BCM5701_B5 0x01050000 230 #define BGE_CHIPID_BCM5703_A0 0x10000000 231 #define BGE_CHIPID_BCM5703_A1 0x10010000 232 #define BGE_CHIPID_BCM5703_A2 0x10020000 233 #define BGE_CHIPID_BCM5704_A0 0x20000000 234 #define BGE_CHIPID_BCM5704_A1 0x20010000 235 #define BGE_CHIPID_BCM5704_A2 0x20020000 236 #define BGE_CHIPID_BCM5705_A0 0x30000000 237 #define BGE_CHIPID_BCM5705_A1 0x30010000 238 #define BGE_CHIPID_BCM5705_A2 0x30020000 239 #define BGE_CHIPID_BCM5705_A3 0x30030000 240 #define BGE_CHIPID_BCM5750_A0 0x40000000 241 #define BGE_CHIPID_BCM5750_A1 0x40010000 242 #define BGE_CHIPID_BCM5714_A0 0x50000000 243 244 /* shorthand one */ 245 #define BGE_ASICREV(x) ((x) >> 28) 246 #define BGE_ASICREV_BCM5700 0x07 247 #define BGE_ASICREV_BCM5701 0x00 248 #define BGE_ASICREV_BCM5703 0x01 249 #define BGE_ASICREV_BCM5704 0x02 250 #define BGE_ASICREV_BCM5705 0x03 251 #define BGE_ASICREV_BCM5750 0x04 252 #define BGE_ASICREV_BCM5714 0x05 253 #define BGE_ASICREV_BCM5752 0x06 254 255 /* chip revisions */ 256 #define BGE_CHIPREV(x) ((x) >> 24) 257 #define BGE_CHIPREV_5700_AX 0x70 258 #define BGE_CHIPREV_5700_BX 0x71 259 #define BGE_CHIPREV_5700_CX 0x72 260 #define BGE_CHIPREV_5701_AX 0x00 261 262 /* PCI DMA Read/Write Control register */ 263 #define BGE_PCIDMARWCTL_MINDMA 0x000000FF 264 #define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 265 #define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 266 #define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 267 #define BGE_PCIDMARWCTL_RD_WAT 0x00070000 268 # define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 269 #define BGE_PCIDMARWCTL_WR_WAT 0x00380000 270 # define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 271 #define BGE_PCIDMARWCTL_USE_MRM 0x00400000 272 #define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 273 #define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 274 # define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 275 #define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 276 # define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 277 278 #define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 279 #define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 280 #define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 281 #define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 282 #define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 283 #define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 284 #define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 285 #define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 286 287 #define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 288 #define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 289 #define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 290 #define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 291 #define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 292 #define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 293 #define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 294 #define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 295 296 /* 297 * PCI state register -- note, this register is read only 298 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 299 * register is set. 300 */ 301 #define BGE_PCISTATE_FORCE_RESET 0x00000001 302 #define BGE_PCISTATE_INTR_STATE 0x00000002 303 #define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 304 #define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 305 #define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 306 #define BGE_PCISTATE_WANT_EXPROM 0x00000020 307 #define BGE_PCISTATE_EXPROM_RETRY 0x00000040 308 #define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 309 #define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 310 311 /* 312 * PCI Clock Control register -- note, this register is read only 313 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 314 * register is set. 315 */ 316 #define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 317 #define BGE_PCICLOCKCTL_M66EN 0x00000080 318 #define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 319 #define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 320 #define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 321 #define BGE_PCICLOCKCTL_ALTCLK 0x00001000 322 #define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 323 #define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 324 #define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 325 #define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 326 327 328 #ifndef PCIM_CMD_MWIEN 329 #define PCIM_CMD_MWIEN 0x0010 330 #endif 331 332 /* 333 * High priority mailbox registers 334 * Each mailbox is 64-bits wide, though we only use the 335 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 336 * first. The NIC will load the mailbox after the lower 32 bit word 337 * has been updated. 338 */ 339 #define BGE_MBX_IRQ0_HI 0x0200 340 #define BGE_MBX_IRQ0_LO 0x0204 341 #define BGE_MBX_IRQ1_HI 0x0208 342 #define BGE_MBX_IRQ1_LO 0x020C 343 #define BGE_MBX_IRQ2_HI 0x0210 344 #define BGE_MBX_IRQ2_LO 0x0214 345 #define BGE_MBX_IRQ3_HI 0x0218 346 #define BGE_MBX_IRQ3_LO 0x021C 347 #define BGE_MBX_GEN0_HI 0x0220 348 #define BGE_MBX_GEN0_LO 0x0224 349 #define BGE_MBX_GEN1_HI 0x0228 350 #define BGE_MBX_GEN1_LO 0x022C 351 #define BGE_MBX_GEN2_HI 0x0230 352 #define BGE_MBX_GEN2_LO 0x0234 353 #define BGE_MBX_GEN3_HI 0x0228 354 #define BGE_MBX_GEN3_LO 0x022C 355 #define BGE_MBX_GEN4_HI 0x0240 356 #define BGE_MBX_GEN4_LO 0x0244 357 #define BGE_MBX_GEN5_HI 0x0248 358 #define BGE_MBX_GEN5_LO 0x024C 359 #define BGE_MBX_GEN6_HI 0x0250 360 #define BGE_MBX_GEN6_LO 0x0254 361 #define BGE_MBX_GEN7_HI 0x0258 362 #define BGE_MBX_GEN7_LO 0x025C 363 #define BGE_MBX_RELOAD_STATS_HI 0x0260 364 #define BGE_MBX_RELOAD_STATS_LO 0x0264 365 #define BGE_MBX_RX_STD_PROD_HI 0x0268 366 #define BGE_MBX_RX_STD_PROD_LO 0x026C 367 #define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 368 #define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 369 #define BGE_MBX_RX_MINI_PROD_HI 0x0278 370 #define BGE_MBX_RX_MINI_PROD_LO 0x027C 371 #define BGE_MBX_RX_CONS0_HI 0x0280 372 #define BGE_MBX_RX_CONS0_LO 0x0284 373 #define BGE_MBX_RX_CONS1_HI 0x0288 374 #define BGE_MBX_RX_CONS1_LO 0x028C 375 #define BGE_MBX_RX_CONS2_HI 0x0290 376 #define BGE_MBX_RX_CONS2_LO 0x0294 377 #define BGE_MBX_RX_CONS3_HI 0x0298 378 #define BGE_MBX_RX_CONS3_LO 0x029C 379 #define BGE_MBX_RX_CONS4_HI 0x02A0 380 #define BGE_MBX_RX_CONS4_LO 0x02A4 381 #define BGE_MBX_RX_CONS5_HI 0x02A8 382 #define BGE_MBX_RX_CONS5_LO 0x02AC 383 #define BGE_MBX_RX_CONS6_HI 0x02B0 384 #define BGE_MBX_RX_CONS6_LO 0x02B4 385 #define BGE_MBX_RX_CONS7_HI 0x02B8 386 #define BGE_MBX_RX_CONS7_LO 0x02BC 387 #define BGE_MBX_RX_CONS8_HI 0x02C0 388 #define BGE_MBX_RX_CONS8_LO 0x02C4 389 #define BGE_MBX_RX_CONS9_HI 0x02C8 390 #define BGE_MBX_RX_CONS9_LO 0x02CC 391 #define BGE_MBX_RX_CONS10_HI 0x02D0 392 #define BGE_MBX_RX_CONS10_LO 0x02D4 393 #define BGE_MBX_RX_CONS11_HI 0x02D8 394 #define BGE_MBX_RX_CONS11_LO 0x02DC 395 #define BGE_MBX_RX_CONS12_HI 0x02E0 396 #define BGE_MBX_RX_CONS12_LO 0x02E4 397 #define BGE_MBX_RX_CONS13_HI 0x02E8 398 #define BGE_MBX_RX_CONS13_LO 0x02EC 399 #define BGE_MBX_RX_CONS14_HI 0x02F0 400 #define BGE_MBX_RX_CONS14_LO 0x02F4 401 #define BGE_MBX_RX_CONS15_HI 0x02F8 402 #define BGE_MBX_RX_CONS15_LO 0x02FC 403 #define BGE_MBX_TX_HOST_PROD0_HI 0x0300 404 #define BGE_MBX_TX_HOST_PROD0_LO 0x0304 405 #define BGE_MBX_TX_HOST_PROD1_HI 0x0308 406 #define BGE_MBX_TX_HOST_PROD1_LO 0x030C 407 #define BGE_MBX_TX_HOST_PROD2_HI 0x0310 408 #define BGE_MBX_TX_HOST_PROD2_LO 0x0314 409 #define BGE_MBX_TX_HOST_PROD3_HI 0x0318 410 #define BGE_MBX_TX_HOST_PROD3_LO 0x031C 411 #define BGE_MBX_TX_HOST_PROD4_HI 0x0320 412 #define BGE_MBX_TX_HOST_PROD4_LO 0x0324 413 #define BGE_MBX_TX_HOST_PROD5_HI 0x0328 414 #define BGE_MBX_TX_HOST_PROD5_LO 0x032C 415 #define BGE_MBX_TX_HOST_PROD6_HI 0x0330 416 #define BGE_MBX_TX_HOST_PROD6_LO 0x0334 417 #define BGE_MBX_TX_HOST_PROD7_HI 0x0338 418 #define BGE_MBX_TX_HOST_PROD7_LO 0x033C 419 #define BGE_MBX_TX_HOST_PROD8_HI 0x0340 420 #define BGE_MBX_TX_HOST_PROD8_LO 0x0344 421 #define BGE_MBX_TX_HOST_PROD9_HI 0x0348 422 #define BGE_MBX_TX_HOST_PROD9_LO 0x034C 423 #define BGE_MBX_TX_HOST_PROD10_HI 0x0350 424 #define BGE_MBX_TX_HOST_PROD10_LO 0x0354 425 #define BGE_MBX_TX_HOST_PROD11_HI 0x0358 426 #define BGE_MBX_TX_HOST_PROD11_LO 0x035C 427 #define BGE_MBX_TX_HOST_PROD12_HI 0x0360 428 #define BGE_MBX_TX_HOST_PROD12_LO 0x0364 429 #define BGE_MBX_TX_HOST_PROD13_HI 0x0368 430 #define BGE_MBX_TX_HOST_PROD13_LO 0x036C 431 #define BGE_MBX_TX_HOST_PROD14_HI 0x0370 432 #define BGE_MBX_TX_HOST_PROD14_LO 0x0374 433 #define BGE_MBX_TX_HOST_PROD15_HI 0x0378 434 #define BGE_MBX_TX_HOST_PROD15_LO 0x037C 435 #define BGE_MBX_TX_NIC_PROD0_HI 0x0380 436 #define BGE_MBX_TX_NIC_PROD0_LO 0x0384 437 #define BGE_MBX_TX_NIC_PROD1_HI 0x0388 438 #define BGE_MBX_TX_NIC_PROD1_LO 0x038C 439 #define BGE_MBX_TX_NIC_PROD2_HI 0x0390 440 #define BGE_MBX_TX_NIC_PROD2_LO 0x0394 441 #define BGE_MBX_TX_NIC_PROD3_HI 0x0398 442 #define BGE_MBX_TX_NIC_PROD3_LO 0x039C 443 #define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 444 #define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 445 #define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 446 #define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 447 #define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 448 #define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 449 #define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 450 #define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 451 #define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 452 #define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 453 #define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 454 #define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 455 #define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 456 #define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 457 #define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 458 #define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 459 #define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 460 #define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 461 #define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 462 #define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 463 #define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 464 #define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 465 #define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 466 #define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 467 468 #define BGE_TX_RINGS_MAX 4 469 #define BGE_TX_RINGS_EXTSSRAM_MAX 16 470 #define BGE_RX_RINGS_MAX 16 471 472 /* Ethernet MAC control registers */ 473 #define BGE_MAC_MODE 0x0400 474 #define BGE_MAC_STS 0x0404 475 #define BGE_MAC_EVT_ENB 0x0408 476 #define BGE_MAC_LED_CTL 0x040C 477 #define BGE_MAC_ADDR1_LO 0x0410 478 #define BGE_MAC_ADDR1_HI 0x0414 479 #define BGE_MAC_ADDR2_LO 0x0418 480 #define BGE_MAC_ADDR2_HI 0x041C 481 #define BGE_MAC_ADDR3_LO 0x0420 482 #define BGE_MAC_ADDR3_HI 0x0424 483 #define BGE_MAC_ADDR4_LO 0x0428 484 #define BGE_MAC_ADDR4_HI 0x042C 485 #define BGE_WOL_PATPTR 0x0430 486 #define BGE_WOL_PATCFG 0x0434 487 #define BGE_TX_RANDOM_BACKOFF 0x0438 488 #define BGE_RX_MTU 0x043C 489 #define BGE_GBIT_PCS_TEST 0x0440 490 #define BGE_TX_TBI_AUTONEG 0x0444 491 #define BGE_RX_TBI_AUTONEG 0x0448 492 #define BGE_MI_COMM 0x044C 493 #define BGE_MI_STS 0x0450 494 #define BGE_MI_MODE 0x0454 495 #define BGE_AUTOPOLL_STS 0x0458 496 #define BGE_TX_MODE 0x045C 497 #define BGE_TX_STS 0x0460 498 #define BGE_TX_LENGTHS 0x0464 499 #define BGE_RX_MODE 0x0468 500 #define BGE_RX_STS 0x046C 501 #define BGE_MAR0 0x0470 502 #define BGE_MAR1 0x0474 503 #define BGE_MAR2 0x0478 504 #define BGE_MAR3 0x047C 505 #define BGE_RX_BD_RULES_CTL0 0x0480 506 #define BGE_RX_BD_RULES_MASKVAL0 0x0484 507 #define BGE_RX_BD_RULES_CTL1 0x0488 508 #define BGE_RX_BD_RULES_MASKVAL1 0x048C 509 #define BGE_RX_BD_RULES_CTL2 0x0490 510 #define BGE_RX_BD_RULES_MASKVAL2 0x0494 511 #define BGE_RX_BD_RULES_CTL3 0x0498 512 #define BGE_RX_BD_RULES_MASKVAL3 0x049C 513 #define BGE_RX_BD_RULES_CTL4 0x04A0 514 #define BGE_RX_BD_RULES_MASKVAL4 0x04A4 515 #define BGE_RX_BD_RULES_CTL5 0x04A8 516 #define BGE_RX_BD_RULES_MASKVAL5 0x04AC 517 #define BGE_RX_BD_RULES_CTL6 0x04B0 518 #define BGE_RX_BD_RULES_MASKVAL6 0x04B4 519 #define BGE_RX_BD_RULES_CTL7 0x04B8 520 #define BGE_RX_BD_RULES_MASKVAL7 0x04BC 521 #define BGE_RX_BD_RULES_CTL8 0x04C0 522 #define BGE_RX_BD_RULES_MASKVAL8 0x04C4 523 #define BGE_RX_BD_RULES_CTL9 0x04C8 524 #define BGE_RX_BD_RULES_MASKVAL9 0x04CC 525 #define BGE_RX_BD_RULES_CTL10 0x04D0 526 #define BGE_RX_BD_RULES_MASKVAL10 0x04D4 527 #define BGE_RX_BD_RULES_CTL11 0x04D8 528 #define BGE_RX_BD_RULES_MASKVAL11 0x04DC 529 #define BGE_RX_BD_RULES_CTL12 0x04E0 530 #define BGE_RX_BD_RULES_MASKVAL12 0x04E4 531 #define BGE_RX_BD_RULES_CTL13 0x04E8 532 #define BGE_RX_BD_RULES_MASKVAL13 0x04EC 533 #define BGE_RX_BD_RULES_CTL14 0x04F0 534 #define BGE_RX_BD_RULES_MASKVAL14 0x04F4 535 #define BGE_RX_BD_RULES_CTL15 0x04F8 536 #define BGE_RX_BD_RULES_MASKVAL15 0x04FC 537 #define BGE_RX_RULES_CFG 0x0500 538 #define BGE_SERDES_CFG 0x0590 539 #define BGE_SERDES_STS 0x0594 540 #define BGE_SGDIG_CFG 0x05B0 541 #define BGE_SGDIG_STS 0x05B4 542 #define BGE_RX_STATS 0x0800 543 #define BGE_TX_STATS 0x0880 544 545 /* Ethernet MAC Mode register */ 546 #define BGE_MACMODE_RESET 0x00000001 547 #define BGE_MACMODE_HALF_DUPLEX 0x00000002 548 #define BGE_MACMODE_PORTMODE 0x0000000C 549 #define BGE_MACMODE_LOOPBACK 0x00000010 550 #define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 551 #define BGE_MACMODE_TX_BURST_ENB 0x00000100 552 #define BGE_MACMODE_MAX_DEFER 0x00000200 553 #define BGE_MACMODE_LINK_POLARITY 0x00000400 554 #define BGE_MACMODE_RX_STATS_ENB 0x00000800 555 #define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 556 #define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 557 #define BGE_MACMODE_TX_STATS_ENB 0x00004000 558 #define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 559 #define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 560 #define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 561 #define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 562 #define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 563 #define BGE_MACMODE_MIP_ENB 0x00100000 564 #define BGE_MACMODE_TXDMA_ENB 0x00200000 565 #define BGE_MACMODE_RXDMA_ENB 0x00400000 566 #define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 567 568 #define BGE_PORTMODE_NONE 0x00000000 569 #define BGE_PORTMODE_MII 0x00000004 570 #define BGE_PORTMODE_GMII 0x00000008 571 #define BGE_PORTMODE_TBI 0x0000000C 572 573 /* MAC Status register */ 574 #define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 575 #define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 576 #define BGE_MACSTAT_RX_CFG 0x00000004 577 #define BGE_MACSTAT_CFG_CHANGED 0x00000008 578 #define BGE_MACSTAT_SYNC_CHANGED 0x00000010 579 #define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 580 #define BGE_MACSTAT_LINK_CHANGED 0x00001000 581 #define BGE_MACSTAT_MI_COMPLETE 0x00400000 582 #define BGE_MACSTAT_MI_INTERRUPT 0x00800000 583 #define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 584 #define BGE_MACSTAT_ODI_ERROR 0x02000000 585 #define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 586 #define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 587 588 /* MAC Event Enable Register */ 589 #define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 590 #define BGE_EVTENB_LINK_CHANGED 0x00001000 591 #define BGE_EVTENB_MI_COMPLETE 0x00400000 592 #define BGE_EVTENB_MI_INTERRUPT 0x00800000 593 #define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 594 #define BGE_EVTENB_ODI_ERROR 0x02000000 595 #define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 596 #define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 597 598 /* LED Control Register */ 599 #define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 600 #define BGE_LEDCTL_1000MBPS_LED 0x00000002 601 #define BGE_LEDCTL_100MBPS_LED 0x00000004 602 #define BGE_LEDCTL_10MBPS_LED 0x00000008 603 #define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 604 #define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 605 #define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 606 #define BGE_LEDCTL_1000MBPS_STS 0x00000080 607 #define BGE_LEDCTL_100MBPS_STS 0x00000100 608 #define BGE_LEDCTL_10MBPS_STS 0x00000200 609 #define BGE_LEDCTL_TRADLED_STS 0x00000400 610 #define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 611 #define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 612 613 /* TX backoff seed register */ 614 #define BGE_TX_BACKOFF_SEED_MASK 0x3F 615 616 /* Autopoll status register */ 617 #define BGE_AUTOPOLLSTS_ERROR 0x00000001 618 619 /* Transmit MAC mode register */ 620 #define BGE_TXMODE_RESET 0x00000001 621 #define BGE_TXMODE_ENABLE 0x00000002 622 #define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 623 #define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 624 #define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 625 626 /* Transmit MAC status register */ 627 #define BGE_TXSTAT_RX_XOFFED 0x00000001 628 #define BGE_TXSTAT_SENT_XOFF 0x00000002 629 #define BGE_TXSTAT_SENT_XON 0x00000004 630 #define BGE_TXSTAT_LINK_UP 0x00000008 631 #define BGE_TXSTAT_ODI_UFLOW 0x00000010 632 #define BGE_TXSTAT_ODI_OFLOW 0x00000020 633 634 /* Transmit MAC lengths register */ 635 #define BGE_TXLEN_SLOTTIME 0x000000FF 636 #define BGE_TXLEN_IPG 0x00000F00 637 #define BGE_TXLEN_CRS 0x00003000 638 639 /* Receive MAC mode register */ 640 #define BGE_RXMODE_RESET 0x00000001 641 #define BGE_RXMODE_ENABLE 0x00000002 642 #define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 643 #define BGE_RXMODE_RX_GIANTS 0x00000020 644 #define BGE_RXMODE_RX_RUNTS 0x00000040 645 #define BGE_RXMODE_8022_LENCHECK 0x00000080 646 #define BGE_RXMODE_RX_PROMISC 0x00000100 647 #define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 648 #define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 649 650 /* Receive MAC status register */ 651 #define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 652 #define BGE_RXSTAT_RCVD_XOFF 0x00000002 653 #define BGE_RXSTAT_RCVD_XON 0x00000004 654 655 /* Receive Rules Control register */ 656 #define BGE_RXRULECTL_OFFSET 0x000000FF 657 #define BGE_RXRULECTL_CLASS 0x00001F00 658 #define BGE_RXRULECTL_HDRTYPE 0x0000E000 659 #define BGE_RXRULECTL_COMPARE_OP 0x00030000 660 #define BGE_RXRULECTL_MAP 0x01000000 661 #define BGE_RXRULECTL_DISCARD 0x02000000 662 #define BGE_RXRULECTL_MASK 0x04000000 663 #define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 664 #define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 665 #define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 666 #define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 667 668 /* Receive Rules Mask register */ 669 #define BGE_RXRULEMASK_VALUE 0x0000FFFF 670 #define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 671 672 /* SERDES configuration register */ 673 #define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */ 674 #define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */ 675 #define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */ 676 #define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */ 677 #define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */ 678 #define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */ 679 #define BGE_SERDESCFG_TXMODE 0x00001000 680 #define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */ 681 #define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */ 682 #define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */ 683 #define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */ 684 #define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */ 685 #define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */ 686 #define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */ 687 #define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */ 688 #define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */ 689 690 /* SERDES status register */ 691 #define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */ 692 #define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */ 693 694 /* SGDIG config (not documented) */ 695 #define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 696 #define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 697 #define BGE_SGDIGCFG_SEND 0x40000000 698 #define BGE_SGDIGCFG_AUTO 0x80000000 699 700 /* SGDIG status (not documented) */ 701 #define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 702 #define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 703 #define BGE_SGDIGSTS_DONE 0x00000002 704 705 706 /* MI communication register */ 707 #define BGE_MICOMM_DATA 0x0000FFFF 708 #define BGE_MICOMM_REG 0x001F0000 709 #define BGE_MICOMM_PHY 0x03E00000 710 #define BGE_MICOMM_CMD 0x0C000000 711 #define BGE_MICOMM_READFAIL 0x10000000 712 #define BGE_MICOMM_BUSY 0x20000000 713 714 #define BGE_MIREG(x) ((x & 0x1F) << 16) 715 #define BGE_MIPHY(x) ((x & 0x1F) << 21) 716 #define BGE_MICMD_WRITE 0x04000000 717 #define BGE_MICMD_READ 0x08000000 718 719 /* MI status register */ 720 #define BGE_MISTS_LINK 0x00000001 721 #define BGE_MISTS_10MBPS 0x00000002 722 723 #define BGE_MIMODE_SHORTPREAMBLE 0x00000002 724 #define BGE_MIMODE_AUTOPOLL 0x00000010 725 #define BGE_MIMODE_CLKCNT 0x001F0000 726 727 728 /* 729 * Send data initiator control registers. 730 */ 731 #define BGE_SDI_MODE 0x0C00 732 #define BGE_SDI_STATUS 0x0C04 733 #define BGE_SDI_STATS_CTL 0x0C08 734 #define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 735 #define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 736 #define BGE_LOCSTATS_COS0 0x0C80 737 #define BGE_LOCSTATS_COS1 0x0C84 738 #define BGE_LOCSTATS_COS2 0x0C88 739 #define BGE_LOCSTATS_COS3 0x0C8C 740 #define BGE_LOCSTATS_COS4 0x0C90 741 #define BGE_LOCSTATS_COS5 0x0C84 742 #define BGE_LOCSTATS_COS6 0x0C98 743 #define BGE_LOCSTATS_COS7 0x0C9C 744 #define BGE_LOCSTATS_COS8 0x0CA0 745 #define BGE_LOCSTATS_COS9 0x0CA4 746 #define BGE_LOCSTATS_COS10 0x0CA8 747 #define BGE_LOCSTATS_COS11 0x0CAC 748 #define BGE_LOCSTATS_COS12 0x0CB0 749 #define BGE_LOCSTATS_COS13 0x0CB4 750 #define BGE_LOCSTATS_COS14 0x0CB8 751 #define BGE_LOCSTATS_COS15 0x0CBC 752 #define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 753 #define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 754 #define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 755 #define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 756 #define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 757 #define BGE_LOCSTATS_IRQS 0x0CD4 758 #define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 759 #define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 760 761 /* Send Data Initiator mode register */ 762 #define BGE_SDIMODE_RESET 0x00000001 763 #define BGE_SDIMODE_ENABLE 0x00000002 764 #define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 765 766 /* Send Data Initiator stats register */ 767 #define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 768 769 /* Send Data Initiator stats control register */ 770 #define BGE_SDISTATSCTL_ENABLE 0x00000001 771 #define BGE_SDISTATSCTL_FASTER 0x00000002 772 #define BGE_SDISTATSCTL_CLEAR 0x00000004 773 #define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 774 #define BGE_SDISTATSCTL_FORCEZERO 0x00000010 775 776 /* 777 * Send Data Completion Control registers 778 */ 779 #define BGE_SDC_MODE 0x1000 780 #define BGE_SDC_STATUS 0x1004 781 782 /* Send Data completion mode register */ 783 #define BGE_SDCMODE_RESET 0x00000001 784 #define BGE_SDCMODE_ENABLE 0x00000002 785 #define BGE_SDCMODE_ATTN 0x00000004 786 787 /* Send Data completion status register */ 788 #define BGE_SDCSTAT_ATTN 0x00000004 789 790 /* 791 * Send BD Ring Selector Control registers 792 */ 793 #define BGE_SRS_MODE 0x1400 794 #define BGE_SRS_STATUS 0x1404 795 #define BGE_SRS_HWDIAG 0x1408 796 #define BGE_SRS_LOC_NIC_CONS0 0x1440 797 #define BGE_SRS_LOC_NIC_CONS1 0x1444 798 #define BGE_SRS_LOC_NIC_CONS2 0x1448 799 #define BGE_SRS_LOC_NIC_CONS3 0x144C 800 #define BGE_SRS_LOC_NIC_CONS4 0x1450 801 #define BGE_SRS_LOC_NIC_CONS5 0x1454 802 #define BGE_SRS_LOC_NIC_CONS6 0x1458 803 #define BGE_SRS_LOC_NIC_CONS7 0x145C 804 #define BGE_SRS_LOC_NIC_CONS8 0x1460 805 #define BGE_SRS_LOC_NIC_CONS9 0x1464 806 #define BGE_SRS_LOC_NIC_CONS10 0x1468 807 #define BGE_SRS_LOC_NIC_CONS11 0x146C 808 #define BGE_SRS_LOC_NIC_CONS12 0x1470 809 #define BGE_SRS_LOC_NIC_CONS13 0x1474 810 #define BGE_SRS_LOC_NIC_CONS14 0x1478 811 #define BGE_SRS_LOC_NIC_CONS15 0x147C 812 813 /* Send BD Ring Selector Mode register */ 814 #define BGE_SRSMODE_RESET 0x00000001 815 #define BGE_SRSMODE_ENABLE 0x00000002 816 #define BGE_SRSMODE_ATTN 0x00000004 817 818 /* Send BD Ring Selector Status register */ 819 #define BGE_SRSSTAT_ERROR 0x00000004 820 821 /* Send BD Ring Selector HW Diagnostics register */ 822 #define BGE_SRSHWDIAG_STATE 0x0000000F 823 #define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 824 #define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 825 #define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 826 827 /* 828 * Send BD Initiator Selector Control registers 829 */ 830 #define BGE_SBDI_MODE 0x1800 831 #define BGE_SBDI_STATUS 0x1804 832 #define BGE_SBDI_LOC_NIC_PROD0 0x1808 833 #define BGE_SBDI_LOC_NIC_PROD1 0x180C 834 #define BGE_SBDI_LOC_NIC_PROD2 0x1810 835 #define BGE_SBDI_LOC_NIC_PROD3 0x1814 836 #define BGE_SBDI_LOC_NIC_PROD4 0x1818 837 #define BGE_SBDI_LOC_NIC_PROD5 0x181C 838 #define BGE_SBDI_LOC_NIC_PROD6 0x1820 839 #define BGE_SBDI_LOC_NIC_PROD7 0x1824 840 #define BGE_SBDI_LOC_NIC_PROD8 0x1828 841 #define BGE_SBDI_LOC_NIC_PROD9 0x182C 842 #define BGE_SBDI_LOC_NIC_PROD10 0x1830 843 #define BGE_SBDI_LOC_NIC_PROD11 0x1834 844 #define BGE_SBDI_LOC_NIC_PROD12 0x1838 845 #define BGE_SBDI_LOC_NIC_PROD13 0x183C 846 #define BGE_SBDI_LOC_NIC_PROD14 0x1840 847 #define BGE_SBDI_LOC_NIC_PROD15 0x1844 848 849 /* Send BD Initiator Mode register */ 850 #define BGE_SBDIMODE_RESET 0x00000001 851 #define BGE_SBDIMODE_ENABLE 0x00000002 852 #define BGE_SBDIMODE_ATTN 0x00000004 853 854 /* Send BD Initiator Status register */ 855 #define BGE_SBDISTAT_ERROR 0x00000004 856 857 /* 858 * Send BD Completion Control registers 859 */ 860 #define BGE_SBDC_MODE 0x1C00 861 #define BGE_SBDC_STATUS 0x1C04 862 863 /* Send BD Completion Control Mode register */ 864 #define BGE_SBDCMODE_RESET 0x00000001 865 #define BGE_SBDCMODE_ENABLE 0x00000002 866 #define BGE_SBDCMODE_ATTN 0x00000004 867 868 /* Send BD Completion Control Status register */ 869 #define BGE_SBDCSTAT_ATTN 0x00000004 870 871 /* 872 * Receive List Placement Control registers 873 */ 874 #define BGE_RXLP_MODE 0x2000 875 #define BGE_RXLP_STATUS 0x2004 876 #define BGE_RXLP_SEL_LIST_LOCK 0x2008 877 #define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 878 #define BGE_RXLP_CFG 0x2010 879 #define BGE_RXLP_STATS_CTL 0x2014 880 #define BGE_RXLP_STATS_ENABLE_MASK 0x2018 881 #define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 882 #define BGE_RXLP_HEAD0 0x2100 883 #define BGE_RXLP_TAIL0 0x2104 884 #define BGE_RXLP_COUNT0 0x2108 885 #define BGE_RXLP_HEAD1 0x2110 886 #define BGE_RXLP_TAIL1 0x2114 887 #define BGE_RXLP_COUNT1 0x2118 888 #define BGE_RXLP_HEAD2 0x2120 889 #define BGE_RXLP_TAIL2 0x2124 890 #define BGE_RXLP_COUNT2 0x2128 891 #define BGE_RXLP_HEAD3 0x2130 892 #define BGE_RXLP_TAIL3 0x2134 893 #define BGE_RXLP_COUNT3 0x2138 894 #define BGE_RXLP_HEAD4 0x2140 895 #define BGE_RXLP_TAIL4 0x2144 896 #define BGE_RXLP_COUNT4 0x2148 897 #define BGE_RXLP_HEAD5 0x2150 898 #define BGE_RXLP_TAIL5 0x2154 899 #define BGE_RXLP_COUNT5 0x2158 900 #define BGE_RXLP_HEAD6 0x2160 901 #define BGE_RXLP_TAIL6 0x2164 902 #define BGE_RXLP_COUNT6 0x2168 903 #define BGE_RXLP_HEAD7 0x2170 904 #define BGE_RXLP_TAIL7 0x2174 905 #define BGE_RXLP_COUNT7 0x2178 906 #define BGE_RXLP_HEAD8 0x2180 907 #define BGE_RXLP_TAIL8 0x2184 908 #define BGE_RXLP_COUNT8 0x2188 909 #define BGE_RXLP_HEAD9 0x2190 910 #define BGE_RXLP_TAIL9 0x2194 911 #define BGE_RXLP_COUNT9 0x2198 912 #define BGE_RXLP_HEAD10 0x21A0 913 #define BGE_RXLP_TAIL10 0x21A4 914 #define BGE_RXLP_COUNT10 0x21A8 915 #define BGE_RXLP_HEAD11 0x21B0 916 #define BGE_RXLP_TAIL11 0x21B4 917 #define BGE_RXLP_COUNT11 0x21B8 918 #define BGE_RXLP_HEAD12 0x21C0 919 #define BGE_RXLP_TAIL12 0x21C4 920 #define BGE_RXLP_COUNT12 0x21C8 921 #define BGE_RXLP_HEAD13 0x21D0 922 #define BGE_RXLP_TAIL13 0x21D4 923 #define BGE_RXLP_COUNT13 0x21D8 924 #define BGE_RXLP_HEAD14 0x21E0 925 #define BGE_RXLP_TAIL14 0x21E4 926 #define BGE_RXLP_COUNT14 0x21E8 927 #define BGE_RXLP_HEAD15 0x21F0 928 #define BGE_RXLP_TAIL15 0x21F4 929 #define BGE_RXLP_COUNT15 0x21F8 930 #define BGE_RXLP_LOCSTAT_COS0 0x2200 931 #define BGE_RXLP_LOCSTAT_COS1 0x2204 932 #define BGE_RXLP_LOCSTAT_COS2 0x2208 933 #define BGE_RXLP_LOCSTAT_COS3 0x220C 934 #define BGE_RXLP_LOCSTAT_COS4 0x2210 935 #define BGE_RXLP_LOCSTAT_COS5 0x2214 936 #define BGE_RXLP_LOCSTAT_COS6 0x2218 937 #define BGE_RXLP_LOCSTAT_COS7 0x221C 938 #define BGE_RXLP_LOCSTAT_COS8 0x2220 939 #define BGE_RXLP_LOCSTAT_COS9 0x2224 940 #define BGE_RXLP_LOCSTAT_COS10 0x2228 941 #define BGE_RXLP_LOCSTAT_COS11 0x222C 942 #define BGE_RXLP_LOCSTAT_COS12 0x2230 943 #define BGE_RXLP_LOCSTAT_COS13 0x2234 944 #define BGE_RXLP_LOCSTAT_COS14 0x2238 945 #define BGE_RXLP_LOCSTAT_COS15 0x223C 946 #define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 947 #define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 948 #define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 949 #define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 950 #define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 951 #define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 952 #define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 953 954 955 /* Receive List Placement mode register */ 956 #define BGE_RXLPMODE_RESET 0x00000001 957 #define BGE_RXLPMODE_ENABLE 0x00000002 958 #define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 959 #define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 960 #define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 961 962 /* Receive List Placement Status register */ 963 #define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 964 #define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 965 #define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 966 967 /* 968 * Receive Data and Receive BD Initiator Control Registers 969 */ 970 #define BGE_RDBDI_MODE 0x2400 971 #define BGE_RDBDI_STATUS 0x2404 972 #define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 973 #define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 974 #define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 975 #define BGE_RX_JUMBO_RCB_NICADDR 0x244C 976 #define BGE_RX_STD_RCB_HADDR_HI 0x2450 977 #define BGE_RX_STD_RCB_HADDR_LO 0x2454 978 #define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 979 #define BGE_RX_STD_RCB_NICADDR 0x245C 980 #define BGE_RX_MINI_RCB_HADDR_HI 0x2460 981 #define BGE_RX_MINI_RCB_HADDR_LO 0x2464 982 #define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 983 #define BGE_RX_MINI_RCB_NICADDR 0x246C 984 #define BGE_RDBDI_JUMBO_RX_CONS 0x2470 985 #define BGE_RDBDI_STD_RX_CONS 0x2474 986 #define BGE_RDBDI_MINI_RX_CONS 0x2478 987 #define BGE_RDBDI_RETURN_PROD0 0x2480 988 #define BGE_RDBDI_RETURN_PROD1 0x2484 989 #define BGE_RDBDI_RETURN_PROD2 0x2488 990 #define BGE_RDBDI_RETURN_PROD3 0x248C 991 #define BGE_RDBDI_RETURN_PROD4 0x2490 992 #define BGE_RDBDI_RETURN_PROD5 0x2494 993 #define BGE_RDBDI_RETURN_PROD6 0x2498 994 #define BGE_RDBDI_RETURN_PROD7 0x249C 995 #define BGE_RDBDI_RETURN_PROD8 0x24A0 996 #define BGE_RDBDI_RETURN_PROD9 0x24A4 997 #define BGE_RDBDI_RETURN_PROD10 0x24A8 998 #define BGE_RDBDI_RETURN_PROD11 0x24AC 999 #define BGE_RDBDI_RETURN_PROD12 0x24B0 1000 #define BGE_RDBDI_RETURN_PROD13 0x24B4 1001 #define BGE_RDBDI_RETURN_PROD14 0x24B8 1002 #define BGE_RDBDI_RETURN_PROD15 0x24BC 1003 #define BGE_RDBDI_HWDIAG 0x24C0 1004 1005 1006 /* Receive Data and Receive BD Initiator Mode register */ 1007 #define BGE_RDBDIMODE_RESET 0x00000001 1008 #define BGE_RDBDIMODE_ENABLE 0x00000002 1009 #define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1010 #define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1011 #define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1012 1013 /* Receive Data and Receive BD Initiator Status register */ 1014 #define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1015 #define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1016 #define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1017 1018 1019 /* 1020 * Receive Data Completion Control registers 1021 */ 1022 #define BGE_RDC_MODE 0x2800 1023 1024 /* Receive Data Completion Mode register */ 1025 #define BGE_RDCMODE_RESET 0x00000001 1026 #define BGE_RDCMODE_ENABLE 0x00000002 1027 #define BGE_RDCMODE_ATTN 0x00000004 1028 1029 /* 1030 * Receive BD Initiator Control registers 1031 */ 1032 #define BGE_RBDI_MODE 0x2C00 1033 #define BGE_RBDI_STATUS 0x2C04 1034 #define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1035 #define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1036 #define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1037 #define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1038 #define BGE_RBDI_STD_REPL_THRESH 0x2C18 1039 #define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1040 1041 /* Receive BD Initiator Mode register */ 1042 #define BGE_RBDIMODE_RESET 0x00000001 1043 #define BGE_RBDIMODE_ENABLE 0x00000002 1044 #define BGE_RBDIMODE_ATTN 0x00000004 1045 1046 /* Receive BD Initiator Status register */ 1047 #define BGE_RBDISTAT_ATTN 0x00000004 1048 1049 /* 1050 * Receive BD Completion Control registers 1051 */ 1052 #define BGE_RBDC_MODE 0x3000 1053 #define BGE_RBDC_STATUS 0x3004 1054 #define BGE_RBDC_JUMBO_BD_PROD 0x3008 1055 #define BGE_RBDC_STD_BD_PROD 0x300C 1056 #define BGE_RBDC_MINI_BD_PROD 0x3010 1057 1058 /* Receive BD completion mode register */ 1059 #define BGE_RBDCMODE_RESET 0x00000001 1060 #define BGE_RBDCMODE_ENABLE 0x00000002 1061 #define BGE_RBDCMODE_ATTN 0x00000004 1062 1063 /* Receive BD completion status register */ 1064 #define BGE_RBDCSTAT_ERROR 0x00000004 1065 1066 /* 1067 * Receive List Selector Control registers 1068 */ 1069 #define BGE_RXLS_MODE 0x3400 1070 #define BGE_RXLS_STATUS 0x3404 1071 1072 /* Receive List Selector Mode register */ 1073 #define BGE_RXLSMODE_RESET 0x00000001 1074 #define BGE_RXLSMODE_ENABLE 0x00000002 1075 #define BGE_RXLSMODE_ATTN 0x00000004 1076 1077 /* Receive List Selector Status register */ 1078 #define BGE_RXLSSTAT_ERROR 0x00000004 1079 1080 /* 1081 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1082 */ 1083 #define BGE_MBCF_MODE 0x3800 1084 #define BGE_MBCF_STATUS 0x3804 1085 1086 /* Mbuf Cluster Free mode register */ 1087 #define BGE_MBCFMODE_RESET 0x00000001 1088 #define BGE_MBCFMODE_ENABLE 0x00000002 1089 #define BGE_MBCFMODE_ATTN 0x00000004 1090 1091 /* Mbuf Cluster Free status register */ 1092 #define BGE_MBCFSTAT_ERROR 0x00000004 1093 1094 /* 1095 * Host Coalescing Control registers 1096 */ 1097 #define BGE_HCC_MODE 0x3C00 1098 #define BGE_HCC_STATUS 0x3C04 1099 #define BGE_HCC_RX_COAL_TICKS 0x3C08 1100 #define BGE_HCC_TX_COAL_TICKS 0x3C0C 1101 #define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1102 #define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1103 #define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1104 #define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1105 #define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1106 #define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */ 1107 #define BGE_HCC_STATS_TICKS 0x3C28 1108 #define BGE_HCC_STATS_ADDR_HI 0x3C30 1109 #define BGE_HCC_STATS_ADDR_LO 0x3C34 1110 #define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1111 #define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1112 #define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1113 #define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1114 #define BGE_FLOW_ATTN 0x3C48 1115 #define BGE_HCC_JUMBO_BD_CONS 0x3C50 1116 #define BGE_HCC_STD_BD_CONS 0x3C54 1117 #define BGE_HCC_MINI_BD_CONS 0x3C58 1118 #define BGE_HCC_RX_RETURN_PROD0 0x3C80 1119 #define BGE_HCC_RX_RETURN_PROD1 0x3C84 1120 #define BGE_HCC_RX_RETURN_PROD2 0x3C88 1121 #define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1122 #define BGE_HCC_RX_RETURN_PROD4 0x3C90 1123 #define BGE_HCC_RX_RETURN_PROD5 0x3C94 1124 #define BGE_HCC_RX_RETURN_PROD6 0x3C98 1125 #define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1126 #define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1127 #define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1128 #define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1129 #define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1130 #define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1131 #define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1132 #define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1133 #define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1134 #define BGE_HCC_TX_BD_CONS0 0x3CC0 1135 #define BGE_HCC_TX_BD_CONS1 0x3CC4 1136 #define BGE_HCC_TX_BD_CONS2 0x3CC8 1137 #define BGE_HCC_TX_BD_CONS3 0x3CCC 1138 #define BGE_HCC_TX_BD_CONS4 0x3CD0 1139 #define BGE_HCC_TX_BD_CONS5 0x3CD4 1140 #define BGE_HCC_TX_BD_CONS6 0x3CD8 1141 #define BGE_HCC_TX_BD_CONS7 0x3CDC 1142 #define BGE_HCC_TX_BD_CONS8 0x3CE0 1143 #define BGE_HCC_TX_BD_CONS9 0x3CE4 1144 #define BGE_HCC_TX_BD_CONS10 0x3CE8 1145 #define BGE_HCC_TX_BD_CONS11 0x3CEC 1146 #define BGE_HCC_TX_BD_CONS12 0x3CF0 1147 #define BGE_HCC_TX_BD_CONS13 0x3CF4 1148 #define BGE_HCC_TX_BD_CONS14 0x3CF8 1149 #define BGE_HCC_TX_BD_CONS15 0x3CFC 1150 1151 1152 /* Host coalescing mode register */ 1153 #define BGE_HCCMODE_RESET 0x00000001 1154 #define BGE_HCCMODE_ENABLE 0x00000002 1155 #define BGE_HCCMODE_ATTN 0x00000004 1156 #define BGE_HCCMODE_COAL_NOW 0x00000008 1157 #define BGE_HCCMODE_MSI_BITS 0x0x000070 1158 #define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1159 1160 #define BGE_STATBLKSZ_FULL 0x00000000 1161 #define BGE_STATBLKSZ_64BYTE 0x00000080 1162 #define BGE_STATBLKSZ_32BYTE 0x00000100 1163 1164 /* Host coalescing status register */ 1165 #define BGE_HCCSTAT_ERROR 0x00000004 1166 1167 /* Flow attention register */ 1168 #define BGE_FLOWATTN_MB_LOWAT 0x00000040 1169 #define BGE_FLOWATTN_MEMARB 0x00000080 1170 #define BGE_FLOWATTN_HOSTCOAL 0x00008000 1171 #define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1172 #define BGE_FLOWATTN_RCB_INVAL 0x00020000 1173 #define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1174 #define BGE_FLOWATTN_RDBDI 0x00080000 1175 #define BGE_FLOWATTN_RXLS 0x00100000 1176 #define BGE_FLOWATTN_RXLP 0x00200000 1177 #define BGE_FLOWATTN_RBDC 0x00400000 1178 #define BGE_FLOWATTN_RBDI 0x00800000 1179 #define BGE_FLOWATTN_SDC 0x08000000 1180 #define BGE_FLOWATTN_SDI 0x10000000 1181 #define BGE_FLOWATTN_SRS 0x20000000 1182 #define BGE_FLOWATTN_SBDC 0x40000000 1183 #define BGE_FLOWATTN_SBDI 0x80000000 1184 1185 /* 1186 * Memory arbiter registers 1187 */ 1188 #define BGE_MARB_MODE 0x4000 1189 #define BGE_MARB_STATUS 0x4004 1190 #define BGE_MARB_TRAPADDR_HI 0x4008 1191 #define BGE_MARB_TRAPADDR_LO 0x400C 1192 1193 /* Memory arbiter mode register */ 1194 #define BGE_MARBMODE_RESET 0x00000001 1195 #define BGE_MARBMODE_ENABLE 0x00000002 1196 #define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1197 #define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1198 #define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1199 #define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1200 #define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1201 #define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1202 #define BGE_MARBMODE_PCI_TRAP 0x00000100 1203 #define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1204 #define BGE_MARBMODE_RXQ_TRAP 0x00000400 1205 #define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1206 #define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1207 #define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1208 #define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1209 #define BGE_MARBMODE_MBUF_TRAP 0x00008000 1210 #define BGE_MARBMODE_TXDI_TRAP 0x00010000 1211 #define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1212 #define BGE_MARBMODE_TXBD_TRAP 0x00040000 1213 #define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1214 #define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1215 #define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1216 #define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1217 #define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1218 #define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1219 #define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1220 1221 /* Memory arbiter status register */ 1222 #define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1223 #define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1224 #define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1225 #define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1226 #define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1227 #define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1228 #define BGE_MARBSTAT_PCI_TRAP 0x00000100 1229 #define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1230 #define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1231 #define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1232 #define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1233 #define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1234 #define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1235 #define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1236 #define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1237 #define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1238 #define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1239 #define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1240 #define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1241 #define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1242 #define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1243 #define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1244 #define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1245 #define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1246 1247 /* 1248 * Buffer manager control registers 1249 */ 1250 #define BGE_BMAN_MODE 0x4400 1251 #define BGE_BMAN_STATUS 0x4404 1252 #define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1253 #define BGE_BMAN_MBUFPOOL_LEN 0x440C 1254 #define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1255 #define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1256 #define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1257 #define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1258 #define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1259 #define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1260 #define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1261 #define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1262 #define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1263 #define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1264 #define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1265 #define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1266 #define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1267 #define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1268 #define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1269 #define BGE_BMAN_HWDIAG_1 0x444C 1270 #define BGE_BMAN_HWDIAG_2 0x4450 1271 #define BGE_BMAN_HWDIAG_3 0x4454 1272 1273 /* Buffer manager mode register */ 1274 #define BGE_BMANMODE_RESET 0x00000001 1275 #define BGE_BMANMODE_ENABLE 0x00000002 1276 #define BGE_BMANMODE_ATTN 0x00000004 1277 #define BGE_BMANMODE_TESTMODE 0x00000008 1278 #define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1279 1280 /* Buffer manager status register */ 1281 #define BGE_BMANSTAT_ERRO 0x00000004 1282 #define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1283 1284 1285 /* 1286 * Read DMA Control registers 1287 */ 1288 #define BGE_RDMA_MODE 0x4800 1289 #define BGE_RDMA_STATUS 0x4804 1290 1291 /* Read DMA mode register */ 1292 #define BGE_RDMAMODE_RESET 0x00000001 1293 #define BGE_RDMAMODE_ENABLE 0x00000002 1294 #define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1295 #define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1296 #define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1297 #define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1298 #define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1299 #define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1300 #define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1301 #define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1302 #define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1303 1304 /* Read DMA status register */ 1305 #define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1306 #define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1307 #define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1308 #define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1309 #define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1310 #define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1311 #define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1312 #define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1313 1314 /* 1315 * Write DMA control registers 1316 */ 1317 #define BGE_WDMA_MODE 0x4C00 1318 #define BGE_WDMA_STATUS 0x4C04 1319 1320 /* Write DMA mode register */ 1321 #define BGE_WDMAMODE_RESET 0x00000001 1322 #define BGE_WDMAMODE_ENABLE 0x00000002 1323 #define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1324 #define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1325 #define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1326 #define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1327 #define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1328 #define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1329 #define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1330 #define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1331 #define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1332 1333 /* Write DMA status register */ 1334 #define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1335 #define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1336 #define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1337 #define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1338 #define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1339 #define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1340 #define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1341 #define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1342 1343 1344 /* 1345 * RX CPU registers 1346 */ 1347 #define BGE_RXCPU_MODE 0x5000 1348 #define BGE_RXCPU_STATUS 0x5004 1349 #define BGE_RXCPU_PC 0x501C 1350 1351 /* RX CPU mode register */ 1352 #define BGE_RXCPUMODE_RESET 0x00000001 1353 #define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1354 #define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1355 #define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1356 #define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1357 #define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1358 #define BGE_RXCPUMODE_ROMFAIL 0x00000040 1359 #define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1360 #define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1361 #define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1362 #define BGE_RXCPUMODE_HALTCPU 0x00000400 1363 #define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1364 #define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1365 #define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1366 1367 /* RX CPU status register */ 1368 #define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1369 #define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1370 #define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1371 #define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1372 #define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1373 #define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1374 #define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1375 #define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1376 #define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1377 #define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1378 #define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1379 #define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1380 #define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1381 #define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1382 #define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1383 #define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1384 #define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1385 1386 1387 /* 1388 * TX CPU registers 1389 */ 1390 #define BGE_TXCPU_MODE 0x5400 1391 #define BGE_TXCPU_STATUS 0x5404 1392 #define BGE_TXCPU_PC 0x541C 1393 1394 /* TX CPU mode register */ 1395 #define BGE_TXCPUMODE_RESET 0x00000001 1396 #define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1397 #define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1398 #define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1399 #define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1400 #define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1401 #define BGE_TXCPUMODE_ROMFAIL 0x00000040 1402 #define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1403 #define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1404 #define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1405 #define BGE_TXCPUMODE_HALTCPU 0x00000400 1406 #define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1407 #define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1408 1409 /* TX CPU status register */ 1410 #define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1411 #define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1412 #define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1413 #define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1414 #define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1415 #define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1416 #define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1417 #define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1418 #define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1419 #define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1420 #define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1421 #define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1422 #define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1423 #define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1424 #define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1425 #define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1426 #define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1427 1428 1429 /* 1430 * Low priority mailbox registers 1431 */ 1432 #define BGE_LPMBX_IRQ0_HI 0x5800 1433 #define BGE_LPMBX_IRQ0_LO 0x5804 1434 #define BGE_LPMBX_IRQ1_HI 0x5808 1435 #define BGE_LPMBX_IRQ1_LO 0x580C 1436 #define BGE_LPMBX_IRQ2_HI 0x5810 1437 #define BGE_LPMBX_IRQ2_LO 0x5814 1438 #define BGE_LPMBX_IRQ3_HI 0x5818 1439 #define BGE_LPMBX_IRQ3_LO 0x581C 1440 #define BGE_LPMBX_GEN0_HI 0x5820 1441 #define BGE_LPMBX_GEN0_LO 0x5824 1442 #define BGE_LPMBX_GEN1_HI 0x5828 1443 #define BGE_LPMBX_GEN1_LO 0x582C 1444 #define BGE_LPMBX_GEN2_HI 0x5830 1445 #define BGE_LPMBX_GEN2_LO 0x5834 1446 #define BGE_LPMBX_GEN3_HI 0x5828 1447 #define BGE_LPMBX_GEN3_LO 0x582C 1448 #define BGE_LPMBX_GEN4_HI 0x5840 1449 #define BGE_LPMBX_GEN4_LO 0x5844 1450 #define BGE_LPMBX_GEN5_HI 0x5848 1451 #define BGE_LPMBX_GEN5_LO 0x584C 1452 #define BGE_LPMBX_GEN6_HI 0x5850 1453 #define BGE_LPMBX_GEN6_LO 0x5854 1454 #define BGE_LPMBX_GEN7_HI 0x5858 1455 #define BGE_LPMBX_GEN7_LO 0x585C 1456 #define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1457 #define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1458 #define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1459 #define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1460 #define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1461 #define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1462 #define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1463 #define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1464 #define BGE_LPMBX_RX_CONS0_HI 0x5880 1465 #define BGE_LPMBX_RX_CONS0_LO 0x5884 1466 #define BGE_LPMBX_RX_CONS1_HI 0x5888 1467 #define BGE_LPMBX_RX_CONS1_LO 0x588C 1468 #define BGE_LPMBX_RX_CONS2_HI 0x5890 1469 #define BGE_LPMBX_RX_CONS2_LO 0x5894 1470 #define BGE_LPMBX_RX_CONS3_HI 0x5898 1471 #define BGE_LPMBX_RX_CONS3_LO 0x589C 1472 #define BGE_LPMBX_RX_CONS4_HI 0x58A0 1473 #define BGE_LPMBX_RX_CONS4_LO 0x58A4 1474 #define BGE_LPMBX_RX_CONS5_HI 0x58A8 1475 #define BGE_LPMBX_RX_CONS5_LO 0x58AC 1476 #define BGE_LPMBX_RX_CONS6_HI 0x58B0 1477 #define BGE_LPMBX_RX_CONS6_LO 0x58B4 1478 #define BGE_LPMBX_RX_CONS7_HI 0x58B8 1479 #define BGE_LPMBX_RX_CONS7_LO 0x58BC 1480 #define BGE_LPMBX_RX_CONS8_HI 0x58C0 1481 #define BGE_LPMBX_RX_CONS8_LO 0x58C4 1482 #define BGE_LPMBX_RX_CONS9_HI 0x58C8 1483 #define BGE_LPMBX_RX_CONS9_LO 0x58CC 1484 #define BGE_LPMBX_RX_CONS10_HI 0x58D0 1485 #define BGE_LPMBX_RX_CONS10_LO 0x58D4 1486 #define BGE_LPMBX_RX_CONS11_HI 0x58D8 1487 #define BGE_LPMBX_RX_CONS11_LO 0x58DC 1488 #define BGE_LPMBX_RX_CONS12_HI 0x58E0 1489 #define BGE_LPMBX_RX_CONS12_LO 0x58E4 1490 #define BGE_LPMBX_RX_CONS13_HI 0x58E8 1491 #define BGE_LPMBX_RX_CONS13_LO 0x58EC 1492 #define BGE_LPMBX_RX_CONS14_HI 0x58F0 1493 #define BGE_LPMBX_RX_CONS14_LO 0x58F4 1494 #define BGE_LPMBX_RX_CONS15_HI 0x58F8 1495 #define BGE_LPMBX_RX_CONS15_LO 0x58FC 1496 #define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1497 #define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1498 #define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1499 #define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1500 #define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1501 #define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1502 #define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1503 #define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1504 #define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1505 #define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1506 #define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1507 #define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1508 #define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1509 #define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1510 #define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1511 #define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1512 #define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1513 #define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1514 #define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1515 #define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1516 #define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1517 #define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1518 #define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1519 #define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1520 #define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1521 #define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1522 #define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1523 #define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1524 #define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1525 #define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1526 #define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1527 #define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1528 #define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1529 #define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1530 #define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1531 #define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1532 #define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1533 #define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1534 #define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1535 #define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1536 #define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1537 #define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1538 #define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1539 #define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1540 #define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1541 #define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1542 #define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1543 #define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1544 #define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1545 #define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1546 #define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1547 #define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1548 #define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1549 #define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1550 #define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1551 #define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1552 #define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1553 #define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1554 #define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1555 #define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1556 #define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1557 #define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1558 #define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1559 #define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1560 1561 /* 1562 * Flow throw Queue reset register 1563 */ 1564 #define BGE_FTQ_RESET 0x5C00 1565 1566 #define BGE_FTQRESET_DMAREAD 0x00000002 1567 #define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1568 #define BGE_FTQRESET_DMADONE 0x00000010 1569 #define BGE_FTQRESET_SBDC 0x00000020 1570 #define BGE_FTQRESET_SDI 0x00000040 1571 #define BGE_FTQRESET_WDMA 0x00000080 1572 #define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1573 #define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1574 #define BGE_FTQRESET_SDC 0x00000400 1575 #define BGE_FTQRESET_HCC 0x00000800 1576 #define BGE_FTQRESET_TXFIFO 0x00001000 1577 #define BGE_FTQRESET_MBC 0x00002000 1578 #define BGE_FTQRESET_RBDC 0x00004000 1579 #define BGE_FTQRESET_RXLP 0x00008000 1580 #define BGE_FTQRESET_RDBDI 0x00010000 1581 #define BGE_FTQRESET_RDC 0x00020000 1582 #define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1583 1584 /* 1585 * Message Signaled Interrupt registers 1586 */ 1587 #define BGE_MSI_MODE 0x6000 1588 #define BGE_MSI_STATUS 0x6004 1589 #define BGE_MSI_FIFOACCESS 0x6008 1590 1591 /* MSI mode register */ 1592 #define BGE_MSIMODE_RESET 0x00000001 1593 #define BGE_MSIMODE_ENABLE 0x00000002 1594 #define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1595 #define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1596 #define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1597 #define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1598 #define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1599 1600 /* MSI status register */ 1601 #define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1602 #define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1603 #define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1604 #define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1605 #define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1606 1607 1608 /* 1609 * DMA Completion registers 1610 */ 1611 #define BGE_DMAC_MODE 0x6400 1612 1613 /* DMA Completion mode register */ 1614 #define BGE_DMACMODE_RESET 0x00000001 1615 #define BGE_DMACMODE_ENABLE 0x00000002 1616 1617 1618 /* 1619 * General control registers. 1620 */ 1621 #define BGE_MODE_CTL 0x6800 1622 #define BGE_MISC_CFG 0x6804 1623 #define BGE_MISC_LOCAL_CTL 0x6808 1624 #define BGE_EE_ADDR 0x6838 1625 #define BGE_EE_DATA 0x683C 1626 #define BGE_EE_CTL 0x6840 1627 #define BGE_MDI_CTL 0x6844 1628 #define BGE_EE_DELAY 0x6848 1629 1630 /* Mode control register */ 1631 #define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1632 #define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1633 #define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1634 #define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1635 #define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1636 #define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1637 #define BGE_MODECTL_NO_RX_CRC 0x00000400 1638 #define BGE_MODECTL_RX_BADFRAMES 0x00000800 1639 #define BGE_MODECTL_NO_TX_INTR 0x00002000 1640 #define BGE_MODECTL_NO_RX_INTR 0x00004000 1641 #define BGE_MODECTL_FORCE_PCI32 0x00008000 1642 #define BGE_MODECTL_STACKUP 0x00010000 1643 #define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1644 #define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1645 #define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1646 #define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1647 #define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1648 #define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1649 #define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1650 #define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1651 #define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1652 #define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1653 1654 /* Misc. config register */ 1655 #define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1656 #define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1657 1658 #define BGE_32BITTIME_66MHZ (0x41 << 1) 1659 1660 /* Misc. Local Control */ 1661 #define BGE_MLC_INTR_STATE 0x00000001 1662 #define BGE_MLC_INTR_CLR 0x00000002 1663 #define BGE_MLC_INTR_SET 0x00000004 1664 #define BGE_MLC_INTR_ONATTN 0x00000008 1665 #define BGE_MLC_MISCIO_IN0 0x00000100 1666 #define BGE_MLC_MISCIO_IN1 0x00000200 1667 #define BGE_MLC_MISCIO_IN2 0x00000400 1668 #define BGE_MLC_MISCIO_OUTEN0 0x00000800 1669 #define BGE_MLC_MISCIO_OUTEN1 0x00001000 1670 #define BGE_MLC_MISCIO_OUTEN2 0x00002000 1671 #define BGE_MLC_MISCIO_OUT0 0x00004000 1672 #define BGE_MLC_MISCIO_OUT1 0x00008000 1673 #define BGE_MLC_MISCIO_OUT2 0x00010000 1674 #define BGE_MLC_EXTRAM_ENB 0x00020000 1675 #define BGE_MLC_SRAM_SIZE 0x001C0000 1676 #define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1677 #define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1678 #define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1679 #define BGE_MLC_AUTO_EEPROM 0x01000000 1680 1681 #define BGE_SSRAMSIZE_256KB 0x00000000 1682 #define BGE_SSRAMSIZE_512KB 0x00040000 1683 #define BGE_SSRAMSIZE_1MB 0x00080000 1684 #define BGE_SSRAMSIZE_2MB 0x000C0000 1685 #define BGE_SSRAMSIZE_4MB 0x00100000 1686 #define BGE_SSRAMSIZE_8MB 0x00140000 1687 #define BGE_SSRAMSIZE_16M 0x00180000 1688 1689 /* EEPROM address register */ 1690 #define BGE_EEADDR_ADDRESS 0x0000FFFC 1691 #define BGE_EEADDR_HALFCLK 0x01FF0000 1692 #define BGE_EEADDR_START 0x02000000 1693 #define BGE_EEADDR_DEVID 0x1C000000 1694 #define BGE_EEADDR_RESET 0x20000000 1695 #define BGE_EEADDR_DONE 0x40000000 1696 #define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1697 1698 #define BGE_EEDEVID(x) ((x & 7) << 26) 1699 #define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1700 #define BGE_HALFCLK_384SCL 0x60 1701 #define BGE_EE_READCMD \ 1702 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1703 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1704 #define BGE_EE_WRCMD \ 1705 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1706 BGE_EEADDR_START|BGE_EEADDR_DONE) 1707 1708 /* EEPROM Control register */ 1709 #define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1710 #define BGE_EECTL_CLKOUT 0x00000002 1711 #define BGE_EECTL_CLKIN 0x00000004 1712 #define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1713 #define BGE_EECTL_DATAOUT 0x00000010 1714 #define BGE_EECTL_DATAIN 0x00000020 1715 1716 /* MDI (MII/GMII) access register */ 1717 #define BGE_MDI_DATA 0x00000001 1718 #define BGE_MDI_DIR 0x00000002 1719 #define BGE_MDI_SEL 0x00000004 1720 #define BGE_MDI_CLK 0x00000008 1721 1722 #define BGE_MEMWIN_START 0x00008000 1723 #define BGE_MEMWIN_END 0x0000FFFF 1724 1725 1726 #define BGE_MEMWIN_READ(sc, x, val) \ 1727 do { \ 1728 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1729 (0xFFFF0000 & x), 4); \ 1730 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1731 } while(0) 1732 1733 #define BGE_MEMWIN_WRITE(sc, x, val) \ 1734 do { \ 1735 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1736 (0xFFFF0000 & x), 4); \ 1737 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1738 } while(0) 1739 1740 /* 1741 * This magic number is used to prevent PXE restart when we 1742 * issue a software reset. We write this magic number to the 1743 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1744 * code from running. 1745 */ 1746 #define BGE_MAGIC_NUMBER 0x4B657654 1747 1748 typedef struct { 1749 u_int32_t bge_addr_hi; 1750 u_int32_t bge_addr_lo; 1751 } bge_hostaddr; 1752 1753 #define BGE_HOSTADDR(x, y) \ 1754 do { \ 1755 (x).bge_addr_lo = ((u_int64_t) (y) & 0xffffffff); \ 1756 (x).bge_addr_hi = ((u_int64_t) (y) >> 32); \ 1757 } while(0) 1758 1759 #define BGE_ADDR_LO(y) \ 1760 ((u_int64_t) (y) & 0xFFFFFFFF) 1761 #define BGE_ADDR_HI(y) \ 1762 ((u_int64_t) (y) >> 32) 1763 1764 /* Ring control block structure */ 1765 struct bge_rcb { 1766 bge_hostaddr bge_hostaddr; 1767 u_int32_t bge_maxlen_flags; 1768 u_int32_t bge_nicaddr; 1769 }; 1770 #define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1771 1772 #define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1773 #define BGE_RCB_FLAG_RING_DISABLED 0x0002 1774 1775 struct bge_tx_bd { 1776 bge_hostaddr bge_addr; 1777 u_int16_t bge_flags; 1778 u_int16_t bge_len; 1779 u_int16_t bge_vlan_tag; 1780 u_int16_t bge_rsvd; 1781 }; 1782 1783 #define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1784 #define BGE_TXBDFLAG_IP_CSUM 0x0002 1785 #define BGE_TXBDFLAG_END 0x0004 1786 #define BGE_TXBDFLAG_IP_FRAG 0x0008 1787 #define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1788 #define BGE_TXBDFLAG_VLAN_TAG 0x0040 1789 #define BGE_TXBDFLAG_COAL_NOW 0x0080 1790 #define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1791 #define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1792 #define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1793 #define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1794 #define BGE_TXBDFLAG_NO_CRC 0x8000 1795 1796 #define BGE_NIC_TXRING_ADDR(ringno, size) \ 1797 BGE_SEND_RING_1_TO_4 + \ 1798 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1799 1800 struct bge_rx_bd { 1801 bge_hostaddr bge_addr; 1802 u_int16_t bge_len; 1803 u_int16_t bge_idx; 1804 u_int16_t bge_flags; 1805 u_int16_t bge_type; 1806 u_int16_t bge_tcp_udp_csum; 1807 u_int16_t bge_ip_csum; 1808 u_int16_t bge_vlan_tag; 1809 u_int16_t bge_error_flag; 1810 u_int32_t bge_rsvd; 1811 u_int32_t bge_opaque; 1812 }; 1813 1814 struct bge_extrx_bd { 1815 bge_hostaddr bge_addr1; 1816 bge_hostaddr bge_addr2; 1817 bge_hostaddr bge_addr3; 1818 u_int16_t bge_len2; 1819 u_int16_t bge_len1; 1820 u_int16_t bge_rsvd1; 1821 u_int16_t bge_len3; 1822 bge_hostaddr bge_addr0; 1823 u_int16_t bge_len0; 1824 u_int16_t bge_idx; 1825 u_int16_t bge_flags; 1826 u_int16_t bge_type; 1827 u_int16_t bge_tcp_udp_csum; 1828 u_int16_t bge_ip_csum; 1829 u_int16_t bge_vlan_tag; 1830 u_int16_t bge_error_flag; 1831 u_int32_t bge_rsvd0; 1832 u_int32_t bge_opaque; 1833 }; 1834 1835 #define BGE_RXBDFLAG_END 0x0004 1836 #define BGE_RXBDFLAG_JUMBO_RING 0x0020 1837 #define BGE_RXBDFLAG_VLAN_TAG 0x0040 1838 #define BGE_RXBDFLAG_ERROR 0x0400 1839 #define BGE_RXBDFLAG_MINI_RING 0x0800 1840 #define BGE_RXBDFLAG_IP_CSUM 0x1000 1841 #define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1842 #define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1843 1844 #define BGE_RXERRFLAG_BAD_CRC 0x0001 1845 #define BGE_RXERRFLAG_COLL_DETECT 0x0002 1846 #define BGE_RXERRFLAG_LINK_LOST 0x0004 1847 #define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1848 #define BGE_RXERRFLAG_MAC_ABORT 0x0010 1849 #define BGE_RXERRFLAG_RUNT 0x0020 1850 #define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1851 #define BGE_RXERRFLAG_GIANT 0x0080 1852 1853 struct bge_sts_idx { 1854 u_int16_t bge_rx_prod_idx; 1855 u_int16_t bge_tx_cons_idx; 1856 }; 1857 1858 struct bge_status_block { 1859 u_int32_t bge_status; 1860 u_int32_t bge_rsvd0; 1861 u_int16_t bge_rx_jumbo_cons_idx; 1862 u_int16_t bge_rx_std_cons_idx; 1863 u_int16_t bge_rx_mini_cons_idx; 1864 u_int16_t bge_rsvd1; 1865 struct bge_sts_idx bge_idx[16]; 1866 }; 1867 1868 #define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1869 #define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1870 1871 #define BGE_STATFLAG_UPDATED 0x00000001 1872 #define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1873 #define BGE_STATFLAG_ERROR 0x00000004 1874 1875 1876 /* 1877 * Broadcom Vendor ID 1878 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1879 * even though they're now manufactured by Broadcom) 1880 */ 1881 #define BCOM_VENDORID 0x14E4 1882 #define BCOM_DEVICEID_BCM5700 0x1644 1883 #define BCOM_DEVICEID_BCM5701 0x1645 1884 #define BCOM_DEVICEID_BCM5702 0x16A6 1885 #define BCOM_DEVICEID_BCM5702X 0x16C6 1886 #define BCOM_DEVICEID_BCM5703 0x16A7 1887 #define BCOM_DEVICEID_BCM5703X 0x16C7 1888 #define BCOM_DEVICEID_BCM5704C 0x1648 1889 #define BCOM_DEVICEID_BCM5704S 0x16A8 1890 #define BCOM_DEVICEID_BCM5705 0x1653 1891 #define BCOM_DEVICEID_BCM5705K 0x1654 1892 #define BCOM_DEVICEID_BCM5721 0x1659 1893 #define BCOM_DEVICEID_BCM5705M 0x165D 1894 #define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1895 #define BCOM_DEVICEID_BCM5714C 0x1668 1896 #define BCOM_DEVICEID_BCM5750 0x1676 1897 #define BCOM_DEVICEID_BCM5750M 0x167C 1898 #define BCOM_DEVICEID_BCM5751 0x1677 1899 #define BCOM_DEVICEID_BCM5751M 0x167D 1900 #define BCOM_DEVICEID_BCM5752 0x1600 1901 #define BCOM_DEVICEID_BCM5782 0x1696 1902 #define BCOM_DEVICEID_BCM5788 0x169C 1903 #define BCOM_DEVICEID_BCM5789 0x169D 1904 #define BCOM_DEVICEID_BCM5901 0x170D 1905 #define BCOM_DEVICEID_BCM5901A2 0x170E 1906 1907 /* 1908 * Alteon AceNIC PCI vendor/device ID. 1909 */ 1910 #define ALT_VENDORID 0x12AE 1911 #define ALT_DEVICEID_ACENIC 0x0001 1912 #define ALT_DEVICEID_ACENIC_COPPER 0x0002 1913 #define ALT_DEVICEID_BCM5700 0x0003 1914 #define ALT_DEVICEID_BCM5701 0x0004 1915 1916 /* 1917 * 3Com 3c985 PCI vendor/device ID. 1918 */ 1919 #define TC_VENDORID 0x10B7 1920 #define TC_DEVICEID_3C985 0x0001 1921 #define TC_DEVICEID_3C996 0x0003 1922 1923 /* 1924 * SysKonnect PCI vendor ID 1925 */ 1926 #define SK_VENDORID 0x1148 1927 #define SK_DEVICEID_ALTIMA 0x4400 1928 #define SK_SUBSYSID_9D21 0x4421 1929 #define SK_SUBSYSID_9D41 0x4441 1930 1931 /* 1932 * Altima PCI vendor/device ID. 1933 */ 1934 #define ALTIMA_VENDORID 0x173b 1935 #define ALTIMA_DEVICE_AC1000 0x03e8 1936 #define ALTIMA_DEVICE_AC1002 0x03e9 1937 #define ALTIMA_DEVICE_AC9100 0x03ea 1938 1939 /* 1940 * Dell PCI vendor ID 1941 */ 1942 1943 #define DELL_VENDORID 0x1028 1944 1945 /* 1946 * Offset of MAC address inside EEPROM. 1947 */ 1948 #define BGE_EE_MAC_OFFSET 0x7C 1949 #define BGE_EE_HWCFG_OFFSET 0xC8 1950 1951 #define BGE_HWCFG_VOLTAGE 0x00000003 1952 #define BGE_HWCFG_PHYLED_MODE 0x0000000C 1953 #define BGE_HWCFG_MEDIA 0x00000030 1954 1955 #define BGE_VOLTAGE_1POINT3 0x00000000 1956 #define BGE_VOLTAGE_1POINT8 0x00000001 1957 1958 #define BGE_PHYLEDMODE_UNSPEC 0x00000000 1959 #define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1960 #define BGE_PHYLEDMODE_SINGLELED 0x00000008 1961 1962 #define BGE_MEDIA_UNSPEC 0x00000000 1963 #define BGE_MEDIA_COPPER 0x00000010 1964 #define BGE_MEDIA_FIBER 0x00000020 1965 1966 #define BGE_PCI_READ_CMD 0x06000000 1967 #define BGE_PCI_WRITE_CMD 0x70000000 1968 1969 #define BGE_TICKS_PER_SEC 1000000 1970 1971 /* 1972 * Ring size constants. 1973 */ 1974 #define BGE_EVENT_RING_CNT 256 1975 #define BGE_CMD_RING_CNT 64 1976 #define BGE_STD_RX_RING_CNT 512 1977 #define BGE_JUMBO_RX_RING_CNT 256 1978 #define BGE_MINI_RX_RING_CNT 1024 1979 #define BGE_RETURN_RING_CNT 1024 1980 1981 /* 5705 has smaller return ring size */ 1982 1983 #define BGE_RETURN_RING_CNT_5705 512 1984 1985 /* 1986 * Possible TX ring sizes. 1987 */ 1988 #define BGE_TX_RING_CNT_128 128 1989 #define BGE_TX_RING_BASE_128 0x3800 1990 1991 #define BGE_TX_RING_CNT_256 256 1992 #define BGE_TX_RING_BASE_256 0x3000 1993 1994 #define BGE_TX_RING_CNT_512 512 1995 #define BGE_TX_RING_BASE_512 0x2000 1996 1997 #define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1998 #define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1999 2000 /* 2001 * Tigon III statistics counters. 2002 */ 2003 /* Statistics maintained MAC Receive block. */ 2004 struct bge_rx_mac_stats { 2005 bge_hostaddr ifHCInOctets; 2006 bge_hostaddr Reserved1; 2007 bge_hostaddr etherStatsFragments; 2008 bge_hostaddr ifHCInUcastPkts; 2009 bge_hostaddr ifHCInMulticastPkts; 2010 bge_hostaddr ifHCInBroadcastPkts; 2011 bge_hostaddr dot3StatsFCSErrors; 2012 bge_hostaddr dot3StatsAlignmentErrors; 2013 bge_hostaddr xonPauseFramesReceived; 2014 bge_hostaddr xoffPauseFramesReceived; 2015 bge_hostaddr macControlFramesReceived; 2016 bge_hostaddr xoffStateEntered; 2017 bge_hostaddr dot3StatsFramesTooLong; 2018 bge_hostaddr etherStatsJabbers; 2019 bge_hostaddr etherStatsUndersizePkts; 2020 bge_hostaddr inRangeLengthError; 2021 bge_hostaddr outRangeLengthError; 2022 bge_hostaddr etherStatsPkts64Octets; 2023 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2024 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2025 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2026 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2027 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2028 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2029 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2030 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2031 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2032 }; 2033 2034 2035 /* Statistics maintained MAC Transmit block. */ 2036 struct bge_tx_mac_stats { 2037 bge_hostaddr ifHCOutOctets; 2038 bge_hostaddr Reserved2; 2039 bge_hostaddr etherStatsCollisions; 2040 bge_hostaddr outXonSent; 2041 bge_hostaddr outXoffSent; 2042 bge_hostaddr flowControlDone; 2043 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2044 bge_hostaddr dot3StatsSingleCollisionFrames; 2045 bge_hostaddr dot3StatsMultipleCollisionFrames; 2046 bge_hostaddr dot3StatsDeferredTransmissions; 2047 bge_hostaddr Reserved3; 2048 bge_hostaddr dot3StatsExcessiveCollisions; 2049 bge_hostaddr dot3StatsLateCollisions; 2050 bge_hostaddr dot3Collided2Times; 2051 bge_hostaddr dot3Collided3Times; 2052 bge_hostaddr dot3Collided4Times; 2053 bge_hostaddr dot3Collided5Times; 2054 bge_hostaddr dot3Collided6Times; 2055 bge_hostaddr dot3Collided7Times; 2056 bge_hostaddr dot3Collided8Times; 2057 bge_hostaddr dot3Collided9Times; 2058 bge_hostaddr dot3Collided10Times; 2059 bge_hostaddr dot3Collided11Times; 2060 bge_hostaddr dot3Collided12Times; 2061 bge_hostaddr dot3Collided13Times; 2062 bge_hostaddr dot3Collided14Times; 2063 bge_hostaddr dot3Collided15Times; 2064 bge_hostaddr ifHCOutUcastPkts; 2065 bge_hostaddr ifHCOutMulticastPkts; 2066 bge_hostaddr ifHCOutBroadcastPkts; 2067 bge_hostaddr dot3StatsCarrierSenseErrors; 2068 bge_hostaddr ifOutDiscards; 2069 bge_hostaddr ifOutErrors; 2070 }; 2071 2072 /* Stats counters access through registers */ 2073 struct bge_mac_stats_regs { 2074 u_int32_t ifHCOutOctets; 2075 u_int32_t Reserved0; 2076 u_int32_t etherStatsCollisions; 2077 u_int32_t outXonSent; 2078 u_int32_t outXoffSent; 2079 u_int32_t Reserved1; 2080 u_int32_t dot3StatsInternalMacTransmitErrors; 2081 u_int32_t dot3StatsSingleCollisionFrames; 2082 u_int32_t dot3StatsMultipleCollisionFrames; 2083 u_int32_t dot3StatsDeferredTransmissions; 2084 u_int32_t Reserved2; 2085 u_int32_t dot3StatsExcessiveCollisions; 2086 u_int32_t dot3StatsLateCollisions; 2087 u_int32_t Reserved3[14]; 2088 u_int32_t ifHCOutUcastPkts; 2089 u_int32_t ifHCOutMulticastPkts; 2090 u_int32_t ifHCOutBroadcastPkts; 2091 u_int32_t Reserved4[2]; 2092 u_int32_t ifHCInOctets; 2093 u_int32_t Reserved5; 2094 u_int32_t etherStatsFragments; 2095 u_int32_t ifHCInUcastPkts; 2096 u_int32_t ifHCInMulticastPkts; 2097 u_int32_t ifHCInBroadcastPkts; 2098 u_int32_t dot3StatsFCSErrors; 2099 u_int32_t dot3StatsAlignmentErrors; 2100 u_int32_t xonPauseFramesReceived; 2101 u_int32_t xoffPauseFramesReceived; 2102 u_int32_t macControlFramesReceived; 2103 u_int32_t xoffStateEntered; 2104 u_int32_t dot3StatsFramesTooLong; 2105 u_int32_t etherStatsJabbers; 2106 u_int32_t etherStatsUndersizePkts; 2107 }; 2108 2109 struct bge_stats { 2110 u_int8_t Reserved0[256]; 2111 2112 /* Statistics maintained by Receive MAC. */ 2113 struct bge_rx_mac_stats rxstats; 2114 2115 bge_hostaddr Unused1[37]; 2116 2117 /* Statistics maintained by Transmit MAC. */ 2118 struct bge_tx_mac_stats txstats; 2119 2120 bge_hostaddr Unused2[31]; 2121 2122 /* Statistics maintained by Receive List Placement. */ 2123 bge_hostaddr COSIfHCInPkts[16]; 2124 bge_hostaddr COSFramesDroppedDueToFilters; 2125 bge_hostaddr nicDmaWriteQueueFull; 2126 bge_hostaddr nicDmaWriteHighPriQueueFull; 2127 bge_hostaddr nicNoMoreRxBDs; 2128 bge_hostaddr ifInDiscards; 2129 bge_hostaddr ifInErrors; 2130 bge_hostaddr nicRecvThresholdHit; 2131 2132 bge_hostaddr Unused3[9]; 2133 2134 /* Statistics maintained by Send Data Initiator. */ 2135 bge_hostaddr COSIfHCOutPkts[16]; 2136 bge_hostaddr nicDmaReadQueueFull; 2137 bge_hostaddr nicDmaReadHighPriQueueFull; 2138 bge_hostaddr nicSendDataCompQueueFull; 2139 2140 /* Statistics maintained by Host Coalescing. */ 2141 bge_hostaddr nicRingSetSendProdIndex; 2142 bge_hostaddr nicRingStatusUpdate; 2143 bge_hostaddr nicInterrupts; 2144 bge_hostaddr nicAvoidedInterrupts; 2145 bge_hostaddr nicSendThresholdHit; 2146 2147 u_int8_t Reserved4[320]; 2148 }; 2149 2150 /* 2151 * Tigon general information block. This resides in host memory 2152 * and contains the status counters, ring control blocks and 2153 * producer pointers. 2154 */ 2155 2156 struct bge_gib { 2157 struct bge_stats bge_stats; 2158 struct bge_rcb bge_tx_rcb[16]; 2159 struct bge_rcb bge_std_rx_rcb; 2160 struct bge_rcb bge_jumbo_rx_rcb; 2161 struct bge_rcb bge_mini_rx_rcb; 2162 struct bge_rcb bge_return_rcb; 2163 }; 2164 2165 #define BGE_FRAMELEN 1518 2166 #define BGE_MAX_FRAMELEN 1536 2167 #define BGE_JUMBO_FRAMELEN 9018 2168 #define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2169 #define BGE_MIN_FRAMELEN 60 2170 2171 /* 2172 * Other utility macros. 2173 */ 2174 #define BGE_INC(x, y) (x) = (x + 1) % y 2175 2176 /* 2177 * Vital product data and structures. 2178 */ 2179 #define BGE_VPD_FLAG 0x8000 2180 2181 /* VPD structures */ 2182 struct vpd_res { 2183 u_int8_t vr_id; 2184 u_int8_t vr_len; 2185 u_int8_t vr_pad; 2186 }; 2187 2188 struct vpd_key { 2189 char vk_key[2]; 2190 u_int8_t vk_len; 2191 }; 2192 2193 #define VPD_RES_ID 0x82 /* ID string */ 2194 #define VPD_RES_READ 0x90 /* start of read only area */ 2195 #define VPD_RES_WRITE 0x81 /* start of read/write area */ 2196 #define VPD_RES_END 0x78 /* end tag */ 2197 2198 2199 /* 2200 * Register access macros. The Tigon always uses memory mapped register 2201 * accesses and all registers must be accessed with 32 bit operations. 2202 */ 2203 2204 #define CSR_WRITE_4(sc, reg, val) \ 2205 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2206 2207 #define CSR_READ_4(sc, reg) \ 2208 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2209 2210 #define BGE_SETBIT(sc, reg, x) \ 2211 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2212 #define BGE_CLRBIT(sc, reg, x) \ 2213 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2214 2215 #define PCI_SETBIT(dev, reg, x, s) \ 2216 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2217 #define PCI_CLRBIT(dev, reg, x, s) \ 2218 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2219 2220 /* 2221 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2222 * values are tuneable. They control the actual amount of buffers 2223 * allocated for the standard, mini and jumbo receive rings. 2224 */ 2225 2226 #define BGE_SSLOTS 256 2227 #define BGE_MSLOTS 256 2228 #define BGE_JSLOTS 384 2229 2230 #define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2231 #define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2232 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2233 #define BGE_JPAGESZ PAGE_SIZE 2234 #define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2235 #define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2236 2237 #define BGE_NSEG_JUMBO (MJUM9BYTES/PAGE_SIZE + 1) 2238 #define BGE_NSEG_NEW 32 2239 2240 /* 2241 * Ring structures. Most of these reside in host memory and we tell 2242 * the NIC where they are via the ring control blocks. The exceptions 2243 * are the tx and command rings, which live in NIC memory and which 2244 * we access via the shared memory window. 2245 */ 2246 2247 struct bge_ring_data { 2248 struct bge_rx_bd *bge_rx_std_ring; 2249 bus_addr_t bge_rx_std_ring_paddr; 2250 struct bge_extrx_bd *bge_rx_jumbo_ring; 2251 bus_addr_t bge_rx_jumbo_ring_paddr; 2252 struct bge_rx_bd *bge_rx_return_ring; 2253 bus_addr_t bge_rx_return_ring_paddr; 2254 struct bge_tx_bd *bge_tx_ring; 2255 bus_addr_t bge_tx_ring_paddr; 2256 struct bge_status_block *bge_status_block; 2257 bus_addr_t bge_status_block_paddr; 2258 struct bge_stats *bge_stats; 2259 bus_addr_t bge_stats_paddr; 2260 struct bge_gib bge_info; 2261 }; 2262 2263 #define BGE_STD_RX_RING_SZ \ 2264 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2265 #define BGE_JUMBO_RX_RING_SZ \ 2266 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2267 #define BGE_TX_RING_SZ \ 2268 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2269 #define BGE_RX_RTN_RING_SZ(x) \ 2270 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2271 2272 #define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2273 2274 #define BGE_STATS_SZ sizeof (struct bge_stats) 2275 2276 /* 2277 * Mbuf pointers. We need these to keep track of the virtual addresses 2278 * of our mbuf chains since we can only convert from physical to virtual, 2279 * not the other way around. 2280 */ 2281 struct bge_chain_data { 2282 bus_dma_tag_t bge_parent_tag; 2283 bus_dma_tag_t bge_rx_std_ring_tag; 2284 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2285 bus_dma_tag_t bge_rx_return_ring_tag; 2286 bus_dma_tag_t bge_tx_ring_tag; 2287 bus_dma_tag_t bge_status_tag; 2288 bus_dma_tag_t bge_stats_tag; 2289 bus_dma_tag_t bge_mtag; /* mbuf mapping tag */ 2290 bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag */ 2291 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2292 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2293 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2294 bus_dmamap_t bge_rx_std_ring_map; 2295 bus_dmamap_t bge_rx_jumbo_ring_map; 2296 bus_dmamap_t bge_tx_ring_map; 2297 bus_dmamap_t bge_rx_return_ring_map; 2298 bus_dmamap_t bge_status_map; 2299 bus_dmamap_t bge_stats_map; 2300 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2301 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2302 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2303 }; 2304 2305 struct bge_dmamap_arg { 2306 struct bge_softc *sc; 2307 bus_addr_t bge_busaddr; 2308 u_int16_t bge_flags; 2309 int bge_idx; 2310 int bge_maxsegs; 2311 struct bge_tx_bd *bge_ring; 2312 }; 2313 2314 struct bge_type { 2315 u_int16_t bge_vid; 2316 u_int16_t bge_did; 2317 char *bge_name; 2318 }; 2319 2320 #define BGE_HWREV_TIGON 0x01 2321 #define BGE_HWREV_TIGON_II 0x02 2322 #define BGE_TIMEOUT 100000 2323 #define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2324 2325 struct bge_bcom_hack { 2326 int reg; 2327 int val; 2328 }; 2329 2330 struct bge_softc { 2331 struct ifnet *bge_ifp; /* interface info */ 2332 device_t bge_dev; 2333 struct mtx bge_mtx; 2334 device_t bge_miibus; 2335 bus_space_handle_t bge_bhandle; 2336 vm_offset_t bge_vhandle; 2337 bus_space_tag_t bge_btag; 2338 void *bge_intrhand; 2339 struct resource *bge_irq; 2340 struct resource *bge_res; 2341 struct ifmedia bge_ifmedia; /* TBI media info */ 2342 u_int8_t bge_unit; /* interface number */ 2343 u_int8_t bge_extram; /* has external SSRAM */ 2344 u_int8_t bge_tbi; 2345 u_int8_t bge_rx_alignment_bug; 2346 u_int32_t bge_chipid; 2347 u_int8_t bge_asicrev; 2348 u_int8_t bge_chiprev; 2349 u_int8_t bge_no_3_led; 2350 u_int8_t bge_pcie; 2351 struct bge_ring_data bge_ldata; /* rings */ 2352 struct bge_chain_data bge_cdata; /* mbufs */ 2353 u_int16_t bge_tx_saved_considx; 2354 u_int16_t bge_rx_saved_considx; 2355 u_int16_t bge_ev_saved_considx; 2356 u_int16_t bge_return_ring_cnt; 2357 u_int16_t bge_std; /* current std ring head */ 2358 u_int16_t bge_jumbo; /* current jumo ring head */ 2359 u_int32_t bge_stat_ticks; 2360 u_int32_t bge_rx_coal_ticks; 2361 u_int32_t bge_tx_coal_ticks; 2362 u_int32_t bge_rx_max_coal_bds; 2363 u_int32_t bge_tx_max_coal_bds; 2364 u_int32_t bge_tx_buf_ratio; 2365 int bge_if_flags; 2366 int bge_txcnt; 2367 int bge_link; 2368 struct callout bge_stat_ch; 2369 char *bge_vpd_prodname; 2370 char *bge_vpd_readonly; 2371 #ifdef DEVICE_POLLING 2372 int rxcycles; 2373 #endif /* DEVICE_POLLING */ 2374 }; 2375 2376 #define BGE_LOCK_INIT(_sc, _name) \ 2377 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2378 #define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2379 #define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2380 #define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2381 #define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx) 2382