xref: /freebsd/sys/dev/bge/if_bgereg.h (revision 77982948d1da34a123ec554f8bcf6c3bb139bf8f)
1098ca2bdSWarner Losh /*-
295d67482SBill Paul  * Copyright (c) 2001 Wind River Systems
395d67482SBill Paul  * Copyright (c) 1997, 1998, 1999, 2001
495d67482SBill Paul  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
595d67482SBill Paul  *
695d67482SBill Paul  * Redistribution and use in source and binary forms, with or without
795d67482SBill Paul  * modification, are permitted provided that the following conditions
895d67482SBill Paul  * are met:
995d67482SBill Paul  * 1. Redistributions of source code must retain the above copyright
1095d67482SBill Paul  *    notice, this list of conditions and the following disclaimer.
1195d67482SBill Paul  * 2. Redistributions in binary form must reproduce the above copyright
1295d67482SBill Paul  *    notice, this list of conditions and the following disclaimer in the
1395d67482SBill Paul  *    documentation and/or other materials provided with the distribution.
1495d67482SBill Paul  * 3. All advertising materials mentioning features or use of this software
1595d67482SBill Paul  *    must display the following acknowledgement:
1695d67482SBill Paul  *	This product includes software developed by Bill Paul.
1795d67482SBill Paul  * 4. Neither the name of the author nor the names of any co-contributors
1895d67482SBill Paul  *    may be used to endorse or promote products derived from this software
1995d67482SBill Paul  *    without specific prior written permission.
2095d67482SBill Paul  *
2195d67482SBill Paul  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
2295d67482SBill Paul  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
2395d67482SBill Paul  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
2495d67482SBill Paul  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
2595d67482SBill Paul  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
2695d67482SBill Paul  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
2795d67482SBill Paul  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
2895d67482SBill Paul  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
2995d67482SBill Paul  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
3095d67482SBill Paul  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
3195d67482SBill Paul  * THE POSSIBILITY OF SUCH DAMAGE.
3295d67482SBill Paul  *
3395d67482SBill Paul  * $FreeBSD$
3495d67482SBill Paul  */
3595d67482SBill Paul 
3695d67482SBill Paul /*
3795d67482SBill Paul  * BCM570x memory map. The internal memory layout varies somewhat
3895d67482SBill Paul  * depending on whether or not we have external SSRAM attached.
3995d67482SBill Paul  * The BCM5700 can have up to 16MB of external memory. The BCM5701
4095d67482SBill Paul  * is apparently not designed to use external SSRAM. The mappings
4195d67482SBill Paul  * up to the first 4 send rings are the same for both internal and
4295d67482SBill Paul  * external memory configurations. Note that mini RX ring space is
4395d67482SBill Paul  * only available with external SSRAM configurations, which means
4495d67482SBill Paul  * the mini RX ring is not supported on the BCM5701.
4595d67482SBill Paul  *
4695d67482SBill Paul  * The NIC's memory can be accessed by the host in one of 3 ways:
4795d67482SBill Paul  *
4895d67482SBill Paul  * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
4995d67482SBill Paul  *    registers in PCI config space can be used to read any 32-bit
5095d67482SBill Paul  *    address within the NIC's memory.
5195d67482SBill Paul  *
5295d67482SBill Paul  * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
5395d67482SBill Paul  *    space can be used in conjunction with the memory window in the
5495d67482SBill Paul  *    device register space at offset 0x8000 to read any 32K chunk
5595d67482SBill Paul  *    of NIC memory.
5695d67482SBill Paul  *
5795d67482SBill Paul  * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
5895d67482SBill Paul  *    set, the device I/O mapping consumes 32MB of host address space,
5995d67482SBill Paul  *    allowing all of the registers and internal NIC memory to be
6095d67482SBill Paul  *    accessed directly. NIC memory addresses are offset by 0x01000000.
6195d67482SBill Paul  *    Flat mode consumes so much host address space that it is not
6295d67482SBill Paul  *    recommended.
6395d67482SBill Paul  */
6495d67482SBill Paul #define	BGE_PAGE_ZERO			0x00000000
6595d67482SBill Paul #define	BGE_PAGE_ZERO_END		0x000000FF
6695d67482SBill Paul #define	BGE_SEND_RING_RCB		0x00000100
6795d67482SBill Paul #define	BGE_SEND_RING_RCB_END		0x000001FF
6895d67482SBill Paul #define	BGE_RX_RETURN_RING_RCB		0x00000200
6995d67482SBill Paul #define	BGE_RX_RETURN_RING_RCB_END	0x000002FF
7095d67482SBill Paul #define	BGE_STATS_BLOCK			0x00000300
7195d67482SBill Paul #define	BGE_STATS_BLOCK_END		0x00000AFF
7295d67482SBill Paul #define	BGE_STATUS_BLOCK		0x00000B00
7395d67482SBill Paul #define	BGE_STATUS_BLOCK_END		0x00000B4F
7495d67482SBill Paul #define	BGE_SOFTWARE_GENCOMM		0x00000B50
7541abcc1bSPaul Saab #define	BGE_SOFTWARE_GENCOMM_SIG	0x00000B54
7641abcc1bSPaul Saab #define	BGE_SOFTWARE_GENCOMM_NICCFG	0x00000B58
778cb1383cSDoug Ambrisko #define	BGE_SOFTWARE_GENCOMM_FW		0x00000B78
788cb1383cSDoug Ambrisko #define	BGE_SOFTWARE_GENNCOMM_FW_LEN	0x00000B7C
798cb1383cSDoug Ambrisko #define	BGE_SOFTWARE_GENNCOMM_FW_DATA	0x00000B80
8095d67482SBill Paul #define	BGE_SOFTWARE_GENCOMM_END	0x00000FFF
8195d67482SBill Paul #define	BGE_UNMAPPED			0x00001000
8295d67482SBill Paul #define	BGE_UNMAPPED_END		0x00001FFF
8395d67482SBill Paul #define	BGE_DMA_DESCRIPTORS		0x00002000
8495d67482SBill Paul #define	BGE_DMA_DESCRIPTORS_END		0x00003FFF
8595d67482SBill Paul #define	BGE_SEND_RING_1_TO_4		0x00004000
8695d67482SBill Paul #define	BGE_SEND_RING_1_TO_4_END	0x00005FFF
8795d67482SBill Paul 
88797b2220SJung-uk Kim /* Firmware interface */
89797b2220SJung-uk Kim #define	BGE_FW_DRV_ALIVE		0x00000001
90797b2220SJung-uk Kim #define	BGE_FW_PAUSE			0x00000002
91797b2220SJung-uk Kim 
9295d67482SBill Paul /* Mappings for internal memory configuration */
9395d67482SBill Paul #define	BGE_STD_RX_RINGS		0x00006000
9495d67482SBill Paul #define	BGE_STD_RX_RINGS_END		0x00006FFF
9595d67482SBill Paul #define	BGE_JUMBO_RX_RINGS		0x00007000
9695d67482SBill Paul #define	BGE_JUMBO_RX_RINGS_END		0x00007FFF
9795d67482SBill Paul #define	BGE_BUFFPOOL_1			0x00008000
9895d67482SBill Paul #define	BGE_BUFFPOOL_1_END		0x0000FFFF
9995d67482SBill Paul #define	BGE_BUFFPOOL_2			0x00010000 /* or expansion ROM */
10095d67482SBill Paul #define	BGE_BUFFPOOL_2_END		0x00017FFF
10195d67482SBill Paul #define	BGE_BUFFPOOL_3			0x00018000 /* or expansion ROM */
10295d67482SBill Paul #define	BGE_BUFFPOOL_3_END		0x0001FFFF
10395d67482SBill Paul 
10495d67482SBill Paul /* Mappings for external SSRAM configurations */
10595d67482SBill Paul #define	BGE_SEND_RING_5_TO_6		0x00006000
10695d67482SBill Paul #define	BGE_SEND_RING_5_TO_6_END	0x00006FFF
10795d67482SBill Paul #define	BGE_SEND_RING_7_TO_8		0x00007000
10895d67482SBill Paul #define	BGE_SEND_RING_7_TO_8_END	0x00007FFF
10995d67482SBill Paul #define	BGE_SEND_RING_9_TO_16		0x00008000
11095d67482SBill Paul #define	BGE_SEND_RING_9_TO_16_END	0x0000BFFF
11195d67482SBill Paul #define	BGE_EXT_STD_RX_RINGS		0x0000C000
11295d67482SBill Paul #define	BGE_EXT_STD_RX_RINGS_END	0x0000CFFF
11395d67482SBill Paul #define	BGE_EXT_JUMBO_RX_RINGS		0x0000D000
11495d67482SBill Paul #define	BGE_EXT_JUMBO_RX_RINGS_END	0x0000DFFF
11595d67482SBill Paul #define	BGE_MINI_RX_RINGS		0x0000E000
11695d67482SBill Paul #define	BGE_MINI_RX_RINGS_END		0x0000FFFF
11795d67482SBill Paul #define	BGE_AVAIL_REGION1		0x00010000 /* or expansion ROM */
11895d67482SBill Paul #define	BGE_AVAIL_REGION1_END		0x00017FFF
11995d67482SBill Paul #define	BGE_AVAIL_REGION2		0x00018000 /* or expansion ROM */
12095d67482SBill Paul #define	BGE_AVAIL_REGION2_END		0x0001FFFF
12195d67482SBill Paul #define	BGE_EXT_SSRAM			0x00020000
12295d67482SBill Paul #define	BGE_EXT_SSRAM_END		0x000FFFFF
12395d67482SBill Paul 
12495d67482SBill Paul 
12595d67482SBill Paul /*
12695d67482SBill Paul  * BCM570x register offsets. These are memory mapped registers
12795d67482SBill Paul  * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
12895d67482SBill Paul  * Each register must be accessed using 32 bit operations.
12995d67482SBill Paul  *
13095d67482SBill Paul  * All registers are accessed through a 32K shared memory block.
13195d67482SBill Paul  * The first group of registers are actually copies of the PCI
13295d67482SBill Paul  * configuration space registers.
13395d67482SBill Paul  */
13495d67482SBill Paul 
13595d67482SBill Paul /*
13695d67482SBill Paul  * PCI registers defined in the PCI 2.2 spec.
13795d67482SBill Paul  */
13895d67482SBill Paul #define	BGE_PCI_VID			0x00
13995d67482SBill Paul #define	BGE_PCI_DID			0x02
14095d67482SBill Paul #define	BGE_PCI_CMD			0x04
14195d67482SBill Paul #define	BGE_PCI_STS			0x06
14295d67482SBill Paul #define	BGE_PCI_REV			0x08
14395d67482SBill Paul #define	BGE_PCI_CLASS			0x09
14495d67482SBill Paul #define	BGE_PCI_CACHESZ			0x0C
14595d67482SBill Paul #define	BGE_PCI_LATTIMER		0x0D
14695d67482SBill Paul #define	BGE_PCI_HDRTYPE			0x0E
14795d67482SBill Paul #define	BGE_PCI_BIST			0x0F
14895d67482SBill Paul #define	BGE_PCI_BAR0			0x10
14995d67482SBill Paul #define	BGE_PCI_BAR1			0x14
15095d67482SBill Paul #define	BGE_PCI_SUBSYS			0x2C
15195d67482SBill Paul #define	BGE_PCI_SUBVID			0x2E
15295d67482SBill Paul #define	BGE_PCI_ROMBASE			0x30
15395d67482SBill Paul #define	BGE_PCI_CAPPTR			0x34
15495d67482SBill Paul #define	BGE_PCI_INTLINE			0x3C
15595d67482SBill Paul #define	BGE_PCI_INTPIN			0x3D
15695d67482SBill Paul #define	BGE_PCI_MINGNT			0x3E
15795d67482SBill Paul #define	BGE_PCI_MAXLAT			0x3F
15895d67482SBill Paul #define	BGE_PCI_PCIXCAP			0x40
15995d67482SBill Paul #define	BGE_PCI_NEXTPTR_PM		0x41
16095d67482SBill Paul #define	BGE_PCI_PCIX_CMD		0x42
16195d67482SBill Paul #define	BGE_PCI_PCIX_STS		0x44
16295d67482SBill Paul #define	BGE_PCI_PWRMGMT_CAPID		0x48
16395d67482SBill Paul #define	BGE_PCI_NEXTPTR_VPD		0x49
16495d67482SBill Paul #define	BGE_PCI_PWRMGMT_CAPS		0x4A
16595d67482SBill Paul #define	BGE_PCI_PWRMGMT_CMD		0x4C
16695d67482SBill Paul #define	BGE_PCI_PWRMGMT_STS		0x4D
16795d67482SBill Paul #define	BGE_PCI_PWRMGMT_DATA		0x4F
16895d67482SBill Paul #define	BGE_PCI_VPD_CAPID		0x50
16995d67482SBill Paul #define	BGE_PCI_NEXTPTR_MSI		0x51
17095d67482SBill Paul #define	BGE_PCI_VPD_ADDR		0x52
17195d67482SBill Paul #define	BGE_PCI_VPD_DATA		0x54
17295d67482SBill Paul #define	BGE_PCI_MSI_CAPID		0x58
17395d67482SBill Paul #define	BGE_PCI_NEXTPTR_NONE		0x59
17495d67482SBill Paul #define	BGE_PCI_MSI_CTL			0x5A
17595d67482SBill Paul #define	BGE_PCI_MSI_ADDR_HI		0x5C
17695d67482SBill Paul #define	BGE_PCI_MSI_ADDR_LO		0x60
17795d67482SBill Paul #define	BGE_PCI_MSI_DATA		0x64
17895d67482SBill Paul 
1794f09c4c7SMarius Strobl /*
1804f09c4c7SMarius Strobl  * PCI Express definitions
1814f09c4c7SMarius Strobl  * According to
1824f09c4c7SMarius Strobl  * PCI Express base specification, REV. 1.0a
1834f09c4c7SMarius Strobl  */
1844f09c4c7SMarius Strobl 
1854f09c4c7SMarius Strobl /* PCI Express device control, 16bits */
1864f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL			0x08
1874f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_MASK	0x7000
1884f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_128	0x0000
1894f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_256	0x1000
1904f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_512	0x2000
1914f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_1024	0x3000
1924f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_2048	0x4000
1934f09c4c7SMarius Strobl #define	BGE_PCIE_DEVCTL_MAX_READRQ_4096	0x5000
1944f09c4c7SMarius Strobl 
195e53d81eeSPaul Saab /* PCI MSI. ??? */
196e53d81eeSPaul Saab #define	BGE_PCIE_CAPID_REG		0xD0
197e53d81eeSPaul Saab #define	BGE_PCIE_CAPID			0x10
198e53d81eeSPaul Saab 
19995d67482SBill Paul /*
20095d67482SBill Paul  * PCI registers specific to the BCM570x family.
20195d67482SBill Paul  */
20295d67482SBill Paul #define	BGE_PCI_MISC_CTL		0x68
20395d67482SBill Paul #define	BGE_PCI_DMA_RW_CTL		0x6C
20495d67482SBill Paul #define	BGE_PCI_PCISTATE		0x70
20595d67482SBill Paul #define	BGE_PCI_CLKCTL			0x74
20695d67482SBill Paul #define	BGE_PCI_REG_BASEADDR		0x78
20795d67482SBill Paul #define	BGE_PCI_MEMWIN_BASEADDR		0x7C
20895d67482SBill Paul #define	BGE_PCI_REG_DATA		0x80
20995d67482SBill Paul #define	BGE_PCI_MEMWIN_DATA		0x84
21095d67482SBill Paul #define	BGE_PCI_MODECTL			0x88
21195d67482SBill Paul #define	BGE_PCI_MISC_CFG		0x8C
21295d67482SBill Paul #define	BGE_PCI_MISC_LOCALCTL		0x90
21395d67482SBill Paul #define	BGE_PCI_UNDI_RX_STD_PRODIDX_HI	0x98
21495d67482SBill Paul #define	BGE_PCI_UNDI_RX_STD_PRODIDX_LO	0x9C
21595d67482SBill Paul #define	BGE_PCI_UNDI_RX_RTN_CONSIDX_HI	0xA0
21695d67482SBill Paul #define	BGE_PCI_UNDI_RX_RTN_CONSIDX_LO	0xA4
21795d67482SBill Paul #define	BGE_PCI_UNDI_TX_BD_PRODIDX_HI	0xA8
21895d67482SBill Paul #define	BGE_PCI_UNDI_TX_BD_PRODIDX_LO	0xAC
21995d67482SBill Paul #define	BGE_PCI_ISR_MBX_HI		0xB0
22095d67482SBill Paul #define	BGE_PCI_ISR_MBX_LO		0xB4
221a5779553SStanislav Sedov #define	BGE_PCI_PRODID_ASICREV		0xBC
22295d67482SBill Paul 
22395d67482SBill Paul /* PCI Misc. Host control register */
22495d67482SBill Paul #define	BGE_PCIMISCCTL_CLEAR_INTA	0x00000001
22595d67482SBill Paul #define	BGE_PCIMISCCTL_MASK_PCI_INTR	0x00000002
22695d67482SBill Paul #define	BGE_PCIMISCCTL_ENDIAN_BYTESWAP	0x00000004
22795d67482SBill Paul #define	BGE_PCIMISCCTL_ENDIAN_WORDSWAP	0x00000008
22895d67482SBill Paul #define	BGE_PCIMISCCTL_PCISTATE_RW	0x00000010
22995d67482SBill Paul #define	BGE_PCIMISCCTL_CLOCKCTL_RW	0x00000020
23095d67482SBill Paul #define	BGE_PCIMISCCTL_REG_WORDSWAP	0x00000040
23195d67482SBill Paul #define	BGE_PCIMISCCTL_INDIRECT_ACCESS	0x00000080
23295d67482SBill Paul #define	BGE_PCIMISCCTL_ASICREV		0xFFFF0000
233a5779553SStanislav Sedov #define	BGE_PCIMISCCTL_ASICREV_SHIFT	16
23495d67482SBill Paul 
235e907febfSPyun YongHyeon #define	BGE_HIF_SWAP_OPTIONS	(BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
236e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
237e907febfSPyun YongHyeon #define	BGE_DMA_SWAP_OPTIONS \
238e907febfSPyun YongHyeon 	BGE_MODECTL_WORDSWAP_NONFRAME| \
239e907febfSPyun YongHyeon 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
240e907febfSPyun YongHyeon #else
241e907febfSPyun YongHyeon #define	BGE_DMA_SWAP_OPTIONS \
242e907febfSPyun YongHyeon 	BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
243e907febfSPyun YongHyeon 	BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
244e907febfSPyun YongHyeon #endif
24595d67482SBill Paul 
246e907febfSPyun YongHyeon #define	BGE_INIT \
247e907febfSPyun YongHyeon 	(BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
248e907febfSPyun YongHyeon 	 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
24995d67482SBill Paul 
250a5779553SStanislav Sedov #define	BGE_CHIPID_TIGON_I		0x4000
251a5779553SStanislav Sedov #define	BGE_CHIPID_TIGON_II		0x6000
252a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_A0		0x7000
253a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_A1		0x7001
254a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_B0		0x7100
255a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_B1		0x7101
256a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_B2		0x7102
257a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_B3		0x7103
258a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_ALTIMA	0x7104
259a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5700_C0		0x7200
260a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5701_A0		0x0000	/* grrrr */
261a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5701_B0		0x0100
262a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5701_B2		0x0102
263a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5701_B5		0x0105
264a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5703_A0		0x1000
265a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5703_A1		0x1001
266a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5703_A2		0x1002
267a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5703_A3		0x1003
268a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5703_B0		0x1100
269a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5704_A0		0x2000
270a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5704_A1		0x2001
271a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5704_A2		0x2002
272a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5704_A3		0x2003
273a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5704_B0		0x2100
274a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5705_A0		0x3000
275a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5705_A1		0x3001
276a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5705_A2		0x3002
277a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5705_A3		0x3003
278a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_A0		0x4000
279a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_A1		0x4001
280a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_A3		0x4000
281a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_B0		0x4100
282a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_B1		0x4101
283a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_C0		0x4200
284a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_C1		0x4201
285a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5750_C2		0x4202
286a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5714_A0		0x5000
287a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5752_A0		0x6000
288a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5752_A1		0x6001
289a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5752_A2		0x6002
290a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5714_B0		0x8000
291a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5714_B3		0x8003
292a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5715_A0		0x9000
293a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5715_A1		0x9001
294a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5715_A3		0x9003
295a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5755_A0		0xa000
296a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5755_A1		0xa001
297a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5755_A2		0xa002
298a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5722_A0		0xa200
299a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5754_A0		0xb000
300a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5754_A1		0xb001
301a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5754_A2		0xb002
302a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5761_A0		0x5761000
303a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5761_A1		0x5761100
304a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5784_A0		0x5784000
305a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5784_A1		0x5784100
306a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5787_A0		0xb000
307a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5787_A1		0xb001
308a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5787_A2		0xb002
309a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5906_A1		0xc001
310a5779553SStanislav Sedov #define	BGE_CHIPID_BCM5906_A2		0xc002
311a5779553SStanislav Sedov #define	BGE_CHIPID_BCM57780_A0		0x57780000
312a5779553SStanislav Sedov #define	BGE_CHIPID_BCM57780_A1		0x57780001
31395d67482SBill Paul 
314a1d52896SBill Paul /* shorthand one */
315a5779553SStanislav Sedov #define	BGE_ASICREV(x)			((x) >> 12)
3165cba12d3SPaul Saab #define	BGE_ASICREV_BCM5701		0x00
3175cba12d3SPaul Saab #define	BGE_ASICREV_BCM5703		0x01
3185cba12d3SPaul Saab #define	BGE_ASICREV_BCM5704		0x02
3190434d1b8SBill Paul #define	BGE_ASICREV_BCM5705		0x03
320e53d81eeSPaul Saab #define	BGE_ASICREV_BCM5750		0x04
3214c0da0ffSGleb Smirnoff #define	BGE_ASICREV_BCM5714_A0		0x05
322560c1670SGleb Smirnoff #define	BGE_ASICREV_BCM5752		0x06
3234c0da0ffSGleb Smirnoff #define	BGE_ASICREV_BCM5700		0x07
3244c0da0ffSGleb Smirnoff #define	BGE_ASICREV_BCM5780		0x08
3254c0da0ffSGleb Smirnoff #define	BGE_ASICREV_BCM5714		0x09
3269e86676bSGleb Smirnoff #define	BGE_ASICREV_BCM5755		0x0a
3276f8718a3SScott Long #define	BGE_ASICREV_BCM5754		0x0b
3289e86676bSGleb Smirnoff #define	BGE_ASICREV_BCM5787		0x0b
32938cc658fSJohn Baldwin #define	BGE_ASICREV_BCM5906		0x0c
330a5779553SStanislav Sedov /* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
331a5779553SStanislav Sedov #define	BGE_ASICREV_USE_PRODID_REG	0x0f
332a5779553SStanislav Sedov /* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
333a5779553SStanislav Sedov #define	BGE_ASICREV_BCM5761		0x5761
334a5779553SStanislav Sedov #define	BGE_ASICREV_BCM5784		0x5784
335a5779553SStanislav Sedov #define	BGE_ASICREV_BCM5785		0x5785
336a5779553SStanislav Sedov #define	BGE_ASICREV_BCM57780		0x57780
337a1d52896SBill Paul 
338e0ced696SPaul Saab /* chip revisions */
339a5779553SStanislav Sedov #define	BGE_CHIPREV(x)			((x) >> 8)
340e0ced696SPaul Saab #define	BGE_CHIPREV_5700_AX		0x70
341e0ced696SPaul Saab #define	BGE_CHIPREV_5700_BX		0x71
342e0ced696SPaul Saab #define	BGE_CHIPREV_5700_CX		0x72
343e0ced696SPaul Saab #define	BGE_CHIPREV_5701_AX		0x00
3445ee49a3aSJung-uk Kim #define	BGE_CHIPREV_5703_AX		0x10
3455ee49a3aSJung-uk Kim #define	BGE_CHIPREV_5704_AX		0x20
3465ee49a3aSJung-uk Kim #define	BGE_CHIPREV_5704_BX		0x21
347bf6ef57aSJohn Polstra #define	BGE_CHIPREV_5750_AX		0x40
348bf6ef57aSJohn Polstra #define	BGE_CHIPREV_5750_BX		0x41
349a5779553SStanislav Sedov /* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
350a5779553SStanislav Sedov #define	BGE_CHIPREV_5761_AX		0x57611
351a5779553SStanislav Sedov #define	BGE_CHIPREV_5784_AX		0x57841
352e0ced696SPaul Saab 
35395d67482SBill Paul /* PCI DMA Read/Write Control register */
35495d67482SBill Paul #define	BGE_PCIDMARWCTL_MINDMA		0x000000FF
35595d67482SBill Paul #define	BGE_PCIDMARWCTL_RDADRR_BNDRY	0x00000700
35695d67482SBill Paul #define	BGE_PCIDMARWCTL_WRADDR_BNDRY	0x00003800
357186f842bSJung-uk Kim #define	BGE_PCIDMARWCTL_ONEDMA_ATONCE	0x0000C000
358186f842bSJung-uk Kim #define	BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL	0x00004000
359186f842bSJung-uk Kim #define	BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL	0x00008000
36095d67482SBill Paul #define	BGE_PCIDMARWCTL_RD_WAT		0x00070000
36195d67482SBill Paul #define	BGE_PCIDMARWCTL_WR_WAT		0x00380000
36295d67482SBill Paul #define	BGE_PCIDMARWCTL_USE_MRM		0x00400000
36395d67482SBill Paul #define	BGE_PCIDMARWCTL_ASRT_ALL_BE	0x00800000
36495d67482SBill Paul #define	BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD	0x0F000000
36595d67482SBill Paul #define	BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD	0xF0000000
366797b2220SJung-uk Kim 
367797b2220SJung-uk Kim #define	BGE_PCIDMARWCTL_RD_WAT_SHIFT(x)	((x) << 16)
368797b2220SJung-uk Kim #define	BGE_PCIDMARWCTL_WR_WAT_SHIFT(x)	((x) << 19)
369797b2220SJung-uk Kim #define	BGE_PCIDMARWCTL_RD_CMD_SHIFT(x)	((x) << 24)
370797b2220SJung-uk Kim #define	BGE_PCIDMARWCTL_WR_CMD_SHIFT(x)	((x) << 28)
37195d67482SBill Paul 
37295d67482SBill Paul #define	BGE_PCI_READ_BNDRY_DISABLE	0x00000000
37395d67482SBill Paul #define	BGE_PCI_READ_BNDRY_16BYTES	0x00000100
37495d67482SBill Paul #define	BGE_PCI_READ_BNDRY_32BYTES	0x00000200
37595d67482SBill Paul #define	BGE_PCI_READ_BNDRY_64BYTES	0x00000300
37695d67482SBill Paul #define	BGE_PCI_READ_BNDRY_128BYTES	0x00000400
37795d67482SBill Paul #define	BGE_PCI_READ_BNDRY_256BYTES	0x00000500
37895d67482SBill Paul #define	BGE_PCI_READ_BNDRY_512BYTES	0x00000600
37995d67482SBill Paul #define	BGE_PCI_READ_BNDRY_1024BYTES	0x00000700
38095d67482SBill Paul 
38195d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_DISABLE	0x00000000
38295d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_16BYTES	0x00000800
38395d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_32BYTES	0x00001000
38495d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_64BYTES	0x00001800
38595d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_128BYTES	0x00002000
38695d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_256BYTES	0x00002800
38795d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_512BYTES	0x00003000
38895d67482SBill Paul #define	BGE_PCI_WRITE_BNDRY_1024BYTES	0x00003800
38995d67482SBill Paul 
39095d67482SBill Paul /*
39195d67482SBill Paul  * PCI state register -- note, this register is read only
39295d67482SBill Paul  * unless the PCISTATE_WR bit of the PCI Misc. Host Control
39395d67482SBill Paul  * register is set.
39495d67482SBill Paul  */
39595d67482SBill Paul #define	BGE_PCISTATE_FORCE_RESET	0x00000001
39695d67482SBill Paul #define	BGE_PCISTATE_INTR_STATE		0x00000002
39795d67482SBill Paul #define	BGE_PCISTATE_PCI_BUSMODE	0x00000004 /* 1 = PCI, 0 = PCI-X */
3980fb18ca8SJohn Polstra #define	BGE_PCISTATE_PCI_BUSSPEED	0x00000008 /* 1 = 66/133, 0 = 33/66 */
39995d67482SBill Paul #define	BGE_PCISTATE_32BIT_BUS		0x00000010 /* 1 = 32bit, 0 = 64bit */
40095d67482SBill Paul #define	BGE_PCISTATE_WANT_EXPROM	0x00000020
40195d67482SBill Paul #define	BGE_PCISTATE_EXPROM_RETRY	0x00000040
40295d67482SBill Paul #define	BGE_PCISTATE_FLATVIEW_MODE	0x00000100
40395d67482SBill Paul #define	BGE_PCISTATE_PCI_TGT_RETRY_MAX	0x00000E00
40495d67482SBill Paul 
40595d67482SBill Paul /*
40695d67482SBill Paul  * PCI Clock Control register -- note, this register is read only
40795d67482SBill Paul  * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
40895d67482SBill Paul  * register is set.
40995d67482SBill Paul  */
41095d67482SBill Paul #define	BGE_PCICLOCKCTL_DETECTED_SPEED	0x0000000F
41195d67482SBill Paul #define	BGE_PCICLOCKCTL_M66EN		0x00000080
41295d67482SBill Paul #define	BGE_PCICLOCKCTL_LOWPWR_CLKMODE	0x00000200
41395d67482SBill Paul #define	BGE_PCICLOCKCTL_RXCPU_CLK_DIS	0x00000400
41495d67482SBill Paul #define	BGE_PCICLOCKCTL_TXCPU_CLK_DIS	0x00000800
41595d67482SBill Paul #define	BGE_PCICLOCKCTL_ALTCLK		0x00001000
41695d67482SBill Paul #define	BGE_PCICLOCKCTL_ALTCLK_SRC	0x00002000
41795d67482SBill Paul #define	BGE_PCICLOCKCTL_PCIPLL_DISABLE	0x00004000
41895d67482SBill Paul #define	BGE_PCICLOCKCTL_SYSPLL_DISABLE	0x00008000
41995d67482SBill Paul #define	BGE_PCICLOCKCTL_BIST_ENABLE	0x00010000
42095d67482SBill Paul 
42195d67482SBill Paul 
42295d67482SBill Paul #ifndef PCIM_CMD_MWIEN
42395d67482SBill Paul #define	PCIM_CMD_MWIEN			0x0010
42495d67482SBill Paul #endif
425c9ffd9f0SMarius Strobl #ifndef PCIM_CMD_INTxDIS
426c9ffd9f0SMarius Strobl #define	PCIM_CMD_INTxDIS		0x0400
427c9ffd9f0SMarius Strobl #endif
42895d67482SBill Paul 
42995d67482SBill Paul /*
43095d67482SBill Paul  * High priority mailbox registers
43195d67482SBill Paul  * Each mailbox is 64-bits wide, though we only use the
43295d67482SBill Paul  * lower 32 bits. To write a 64-bit value, write the upper 32 bits
43395d67482SBill Paul  * first. The NIC will load the mailbox after the lower 32 bit word
43495d67482SBill Paul  * has been updated.
43595d67482SBill Paul  */
43695d67482SBill Paul #define	BGE_MBX_IRQ0_HI			0x0200
43795d67482SBill Paul #define	BGE_MBX_IRQ0_LO			0x0204
43895d67482SBill Paul #define	BGE_MBX_IRQ1_HI			0x0208
43995d67482SBill Paul #define	BGE_MBX_IRQ1_LO			0x020C
44095d67482SBill Paul #define	BGE_MBX_IRQ2_HI			0x0210
44195d67482SBill Paul #define	BGE_MBX_IRQ2_LO			0x0214
44295d67482SBill Paul #define	BGE_MBX_IRQ3_HI			0x0218
44395d67482SBill Paul #define	BGE_MBX_IRQ3_LO			0x021C
44495d67482SBill Paul #define	BGE_MBX_GEN0_HI			0x0220
44595d67482SBill Paul #define	BGE_MBX_GEN0_LO			0x0224
44695d67482SBill Paul #define	BGE_MBX_GEN1_HI			0x0228
44795d67482SBill Paul #define	BGE_MBX_GEN1_LO			0x022C
44895d67482SBill Paul #define	BGE_MBX_GEN2_HI			0x0230
44995d67482SBill Paul #define	BGE_MBX_GEN2_LO			0x0234
45095d67482SBill Paul #define	BGE_MBX_GEN3_HI			0x0228
45195d67482SBill Paul #define	BGE_MBX_GEN3_LO			0x022C
45295d67482SBill Paul #define	BGE_MBX_GEN4_HI			0x0240
45395d67482SBill Paul #define	BGE_MBX_GEN4_LO			0x0244
45495d67482SBill Paul #define	BGE_MBX_GEN5_HI			0x0248
45595d67482SBill Paul #define	BGE_MBX_GEN5_LO			0x024C
45695d67482SBill Paul #define	BGE_MBX_GEN6_HI			0x0250
45795d67482SBill Paul #define	BGE_MBX_GEN6_LO			0x0254
45895d67482SBill Paul #define	BGE_MBX_GEN7_HI			0x0258
45995d67482SBill Paul #define	BGE_MBX_GEN7_LO			0x025C
46095d67482SBill Paul #define	BGE_MBX_RELOAD_STATS_HI		0x0260
46195d67482SBill Paul #define	BGE_MBX_RELOAD_STATS_LO		0x0264
46295d67482SBill Paul #define	BGE_MBX_RX_STD_PROD_HI		0x0268
46395d67482SBill Paul #define	BGE_MBX_RX_STD_PROD_LO		0x026C
46495d67482SBill Paul #define	BGE_MBX_RX_JUMBO_PROD_HI	0x0270
46595d67482SBill Paul #define	BGE_MBX_RX_JUMBO_PROD_LO	0x0274
46695d67482SBill Paul #define	BGE_MBX_RX_MINI_PROD_HI		0x0278
46795d67482SBill Paul #define	BGE_MBX_RX_MINI_PROD_LO		0x027C
46895d67482SBill Paul #define	BGE_MBX_RX_CONS0_HI		0x0280
46995d67482SBill Paul #define	BGE_MBX_RX_CONS0_LO		0x0284
47095d67482SBill Paul #define	BGE_MBX_RX_CONS1_HI		0x0288
47195d67482SBill Paul #define	BGE_MBX_RX_CONS1_LO		0x028C
47295d67482SBill Paul #define	BGE_MBX_RX_CONS2_HI		0x0290
47395d67482SBill Paul #define	BGE_MBX_RX_CONS2_LO		0x0294
47495d67482SBill Paul #define	BGE_MBX_RX_CONS3_HI		0x0298
47595d67482SBill Paul #define	BGE_MBX_RX_CONS3_LO		0x029C
47695d67482SBill Paul #define	BGE_MBX_RX_CONS4_HI		0x02A0
47795d67482SBill Paul #define	BGE_MBX_RX_CONS4_LO		0x02A4
47895d67482SBill Paul #define	BGE_MBX_RX_CONS5_HI		0x02A8
47995d67482SBill Paul #define	BGE_MBX_RX_CONS5_LO		0x02AC
48095d67482SBill Paul #define	BGE_MBX_RX_CONS6_HI		0x02B0
48195d67482SBill Paul #define	BGE_MBX_RX_CONS6_LO		0x02B4
48295d67482SBill Paul #define	BGE_MBX_RX_CONS7_HI		0x02B8
48395d67482SBill Paul #define	BGE_MBX_RX_CONS7_LO		0x02BC
48495d67482SBill Paul #define	BGE_MBX_RX_CONS8_HI		0x02C0
48595d67482SBill Paul #define	BGE_MBX_RX_CONS8_LO		0x02C4
48695d67482SBill Paul #define	BGE_MBX_RX_CONS9_HI		0x02C8
48795d67482SBill Paul #define	BGE_MBX_RX_CONS9_LO		0x02CC
48895d67482SBill Paul #define	BGE_MBX_RX_CONS10_HI		0x02D0
48995d67482SBill Paul #define	BGE_MBX_RX_CONS10_LO		0x02D4
49095d67482SBill Paul #define	BGE_MBX_RX_CONS11_HI		0x02D8
49195d67482SBill Paul #define	BGE_MBX_RX_CONS11_LO		0x02DC
49295d67482SBill Paul #define	BGE_MBX_RX_CONS12_HI		0x02E0
49395d67482SBill Paul #define	BGE_MBX_RX_CONS12_LO		0x02E4
49495d67482SBill Paul #define	BGE_MBX_RX_CONS13_HI		0x02E8
49595d67482SBill Paul #define	BGE_MBX_RX_CONS13_LO		0x02EC
49695d67482SBill Paul #define	BGE_MBX_RX_CONS14_HI		0x02F0
49795d67482SBill Paul #define	BGE_MBX_RX_CONS14_LO		0x02F4
49895d67482SBill Paul #define	BGE_MBX_RX_CONS15_HI		0x02F8
49995d67482SBill Paul #define	BGE_MBX_RX_CONS15_LO		0x02FC
50095d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD0_HI	0x0300
50195d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD0_LO	0x0304
50295d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD1_HI	0x0308
50395d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD1_LO	0x030C
50495d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD2_HI	0x0310
50595d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD2_LO	0x0314
50695d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD3_HI	0x0318
50795d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD3_LO	0x031C
50895d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD4_HI	0x0320
50995d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD4_LO	0x0324
51095d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD5_HI	0x0328
51195d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD5_LO	0x032C
51295d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD6_HI	0x0330
51395d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD6_LO	0x0334
51495d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD7_HI	0x0338
51595d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD7_LO	0x033C
51695d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD8_HI	0x0340
51795d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD8_LO	0x0344
51895d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD9_HI	0x0348
51995d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD9_LO	0x034C
52095d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD10_HI	0x0350
52195d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD10_LO	0x0354
52295d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD11_HI	0x0358
52395d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD11_LO	0x035C
52495d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD12_HI	0x0360
52595d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD12_LO	0x0364
52695d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD13_HI	0x0368
52795d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD13_LO	0x036C
52895d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD14_HI	0x0370
52995d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD14_LO	0x0374
53095d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD15_HI	0x0378
53195d67482SBill Paul #define	BGE_MBX_TX_HOST_PROD15_LO	0x037C
53295d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD0_HI		0x0380
53395d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD0_LO		0x0384
53495d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD1_HI		0x0388
53595d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD1_LO		0x038C
53695d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD2_HI		0x0390
53795d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD2_LO		0x0394
53895d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD3_HI		0x0398
53995d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD3_LO		0x039C
54095d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD4_HI		0x03A0
54195d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD4_LO		0x03A4
54295d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD5_HI		0x03A8
54395d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD5_LO		0x03AC
54495d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD6_HI		0x03B0
54595d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD6_LO		0x03B4
54695d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD7_HI		0x03B8
54795d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD7_LO		0x03BC
54895d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD8_HI		0x03C0
54995d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD8_LO		0x03C4
55095d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD9_HI		0x03C8
55195d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD9_LO		0x03CC
55295d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD10_HI	0x03D0
55395d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD10_LO	0x03D4
55495d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD11_HI	0x03D8
55595d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD11_LO	0x03DC
55695d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD12_HI	0x03E0
55795d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD12_LO	0x03E4
55895d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD13_HI	0x03E8
55995d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD13_LO	0x03EC
56095d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD14_HI	0x03F0
56195d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD14_LO	0x03F4
56295d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD15_HI	0x03F8
56395d67482SBill Paul #define	BGE_MBX_TX_NIC_PROD15_LO	0x03FC
56495d67482SBill Paul 
56595d67482SBill Paul #define	BGE_TX_RINGS_MAX		4
56695d67482SBill Paul #define	BGE_TX_RINGS_EXTSSRAM_MAX	16
56795d67482SBill Paul #define	BGE_RX_RINGS_MAX		16
56895d67482SBill Paul 
56995d67482SBill Paul /* Ethernet MAC control registers */
57095d67482SBill Paul #define	BGE_MAC_MODE			0x0400
57195d67482SBill Paul #define	BGE_MAC_STS			0x0404
57295d67482SBill Paul #define	BGE_MAC_EVT_ENB			0x0408
57395d67482SBill Paul #define	BGE_MAC_LED_CTL			0x040C
57495d67482SBill Paul #define	BGE_MAC_ADDR1_LO		0x0410
57595d67482SBill Paul #define	BGE_MAC_ADDR1_HI		0x0414
57695d67482SBill Paul #define	BGE_MAC_ADDR2_LO		0x0418
57795d67482SBill Paul #define	BGE_MAC_ADDR2_HI		0x041C
57895d67482SBill Paul #define	BGE_MAC_ADDR3_LO		0x0420
57995d67482SBill Paul #define	BGE_MAC_ADDR3_HI		0x0424
58095d67482SBill Paul #define	BGE_MAC_ADDR4_LO		0x0428
58195d67482SBill Paul #define	BGE_MAC_ADDR4_HI		0x042C
58295d67482SBill Paul #define	BGE_WOL_PATPTR			0x0430
58395d67482SBill Paul #define	BGE_WOL_PATCFG			0x0434
58495d67482SBill Paul #define	BGE_TX_RANDOM_BACKOFF		0x0438
58595d67482SBill Paul #define	BGE_RX_MTU			0x043C
58695d67482SBill Paul #define	BGE_GBIT_PCS_TEST		0x0440
58795d67482SBill Paul #define	BGE_TX_TBI_AUTONEG		0x0444
58895d67482SBill Paul #define	BGE_RX_TBI_AUTONEG		0x0448
58995d67482SBill Paul #define	BGE_MI_COMM			0x044C
59095d67482SBill Paul #define	BGE_MI_STS			0x0450
59195d67482SBill Paul #define	BGE_MI_MODE			0x0454
59295d67482SBill Paul #define	BGE_AUTOPOLL_STS		0x0458
59395d67482SBill Paul #define	BGE_TX_MODE			0x045C
59495d67482SBill Paul #define	BGE_TX_STS			0x0460
59595d67482SBill Paul #define	BGE_TX_LENGTHS			0x0464
59695d67482SBill Paul #define	BGE_RX_MODE			0x0468
59795d67482SBill Paul #define	BGE_RX_STS			0x046C
59895d67482SBill Paul #define	BGE_MAR0			0x0470
59995d67482SBill Paul #define	BGE_MAR1			0x0474
60095d67482SBill Paul #define	BGE_MAR2			0x0478
60195d67482SBill Paul #define	BGE_MAR3			0x047C
60295d67482SBill Paul #define	BGE_RX_BD_RULES_CTL0		0x0480
60395d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL0	0x0484
60495d67482SBill Paul #define	BGE_RX_BD_RULES_CTL1		0x0488
60595d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL1	0x048C
60695d67482SBill Paul #define	BGE_RX_BD_RULES_CTL2		0x0490
60795d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL2	0x0494
60895d67482SBill Paul #define	BGE_RX_BD_RULES_CTL3		0x0498
60995d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL3	0x049C
61095d67482SBill Paul #define	BGE_RX_BD_RULES_CTL4		0x04A0
61195d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL4	0x04A4
61295d67482SBill Paul #define	BGE_RX_BD_RULES_CTL5		0x04A8
61395d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL5	0x04AC
61495d67482SBill Paul #define	BGE_RX_BD_RULES_CTL6		0x04B0
61595d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL6	0x04B4
61695d67482SBill Paul #define	BGE_RX_BD_RULES_CTL7		0x04B8
61795d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL7	0x04BC
61895d67482SBill Paul #define	BGE_RX_BD_RULES_CTL8		0x04C0
61995d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL8	0x04C4
62095d67482SBill Paul #define	BGE_RX_BD_RULES_CTL9		0x04C8
62195d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL9	0x04CC
62295d67482SBill Paul #define	BGE_RX_BD_RULES_CTL10		0x04D0
62395d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL10	0x04D4
62495d67482SBill Paul #define	BGE_RX_BD_RULES_CTL11		0x04D8
62595d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL11	0x04DC
62695d67482SBill Paul #define	BGE_RX_BD_RULES_CTL12		0x04E0
62795d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL12	0x04E4
62895d67482SBill Paul #define	BGE_RX_BD_RULES_CTL13		0x04E8
62995d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL13	0x04EC
63095d67482SBill Paul #define	BGE_RX_BD_RULES_CTL14		0x04F0
63195d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL14	0x04F4
63295d67482SBill Paul #define	BGE_RX_BD_RULES_CTL15		0x04F8
63395d67482SBill Paul #define	BGE_RX_BD_RULES_MASKVAL15	0x04FC
63495d67482SBill Paul #define	BGE_RX_RULES_CFG		0x0500
635da3003f0SBill Paul #define	BGE_SERDES_CFG			0x0590
636da3003f0SBill Paul #define	BGE_SERDES_STS			0x0594
637da3003f0SBill Paul #define	BGE_SGDIG_CFG			0x05B0
638da3003f0SBill Paul #define	BGE_SGDIG_STS			0x05B4
6397e6e2507SJung-uk Kim #define	BGE_MAC_STATS			0x0800
64095d67482SBill Paul 
64195d67482SBill Paul /* Ethernet MAC Mode register */
64295d67482SBill Paul #define	BGE_MACMODE_RESET		0x00000001
64395d67482SBill Paul #define	BGE_MACMODE_HALF_DUPLEX		0x00000002
64495d67482SBill Paul #define	BGE_MACMODE_PORTMODE		0x0000000C
64595d67482SBill Paul #define	BGE_MACMODE_LOOPBACK		0x00000010
64695d67482SBill Paul #define	BGE_MACMODE_RX_TAGGEDPKT	0x00000080
64795d67482SBill Paul #define	BGE_MACMODE_TX_BURST_ENB	0x00000100
64895d67482SBill Paul #define	BGE_MACMODE_MAX_DEFER		0x00000200
64995d67482SBill Paul #define	BGE_MACMODE_LINK_POLARITY	0x00000400
65095d67482SBill Paul #define	BGE_MACMODE_RX_STATS_ENB	0x00000800
65195d67482SBill Paul #define	BGE_MACMODE_RX_STATS_CLEAR	0x00001000
65295d67482SBill Paul #define	BGE_MACMODE_RX_STATS_FLUSH	0x00002000
65395d67482SBill Paul #define	BGE_MACMODE_TX_STATS_ENB	0x00004000
65495d67482SBill Paul #define	BGE_MACMODE_TX_STATS_CLEAR	0x00008000
65595d67482SBill Paul #define	BGE_MACMODE_TX_STATS_FLUSH	0x00010000
65695d67482SBill Paul #define	BGE_MACMODE_TBI_SEND_CFGS	0x00020000
65795d67482SBill Paul #define	BGE_MACMODE_MAGIC_PKT_ENB	0x00040000
65895d67482SBill Paul #define	BGE_MACMODE_ACPI_PWRON_ENB	0x00080000
65995d67482SBill Paul #define	BGE_MACMODE_MIP_ENB		0x00100000
66095d67482SBill Paul #define	BGE_MACMODE_TXDMA_ENB		0x00200000
66195d67482SBill Paul #define	BGE_MACMODE_RXDMA_ENB		0x00400000
66295d67482SBill Paul #define	BGE_MACMODE_FRMHDR_DMA_ENB	0x00800000
66395d67482SBill Paul 
66495d67482SBill Paul #define	BGE_PORTMODE_NONE		0x00000000
66595d67482SBill Paul #define	BGE_PORTMODE_MII		0x00000004
66695d67482SBill Paul #define	BGE_PORTMODE_GMII		0x00000008
66795d67482SBill Paul #define	BGE_PORTMODE_TBI		0x0000000C
66895d67482SBill Paul 
66995d67482SBill Paul /* MAC Status register */
67095d67482SBill Paul #define	BGE_MACSTAT_TBI_PCS_SYNCHED	0x00000001
67195d67482SBill Paul #define	BGE_MACSTAT_TBI_SIGNAL_DETECT	0x00000002
67295d67482SBill Paul #define	BGE_MACSTAT_RX_CFG		0x00000004
67395d67482SBill Paul #define	BGE_MACSTAT_CFG_CHANGED		0x00000008
67495d67482SBill Paul #define	BGE_MACSTAT_SYNC_CHANGED	0x00000010
67595d67482SBill Paul #define	BGE_MACSTAT_PORT_DECODE_ERROR	0x00000400
67695d67482SBill Paul #define	BGE_MACSTAT_LINK_CHANGED	0x00001000
67795d67482SBill Paul #define	BGE_MACSTAT_MI_COMPLETE		0x00400000
67895d67482SBill Paul #define	BGE_MACSTAT_MI_INTERRUPT	0x00800000
67995d67482SBill Paul #define	BGE_MACSTAT_AUTOPOLL_ERROR	0x01000000
68095d67482SBill Paul #define	BGE_MACSTAT_ODI_ERROR		0x02000000
68195d67482SBill Paul #define	BGE_MACSTAT_RXSTAT_OFLOW	0x04000000
68295d67482SBill Paul #define	BGE_MACSTAT_TXSTAT_OFLOW	0x08000000
68395d67482SBill Paul 
68495d67482SBill Paul /* MAC Event Enable Register */
68595d67482SBill Paul #define	BGE_EVTENB_PORT_DECODE_ERROR	0x00000400
68695d67482SBill Paul #define	BGE_EVTENB_LINK_CHANGED		0x00001000
68795d67482SBill Paul #define	BGE_EVTENB_MI_COMPLETE		0x00400000
68895d67482SBill Paul #define	BGE_EVTENB_MI_INTERRUPT		0x00800000
68995d67482SBill Paul #define	BGE_EVTENB_AUTOPOLL_ERROR	0x01000000
69095d67482SBill Paul #define	BGE_EVTENB_ODI_ERROR		0x02000000
69195d67482SBill Paul #define	BGE_EVTENB_RXSTAT_OFLOW		0x04000000
69295d67482SBill Paul #define	BGE_EVTENB_TXSTAT_OFLOW		0x08000000
69395d67482SBill Paul 
69495d67482SBill Paul /* LED Control Register */
69595d67482SBill Paul #define	BGE_LEDCTL_LINKLED_OVERRIDE	0x00000001
69695d67482SBill Paul #define	BGE_LEDCTL_1000MBPS_LED		0x00000002
69795d67482SBill Paul #define	BGE_LEDCTL_100MBPS_LED		0x00000004
69895d67482SBill Paul #define	BGE_LEDCTL_10MBPS_LED		0x00000008
69995d67482SBill Paul #define	BGE_LEDCTL_TRAFLED_OVERRIDE	0x00000010
70095d67482SBill Paul #define	BGE_LEDCTL_TRAFLED_BLINK	0x00000020
70195d67482SBill Paul #define	BGE_LEDCTL_TREFLED_BLINK_2	0x00000040
70295d67482SBill Paul #define	BGE_LEDCTL_1000MBPS_STS		0x00000080
70395d67482SBill Paul #define	BGE_LEDCTL_100MBPS_STS		0x00000100
70495d67482SBill Paul #define	BGE_LEDCTL_10MBPS_STS		0x00000200
70595d67482SBill Paul #define	BGE_LEDCTL_TRADLED_STS		0x00000400
70695d67482SBill Paul #define	BGE_LEDCTL_BLINKPERIOD		0x7FF80000
70795d67482SBill Paul #define	BGE_LEDCTL_BLINKPERIOD_OVERRIDE	0x80000000
70895d67482SBill Paul 
70995d67482SBill Paul /* TX backoff seed register */
71095d67482SBill Paul #define	BGE_TX_BACKOFF_SEED_MASK	0x3F
71195d67482SBill Paul 
71295d67482SBill Paul /* Autopoll status register */
71395d67482SBill Paul #define	BGE_AUTOPOLLSTS_ERROR		0x00000001
71495d67482SBill Paul 
71595d67482SBill Paul /* Transmit MAC mode register */
71695d67482SBill Paul #define	BGE_TXMODE_RESET		0x00000001
71795d67482SBill Paul #define	BGE_TXMODE_ENABLE		0x00000002
71895d67482SBill Paul #define	BGE_TXMODE_FLOWCTL_ENABLE	0x00000010
71995d67482SBill Paul #define	BGE_TXMODE_BIGBACKOFF_ENABLE	0x00000020
72095d67482SBill Paul #define	BGE_TXMODE_LONGPAUSE_ENABLE	0x00000040
72195d67482SBill Paul 
72295d67482SBill Paul /* Transmit MAC status register */
72395d67482SBill Paul #define	BGE_TXSTAT_RX_XOFFED		0x00000001
72495d67482SBill Paul #define	BGE_TXSTAT_SENT_XOFF		0x00000002
72595d67482SBill Paul #define	BGE_TXSTAT_SENT_XON		0x00000004
72695d67482SBill Paul #define	BGE_TXSTAT_LINK_UP		0x00000008
72795d67482SBill Paul #define	BGE_TXSTAT_ODI_UFLOW		0x00000010
72895d67482SBill Paul #define	BGE_TXSTAT_ODI_OFLOW		0x00000020
72995d67482SBill Paul 
73095d67482SBill Paul /* Transmit MAC lengths register */
73195d67482SBill Paul #define	BGE_TXLEN_SLOTTIME		0x000000FF
73295d67482SBill Paul #define	BGE_TXLEN_IPG			0x00000F00
73395d67482SBill Paul #define	BGE_TXLEN_CRS			0x00003000
73495d67482SBill Paul 
73595d67482SBill Paul /* Receive MAC mode register */
73695d67482SBill Paul #define	BGE_RXMODE_RESET		0x00000001
73795d67482SBill Paul #define	BGE_RXMODE_ENABLE		0x00000002
73895d67482SBill Paul #define	BGE_RXMODE_FLOWCTL_ENABLE	0x00000004
73995d67482SBill Paul #define	BGE_RXMODE_RX_GIANTS		0x00000020
74095d67482SBill Paul #define	BGE_RXMODE_RX_RUNTS		0x00000040
74195d67482SBill Paul #define	BGE_RXMODE_8022_LENCHECK	0x00000080
74295d67482SBill Paul #define	BGE_RXMODE_RX_PROMISC		0x00000100
74395d67482SBill Paul #define	BGE_RXMODE_RX_NO_CRC_CHECK	0x00000200
74495d67482SBill Paul #define	BGE_RXMODE_RX_KEEP_VLAN_DIAG	0x00000400
74595d67482SBill Paul 
74695d67482SBill Paul /* Receive MAC status register */
74795d67482SBill Paul #define	BGE_RXSTAT_REMOTE_XOFFED	0x00000001
74895d67482SBill Paul #define	BGE_RXSTAT_RCVD_XOFF		0x00000002
74995d67482SBill Paul #define	BGE_RXSTAT_RCVD_XON		0x00000004
75095d67482SBill Paul 
75195d67482SBill Paul /* Receive Rules Control register */
75295d67482SBill Paul #define	BGE_RXRULECTL_OFFSET		0x000000FF
75395d67482SBill Paul #define	BGE_RXRULECTL_CLASS		0x00001F00
75495d67482SBill Paul #define	BGE_RXRULECTL_HDRTYPE		0x0000E000
75595d67482SBill Paul #define	BGE_RXRULECTL_COMPARE_OP	0x00030000
75695d67482SBill Paul #define	BGE_RXRULECTL_MAP		0x01000000
75795d67482SBill Paul #define	BGE_RXRULECTL_DISCARD		0x02000000
75895d67482SBill Paul #define	BGE_RXRULECTL_MASK		0x04000000
75995d67482SBill Paul #define	BGE_RXRULECTL_ACTIVATE_PROC3	0x08000000
76095d67482SBill Paul #define	BGE_RXRULECTL_ACTIVATE_PROC2	0x10000000
76195d67482SBill Paul #define	BGE_RXRULECTL_ACTIVATE_PROC1	0x20000000
76295d67482SBill Paul #define	BGE_RXRULECTL_ANDWITHNEXT	0x40000000
76395d67482SBill Paul 
76495d67482SBill Paul /* Receive Rules Mask register */
76595d67482SBill Paul #define	BGE_RXRULEMASK_VALUE		0x0000FFFF
76695d67482SBill Paul #define	BGE_RXRULEMASK_MASKVAL		0xFFFF0000
76795d67482SBill Paul 
768da3003f0SBill Paul /* SERDES configuration register */
769da3003f0SBill Paul #define	BGE_SERDESCFG_RXR		0x00000007 /* phase interpolator */
770da3003f0SBill Paul #define	BGE_SERDESCFG_RXG		0x00000018 /* rx gain setting */
771da3003f0SBill Paul #define	BGE_SERDESCFG_RXEDGESEL		0x00000040 /* rising/falling egde */
772da3003f0SBill Paul #define	BGE_SERDESCFG_TX_BIAS		0x00000380 /* TXDAC bias setting */
773da3003f0SBill Paul #define	BGE_SERDESCFG_IBMAX		0x00000400 /* bias current +25% */
774da3003f0SBill Paul #define	BGE_SERDESCFG_IBMIN		0x00000800 /* bias current -25% */
775da3003f0SBill Paul #define	BGE_SERDESCFG_TXMODE		0x00001000
776da3003f0SBill Paul #define	BGE_SERDESCFG_TXEDGESEL		0x00002000 /* rising/falling edge */
777da3003f0SBill Paul #define	BGE_SERDESCFG_MODE		0x00004000 /* TXCP/TXCN disabled */
778da3003f0SBill Paul #define	BGE_SERDESCFG_PLLTEST		0x00008000 /* PLL test mode */
779da3003f0SBill Paul #define	BGE_SERDESCFG_CDET		0x00010000 /* comma detect enable */
780da3003f0SBill Paul #define	BGE_SERDESCFG_TBILOOP		0x00020000 /* local loopback */
781da3003f0SBill Paul #define	BGE_SERDESCFG_REMLOOP		0x00040000 /* remote loopback */
782da3003f0SBill Paul #define	BGE_SERDESCFG_INVPHASE		0x00080000 /* Reverse 125Mhz clock */
783da3003f0SBill Paul #define	BGE_SERDESCFG_12REGCTL		0x00300000 /* 1.2v regulator ctl */
784da3003f0SBill Paul #define	BGE_SERDESCFG_REGCTL		0x00C00000 /* regulator ctl (2.5v) */
785da3003f0SBill Paul 
786da3003f0SBill Paul /* SERDES status register */
787da3003f0SBill Paul #define	BGE_SERDESSTS_RXSTAT		0x0000000F /* receive status bits */
788da3003f0SBill Paul #define	BGE_SERDESSTS_CDET		0x00000010 /* comma code detected */
789da3003f0SBill Paul 
790da3003f0SBill Paul /* SGDIG config (not documented) */
791da3003f0SBill Paul #define	BGE_SGDIGCFG_PAUSE_CAP		0x00000800
792da3003f0SBill Paul #define	BGE_SGDIGCFG_ASYM_PAUSE		0x00001000
793da3003f0SBill Paul #define	BGE_SGDIGCFG_SEND		0x40000000
794da3003f0SBill Paul #define	BGE_SGDIGCFG_AUTO		0x80000000
795da3003f0SBill Paul 
796da3003f0SBill Paul /* SGDIG status (not documented) */
797da3003f0SBill Paul #define	BGE_SGDIGSTS_PAUSE_CAP		0x00080000
798da3003f0SBill Paul #define	BGE_SGDIGSTS_ASYM_PAUSE		0x00100000
799da3003f0SBill Paul #define	BGE_SGDIGSTS_DONE		0x00000002
800da3003f0SBill Paul 
801da3003f0SBill Paul 
80295d67482SBill Paul /* MI communication register */
80395d67482SBill Paul #define	BGE_MICOMM_DATA			0x0000FFFF
80495d67482SBill Paul #define	BGE_MICOMM_REG			0x001F0000
80595d67482SBill Paul #define	BGE_MICOMM_PHY			0x03E00000
80695d67482SBill Paul #define	BGE_MICOMM_CMD			0x0C000000
80795d67482SBill Paul #define	BGE_MICOMM_READFAIL		0x10000000
80895d67482SBill Paul #define	BGE_MICOMM_BUSY			0x20000000
80995d67482SBill Paul 
81095d67482SBill Paul #define	BGE_MIREG(x)	((x & 0x1F) << 16)
81195d67482SBill Paul #define	BGE_MIPHY(x)	((x & 0x1F) << 21)
81295d67482SBill Paul #define	BGE_MICMD_WRITE			0x04000000
81395d67482SBill Paul #define	BGE_MICMD_READ			0x08000000
81495d67482SBill Paul 
81595d67482SBill Paul /* MI status register */
81695d67482SBill Paul #define	BGE_MISTS_LINK			0x00000001
81795d67482SBill Paul #define	BGE_MISTS_10MBPS		0x00000002
81895d67482SBill Paul 
81995d67482SBill Paul #define	BGE_MIMODE_SHORTPREAMBLE	0x00000002
82095d67482SBill Paul #define	BGE_MIMODE_AUTOPOLL		0x00000010
82195d67482SBill Paul #define	BGE_MIMODE_CLKCNT		0x001F0000
82295d67482SBill Paul 
82395d67482SBill Paul 
82495d67482SBill Paul /*
82595d67482SBill Paul  * Send data initiator control registers.
82695d67482SBill Paul  */
82795d67482SBill Paul #define	BGE_SDI_MODE			0x0C00
82895d67482SBill Paul #define	BGE_SDI_STATUS			0x0C04
82995d67482SBill Paul #define	BGE_SDI_STATS_CTL		0x0C08
83095d67482SBill Paul #define	BGE_SDI_STATS_ENABLE_MASK	0x0C0C
83195d67482SBill Paul #define	BGE_SDI_STATS_INCREMENT_MASK	0x0C10
83295d67482SBill Paul #define	BGE_LOCSTATS_COS0		0x0C80
83395d67482SBill Paul #define	BGE_LOCSTATS_COS1		0x0C84
83495d67482SBill Paul #define	BGE_LOCSTATS_COS2		0x0C88
83595d67482SBill Paul #define	BGE_LOCSTATS_COS3		0x0C8C
83695d67482SBill Paul #define	BGE_LOCSTATS_COS4		0x0C90
83795d67482SBill Paul #define	BGE_LOCSTATS_COS5		0x0C84
83895d67482SBill Paul #define	BGE_LOCSTATS_COS6		0x0C98
83995d67482SBill Paul #define	BGE_LOCSTATS_COS7		0x0C9C
84095d67482SBill Paul #define	BGE_LOCSTATS_COS8		0x0CA0
84195d67482SBill Paul #define	BGE_LOCSTATS_COS9		0x0CA4
84295d67482SBill Paul #define	BGE_LOCSTATS_COS10		0x0CA8
84395d67482SBill Paul #define	BGE_LOCSTATS_COS11		0x0CAC
84495d67482SBill Paul #define	BGE_LOCSTATS_COS12		0x0CB0
84595d67482SBill Paul #define	BGE_LOCSTATS_COS13		0x0CB4
84695d67482SBill Paul #define	BGE_LOCSTATS_COS14		0x0CB8
84795d67482SBill Paul #define	BGE_LOCSTATS_COS15		0x0CBC
84895d67482SBill Paul #define	BGE_LOCSTATS_DMA_RQ_FULL	0x0CC0
84995d67482SBill Paul #define	BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL	0x0CC4
85095d67482SBill Paul #define	BGE_LOCSTATS_SDC_QUEUE_FULL	0x0CC8
85195d67482SBill Paul #define	BGE_LOCSTATS_NIC_SENDPROD_SET	0x0CCC
85295d67482SBill Paul #define	BGE_LOCSTATS_STATS_UPDATED	0x0CD0
85395d67482SBill Paul #define	BGE_LOCSTATS_IRQS		0x0CD4
85495d67482SBill Paul #define	BGE_LOCSTATS_AVOIDED_IRQS	0x0CD8
85595d67482SBill Paul #define	BGE_LOCSTATS_TX_THRESH_HIT	0x0CDC
85695d67482SBill Paul 
85795d67482SBill Paul /* Send Data Initiator mode register */
85895d67482SBill Paul #define	BGE_SDIMODE_RESET		0x00000001
85995d67482SBill Paul #define	BGE_SDIMODE_ENABLE		0x00000002
86095d67482SBill Paul #define	BGE_SDIMODE_STATS_OFLOW_ATTN	0x00000004
86195d67482SBill Paul 
86295d67482SBill Paul /* Send Data Initiator stats register */
86395d67482SBill Paul #define	BGE_SDISTAT_STATS_OFLOW_ATTN	0x00000004
86495d67482SBill Paul 
86595d67482SBill Paul /* Send Data Initiator stats control register */
86695d67482SBill Paul #define	BGE_SDISTATSCTL_ENABLE		0x00000001
86795d67482SBill Paul #define	BGE_SDISTATSCTL_FASTER		0x00000002
86895d67482SBill Paul #define	BGE_SDISTATSCTL_CLEAR		0x00000004
86995d67482SBill Paul #define	BGE_SDISTATSCTL_FORCEFLUSH	0x00000008
87095d67482SBill Paul #define	BGE_SDISTATSCTL_FORCEZERO	0x00000010
87195d67482SBill Paul 
87295d67482SBill Paul /*
87395d67482SBill Paul  * Send Data Completion Control registers
87495d67482SBill Paul  */
87595d67482SBill Paul #define	BGE_SDC_MODE			0x1000
87695d67482SBill Paul #define	BGE_SDC_STATUS			0x1004
87795d67482SBill Paul 
87895d67482SBill Paul /* Send Data completion mode register */
87995d67482SBill Paul #define	BGE_SDCMODE_RESET		0x00000001
88095d67482SBill Paul #define	BGE_SDCMODE_ENABLE		0x00000002
88195d67482SBill Paul #define	BGE_SDCMODE_ATTN		0x00000004
882a5779553SStanislav Sedov #define	BGE_SDCMODE_CDELAY		0x00000010
88395d67482SBill Paul 
88495d67482SBill Paul /* Send Data completion status register */
88595d67482SBill Paul #define	BGE_SDCSTAT_ATTN		0x00000004
88695d67482SBill Paul 
88795d67482SBill Paul /*
88895d67482SBill Paul  * Send BD Ring Selector Control registers
88995d67482SBill Paul  */
89095d67482SBill Paul #define	BGE_SRS_MODE			0x1400
89195d67482SBill Paul #define	BGE_SRS_STATUS			0x1404
89295d67482SBill Paul #define	BGE_SRS_HWDIAG			0x1408
89395d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS0		0x1440
89495d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS1		0x1444
89595d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS2		0x1448
89695d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS3		0x144C
89795d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS4		0x1450
89895d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS5		0x1454
89995d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS6		0x1458
90095d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS7		0x145C
90195d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS8		0x1460
90295d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS9		0x1464
90395d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS10		0x1468
90495d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS11		0x146C
90595d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS12		0x1470
90695d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS13		0x1474
90795d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS14		0x1478
90895d67482SBill Paul #define	BGE_SRS_LOC_NIC_CONS15		0x147C
90995d67482SBill Paul 
91095d67482SBill Paul /* Send BD Ring Selector Mode register */
91195d67482SBill Paul #define	BGE_SRSMODE_RESET		0x00000001
91295d67482SBill Paul #define	BGE_SRSMODE_ENABLE		0x00000002
91395d67482SBill Paul #define	BGE_SRSMODE_ATTN		0x00000004
91495d67482SBill Paul 
91595d67482SBill Paul /* Send BD Ring Selector Status register */
91695d67482SBill Paul #define	BGE_SRSSTAT_ERROR		0x00000004
91795d67482SBill Paul 
91895d67482SBill Paul /* Send BD Ring Selector HW Diagnostics register */
91995d67482SBill Paul #define	BGE_SRSHWDIAG_STATE		0x0000000F
92095d67482SBill Paul #define	BGE_SRSHWDIAG_CURRINGNUM	0x000000F0
92195d67482SBill Paul #define	BGE_SRSHWDIAG_STAGEDRINGNUM	0x00000F00
92295d67482SBill Paul #define	BGE_SRSHWDIAG_RINGNUM_IN_MBX	0x0000F000
92395d67482SBill Paul 
92495d67482SBill Paul /*
92595d67482SBill Paul  * Send BD Initiator Selector Control registers
92695d67482SBill Paul  */
92795d67482SBill Paul #define	BGE_SBDI_MODE			0x1800
92895d67482SBill Paul #define	BGE_SBDI_STATUS			0x1804
92995d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD0		0x1808
93095d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD1		0x180C
93195d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD2		0x1810
93295d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD3		0x1814
93395d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD4		0x1818
93495d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD5		0x181C
93595d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD6		0x1820
93695d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD7		0x1824
93795d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD8		0x1828
93895d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD9		0x182C
93995d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD10		0x1830
94095d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD11		0x1834
94195d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD12		0x1838
94295d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD13		0x183C
94395d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD14		0x1840
94495d67482SBill Paul #define	BGE_SBDI_LOC_NIC_PROD15		0x1844
94595d67482SBill Paul 
94695d67482SBill Paul /* Send BD Initiator Mode register */
94795d67482SBill Paul #define	BGE_SBDIMODE_RESET		0x00000001
94895d67482SBill Paul #define	BGE_SBDIMODE_ENABLE		0x00000002
94995d67482SBill Paul #define	BGE_SBDIMODE_ATTN		0x00000004
95095d67482SBill Paul 
95195d67482SBill Paul /* Send BD Initiator Status register */
95295d67482SBill Paul #define	BGE_SBDISTAT_ERROR		0x00000004
95395d67482SBill Paul 
95495d67482SBill Paul /*
95595d67482SBill Paul  * Send BD Completion Control registers
95695d67482SBill Paul  */
95795d67482SBill Paul #define	BGE_SBDC_MODE			0x1C00
95895d67482SBill Paul #define	BGE_SBDC_STATUS			0x1C04
95995d67482SBill Paul 
96095d67482SBill Paul /* Send BD Completion Control Mode register */
96195d67482SBill Paul #define	BGE_SBDCMODE_RESET		0x00000001
96295d67482SBill Paul #define	BGE_SBDCMODE_ENABLE		0x00000002
96395d67482SBill Paul #define	BGE_SBDCMODE_ATTN		0x00000004
96495d67482SBill Paul 
96595d67482SBill Paul /* Send BD Completion Control Status register */
96695d67482SBill Paul #define	BGE_SBDCSTAT_ATTN		0x00000004
96795d67482SBill Paul 
96895d67482SBill Paul /*
96995d67482SBill Paul  * Receive List Placement Control registers
97095d67482SBill Paul  */
97195d67482SBill Paul #define	BGE_RXLP_MODE			0x2000
97295d67482SBill Paul #define	BGE_RXLP_STATUS			0x2004
97395d67482SBill Paul #define	BGE_RXLP_SEL_LIST_LOCK		0x2008
97495d67482SBill Paul #define	BGE_RXLP_SEL_NON_EMPTY_BITS	0x200C
97595d67482SBill Paul #define	BGE_RXLP_CFG			0x2010
97695d67482SBill Paul #define	BGE_RXLP_STATS_CTL		0x2014
97795d67482SBill Paul #define	BGE_RXLP_STATS_ENABLE_MASK	0x2018
97895d67482SBill Paul #define	BGE_RXLP_STATS_INCREMENT_MASK	0x201C
97995d67482SBill Paul #define	BGE_RXLP_HEAD0			0x2100
98095d67482SBill Paul #define	BGE_RXLP_TAIL0			0x2104
98195d67482SBill Paul #define	BGE_RXLP_COUNT0			0x2108
98295d67482SBill Paul #define	BGE_RXLP_HEAD1			0x2110
98395d67482SBill Paul #define	BGE_RXLP_TAIL1			0x2114
98495d67482SBill Paul #define	BGE_RXLP_COUNT1			0x2118
98595d67482SBill Paul #define	BGE_RXLP_HEAD2			0x2120
98695d67482SBill Paul #define	BGE_RXLP_TAIL2			0x2124
98795d67482SBill Paul #define	BGE_RXLP_COUNT2			0x2128
98895d67482SBill Paul #define	BGE_RXLP_HEAD3			0x2130
98995d67482SBill Paul #define	BGE_RXLP_TAIL3			0x2134
99095d67482SBill Paul #define	BGE_RXLP_COUNT3			0x2138
99195d67482SBill Paul #define	BGE_RXLP_HEAD4			0x2140
99295d67482SBill Paul #define	BGE_RXLP_TAIL4			0x2144
99395d67482SBill Paul #define	BGE_RXLP_COUNT4			0x2148
99495d67482SBill Paul #define	BGE_RXLP_HEAD5			0x2150
99595d67482SBill Paul #define	BGE_RXLP_TAIL5			0x2154
99695d67482SBill Paul #define	BGE_RXLP_COUNT5			0x2158
99795d67482SBill Paul #define	BGE_RXLP_HEAD6			0x2160
99895d67482SBill Paul #define	BGE_RXLP_TAIL6			0x2164
99995d67482SBill Paul #define	BGE_RXLP_COUNT6			0x2168
100095d67482SBill Paul #define	BGE_RXLP_HEAD7			0x2170
100195d67482SBill Paul #define	BGE_RXLP_TAIL7			0x2174
100295d67482SBill Paul #define	BGE_RXLP_COUNT7			0x2178
100395d67482SBill Paul #define	BGE_RXLP_HEAD8			0x2180
100495d67482SBill Paul #define	BGE_RXLP_TAIL8			0x2184
100595d67482SBill Paul #define	BGE_RXLP_COUNT8			0x2188
100695d67482SBill Paul #define	BGE_RXLP_HEAD9			0x2190
100795d67482SBill Paul #define	BGE_RXLP_TAIL9			0x2194
100895d67482SBill Paul #define	BGE_RXLP_COUNT9			0x2198
100995d67482SBill Paul #define	BGE_RXLP_HEAD10			0x21A0
101095d67482SBill Paul #define	BGE_RXLP_TAIL10			0x21A4
101195d67482SBill Paul #define	BGE_RXLP_COUNT10		0x21A8
101295d67482SBill Paul #define	BGE_RXLP_HEAD11			0x21B0
101395d67482SBill Paul #define	BGE_RXLP_TAIL11			0x21B4
101495d67482SBill Paul #define	BGE_RXLP_COUNT11		0x21B8
101595d67482SBill Paul #define	BGE_RXLP_HEAD12			0x21C0
101695d67482SBill Paul #define	BGE_RXLP_TAIL12			0x21C4
101795d67482SBill Paul #define	BGE_RXLP_COUNT12		0x21C8
101895d67482SBill Paul #define	BGE_RXLP_HEAD13			0x21D0
101995d67482SBill Paul #define	BGE_RXLP_TAIL13			0x21D4
102095d67482SBill Paul #define	BGE_RXLP_COUNT13		0x21D8
102195d67482SBill Paul #define	BGE_RXLP_HEAD14			0x21E0
102295d67482SBill Paul #define	BGE_RXLP_TAIL14			0x21E4
102395d67482SBill Paul #define	BGE_RXLP_COUNT14		0x21E8
102495d67482SBill Paul #define	BGE_RXLP_HEAD15			0x21F0
102595d67482SBill Paul #define	BGE_RXLP_TAIL15			0x21F4
102695d67482SBill Paul #define	BGE_RXLP_COUNT15		0x21F8
102795d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS0		0x2200
102895d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS1		0x2204
102995d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS2		0x2208
103095d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS3		0x220C
103195d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS4		0x2210
103295d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS5		0x2214
103395d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS6		0x2218
103495d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS7		0x221C
103595d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS8		0x2220
103695d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS9		0x2224
103795d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS10		0x2228
103895d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS11		0x222C
103995d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS12		0x2230
104095d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS13		0x2234
104195d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS14		0x2238
104295d67482SBill Paul #define	BGE_RXLP_LOCSTAT_COS15		0x223C
104395d67482SBill Paul #define	BGE_RXLP_LOCSTAT_FILTDROP	0x2240
104495d67482SBill Paul #define	BGE_RXLP_LOCSTAT_DMA_WRQ_FULL	0x2244
104595d67482SBill Paul #define	BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL	0x2248
104695d67482SBill Paul #define	BGE_RXLP_LOCSTAT_OUT_OF_BDS	0x224C
104795d67482SBill Paul #define	BGE_RXLP_LOCSTAT_IFIN_DROPS	0x2250
104895d67482SBill Paul #define	BGE_RXLP_LOCSTAT_IFIN_ERRORS	0x2254
104995d67482SBill Paul #define	BGE_RXLP_LOCSTAT_RXTHRESH_HIT	0x2258
105095d67482SBill Paul 
105195d67482SBill Paul 
105295d67482SBill Paul /* Receive List Placement mode register */
105395d67482SBill Paul #define	BGE_RXLPMODE_RESET		0x00000001
105495d67482SBill Paul #define	BGE_RXLPMODE_ENABLE		0x00000002
105595d67482SBill Paul #define	BGE_RXLPMODE_CLASS0_ATTN	0x00000004
105695d67482SBill Paul #define	BGE_RXLPMODE_MAPOUTRANGE_ATTN	0x00000008
105795d67482SBill Paul #define	BGE_RXLPMODE_STATSOFLOW_ATTN	0x00000010
105895d67482SBill Paul 
105995d67482SBill Paul /* Receive List Placement Status register */
106095d67482SBill Paul #define	BGE_RXLPSTAT_CLASS0_ATTN	0x00000004
106195d67482SBill Paul #define	BGE_RXLPSTAT_MAPOUTRANGE_ATTN	0x00000008
106295d67482SBill Paul #define	BGE_RXLPSTAT_STATSOFLOW_ATTN	0x00000010
106395d67482SBill Paul 
106495d67482SBill Paul /*
106595d67482SBill Paul  * Receive Data and Receive BD Initiator Control Registers
106695d67482SBill Paul  */
106795d67482SBill Paul #define	BGE_RDBDI_MODE			0x2400
106895d67482SBill Paul #define	BGE_RDBDI_STATUS		0x2404
106995d67482SBill Paul #define	BGE_RX_JUMBO_RCB_HADDR_HI	0x2440
107095d67482SBill Paul #define	BGE_RX_JUMBO_RCB_HADDR_LO	0x2444
107195d67482SBill Paul #define	BGE_RX_JUMBO_RCB_MAXLEN_FLAGS	0x2448
107295d67482SBill Paul #define	BGE_RX_JUMBO_RCB_NICADDR	0x244C
107395d67482SBill Paul #define	BGE_RX_STD_RCB_HADDR_HI		0x2450
107495d67482SBill Paul #define	BGE_RX_STD_RCB_HADDR_LO		0x2454
107595d67482SBill Paul #define	BGE_RX_STD_RCB_MAXLEN_FLAGS	0x2458
107695d67482SBill Paul #define	BGE_RX_STD_RCB_NICADDR		0x245C
107795d67482SBill Paul #define	BGE_RX_MINI_RCB_HADDR_HI	0x2460
107895d67482SBill Paul #define	BGE_RX_MINI_RCB_HADDR_LO	0x2464
107995d67482SBill Paul #define	BGE_RX_MINI_RCB_MAXLEN_FLAGS	0x2468
108095d67482SBill Paul #define	BGE_RX_MINI_RCB_NICADDR		0x246C
108195d67482SBill Paul #define	BGE_RDBDI_JUMBO_RX_CONS		0x2470
108295d67482SBill Paul #define	BGE_RDBDI_STD_RX_CONS		0x2474
108395d67482SBill Paul #define	BGE_RDBDI_MINI_RX_CONS		0x2478
108495d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD0		0x2480
108595d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD1		0x2484
108695d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD2		0x2488
108795d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD3		0x248C
108895d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD4		0x2490
108995d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD5		0x2494
109095d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD6		0x2498
109195d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD7		0x249C
109295d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD8		0x24A0
109395d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD9		0x24A4
109495d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD10		0x24A8
109595d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD11		0x24AC
109695d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD12		0x24B0
109795d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD13		0x24B4
109895d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD14		0x24B8
109995d67482SBill Paul #define	BGE_RDBDI_RETURN_PROD15		0x24BC
110095d67482SBill Paul #define	BGE_RDBDI_HWDIAG		0x24C0
110195d67482SBill Paul 
110295d67482SBill Paul 
110395d67482SBill Paul /* Receive Data and Receive BD Initiator Mode register */
110495d67482SBill Paul #define	BGE_RDBDIMODE_RESET		0x00000001
110595d67482SBill Paul #define	BGE_RDBDIMODE_ENABLE		0x00000002
110695d67482SBill Paul #define	BGE_RDBDIMODE_JUMBO_ATTN	0x00000004
110795d67482SBill Paul #define	BGE_RDBDIMODE_GIANT_ATTN	0x00000008
110895d67482SBill Paul #define	BGE_RDBDIMODE_BADRINGSZ_ATTN	0x00000010
110995d67482SBill Paul 
111095d67482SBill Paul /* Receive Data and Receive BD Initiator Status register */
111195d67482SBill Paul #define	BGE_RDBDISTAT_JUMBO_ATTN	0x00000004
111295d67482SBill Paul #define	BGE_RDBDISTAT_GIANT_ATTN	0x00000008
111395d67482SBill Paul #define	BGE_RDBDISTAT_BADRINGSZ_ATTN	0x00000010
111495d67482SBill Paul 
111595d67482SBill Paul 
111695d67482SBill Paul /*
111795d67482SBill Paul  * Receive Data Completion Control registers
111895d67482SBill Paul  */
111995d67482SBill Paul #define	BGE_RDC_MODE			0x2800
112095d67482SBill Paul 
112195d67482SBill Paul /* Receive Data Completion Mode register */
112295d67482SBill Paul #define	BGE_RDCMODE_RESET		0x00000001
112395d67482SBill Paul #define	BGE_RDCMODE_ENABLE		0x00000002
112495d67482SBill Paul #define	BGE_RDCMODE_ATTN		0x00000004
112595d67482SBill Paul 
112695d67482SBill Paul /*
112795d67482SBill Paul  * Receive BD Initiator Control registers
112895d67482SBill Paul  */
112995d67482SBill Paul #define	BGE_RBDI_MODE			0x2C00
113095d67482SBill Paul #define	BGE_RBDI_STATUS			0x2C04
113195d67482SBill Paul #define	BGE_RBDI_NIC_JUMBO_BD_PROD	0x2C08
113295d67482SBill Paul #define	BGE_RBDI_NIC_STD_BD_PROD	0x2C0C
113395d67482SBill Paul #define	BGE_RBDI_NIC_MINI_BD_PROD	0x2C10
113495d67482SBill Paul #define	BGE_RBDI_MINI_REPL_THRESH	0x2C14
113595d67482SBill Paul #define	BGE_RBDI_STD_REPL_THRESH	0x2C18
113695d67482SBill Paul #define	BGE_RBDI_JUMBO_REPL_THRESH	0x2C1C
113795d67482SBill Paul 
113895d67482SBill Paul /* Receive BD Initiator Mode register */
113995d67482SBill Paul #define	BGE_RBDIMODE_RESET		0x00000001
114095d67482SBill Paul #define	BGE_RBDIMODE_ENABLE		0x00000002
114195d67482SBill Paul #define	BGE_RBDIMODE_ATTN		0x00000004
114295d67482SBill Paul 
114395d67482SBill Paul /* Receive BD Initiator Status register */
114495d67482SBill Paul #define	BGE_RBDISTAT_ATTN		0x00000004
114595d67482SBill Paul 
114695d67482SBill Paul /*
114795d67482SBill Paul  * Receive BD Completion Control registers
114895d67482SBill Paul  */
114995d67482SBill Paul #define	BGE_RBDC_MODE			0x3000
115095d67482SBill Paul #define	BGE_RBDC_STATUS			0x3004
115195d67482SBill Paul #define	BGE_RBDC_JUMBO_BD_PROD		0x3008
115295d67482SBill Paul #define	BGE_RBDC_STD_BD_PROD		0x300C
115395d67482SBill Paul #define	BGE_RBDC_MINI_BD_PROD		0x3010
115495d67482SBill Paul 
115595d67482SBill Paul /* Receive BD completion mode register */
115695d67482SBill Paul #define	BGE_RBDCMODE_RESET		0x00000001
115795d67482SBill Paul #define	BGE_RBDCMODE_ENABLE		0x00000002
115895d67482SBill Paul #define	BGE_RBDCMODE_ATTN		0x00000004
115995d67482SBill Paul 
116095d67482SBill Paul /* Receive BD completion status register */
116195d67482SBill Paul #define	BGE_RBDCSTAT_ERROR		0x00000004
116295d67482SBill Paul 
116395d67482SBill Paul /*
116495d67482SBill Paul  * Receive List Selector Control registers
116595d67482SBill Paul  */
116695d67482SBill Paul #define	BGE_RXLS_MODE			0x3400
116795d67482SBill Paul #define	BGE_RXLS_STATUS			0x3404
116895d67482SBill Paul 
116995d67482SBill Paul /* Receive List Selector Mode register */
117095d67482SBill Paul #define	BGE_RXLSMODE_RESET		0x00000001
117195d67482SBill Paul #define	BGE_RXLSMODE_ENABLE		0x00000002
117295d67482SBill Paul #define	BGE_RXLSMODE_ATTN		0x00000004
117395d67482SBill Paul 
117495d67482SBill Paul /* Receive List Selector Status register */
117595d67482SBill Paul #define	BGE_RXLSSTAT_ERROR		0x00000004
117695d67482SBill Paul 
117795d67482SBill Paul /*
117895d67482SBill Paul  * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
117995d67482SBill Paul  */
118095d67482SBill Paul #define	BGE_MBCF_MODE			0x3800
118195d67482SBill Paul #define	BGE_MBCF_STATUS			0x3804
118295d67482SBill Paul 
118395d67482SBill Paul /* Mbuf Cluster Free mode register */
118495d67482SBill Paul #define	BGE_MBCFMODE_RESET		0x00000001
118595d67482SBill Paul #define	BGE_MBCFMODE_ENABLE		0x00000002
118695d67482SBill Paul #define	BGE_MBCFMODE_ATTN		0x00000004
118795d67482SBill Paul 
118895d67482SBill Paul /* Mbuf Cluster Free status register */
118995d67482SBill Paul #define	BGE_MBCFSTAT_ERROR		0x00000004
119095d67482SBill Paul 
119195d67482SBill Paul /*
119295d67482SBill Paul  * Host Coalescing Control registers
119395d67482SBill Paul  */
119495d67482SBill Paul #define	BGE_HCC_MODE			0x3C00
119595d67482SBill Paul #define	BGE_HCC_STATUS			0x3C04
119695d67482SBill Paul #define	BGE_HCC_RX_COAL_TICKS		0x3C08
119795d67482SBill Paul #define	BGE_HCC_TX_COAL_TICKS		0x3C0C
119895d67482SBill Paul #define	BGE_HCC_RX_MAX_COAL_BDS		0x3C10
119995d67482SBill Paul #define	BGE_HCC_TX_MAX_COAL_BDS		0x3C14
120095d67482SBill Paul #define	BGE_HCC_RX_COAL_TICKS_INT	0x3C18 /* ticks during interrupt */
120195d67482SBill Paul #define	BGE_HCC_TX_COAL_TICKS_INT	0x3C1C /* ticks during interrupt */
120295d67482SBill Paul #define	BGE_HCC_RX_MAX_COAL_BDS_INT	0x3C20 /* BDs during interrupt */
1203f53579cfSPaul Saab #define	BGE_HCC_TX_MAX_COAL_BDS_INT	0x3C24 /* BDs during interrupt */
120495d67482SBill Paul #define	BGE_HCC_STATS_TICKS		0x3C28
120595d67482SBill Paul #define	BGE_HCC_STATS_ADDR_HI		0x3C30
120695d67482SBill Paul #define	BGE_HCC_STATS_ADDR_LO		0x3C34
120795d67482SBill Paul #define	BGE_HCC_STATUSBLK_ADDR_HI	0x3C38
120895d67482SBill Paul #define	BGE_HCC_STATUSBLK_ADDR_LO	0x3C3C
120995d67482SBill Paul #define	BGE_HCC_STATS_BASEADDR		0x3C40 /* address in NIC memory */
121095d67482SBill Paul #define	BGE_HCC_STATUSBLK_BASEADDR	0x3C44 /* address in NIC memory */
121195d67482SBill Paul #define	BGE_FLOW_ATTN			0x3C48
121295d67482SBill Paul #define	BGE_HCC_JUMBO_BD_CONS		0x3C50
121395d67482SBill Paul #define	BGE_HCC_STD_BD_CONS		0x3C54
121495d67482SBill Paul #define	BGE_HCC_MINI_BD_CONS		0x3C58
121595d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD0		0x3C80
121695d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD1		0x3C84
121795d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD2		0x3C88
121895d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD3		0x3C8C
121995d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD4		0x3C90
122095d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD5		0x3C94
122195d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD6		0x3C98
122295d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD7		0x3C9C
122395d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD8		0x3CA0
122495d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD9		0x3CA4
122595d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD10	0x3CA8
122695d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD11	0x3CAC
122795d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD12	0x3CB0
122895d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD13	0x3CB4
122995d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD14	0x3CB8
123095d67482SBill Paul #define	BGE_HCC_RX_RETURN_PROD15	0x3CBC
123195d67482SBill Paul #define	BGE_HCC_TX_BD_CONS0		0x3CC0
123295d67482SBill Paul #define	BGE_HCC_TX_BD_CONS1		0x3CC4
123395d67482SBill Paul #define	BGE_HCC_TX_BD_CONS2		0x3CC8
123495d67482SBill Paul #define	BGE_HCC_TX_BD_CONS3		0x3CCC
123595d67482SBill Paul #define	BGE_HCC_TX_BD_CONS4		0x3CD0
123695d67482SBill Paul #define	BGE_HCC_TX_BD_CONS5		0x3CD4
123795d67482SBill Paul #define	BGE_HCC_TX_BD_CONS6		0x3CD8
123895d67482SBill Paul #define	BGE_HCC_TX_BD_CONS7		0x3CDC
123995d67482SBill Paul #define	BGE_HCC_TX_BD_CONS8		0x3CE0
124095d67482SBill Paul #define	BGE_HCC_TX_BD_CONS9		0x3CE4
124195d67482SBill Paul #define	BGE_HCC_TX_BD_CONS10		0x3CE8
124295d67482SBill Paul #define	BGE_HCC_TX_BD_CONS11		0x3CEC
124395d67482SBill Paul #define	BGE_HCC_TX_BD_CONS12		0x3CF0
124495d67482SBill Paul #define	BGE_HCC_TX_BD_CONS13		0x3CF4
124595d67482SBill Paul #define	BGE_HCC_TX_BD_CONS14		0x3CF8
124695d67482SBill Paul #define	BGE_HCC_TX_BD_CONS15		0x3CFC
124795d67482SBill Paul 
124895d67482SBill Paul 
124995d67482SBill Paul /* Host coalescing mode register */
125095d67482SBill Paul #define	BGE_HCCMODE_RESET		0x00000001
125195d67482SBill Paul #define	BGE_HCCMODE_ENABLE		0x00000002
125295d67482SBill Paul #define	BGE_HCCMODE_ATTN		0x00000004
125395d67482SBill Paul #define	BGE_HCCMODE_COAL_NOW		0x00000008
12544a531e8dSPawel Jakub Dawidek #define	BGE_HCCMODE_MSI_BITS		0x00000070
125595d67482SBill Paul #define	BGE_HCCMODE_STATBLK_SIZE	0x00000180
125695d67482SBill Paul 
125795d67482SBill Paul #define	BGE_STATBLKSZ_FULL		0x00000000
125895d67482SBill Paul #define	BGE_STATBLKSZ_64BYTE		0x00000080
125995d67482SBill Paul #define	BGE_STATBLKSZ_32BYTE		0x00000100
126095d67482SBill Paul 
126195d67482SBill Paul /* Host coalescing status register */
126295d67482SBill Paul #define	BGE_HCCSTAT_ERROR		0x00000004
126395d67482SBill Paul 
126495d67482SBill Paul /* Flow attention register */
126595d67482SBill Paul #define	BGE_FLOWATTN_MB_LOWAT		0x00000040
126695d67482SBill Paul #define	BGE_FLOWATTN_MEMARB		0x00000080
126795d67482SBill Paul #define	BGE_FLOWATTN_HOSTCOAL		0x00008000
126895d67482SBill Paul #define	BGE_FLOWATTN_DMADONE_DISCARD	0x00010000
126995d67482SBill Paul #define	BGE_FLOWATTN_RCB_INVAL		0x00020000
127095d67482SBill Paul #define	BGE_FLOWATTN_RXDATA_CORRUPT	0x00040000
127195d67482SBill Paul #define	BGE_FLOWATTN_RDBDI		0x00080000
127295d67482SBill Paul #define	BGE_FLOWATTN_RXLS		0x00100000
127395d67482SBill Paul #define	BGE_FLOWATTN_RXLP		0x00200000
127495d67482SBill Paul #define	BGE_FLOWATTN_RBDC		0x00400000
127595d67482SBill Paul #define	BGE_FLOWATTN_RBDI		0x00800000
127695d67482SBill Paul #define	BGE_FLOWATTN_SDC		0x08000000
127795d67482SBill Paul #define	BGE_FLOWATTN_SDI		0x10000000
127895d67482SBill Paul #define	BGE_FLOWATTN_SRS		0x20000000
127995d67482SBill Paul #define	BGE_FLOWATTN_SBDC		0x40000000
128095d67482SBill Paul #define	BGE_FLOWATTN_SBDI		0x80000000
128195d67482SBill Paul 
128295d67482SBill Paul /*
128395d67482SBill Paul  * Memory arbiter registers
128495d67482SBill Paul  */
128595d67482SBill Paul #define	BGE_MARB_MODE			0x4000
128695d67482SBill Paul #define	BGE_MARB_STATUS			0x4004
128795d67482SBill Paul #define	BGE_MARB_TRAPADDR_HI		0x4008
128895d67482SBill Paul #define	BGE_MARB_TRAPADDR_LO		0x400C
128995d67482SBill Paul 
129095d67482SBill Paul /* Memory arbiter mode register */
129195d67482SBill Paul #define	BGE_MARBMODE_RESET		0x00000001
129295d67482SBill Paul #define	BGE_MARBMODE_ENABLE		0x00000002
129395d67482SBill Paul #define	BGE_MARBMODE_TX_ADDR_TRAP	0x00000004
129495d67482SBill Paul #define	BGE_MARBMODE_RX_ADDR_TRAP	0x00000008
129595d67482SBill Paul #define	BGE_MARBMODE_DMAW1_TRAP		0x00000010
129695d67482SBill Paul #define	BGE_MARBMODE_DMAR1_TRAP		0x00000020
129795d67482SBill Paul #define	BGE_MARBMODE_RXRISC_TRAP	0x00000040
129895d67482SBill Paul #define	BGE_MARBMODE_TXRISC_TRAP	0x00000080
129995d67482SBill Paul #define	BGE_MARBMODE_PCI_TRAP		0x00000100
130095d67482SBill Paul #define	BGE_MARBMODE_DMAR2_TRAP		0x00000200
130195d67482SBill Paul #define	BGE_MARBMODE_RXQ_TRAP		0x00000400
130295d67482SBill Paul #define	BGE_MARBMODE_RXDI1_TRAP		0x00000800
130395d67482SBill Paul #define	BGE_MARBMODE_RXDI2_TRAP		0x00001000
130495d67482SBill Paul #define	BGE_MARBMODE_DC_GRPMEM_TRAP	0x00002000
130595d67482SBill Paul #define	BGE_MARBMODE_HCOAL_TRAP		0x00004000
130695d67482SBill Paul #define	BGE_MARBMODE_MBUF_TRAP		0x00008000
130795d67482SBill Paul #define	BGE_MARBMODE_TXDI_TRAP		0x00010000
130895d67482SBill Paul #define	BGE_MARBMODE_SDC_DMAC_TRAP	0x00020000
130995d67482SBill Paul #define	BGE_MARBMODE_TXBD_TRAP		0x00040000
131095d67482SBill Paul #define	BGE_MARBMODE_BUFFMAN_TRAP	0x00080000
131195d67482SBill Paul #define	BGE_MARBMODE_DMAW2_TRAP		0x00100000
131295d67482SBill Paul #define	BGE_MARBMODE_XTSSRAM_ROFLO_TRAP	0x00200000
131395d67482SBill Paul #define	BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
131495d67482SBill Paul #define	BGE_MARBMODE_XTSSRAM_WOFLO_TRAP	0x00800000
131595d67482SBill Paul #define	BGE_MARBMODE_XTSSRAM_WUFLO_TRAP	0x01000000
131695d67482SBill Paul #define	BGE_MARBMODE_XTSSRAM_PERR_TRAP	0x02000000
131795d67482SBill Paul 
131895d67482SBill Paul /* Memory arbiter status register */
131995d67482SBill Paul #define	BGE_MARBSTAT_TX_ADDR_TRAP	0x00000004
132095d67482SBill Paul #define	BGE_MARBSTAT_RX_ADDR_TRAP	0x00000008
132195d67482SBill Paul #define	BGE_MARBSTAT_DMAW1_TRAP		0x00000010
132295d67482SBill Paul #define	BGE_MARBSTAT_DMAR1_TRAP		0x00000020
132395d67482SBill Paul #define	BGE_MARBSTAT_RXRISC_TRAP	0x00000040
132495d67482SBill Paul #define	BGE_MARBSTAT_TXRISC_TRAP	0x00000080
132595d67482SBill Paul #define	BGE_MARBSTAT_PCI_TRAP		0x00000100
132695d67482SBill Paul #define	BGE_MARBSTAT_DMAR2_TRAP		0x00000200
132795d67482SBill Paul #define	BGE_MARBSTAT_RXQ_TRAP		0x00000400
132895d67482SBill Paul #define	BGE_MARBSTAT_RXDI1_TRAP		0x00000800
132995d67482SBill Paul #define	BGE_MARBSTAT_RXDI2_TRAP		0x00001000
133095d67482SBill Paul #define	BGE_MARBSTAT_DC_GRPMEM_TRAP	0x00002000
133195d67482SBill Paul #define	BGE_MARBSTAT_HCOAL_TRAP		0x00004000
133295d67482SBill Paul #define	BGE_MARBSTAT_MBUF_TRAP		0x00008000
133395d67482SBill Paul #define	BGE_MARBSTAT_TXDI_TRAP		0x00010000
133495d67482SBill Paul #define	BGE_MARBSTAT_SDC_DMAC_TRAP	0x00020000
133595d67482SBill Paul #define	BGE_MARBSTAT_TXBD_TRAP		0x00040000
133695d67482SBill Paul #define	BGE_MARBSTAT_BUFFMAN_TRAP	0x00080000
133795d67482SBill Paul #define	BGE_MARBSTAT_DMAW2_TRAP		0x00100000
133895d67482SBill Paul #define	BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP	0x00200000
133995d67482SBill Paul #define	BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
134095d67482SBill Paul #define	BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP	0x00800000
134195d67482SBill Paul #define	BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP	0x01000000
134295d67482SBill Paul #define	BGE_MARBSTAT_XTSSRAM_PERR_TRAP	0x02000000
134395d67482SBill Paul 
134495d67482SBill Paul /*
134595d67482SBill Paul  * Buffer manager control registers
134695d67482SBill Paul  */
134795d67482SBill Paul #define	BGE_BMAN_MODE			0x4400
134895d67482SBill Paul #define	BGE_BMAN_STATUS			0x4404
134995d67482SBill Paul #define	BGE_BMAN_MBUFPOOL_BASEADDR	0x4408
135095d67482SBill Paul #define	BGE_BMAN_MBUFPOOL_LEN		0x440C
135195d67482SBill Paul #define	BGE_BMAN_MBUFPOOL_READDMA_LOWAT	0x4410
135295d67482SBill Paul #define	BGE_BMAN_MBUFPOOL_MACRX_LOWAT	0x4414
135395d67482SBill Paul #define	BGE_BMAN_MBUFPOOL_HIWAT		0x4418
135495d67482SBill Paul #define	BGE_BMAN_RXCPU_MBALLOC_REQ	0x441C
135595d67482SBill Paul #define	BGE_BMAN_RXCPU_MBALLOC_RESP	0x4420
135695d67482SBill Paul #define	BGE_BMAN_TXCPU_MBALLOC_REQ	0x4424
135795d67482SBill Paul #define	BGE_BMAN_TXCPU_MBALLOC_RESP	0x4428
135895d67482SBill Paul #define	BGE_BMAN_DMA_DESCPOOL_BASEADDR	0x442C
135995d67482SBill Paul #define	BGE_BMAN_DMA_DESCPOOL_LEN	0x4430
136095d67482SBill Paul #define	BGE_BMAN_DMA_DESCPOOL_LOWAT	0x4434
136195d67482SBill Paul #define	BGE_BMAN_DMA_DESCPOOL_HIWAT	0x4438
136295d67482SBill Paul #define	BGE_BMAN_RXCPU_DMAALLOC_REQ	0x443C
136395d67482SBill Paul #define	BGE_BMAN_RXCPU_DMAALLOC_RESP	0x4440
136495d67482SBill Paul #define	BGE_BMAN_TXCPU_DMAALLOC_REQ	0x4444
136595d67482SBill Paul #define	BGE_BMAN_TXCPU_DMALLLOC_RESP	0x4448
136695d67482SBill Paul #define	BGE_BMAN_HWDIAG_1		0x444C
136795d67482SBill Paul #define	BGE_BMAN_HWDIAG_2		0x4450
136895d67482SBill Paul #define	BGE_BMAN_HWDIAG_3		0x4454
136995d67482SBill Paul 
137095d67482SBill Paul /* Buffer manager mode register */
137195d67482SBill Paul #define	BGE_BMANMODE_RESET		0x00000001
137295d67482SBill Paul #define	BGE_BMANMODE_ENABLE		0x00000002
137395d67482SBill Paul #define	BGE_BMANMODE_ATTN		0x00000004
137495d67482SBill Paul #define	BGE_BMANMODE_TESTMODE		0x00000008
137595d67482SBill Paul #define	BGE_BMANMODE_LOMBUF_ATTN	0x00000010
137695d67482SBill Paul 
137795d67482SBill Paul /* Buffer manager status register */
137895d67482SBill Paul #define	BGE_BMANSTAT_ERRO		0x00000004
137995d67482SBill Paul #define	BGE_BMANSTAT_LOWMBUF_ERROR	0x00000010
138095d67482SBill Paul 
138195d67482SBill Paul 
138295d67482SBill Paul /*
138395d67482SBill Paul  * Read DMA Control registers
138495d67482SBill Paul  */
138595d67482SBill Paul #define	BGE_RDMA_MODE			0x4800
138695d67482SBill Paul #define	BGE_RDMA_STATUS			0x4804
138795d67482SBill Paul 
138895d67482SBill Paul /* Read DMA mode register */
138995d67482SBill Paul #define	BGE_RDMAMODE_RESET		0x00000001
139095d67482SBill Paul #define	BGE_RDMAMODE_ENABLE		0x00000002
139195d67482SBill Paul #define	BGE_RDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
139295d67482SBill Paul #define	BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
139395d67482SBill Paul #define	BGE_RDMAMODE_PCI_PERR_ATTN	0x00000010
139495d67482SBill Paul #define	BGE_RDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
139595d67482SBill Paul #define	BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
139695d67482SBill Paul #define	BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
139795d67482SBill Paul #define	BGE_RDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
139895d67482SBill Paul #define	BGE_RDMAMODE_LOCWRITE_TOOBIG	0x00000200
139995d67482SBill Paul #define	BGE_RDMAMODE_ALL_ATTNS		0x000003FC
1400a5779553SStanislav Sedov #define	BGE_RDMAMODE_BD_SBD_CRPT_ATTN	0x00000800
1401a5779553SStanislav Sedov #define	BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN	0x00001000
1402a5779553SStanislav Sedov #define	BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN	0x00002000
14034f09c4c7SMarius Strobl #define	BGE_RDMAMODE_FIFO_SIZE_128	0x00020000
14044f09c4c7SMarius Strobl #define	BGE_RDMAMODE_FIFO_LONG_BURST	0x00030000
1405ca3f1187SPyun YongHyeon #define	BGE_RDMAMODE_TSO4_ENABLE	0x08000000
1406ca3f1187SPyun YongHyeon #define	BGE_RDMAMODE_TSO6_ENABLE	0x10000000
140795d67482SBill Paul 
140895d67482SBill Paul /* Read DMA status register */
140995d67482SBill Paul #define	BGE_RDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
141095d67482SBill Paul #define	BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
141195d67482SBill Paul #define	BGE_RDMASTAT_PCI_PERR_ATTN	0x00000010
141295d67482SBill Paul #define	BGE_RDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
141395d67482SBill Paul #define	BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
141495d67482SBill Paul #define	BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
141595d67482SBill Paul #define	BGE_RDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
141695d67482SBill Paul #define	BGE_RDMASTAT_LOCWRITE_TOOBIG	0x00000200
141795d67482SBill Paul 
141895d67482SBill Paul /*
141995d67482SBill Paul  * Write DMA control registers
142095d67482SBill Paul  */
142195d67482SBill Paul #define	BGE_WDMA_MODE			0x4C00
142295d67482SBill Paul #define	BGE_WDMA_STATUS			0x4C04
142395d67482SBill Paul 
142495d67482SBill Paul /* Write DMA mode register */
142595d67482SBill Paul #define	BGE_WDMAMODE_RESET		0x00000001
142695d67482SBill Paul #define	BGE_WDMAMODE_ENABLE		0x00000002
142795d67482SBill Paul #define	BGE_WDMAMODE_PCI_TGT_ABRT_ATTN	0x00000004
142895d67482SBill Paul #define	BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN	0x00000008
142995d67482SBill Paul #define	BGE_WDMAMODE_PCI_PERR_ATTN	0x00000010
143095d67482SBill Paul #define	BGE_WDMAMODE_PCI_ADDROFLOW_ATTN	0x00000020
143195d67482SBill Paul #define	BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN	0x00000040
143295d67482SBill Paul #define	BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN	0x00000080
143395d67482SBill Paul #define	BGE_WDMAMODE_PCI_FIFOOREAD_ATTN	0x00000100
143495d67482SBill Paul #define	BGE_WDMAMODE_LOCREAD_TOOBIG	0x00000200
143595d67482SBill Paul #define	BGE_WDMAMODE_ALL_ATTNS		0x000003FC
14363889907fSStanislav Sedov #define	BGE_WDMAMODE_STATUS_TAG_FIX	0x20000000
143795d67482SBill Paul 
143895d67482SBill Paul /* Write DMA status register */
143995d67482SBill Paul #define	BGE_WDMASTAT_PCI_TGT_ABRT_ATTN	0x00000004
144095d67482SBill Paul #define	BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN	0x00000008
144195d67482SBill Paul #define	BGE_WDMASTAT_PCI_PERR_ATTN	0x00000010
144295d67482SBill Paul #define	BGE_WDMASTAT_PCI_ADDROFLOW_ATTN	0x00000020
144395d67482SBill Paul #define	BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN	0x00000040
144495d67482SBill Paul #define	BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN	0x00000080
144595d67482SBill Paul #define	BGE_WDMASTAT_PCI_FIFOOREAD_ATTN	0x00000100
144695d67482SBill Paul #define	BGE_WDMASTAT_LOCREAD_TOOBIG	0x00000200
144795d67482SBill Paul 
144895d67482SBill Paul 
144995d67482SBill Paul /*
145095d67482SBill Paul  * RX CPU registers
145195d67482SBill Paul  */
145295d67482SBill Paul #define	BGE_RXCPU_MODE			0x5000
145395d67482SBill Paul #define	BGE_RXCPU_STATUS		0x5004
145495d67482SBill Paul #define	BGE_RXCPU_PC			0x501C
145595d67482SBill Paul 
145695d67482SBill Paul /* RX CPU mode register */
145795d67482SBill Paul #define	BGE_RXCPUMODE_RESET		0x00000001
145895d67482SBill Paul #define	BGE_RXCPUMODE_SINGLESTEP	0x00000002
145995d67482SBill Paul #define	BGE_RXCPUMODE_P0_DATAHLT_ENB	0x00000004
146095d67482SBill Paul #define	BGE_RXCPUMODE_P0_INSTRHLT_ENB	0x00000008
146195d67482SBill Paul #define	BGE_RXCPUMODE_WR_POSTBUF_ENB	0x00000010
146295d67482SBill Paul #define	BGE_RXCPUMODE_DATACACHE_ENB	0x00000020
146395d67482SBill Paul #define	BGE_RXCPUMODE_ROMFAIL		0x00000040
146495d67482SBill Paul #define	BGE_RXCPUMODE_WATCHDOG_ENB	0x00000080
146595d67482SBill Paul #define	BGE_RXCPUMODE_INSTRCACHE_PRF	0x00000100
146695d67482SBill Paul #define	BGE_RXCPUMODE_INSTRCACHE_FLUSH	0x00000200
146795d67482SBill Paul #define	BGE_RXCPUMODE_HALTCPU		0x00000400
146895d67482SBill Paul #define	BGE_RXCPUMODE_INVDATAHLT_ENB	0x00000800
146995d67482SBill Paul #define	BGE_RXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
147095d67482SBill Paul #define	BGE_RXCPUMODE_RADDRTRAPHLT_ENB	0x00002000
147195d67482SBill Paul 
147295d67482SBill Paul /* RX CPU status register */
147395d67482SBill Paul #define	BGE_RXCPUSTAT_HW_BREAKPOINT	0x00000001
147495d67482SBill Paul #define	BGE_RXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
147595d67482SBill Paul #define	BGE_RXCPUSTAT_INVALID_INSTR	0x00000004
147695d67482SBill Paul #define	BGE_RXCPUSTAT_P0_DATAREF	0x00000008
147795d67482SBill Paul #define	BGE_RXCPUSTAT_P0_INSTRREF	0x00000010
147895d67482SBill Paul #define	BGE_RXCPUSTAT_INVALID_DATAACC	0x00000020
147995d67482SBill Paul #define	BGE_RXCPUSTAT_INVALID_INSTRFTCH	0x00000040
148095d67482SBill Paul #define	BGE_RXCPUSTAT_BAD_MEMALIGN	0x00000080
148195d67482SBill Paul #define	BGE_RXCPUSTAT_MADDR_TRAP	0x00000100
148295d67482SBill Paul #define	BGE_RXCPUSTAT_REGADDR_TRAP	0x00000200
148395d67482SBill Paul #define	BGE_RXCPUSTAT_DATAACC_STALL	0x00001000
148495d67482SBill Paul #define	BGE_RXCPUSTAT_INSTRFETCH_STALL	0x00002000
148595d67482SBill Paul #define	BGE_RXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
148695d67482SBill Paul #define	BGE_RXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
148795d67482SBill Paul #define	BGE_RXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
148895d67482SBill Paul #define	BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
148995d67482SBill Paul #define	BGE_RXCPUSTAT_BLOCKING_READ	0x80000000
149095d67482SBill Paul 
149138cc658fSJohn Baldwin /*
149238cc658fSJohn Baldwin  * V? CPU registers
149338cc658fSJohn Baldwin  */
149438cc658fSJohn Baldwin #define	BGE_VCPU_STATUS			0x5100
149538cc658fSJohn Baldwin #define	BGE_VCPU_EXT_CTRL		0x6890
149638cc658fSJohn Baldwin 
149738cc658fSJohn Baldwin #define	BGE_VCPU_STATUS_INIT_DONE	0x04000000
149838cc658fSJohn Baldwin #define	BGE_VCPU_STATUS_DRV_RESET 	0x08000000
149938cc658fSJohn Baldwin 
150038cc658fSJohn Baldwin #define	BGE_VCPU_EXT_CTRL_HALT_CPU	0x00400000
150138cc658fSJohn Baldwin #define	BGE_VCPU_EXT_CTRL_DISABLE_WOL	0x20000000
150295d67482SBill Paul 
150395d67482SBill Paul /*
150495d67482SBill Paul  * TX CPU registers
150595d67482SBill Paul  */
150695d67482SBill Paul #define	BGE_TXCPU_MODE			0x5400
150795d67482SBill Paul #define	BGE_TXCPU_STATUS		0x5404
150895d67482SBill Paul #define	BGE_TXCPU_PC			0x541C
150995d67482SBill Paul 
151095d67482SBill Paul /* TX CPU mode register */
151195d67482SBill Paul #define	BGE_TXCPUMODE_RESET		0x00000001
151295d67482SBill Paul #define	BGE_TXCPUMODE_SINGLESTEP	0x00000002
151395d67482SBill Paul #define	BGE_TXCPUMODE_P0_DATAHLT_ENB	0x00000004
151495d67482SBill Paul #define	BGE_TXCPUMODE_P0_INSTRHLT_ENB	0x00000008
151595d67482SBill Paul #define	BGE_TXCPUMODE_WR_POSTBUF_ENB	0x00000010
151695d67482SBill Paul #define	BGE_TXCPUMODE_DATACACHE_ENB	0x00000020
151795d67482SBill Paul #define	BGE_TXCPUMODE_ROMFAIL		0x00000040
151895d67482SBill Paul #define	BGE_TXCPUMODE_WATCHDOG_ENB	0x00000080
151995d67482SBill Paul #define	BGE_TXCPUMODE_INSTRCACHE_PRF	0x00000100
152095d67482SBill Paul #define	BGE_TXCPUMODE_INSTRCACHE_FLUSH	0x00000200
152195d67482SBill Paul #define	BGE_TXCPUMODE_HALTCPU		0x00000400
152295d67482SBill Paul #define	BGE_TXCPUMODE_INVDATAHLT_ENB	0x00000800
152395d67482SBill Paul #define	BGE_TXCPUMODE_MADDRTRAPHLT_ENB	0x00001000
152495d67482SBill Paul 
152595d67482SBill Paul /* TX CPU status register */
152695d67482SBill Paul #define	BGE_TXCPUSTAT_HW_BREAKPOINT	0x00000001
152795d67482SBill Paul #define	BGE_TXCPUSTAT_HLTINSTR_EXECUTED	0x00000002
152895d67482SBill Paul #define	BGE_TXCPUSTAT_INVALID_INSTR	0x00000004
152995d67482SBill Paul #define	BGE_TXCPUSTAT_P0_DATAREF	0x00000008
153095d67482SBill Paul #define	BGE_TXCPUSTAT_P0_INSTRREF	0x00000010
153195d67482SBill Paul #define	BGE_TXCPUSTAT_INVALID_DATAACC	0x00000020
153295d67482SBill Paul #define	BGE_TXCPUSTAT_INVALID_INSTRFTCH	0x00000040
153395d67482SBill Paul #define	BGE_TXCPUSTAT_BAD_MEMALIGN	0x00000080
153495d67482SBill Paul #define	BGE_TXCPUSTAT_MADDR_TRAP	0x00000100
153595d67482SBill Paul #define	BGE_TXCPUSTAT_REGADDR_TRAP	0x00000200
153695d67482SBill Paul #define	BGE_TXCPUSTAT_DATAACC_STALL	0x00001000
153795d67482SBill Paul #define	BGE_TXCPUSTAT_INSTRFETCH_STALL	0x00002000
153895d67482SBill Paul #define	BGE_TXCPUSTAT_MA_WR_FIFOOFLOW	0x08000000
153995d67482SBill Paul #define	BGE_TXCPUSTAT_MA_RD_FIFOOFLOW	0x10000000
154095d67482SBill Paul #define	BGE_TXCPUSTAT_MA_DATAMASK_OFLOW	0x20000000
154195d67482SBill Paul #define	BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW	0x40000000
154295d67482SBill Paul #define	BGE_TXCPUSTAT_BLOCKING_READ	0x80000000
154395d67482SBill Paul 
154495d67482SBill Paul 
154595d67482SBill Paul /*
154695d67482SBill Paul  * Low priority mailbox registers
154795d67482SBill Paul  */
154895d67482SBill Paul #define	BGE_LPMBX_IRQ0_HI		0x5800
154995d67482SBill Paul #define	BGE_LPMBX_IRQ0_LO		0x5804
155095d67482SBill Paul #define	BGE_LPMBX_IRQ1_HI		0x5808
155195d67482SBill Paul #define	BGE_LPMBX_IRQ1_LO		0x580C
155295d67482SBill Paul #define	BGE_LPMBX_IRQ2_HI		0x5810
155395d67482SBill Paul #define	BGE_LPMBX_IRQ2_LO		0x5814
155495d67482SBill Paul #define	BGE_LPMBX_IRQ3_HI		0x5818
155595d67482SBill Paul #define	BGE_LPMBX_IRQ3_LO		0x581C
155695d67482SBill Paul #define	BGE_LPMBX_GEN0_HI		0x5820
155795d67482SBill Paul #define	BGE_LPMBX_GEN0_LO		0x5824
155895d67482SBill Paul #define	BGE_LPMBX_GEN1_HI		0x5828
155995d67482SBill Paul #define	BGE_LPMBX_GEN1_LO		0x582C
156095d67482SBill Paul #define	BGE_LPMBX_GEN2_HI		0x5830
156195d67482SBill Paul #define	BGE_LPMBX_GEN2_LO		0x5834
156295d67482SBill Paul #define	BGE_LPMBX_GEN3_HI		0x5828
156395d67482SBill Paul #define	BGE_LPMBX_GEN3_LO		0x582C
156495d67482SBill Paul #define	BGE_LPMBX_GEN4_HI		0x5840
156595d67482SBill Paul #define	BGE_LPMBX_GEN4_LO		0x5844
156695d67482SBill Paul #define	BGE_LPMBX_GEN5_HI		0x5848
156795d67482SBill Paul #define	BGE_LPMBX_GEN5_LO		0x584C
156895d67482SBill Paul #define	BGE_LPMBX_GEN6_HI		0x5850
156995d67482SBill Paul #define	BGE_LPMBX_GEN6_LO		0x5854
157095d67482SBill Paul #define	BGE_LPMBX_GEN7_HI		0x5858
157195d67482SBill Paul #define	BGE_LPMBX_GEN7_LO		0x585C
157295d67482SBill Paul #define	BGE_LPMBX_RELOAD_STATS_HI	0x5860
157395d67482SBill Paul #define	BGE_LPMBX_RELOAD_STATS_LO	0x5864
157495d67482SBill Paul #define	BGE_LPMBX_RX_STD_PROD_HI	0x5868
157595d67482SBill Paul #define	BGE_LPMBX_RX_STD_PROD_LO	0x586C
157695d67482SBill Paul #define	BGE_LPMBX_RX_JUMBO_PROD_HI	0x5870
157795d67482SBill Paul #define	BGE_LPMBX_RX_JUMBO_PROD_LO	0x5874
157895d67482SBill Paul #define	BGE_LPMBX_RX_MINI_PROD_HI	0x5878
157995d67482SBill Paul #define	BGE_LPMBX_RX_MINI_PROD_LO	0x587C
158095d67482SBill Paul #define	BGE_LPMBX_RX_CONS0_HI		0x5880
158195d67482SBill Paul #define	BGE_LPMBX_RX_CONS0_LO		0x5884
158295d67482SBill Paul #define	BGE_LPMBX_RX_CONS1_HI		0x5888
158395d67482SBill Paul #define	BGE_LPMBX_RX_CONS1_LO		0x588C
158495d67482SBill Paul #define	BGE_LPMBX_RX_CONS2_HI		0x5890
158595d67482SBill Paul #define	BGE_LPMBX_RX_CONS2_LO		0x5894
158695d67482SBill Paul #define	BGE_LPMBX_RX_CONS3_HI		0x5898
158795d67482SBill Paul #define	BGE_LPMBX_RX_CONS3_LO		0x589C
158895d67482SBill Paul #define	BGE_LPMBX_RX_CONS4_HI		0x58A0
158995d67482SBill Paul #define	BGE_LPMBX_RX_CONS4_LO		0x58A4
159095d67482SBill Paul #define	BGE_LPMBX_RX_CONS5_HI		0x58A8
159195d67482SBill Paul #define	BGE_LPMBX_RX_CONS5_LO		0x58AC
159295d67482SBill Paul #define	BGE_LPMBX_RX_CONS6_HI		0x58B0
159395d67482SBill Paul #define	BGE_LPMBX_RX_CONS6_LO		0x58B4
159495d67482SBill Paul #define	BGE_LPMBX_RX_CONS7_HI		0x58B8
159595d67482SBill Paul #define	BGE_LPMBX_RX_CONS7_LO		0x58BC
159695d67482SBill Paul #define	BGE_LPMBX_RX_CONS8_HI		0x58C0
159795d67482SBill Paul #define	BGE_LPMBX_RX_CONS8_LO		0x58C4
159895d67482SBill Paul #define	BGE_LPMBX_RX_CONS9_HI		0x58C8
159995d67482SBill Paul #define	BGE_LPMBX_RX_CONS9_LO		0x58CC
160095d67482SBill Paul #define	BGE_LPMBX_RX_CONS10_HI		0x58D0
160195d67482SBill Paul #define	BGE_LPMBX_RX_CONS10_LO		0x58D4
160295d67482SBill Paul #define	BGE_LPMBX_RX_CONS11_HI		0x58D8
160395d67482SBill Paul #define	BGE_LPMBX_RX_CONS11_LO		0x58DC
160495d67482SBill Paul #define	BGE_LPMBX_RX_CONS12_HI		0x58E0
160595d67482SBill Paul #define	BGE_LPMBX_RX_CONS12_LO		0x58E4
160695d67482SBill Paul #define	BGE_LPMBX_RX_CONS13_HI		0x58E8
160795d67482SBill Paul #define	BGE_LPMBX_RX_CONS13_LO		0x58EC
160895d67482SBill Paul #define	BGE_LPMBX_RX_CONS14_HI		0x58F0
160995d67482SBill Paul #define	BGE_LPMBX_RX_CONS14_LO		0x58F4
161095d67482SBill Paul #define	BGE_LPMBX_RX_CONS15_HI		0x58F8
161195d67482SBill Paul #define	BGE_LPMBX_RX_CONS15_LO		0x58FC
161295d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD0_HI	0x5900
161395d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD0_LO	0x5904
161495d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD1_HI	0x5908
161595d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD1_LO	0x590C
161695d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD2_HI	0x5910
161795d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD2_LO	0x5914
161895d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD3_HI	0x5918
161995d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD3_LO	0x591C
162095d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD4_HI	0x5920
162195d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD4_LO	0x5924
162295d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD5_HI	0x5928
162395d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD5_LO	0x592C
162495d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD6_HI	0x5930
162595d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD6_LO	0x5934
162695d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD7_HI	0x5938
162795d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD7_LO	0x593C
162895d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD8_HI	0x5940
162995d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD8_LO	0x5944
163095d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD9_HI	0x5948
163195d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD9_LO	0x594C
163295d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD10_HI	0x5950
163395d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD10_LO	0x5954
163495d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD11_HI	0x5958
163595d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD11_LO	0x595C
163695d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD12_HI	0x5960
163795d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD12_LO	0x5964
163895d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD13_HI	0x5968
163995d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD13_LO	0x596C
164095d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD14_HI	0x5970
164195d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD14_LO	0x5974
164295d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD15_HI	0x5978
164395d67482SBill Paul #define	BGE_LPMBX_TX_HOST_PROD15_LO	0x597C
164495d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD0_HI	0x5980
164595d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD0_LO	0x5984
164695d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD1_HI	0x5988
164795d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD1_LO	0x598C
164895d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD2_HI	0x5990
164995d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD2_LO	0x5994
165095d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD3_HI	0x5998
165195d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD3_LO	0x599C
165295d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD4_HI	0x59A0
165395d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD4_LO	0x59A4
165495d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD5_HI	0x59A8
165595d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD5_LO	0x59AC
165695d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD6_HI	0x59B0
165795d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD6_LO	0x59B4
165895d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD7_HI	0x59B8
165995d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD7_LO	0x59BC
166095d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD8_HI	0x59C0
166195d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD8_LO	0x59C4
166295d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD9_HI	0x59C8
166395d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD9_LO	0x59CC
166495d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD10_HI	0x59D0
166595d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD10_LO	0x59D4
166695d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD11_HI	0x59D8
166795d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD11_LO	0x59DC
166895d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD12_HI	0x59E0
166995d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD12_LO	0x59E4
167095d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD13_HI	0x59E8
167195d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD13_LO	0x59EC
167295d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD14_HI	0x59F0
167395d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD14_LO	0x59F4
167495d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD15_HI	0x59F8
167595d67482SBill Paul #define	BGE_LPMBX_TX_NIC_PROD15_LO	0x59FC
167695d67482SBill Paul 
167795d67482SBill Paul /*
167895d67482SBill Paul  * Flow throw Queue reset register
167995d67482SBill Paul  */
168095d67482SBill Paul #define	BGE_FTQ_RESET			0x5C00
168195d67482SBill Paul 
168295d67482SBill Paul #define	BGE_FTQRESET_DMAREAD		0x00000002
168395d67482SBill Paul #define	BGE_FTQRESET_DMAHIPRIO_RD	0x00000004
168495d67482SBill Paul #define	BGE_FTQRESET_DMADONE		0x00000010
168595d67482SBill Paul #define	BGE_FTQRESET_SBDC		0x00000020
168695d67482SBill Paul #define	BGE_FTQRESET_SDI		0x00000040
168795d67482SBill Paul #define	BGE_FTQRESET_WDMA		0x00000080
168895d67482SBill Paul #define	BGE_FTQRESET_DMAHIPRIO_WR	0x00000100
168995d67482SBill Paul #define	BGE_FTQRESET_TYPE1_SOFTWARE	0x00000200
169095d67482SBill Paul #define	BGE_FTQRESET_SDC		0x00000400
169195d67482SBill Paul #define	BGE_FTQRESET_HCC		0x00000800
169295d67482SBill Paul #define	BGE_FTQRESET_TXFIFO		0x00001000
169395d67482SBill Paul #define	BGE_FTQRESET_MBC		0x00002000
169495d67482SBill Paul #define	BGE_FTQRESET_RBDC		0x00004000
169595d67482SBill Paul #define	BGE_FTQRESET_RXLP		0x00008000
169695d67482SBill Paul #define	BGE_FTQRESET_RDBDI		0x00010000
169795d67482SBill Paul #define	BGE_FTQRESET_RDC		0x00020000
169895d67482SBill Paul #define	BGE_FTQRESET_TYPE2_SOFTWARE	0x00040000
169995d67482SBill Paul 
170095d67482SBill Paul /*
170195d67482SBill Paul  * Message Signaled Interrupt registers
170295d67482SBill Paul  */
170395d67482SBill Paul #define	BGE_MSI_MODE			0x6000
170495d67482SBill Paul #define	BGE_MSI_STATUS			0x6004
170595d67482SBill Paul #define	BGE_MSI_FIFOACCESS		0x6008
170695d67482SBill Paul 
170795d67482SBill Paul /* MSI mode register */
170895d67482SBill Paul #define	BGE_MSIMODE_RESET		0x00000001
170995d67482SBill Paul #define	BGE_MSIMODE_ENABLE		0x00000002
1710c3bbfed4SPyun YongHyeon #define	BGE_MSIMODE_ONE_SHOT_DISABLE	0x00000020
1711c3bbfed4SPyun YongHyeon #define	BGE_MSIMODE_MULTIVEC_ENABLE	0x00000080
171295d67482SBill Paul 
171395d67482SBill Paul /* MSI status register */
171495d67482SBill Paul #define	BGE_MSISTAT_PCI_TGT_ABRT_ATTN	0x00000004
171595d67482SBill Paul #define	BGE_MSISTAT_PCI_MSTR_ABRT_ATTN	0x00000008
171695d67482SBill Paul #define	BGE_MSISTAT_PCI_PERR_ATTN	0x00000010
171795d67482SBill Paul #define	BGE_MSISTAT_MSI_FIFOUFLOW_ATTN	0x00000020
171895d67482SBill Paul #define	BGE_MSISTAT_MSI_FIFOOFLOW_ATTN	0x00000040
171995d67482SBill Paul 
172095d67482SBill Paul 
172195d67482SBill Paul /*
172295d67482SBill Paul  * DMA Completion registers
172395d67482SBill Paul  */
172495d67482SBill Paul #define	BGE_DMAC_MODE			0x6400
172595d67482SBill Paul 
172695d67482SBill Paul /* DMA Completion mode register */
172795d67482SBill Paul #define	BGE_DMACMODE_RESET		0x00000001
172895d67482SBill Paul #define	BGE_DMACMODE_ENABLE		0x00000002
172995d67482SBill Paul 
173095d67482SBill Paul 
173195d67482SBill Paul /*
173295d67482SBill Paul  * General control registers.
173395d67482SBill Paul  */
173495d67482SBill Paul #define	BGE_MODE_CTL			0x6800
173595d67482SBill Paul #define	BGE_MISC_CFG			0x6804
173695d67482SBill Paul #define	BGE_MISC_LOCAL_CTL		0x6808
17378cb1383cSDoug Ambrisko #define	BGE_CPU_EVENT			0x6810
173895d67482SBill Paul #define	BGE_EE_ADDR			0x6838
173995d67482SBill Paul #define	BGE_EE_DATA			0x683C
174095d67482SBill Paul #define	BGE_EE_CTL			0x6840
174195d67482SBill Paul #define	BGE_MDI_CTL			0x6844
174295d67482SBill Paul #define	BGE_EE_DELAY			0x6848
17436f8718a3SScott Long #define	BGE_FASTBOOT_PC			0x6894
174495d67482SBill Paul 
174538cc658fSJohn Baldwin /*
174638cc658fSJohn Baldwin  * NVRAM Control registers
174738cc658fSJohn Baldwin  */
174838cc658fSJohn Baldwin #define	BGE_NVRAM_CMD			0x7000
174938cc658fSJohn Baldwin #define	BGE_NVRAM_STAT			0x7004
175038cc658fSJohn Baldwin #define	BGE_NVRAM_WRDATA		0x7008
175138cc658fSJohn Baldwin #define	BGE_NVRAM_ADDR			0x700c
175238cc658fSJohn Baldwin #define	BGE_NVRAM_RDDATA		0x7010
175338cc658fSJohn Baldwin #define	BGE_NVRAM_CFG1			0x7014
175438cc658fSJohn Baldwin #define	BGE_NVRAM_CFG2			0x7018
175538cc658fSJohn Baldwin #define	BGE_NVRAM_CFG3			0x701c
175638cc658fSJohn Baldwin #define	BGE_NVRAM_SWARB			0x7020
175738cc658fSJohn Baldwin #define	BGE_NVRAM_ACCESS		0x7024
175838cc658fSJohn Baldwin #define	BGE_NVRAM_WRITE1		0x7028
175938cc658fSJohn Baldwin 
176038cc658fSJohn Baldwin #define	BGE_NVRAMCMD_RESET		0x00000001
176138cc658fSJohn Baldwin #define	BGE_NVRAMCMD_DONE		0x00000008
176238cc658fSJohn Baldwin #define	BGE_NVRAMCMD_START		0x00000010
176338cc658fSJohn Baldwin #define	BGE_NVRAMCMD_WR			0x00000020 /* 1 = wr, 0 = rd */
176438cc658fSJohn Baldwin #define	BGE_NVRAMCMD_ERASE		0x00000040
176538cc658fSJohn Baldwin #define	BGE_NVRAMCMD_FIRST		0x00000080
176638cc658fSJohn Baldwin #define	BGE_NVRAMCMD_LAST		0x00000100
176738cc658fSJohn Baldwin 
176838cc658fSJohn Baldwin #define	BGE_NVRAM_READCMD \
176938cc658fSJohn Baldwin 	(BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
177038cc658fSJohn Baldwin 	BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
177138cc658fSJohn Baldwin #define	BGE_NVRAM_WRITECMD \
177238cc658fSJohn Baldwin 	(BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
177338cc658fSJohn Baldwin 	BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
177438cc658fSJohn Baldwin 
177538cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_SET0		0x00000001
177638cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_SET1		0x00000002
177738cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_SET2		0x00000003
177838cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_SET3		0x00000004
177938cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_CLR0		0x00000010
178038cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_CLR1		0x00000020
178138cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_CLR2		0x00000040
178238cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_CLR3		0x00000080
178338cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_GNT0		0x00000100
178438cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_GNT1		0x00000200
178538cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_GNT2		0x00000400
178638cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_GNT3		0x00000800
178738cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_REQ0		0x00001000
178838cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_REQ1		0x00002000
178938cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_REQ2		0x00004000
179038cc658fSJohn Baldwin #define	BGE_NVRAMSWARB_REQ3		0x00008000
179138cc658fSJohn Baldwin 
179238cc658fSJohn Baldwin #define	BGE_NVRAMACC_ENABLE		0x00000001
179338cc658fSJohn Baldwin #define	BGE_NVRAMACC_WRENABLE		0x00000002
179438cc658fSJohn Baldwin 
179595d67482SBill Paul /* Mode control register */
179695d67482SBill Paul #define	BGE_MODECTL_INT_SNDCOAL_ONLY	0x00000001
179795d67482SBill Paul #define	BGE_MODECTL_BYTESWAP_NONFRAME	0x00000002
179895d67482SBill Paul #define	BGE_MODECTL_WORDSWAP_NONFRAME	0x00000004
179995d67482SBill Paul #define	BGE_MODECTL_BYTESWAP_DATA	0x00000010
180095d67482SBill Paul #define	BGE_MODECTL_WORDSWAP_DATA	0x00000020
180195d67482SBill Paul #define	BGE_MODECTL_NO_FRAME_CRACKING	0x00000200
180295d67482SBill Paul #define	BGE_MODECTL_NO_RX_CRC		0x00000400
180395d67482SBill Paul #define	BGE_MODECTL_RX_BADFRAMES	0x00000800
180495d67482SBill Paul #define	BGE_MODECTL_NO_TX_INTR		0x00002000
180595d67482SBill Paul #define	BGE_MODECTL_NO_RX_INTR		0x00004000
180695d67482SBill Paul #define	BGE_MODECTL_FORCE_PCI32		0x00008000
180795d67482SBill Paul #define	BGE_MODECTL_STACKUP		0x00010000
180895d67482SBill Paul #define	BGE_MODECTL_HOST_SEND_BDS	0x00020000
180995d67482SBill Paul #define	BGE_MODECTL_TX_NO_PHDR_CSUM	0x00100000
181095d67482SBill Paul #define	BGE_MODECTL_RX_NO_PHDR_CSUM	0x00800000
181195d67482SBill Paul #define	BGE_MODECTL_TX_ATTN_INTR	0x01000000
181295d67482SBill Paul #define	BGE_MODECTL_RX_ATTN_INTR	0x02000000
181395d67482SBill Paul #define	BGE_MODECTL_MAC_ATTN_INTR	0x04000000
181495d67482SBill Paul #define	BGE_MODECTL_DMA_ATTN_INTR	0x08000000
181595d67482SBill Paul #define	BGE_MODECTL_FLOWCTL_ATTN_INTR	0x10000000
181695d67482SBill Paul #define	BGE_MODECTL_4X_SENDRING_SZ	0x20000000
181795d67482SBill Paul #define	BGE_MODECTL_FW_PROCESS_MCASTS	0x40000000
181895d67482SBill Paul 
181995d67482SBill Paul /* Misc. config register */
182095d67482SBill Paul #define	BGE_MISCCFG_RESET_CORE_CLOCKS	0x00000001
182195d67482SBill Paul #define	BGE_MISCCFG_TIMER_PRESCALER	0x000000FE
18224f0794ffSBjoern A. Zeeb #define	BGE_MISCCFG_BOARD_ID		0x0001E000
18234f0794ffSBjoern A. Zeeb #define	BGE_MISCCFG_BOARD_ID_5788	0x00010000
18244f0794ffSBjoern A. Zeeb #define	BGE_MISCCFG_BOARD_ID_5788M	0x00018000
182538cc658fSJohn Baldwin #define	BGE_MISCCFG_EPHY_IDDQ		0x00200000
182695d67482SBill Paul 
182795d67482SBill Paul #define	BGE_32BITTIME_66MHZ		(0x41 << 1)
182895d67482SBill Paul 
182995d67482SBill Paul /* Misc. Local Control */
183095d67482SBill Paul #define	BGE_MLC_INTR_STATE		0x00000001
183195d67482SBill Paul #define	BGE_MLC_INTR_CLR		0x00000002
183295d67482SBill Paul #define	BGE_MLC_INTR_SET		0x00000004
183395d67482SBill Paul #define	BGE_MLC_INTR_ONATTN		0x00000008
183495d67482SBill Paul #define	BGE_MLC_MISCIO_IN0		0x00000100
183595d67482SBill Paul #define	BGE_MLC_MISCIO_IN1		0x00000200
183695d67482SBill Paul #define	BGE_MLC_MISCIO_IN2		0x00000400
183795d67482SBill Paul #define	BGE_MLC_MISCIO_OUTEN0		0x00000800
183895d67482SBill Paul #define	BGE_MLC_MISCIO_OUTEN1		0x00001000
183995d67482SBill Paul #define	BGE_MLC_MISCIO_OUTEN2		0x00002000
184095d67482SBill Paul #define	BGE_MLC_MISCIO_OUT0		0x00004000
184195d67482SBill Paul #define	BGE_MLC_MISCIO_OUT1		0x00008000
184295d67482SBill Paul #define	BGE_MLC_MISCIO_OUT2		0x00010000
184395d67482SBill Paul #define	BGE_MLC_EXTRAM_ENB		0x00020000
184495d67482SBill Paul #define	BGE_MLC_SRAM_SIZE		0x001C0000
184595d67482SBill Paul #define	BGE_MLC_BANK_SEL		0x00200000 /* 0 = 2 banks, 1 == 1 */
184695d67482SBill Paul #define	BGE_MLC_SSRAM_TYPE		0x00400000 /* 1 = ZBT, 0 = standard */
184795d67482SBill Paul #define	BGE_MLC_SSRAM_CYC_DESEL		0x00800000
184895d67482SBill Paul #define	BGE_MLC_AUTO_EEPROM		0x01000000
184995d67482SBill Paul 
185095d67482SBill Paul #define	BGE_SSRAMSIZE_256KB		0x00000000
185195d67482SBill Paul #define	BGE_SSRAMSIZE_512KB		0x00040000
185295d67482SBill Paul #define	BGE_SSRAMSIZE_1MB		0x00080000
185395d67482SBill Paul #define	BGE_SSRAMSIZE_2MB		0x000C0000
185495d67482SBill Paul #define	BGE_SSRAMSIZE_4MB		0x00100000
185595d67482SBill Paul #define	BGE_SSRAMSIZE_8MB		0x00140000
185695d67482SBill Paul #define	BGE_SSRAMSIZE_16M		0x00180000
185795d67482SBill Paul 
185895d67482SBill Paul /* EEPROM address register */
185995d67482SBill Paul #define	BGE_EEADDR_ADDRESS		0x0000FFFC
186095d67482SBill Paul #define	BGE_EEADDR_HALFCLK		0x01FF0000
186195d67482SBill Paul #define	BGE_EEADDR_START		0x02000000
186295d67482SBill Paul #define	BGE_EEADDR_DEVID		0x1C000000
186395d67482SBill Paul #define	BGE_EEADDR_RESET		0x20000000
186495d67482SBill Paul #define	BGE_EEADDR_DONE			0x40000000
186595d67482SBill Paul #define	BGE_EEADDR_RW			0x80000000 /* 1 = rd, 0 = wr */
186695d67482SBill Paul 
186795d67482SBill Paul #define	BGE_EEDEVID(x)			((x & 7) << 26)
186895d67482SBill Paul #define	BGE_EEHALFCLK(x)		((x & 0x1FF) << 16)
186995d67482SBill Paul #define	BGE_HALFCLK_384SCL		0x60
187095d67482SBill Paul #define	BGE_EE_READCMD \
187195d67482SBill Paul 	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
187295d67482SBill Paul 	BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
187395d67482SBill Paul #define	BGE_EE_WRCMD \
187495d67482SBill Paul 	(BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)|	\
187595d67482SBill Paul 	BGE_EEADDR_START|BGE_EEADDR_DONE)
187695d67482SBill Paul 
187795d67482SBill Paul /* EEPROM Control register */
187895d67482SBill Paul #define	BGE_EECTL_CLKOUT_TRISTATE	0x00000001
187995d67482SBill Paul #define	BGE_EECTL_CLKOUT		0x00000002
188095d67482SBill Paul #define	BGE_EECTL_CLKIN			0x00000004
188195d67482SBill Paul #define	BGE_EECTL_DATAOUT_TRISTATE	0x00000008
188295d67482SBill Paul #define	BGE_EECTL_DATAOUT		0x00000010
188395d67482SBill Paul #define	BGE_EECTL_DATAIN		0x00000020
188495d67482SBill Paul 
188595d67482SBill Paul /* MDI (MII/GMII) access register */
188695d67482SBill Paul #define	BGE_MDI_DATA			0x00000001
188795d67482SBill Paul #define	BGE_MDI_DIR			0x00000002
188895d67482SBill Paul #define	BGE_MDI_SEL			0x00000004
188995d67482SBill Paul #define	BGE_MDI_CLK			0x00000008
189095d67482SBill Paul 
189195d67482SBill Paul #define	BGE_MEMWIN_START		0x00008000
189295d67482SBill Paul #define	BGE_MEMWIN_END			0x0000FFFF
189395d67482SBill Paul 
189495d67482SBill Paul 
189595d67482SBill Paul #define	BGE_MEMWIN_READ(sc, x, val)					\
189695d67482SBill Paul 	do {								\
189795d67482SBill Paul 		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
189895d67482SBill Paul 		    (0xFFFF0000 & x), 4);				\
189995d67482SBill Paul 		val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF));	\
190095d67482SBill Paul 	} while(0)
190195d67482SBill Paul 
190295d67482SBill Paul #define	BGE_MEMWIN_WRITE(sc, x, val)					\
190395d67482SBill Paul 	do {								\
190495d67482SBill Paul 		pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR,	\
190595d67482SBill Paul 		    (0xFFFF0000 & x), 4);				\
190695d67482SBill Paul 		CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val);	\
190795d67482SBill Paul 	} while(0)
190895d67482SBill Paul 
190995d67482SBill Paul /*
191021c9e407SDavid Christensen  * This magic number is written to the firmware mailbox at 0xb50
191121c9e407SDavid Christensen  * before a software reset is issued.  After the internal firmware
191221c9e407SDavid Christensen  * has completed its initialization it will write the opposite of
191321c9e407SDavid Christensen  * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the
191421c9e407SDavid Christensen  * driver to synchronize with the firmware.
191595d67482SBill Paul  */
191695d67482SBill Paul #define	BGE_MAGIC_NUMBER                0x4B657654
191795d67482SBill Paul 
191895d67482SBill Paul typedef struct {
1919a6c21371SGleb Smirnoff 	uint32_t		bge_addr_hi;
1920a6c21371SGleb Smirnoff 	uint32_t		bge_addr_lo;
192195d67482SBill Paul } bge_hostaddr;
1922f41ac2beSBill Paul 
1923487a8c7eSPaul Saab #define	BGE_HOSTADDR(x, y)						\
1924487a8c7eSPaul Saab 	do {								\
1925a6c21371SGleb Smirnoff 		(x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff);	\
1926a6c21371SGleb Smirnoff 		(x).bge_addr_hi = ((uint64_t) (y) >> 32);		\
1927487a8c7eSPaul Saab 	} while(0)
192895d67482SBill Paul 
1929f41ac2beSBill Paul #define	BGE_ADDR_LO(y)	\
1930a6c21371SGleb Smirnoff 	((uint64_t) (y) & 0xFFFFFFFF)
1931f41ac2beSBill Paul #define	BGE_ADDR_HI(y)	\
1932a6c21371SGleb Smirnoff 	((uint64_t) (y) >> 32)
1933f41ac2beSBill Paul 
193495d67482SBill Paul /* Ring control block structure */
193595d67482SBill Paul struct bge_rcb {
193695d67482SBill Paul 	bge_hostaddr		bge_hostaddr;
1937a6c21371SGleb Smirnoff 	uint32_t		bge_maxlen_flags;
1938a6c21371SGleb Smirnoff 	uint32_t		bge_nicaddr;
193995d67482SBill Paul };
1940e907febfSPyun YongHyeon 
1941e907febfSPyun YongHyeon #define	RCB_WRITE_4(sc, rcb, offset, val) \
1942c00cf722SMarius Strobl 	bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
194367111612SJohn Polstra #define	BGE_RCB_MAXLEN_FLAGS(maxlen, flags)	((maxlen) << 16 | (flags))
194495d67482SBill Paul 
194595d67482SBill Paul #define	BGE_RCB_FLAG_USE_EXT_RX_BD	0x0001
194695d67482SBill Paul #define	BGE_RCB_FLAG_RING_DISABLED	0x0002
194795d67482SBill Paul 
194895d67482SBill Paul struct bge_tx_bd {
194995d67482SBill Paul 	bge_hostaddr		bge_addr;
1950e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
1951a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
1952a6c21371SGleb Smirnoff 	uint16_t		bge_len;
1953a6c21371SGleb Smirnoff 	uint16_t		bge_vlan_tag;
1954ca3f1187SPyun YongHyeon 	uint16_t		bge_mss;
1955e907febfSPyun YongHyeon #else
1956a6c21371SGleb Smirnoff 	uint16_t		bge_len;
1957a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
1958ca3f1187SPyun YongHyeon 	uint16_t		bge_mss;
1959a6c21371SGleb Smirnoff 	uint16_t		bge_vlan_tag;
1960e907febfSPyun YongHyeon #endif
196195d67482SBill Paul };
196295d67482SBill Paul 
196395d67482SBill Paul #define	BGE_TXBDFLAG_TCP_UDP_CSUM	0x0001
196495d67482SBill Paul #define	BGE_TXBDFLAG_IP_CSUM		0x0002
196595d67482SBill Paul #define	BGE_TXBDFLAG_END		0x0004
196695d67482SBill Paul #define	BGE_TXBDFLAG_IP_FRAG		0x0008
196795d67482SBill Paul #define	BGE_TXBDFLAG_IP_FRAG_END	0x0010
196895d67482SBill Paul #define	BGE_TXBDFLAG_VLAN_TAG		0x0040
196995d67482SBill Paul #define	BGE_TXBDFLAG_COAL_NOW		0x0080
197095d67482SBill Paul #define	BGE_TXBDFLAG_CPU_PRE_DMA	0x0100
197195d67482SBill Paul #define	BGE_TXBDFLAG_CPU_POST_DMA	0x0200
197295d67482SBill Paul #define	BGE_TXBDFLAG_INSERT_SRC_ADDR	0x1000
197395d67482SBill Paul #define	BGE_TXBDFLAG_CHOOSE_SRC_ADDR	0x6000
197495d67482SBill Paul #define	BGE_TXBDFLAG_NO_CRC		0x8000
197595d67482SBill Paul 
197695d67482SBill Paul #define	BGE_NIC_TXRING_ADDR(ringno, size)	\
197795d67482SBill Paul 	BGE_SEND_RING_1_TO_4 +			\
197895d67482SBill Paul 	((ringno * sizeof(struct bge_tx_bd) * size) / 4)
197995d67482SBill Paul 
198095d67482SBill Paul struct bge_rx_bd {
198195d67482SBill Paul 	bge_hostaddr		bge_addr;
1982e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
1983a6c21371SGleb Smirnoff 	uint16_t		bge_len;
1984a6c21371SGleb Smirnoff 	uint16_t		bge_idx;
1985a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
1986a6c21371SGleb Smirnoff 	uint16_t		bge_type;
1987a6c21371SGleb Smirnoff 	uint16_t		bge_tcp_udp_csum;
1988a6c21371SGleb Smirnoff 	uint16_t		bge_ip_csum;
1989a6c21371SGleb Smirnoff 	uint16_t		bge_vlan_tag;
1990a6c21371SGleb Smirnoff 	uint16_t		bge_error_flag;
1991e907febfSPyun YongHyeon #else
1992a6c21371SGleb Smirnoff 	uint16_t		bge_idx;
1993a6c21371SGleb Smirnoff 	uint16_t		bge_len;
1994a6c21371SGleb Smirnoff 	uint16_t		bge_type;
1995a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
1996a6c21371SGleb Smirnoff 	uint16_t		bge_ip_csum;
1997a6c21371SGleb Smirnoff 	uint16_t		bge_tcp_udp_csum;
1998a6c21371SGleb Smirnoff 	uint16_t		bge_error_flag;
1999a6c21371SGleb Smirnoff 	uint16_t		bge_vlan_tag;
2000e907febfSPyun YongHyeon #endif
2001a6c21371SGleb Smirnoff 	uint32_t		bge_rsvd;
2002a6c21371SGleb Smirnoff 	uint32_t		bge_opaque;
200395d67482SBill Paul };
200495d67482SBill Paul 
20051be6acb7SGleb Smirnoff struct bge_extrx_bd {
20061be6acb7SGleb Smirnoff 	bge_hostaddr		bge_addr1;
20071be6acb7SGleb Smirnoff 	bge_hostaddr		bge_addr2;
20081be6acb7SGleb Smirnoff 	bge_hostaddr		bge_addr3;
2009e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
2010a6c21371SGleb Smirnoff 	uint16_t		bge_len2;
2011a6c21371SGleb Smirnoff 	uint16_t		bge_len1;
2012a6c21371SGleb Smirnoff 	uint16_t		bge_rsvd1;
2013a6c21371SGleb Smirnoff 	uint16_t		bge_len3;
2014e907febfSPyun YongHyeon #else
2015a6c21371SGleb Smirnoff 	uint16_t		bge_len1;
2016a6c21371SGleb Smirnoff 	uint16_t		bge_len2;
2017a6c21371SGleb Smirnoff 	uint16_t		bge_len3;
2018a6c21371SGleb Smirnoff 	uint16_t		bge_rsvd1;
2019e907febfSPyun YongHyeon #endif
20201be6acb7SGleb Smirnoff 	bge_hostaddr		bge_addr0;
2021e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
2022a6c21371SGleb Smirnoff 	uint16_t		bge_len0;
2023a6c21371SGleb Smirnoff 	uint16_t		bge_idx;
2024a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
2025a6c21371SGleb Smirnoff 	uint16_t		bge_type;
2026a6c21371SGleb Smirnoff 	uint16_t		bge_tcp_udp_csum;
2027a6c21371SGleb Smirnoff 	uint16_t		bge_ip_csum;
2028a6c21371SGleb Smirnoff 	uint16_t		bge_vlan_tag;
2029a6c21371SGleb Smirnoff 	uint16_t		bge_error_flag;
2030e907febfSPyun YongHyeon #else
2031a6c21371SGleb Smirnoff 	uint16_t		bge_idx;
2032a6c21371SGleb Smirnoff 	uint16_t		bge_len0;
2033a6c21371SGleb Smirnoff 	uint16_t		bge_type;
2034a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
2035a6c21371SGleb Smirnoff 	uint16_t		bge_ip_csum;
2036a6c21371SGleb Smirnoff 	uint16_t		bge_tcp_udp_csum;
2037a6c21371SGleb Smirnoff 	uint16_t		bge_error_flag;
2038a6c21371SGleb Smirnoff 	uint16_t		bge_vlan_tag;
2039e907febfSPyun YongHyeon #endif
2040a6c21371SGleb Smirnoff 	uint32_t		bge_rsvd0;
2041a6c21371SGleb Smirnoff 	uint32_t		bge_opaque;
20421be6acb7SGleb Smirnoff };
20431be6acb7SGleb Smirnoff 
204495d67482SBill Paul #define	BGE_RXBDFLAG_END		0x0004
204595d67482SBill Paul #define	BGE_RXBDFLAG_JUMBO_RING		0x0020
204695d67482SBill Paul #define	BGE_RXBDFLAG_VLAN_TAG		0x0040
204795d67482SBill Paul #define	BGE_RXBDFLAG_ERROR		0x0400
204895d67482SBill Paul #define	BGE_RXBDFLAG_MINI_RING		0x0800
204995d67482SBill Paul #define	BGE_RXBDFLAG_IP_CSUM		0x1000
205095d67482SBill Paul #define	BGE_RXBDFLAG_TCP_UDP_CSUM	0x2000
205195d67482SBill Paul #define	BGE_RXBDFLAG_TCP_UDP_IS_TCP	0x4000
205295d67482SBill Paul 
205395d67482SBill Paul #define	BGE_RXERRFLAG_BAD_CRC		0x0001
205495d67482SBill Paul #define	BGE_RXERRFLAG_COLL_DETECT	0x0002
205595d67482SBill Paul #define	BGE_RXERRFLAG_LINK_LOST		0x0004
205695d67482SBill Paul #define	BGE_RXERRFLAG_PHY_DECODE_ERR	0x0008
205795d67482SBill Paul #define	BGE_RXERRFLAG_MAC_ABORT		0x0010
205895d67482SBill Paul #define	BGE_RXERRFLAG_RUNT		0x0020
205995d67482SBill Paul #define	BGE_RXERRFLAG_TRUNC_NO_RSRCS	0x0040
206095d67482SBill Paul #define	BGE_RXERRFLAG_GIANT		0x0080
206195d67482SBill Paul 
206295d67482SBill Paul struct bge_sts_idx {
2063e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
2064a6c21371SGleb Smirnoff 	uint16_t		bge_rx_prod_idx;
2065a6c21371SGleb Smirnoff 	uint16_t		bge_tx_cons_idx;
2066e907febfSPyun YongHyeon #else
2067a6c21371SGleb Smirnoff 	uint16_t		bge_tx_cons_idx;
2068a6c21371SGleb Smirnoff 	uint16_t		bge_rx_prod_idx;
2069e907febfSPyun YongHyeon #endif
207095d67482SBill Paul };
207195d67482SBill Paul 
207295d67482SBill Paul struct bge_status_block {
2073a6c21371SGleb Smirnoff 	uint32_t		bge_status;
2074a6c21371SGleb Smirnoff 	uint32_t		bge_rsvd0;
2075e907febfSPyun YongHyeon #if BYTE_ORDER == LITTLE_ENDIAN
2076a6c21371SGleb Smirnoff 	uint16_t		bge_rx_jumbo_cons_idx;
2077a6c21371SGleb Smirnoff 	uint16_t		bge_rx_std_cons_idx;
2078a6c21371SGleb Smirnoff 	uint16_t		bge_rx_mini_cons_idx;
2079a6c21371SGleb Smirnoff 	uint16_t		bge_rsvd1;
2080e907febfSPyun YongHyeon #else
2081a6c21371SGleb Smirnoff 	uint16_t		bge_rx_std_cons_idx;
2082a6c21371SGleb Smirnoff 	uint16_t		bge_rx_jumbo_cons_idx;
2083a6c21371SGleb Smirnoff 	uint16_t		bge_rsvd1;
2084a6c21371SGleb Smirnoff 	uint16_t		bge_rx_mini_cons_idx;
2085e907febfSPyun YongHyeon #endif
208695d67482SBill Paul 	struct bge_sts_idx	bge_idx[16];
208795d67482SBill Paul };
208895d67482SBill Paul 
208995d67482SBill Paul #define	BGE_STATFLAG_UPDATED		0x00000001
209095d67482SBill Paul #define	BGE_STATFLAG_LINKSTATE_CHANGED	0x00000002
209195d67482SBill Paul #define	BGE_STATFLAG_ERROR		0x00000004
209295d67482SBill Paul 
209395d67482SBill Paul 
209495d67482SBill Paul /*
209595d67482SBill Paul  * Broadcom Vendor ID
209695d67482SBill Paul  * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
209795d67482SBill Paul  * even though they're now manufactured by Broadcom)
209895d67482SBill Paul  */
209995d67482SBill Paul #define	BCOM_VENDORID			0x14E4
210095d67482SBill Paul #define	BCOM_DEVICEID_BCM5700		0x1644
210195d67482SBill Paul #define	BCOM_DEVICEID_BCM5701		0x1645
21024c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5702		0x1646
21034c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5702X		0x16A6
21044c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5702_ALT	0x16C6
21054c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5703		0x1647
21064c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5703X		0x16A7
21074c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5703_ALT	0x16C7
21086ac6d2c8SPaul Saab #define	BCOM_DEVICEID_BCM5704C		0x1648
21096ac6d2c8SPaul Saab #define	BCOM_DEVICEID_BCM5704S		0x16A8
21104c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5704S_ALT	0x1649
21110434d1b8SBill Paul #define	BCOM_DEVICEID_BCM5705		0x1653
2112c001ccf2SPaul Saab #define	BCOM_DEVICEID_BCM5705K		0x1654
21134c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5705F		0x166E
21140434d1b8SBill Paul #define	BCOM_DEVICEID_BCM5705M		0x165D
21150434d1b8SBill Paul #define	BCOM_DEVICEID_BCM5705M_ALT	0x165E
2116419c028bSPaul Saab #define	BCOM_DEVICEID_BCM5714C		0x1668
21174c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5714S		0x1669
21184c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5715		0x1678
21194c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5715S		0x1679
21204c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5720		0x1658
21214c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5721		0x1659
21228c9056b5SJohn Baldwin #define	BCOM_DEVICEID_BCM5722		0x165A
2123a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5723		0x165B
2124e53d81eeSPaul Saab #define	BCOM_DEVICEID_BCM5750		0x1676
2125e53d81eeSPaul Saab #define	BCOM_DEVICEID_BCM5750M		0x167C
2126e53d81eeSPaul Saab #define	BCOM_DEVICEID_BCM5751		0x1677
21274c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5751F		0x167E
2128d2014b30STai-hwa Liang #define	BCOM_DEVICEID_BCM5751M		0x167D
2129560c1670SGleb Smirnoff #define	BCOM_DEVICEID_BCM5752		0x1600
21304c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5752M		0x1601
21314c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5753		0x16F7
21324c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5753F		0x16FE
21334c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5753M		0x16FD
21349e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5754		0x167A
21359e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5754M		0x1672
21369e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5755		0x167B
21379e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5755M		0x1673
2138f7d1b2ebSXin LI #define	BCOM_DEVICEID_BCM5756		0x1674
2139a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5761		0x1681
2140a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5761E		0x1680
2141a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5761S		0x1688
2142a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5761SE		0x1689
2143a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5764		0x1684
21444c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5780		0x166A
21454c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5780S		0x166B
21464c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5781		0x16DD
21470434d1b8SBill Paul #define	BCOM_DEVICEID_BCM5782		0x1696
2148a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5784		0x1698
2149a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5785F		0x16a0
2150a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5785G		0x1699
21519e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5786		0x169A
21529e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5787		0x169B
21539e86676bSGleb Smirnoff #define	BCOM_DEVICEID_BCM5787M		0x1693
2154a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM5787F		0x167f
21559f71a4c2SBill Paul #define	BCOM_DEVICEID_BCM5788		0x169C
2156c3615d48SMike Silbersack #define	BCOM_DEVICEID_BCM5789		0x169D
21575d99c641SBill Paul #define	BCOM_DEVICEID_BCM5901		0x170D
21585d99c641SBill Paul #define	BCOM_DEVICEID_BCM5901A2		0x170E
21594c0da0ffSGleb Smirnoff #define	BCOM_DEVICEID_BCM5903M		0x16FF
216038cc658fSJohn Baldwin #define	BCOM_DEVICEID_BCM5906		0x1712
216138cc658fSJohn Baldwin #define	BCOM_DEVICEID_BCM5906M		0x1713
2162a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM57760		0x1690
2163a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM57780		0x1692
2164a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM57788		0x1691
2165a5779553SStanislav Sedov #define	BCOM_DEVICEID_BCM57790		0x1694
216695d67482SBill Paul 
216795d67482SBill Paul /*
216895d67482SBill Paul  * Alteon AceNIC PCI vendor/device ID.
216995d67482SBill Paul  */
21704c0da0ffSGleb Smirnoff #define	ALTEON_VENDORID			0x12AE
21714c0da0ffSGleb Smirnoff #define	ALTEON_DEVICEID_ACENIC		0x0001
21724c0da0ffSGleb Smirnoff #define	ALTEON_DEVICEID_ACENIC_COPPER	0x0002
21734c0da0ffSGleb Smirnoff #define	ALTEON_DEVICEID_BCM5700		0x0003
21744c0da0ffSGleb Smirnoff #define	ALTEON_DEVICEID_BCM5701		0x0004
217595d67482SBill Paul 
217695d67482SBill Paul /*
21779a3fc40aSGleb Smirnoff  * 3Com 3c996 PCI vendor/device ID.
217895d67482SBill Paul  */
217995d67482SBill Paul #define	TC_VENDORID			0x10B7
218095d67482SBill Paul #define	TC_DEVICEID_3C996		0x0003
218195d67482SBill Paul 
218295d67482SBill Paul /*
218395d67482SBill Paul  * SysKonnect PCI vendor ID
218495d67482SBill Paul  */
218595d67482SBill Paul #define	SK_VENDORID			0x1148
218695d67482SBill Paul #define	SK_DEVICEID_ALTIMA		0x4400
218795d67482SBill Paul #define	SK_SUBSYSID_9D21		0x4421
218895d67482SBill Paul #define	SK_SUBSYSID_9D41		0x4441
218995d67482SBill Paul 
219095d67482SBill Paul /*
2191586d7c2eSJohn Polstra  * Altima PCI vendor/device ID.
2192586d7c2eSJohn Polstra  */
2193586d7c2eSJohn Polstra #define	ALTIMA_VENDORID			0x173b
2194586d7c2eSJohn Polstra #define	ALTIMA_DEVICE_AC1000		0x03e8
21952aae6624SBill Paul #define	ALTIMA_DEVICE_AC1002		0x03e9
2196470bd96aSJohn Polstra #define	ALTIMA_DEVICE_AC9100		0x03ea
2197586d7c2eSJohn Polstra 
2198586d7c2eSJohn Polstra /*
21996d2a9bd6SDoug Ambrisko  * Dell PCI vendor ID
22006d2a9bd6SDoug Ambrisko  */
22016d2a9bd6SDoug Ambrisko 
22026d2a9bd6SDoug Ambrisko #define	DELL_VENDORID			0x1028
22036d2a9bd6SDoug Ambrisko 
22046d2a9bd6SDoug Ambrisko /*
22054c0da0ffSGleb Smirnoff  * Apple PCI vendor ID.
22064c0da0ffSGleb Smirnoff  */
22074c0da0ffSGleb Smirnoff #define	APPLE_VENDORID			0x106b
22084c0da0ffSGleb Smirnoff #define	APPLE_DEVICE_BCM5701		0x1645
22094c0da0ffSGleb Smirnoff 
22104c0da0ffSGleb Smirnoff /*
221108013fd3SMarius Strobl  * Sun PCI vendor ID
221208013fd3SMarius Strobl  */
221308013fd3SMarius Strobl #define	SUN_VENDORID			0x108e
221408013fd3SMarius Strobl 
221508013fd3SMarius Strobl /*
2216a5779553SStanislav Sedov  * Fujitsu vendor/device IDs
2217a5779553SStanislav Sedov  */
2218a5779553SStanislav Sedov #define	FJTSU_VENDORID			0x10cf
2219a5779553SStanislav Sedov #define	FJTSU_DEVICEID_PW008GE5		0x11a1
2220a5779553SStanislav Sedov #define	FJTSU_DEVICEID_PW008GE4		0x11a2
2221a5779553SStanislav Sedov #define	FJTSU_DEVICEID_PP250450		0x11cc		/* PRIMEPOWER250/450 LAN */
2222a5779553SStanislav Sedov 
2223a5779553SStanislav Sedov /*
222495d67482SBill Paul  * Offset of MAC address inside EEPROM.
222595d67482SBill Paul  */
222695d67482SBill Paul #define	BGE_EE_MAC_OFFSET		0x7C
222738cc658fSJohn Baldwin #define	BGE_EE_MAC_OFFSET_5906		0x10
222895d67482SBill Paul #define	BGE_EE_HWCFG_OFFSET		0xC8
222995d67482SBill Paul 
2230a1d52896SBill Paul #define	BGE_HWCFG_VOLTAGE		0x00000003
2231a1d52896SBill Paul #define	BGE_HWCFG_PHYLED_MODE		0x0000000C
2232a1d52896SBill Paul #define	BGE_HWCFG_MEDIA			0x00000030
22338cb1383cSDoug Ambrisko #define	BGE_HWCFG_ASF			0x00000080
2234a1d52896SBill Paul 
2235a1d52896SBill Paul #define	BGE_VOLTAGE_1POINT3		0x00000000
2236a1d52896SBill Paul #define	BGE_VOLTAGE_1POINT8		0x00000001
2237a1d52896SBill Paul 
2238a1d52896SBill Paul #define	BGE_PHYLEDMODE_UNSPEC		0x00000000
2239a1d52896SBill Paul #define	BGE_PHYLEDMODE_TRIPLELED	0x00000004
2240a1d52896SBill Paul #define	BGE_PHYLEDMODE_SINGLELED	0x00000008
2241a1d52896SBill Paul 
2242a1d52896SBill Paul #define	BGE_MEDIA_UNSPEC		0x00000000
2243a1d52896SBill Paul #define	BGE_MEDIA_COPPER		0x00000010
2244a1d52896SBill Paul #define	BGE_MEDIA_FIBER			0x00000020
2245a1d52896SBill Paul 
224695d67482SBill Paul #define	BGE_TICKS_PER_SEC		1000000
224795d67482SBill Paul 
224895d67482SBill Paul /*
224995d67482SBill Paul  * Ring size constants.
225095d67482SBill Paul  */
225195d67482SBill Paul #define	BGE_EVENT_RING_CNT	256
225295d67482SBill Paul #define	BGE_CMD_RING_CNT	64
225395d67482SBill Paul #define	BGE_STD_RX_RING_CNT	512
225495d67482SBill Paul #define	BGE_JUMBO_RX_RING_CNT	256
225595d67482SBill Paul #define	BGE_MINI_RX_RING_CNT	1024
225695d67482SBill Paul #define	BGE_RETURN_RING_CNT	1024
225795d67482SBill Paul 
22580434d1b8SBill Paul /* 5705 has smaller return ring size */
22590434d1b8SBill Paul 
22600434d1b8SBill Paul #define	BGE_RETURN_RING_CNT_5705	512
22610434d1b8SBill Paul 
226295d67482SBill Paul /*
226395d67482SBill Paul  * Possible TX ring sizes.
226495d67482SBill Paul  */
226595d67482SBill Paul #define	BGE_TX_RING_CNT_128	128
226695d67482SBill Paul #define	BGE_TX_RING_BASE_128	0x3800
226795d67482SBill Paul 
226895d67482SBill Paul #define	BGE_TX_RING_CNT_256	256
226995d67482SBill Paul #define	BGE_TX_RING_BASE_256	0x3000
227095d67482SBill Paul 
227195d67482SBill Paul #define	BGE_TX_RING_CNT_512	512
227295d67482SBill Paul #define	BGE_TX_RING_BASE_512	0x2000
227395d67482SBill Paul 
227495d67482SBill Paul #define	BGE_TX_RING_CNT		BGE_TX_RING_CNT_512
227595d67482SBill Paul #define	BGE_TX_RING_BASE	BGE_TX_RING_BASE_512
227695d67482SBill Paul 
227795d67482SBill Paul /*
227895d67482SBill Paul  * Tigon III statistics counters.
227995d67482SBill Paul  */
22800434d1b8SBill Paul /* Statistics maintained MAC Receive block. */
22810434d1b8SBill Paul struct bge_rx_mac_stats {
228295d67482SBill Paul 	bge_hostaddr		ifHCInOctets;
228395d67482SBill Paul 	bge_hostaddr		Reserved1;
228495d67482SBill Paul 	bge_hostaddr		etherStatsFragments;
228595d67482SBill Paul 	bge_hostaddr		ifHCInUcastPkts;
228695d67482SBill Paul 	bge_hostaddr		ifHCInMulticastPkts;
228795d67482SBill Paul 	bge_hostaddr		ifHCInBroadcastPkts;
228895d67482SBill Paul 	bge_hostaddr		dot3StatsFCSErrors;
228995d67482SBill Paul 	bge_hostaddr		dot3StatsAlignmentErrors;
229095d67482SBill Paul 	bge_hostaddr		xonPauseFramesReceived;
229195d67482SBill Paul 	bge_hostaddr		xoffPauseFramesReceived;
229295d67482SBill Paul 	bge_hostaddr		macControlFramesReceived;
229395d67482SBill Paul 	bge_hostaddr		xoffStateEntered;
229495d67482SBill Paul 	bge_hostaddr		dot3StatsFramesTooLong;
229595d67482SBill Paul 	bge_hostaddr		etherStatsJabbers;
229695d67482SBill Paul 	bge_hostaddr		etherStatsUndersizePkts;
229795d67482SBill Paul 	bge_hostaddr		inRangeLengthError;
229895d67482SBill Paul 	bge_hostaddr		outRangeLengthError;
229995d67482SBill Paul 	bge_hostaddr		etherStatsPkts64Octets;
230095d67482SBill Paul 	bge_hostaddr		etherStatsPkts65Octetsto127Octets;
230195d67482SBill Paul 	bge_hostaddr		etherStatsPkts128Octetsto255Octets;
230295d67482SBill Paul 	bge_hostaddr		etherStatsPkts256Octetsto511Octets;
230395d67482SBill Paul 	bge_hostaddr		etherStatsPkts512Octetsto1023Octets;
230495d67482SBill Paul 	bge_hostaddr		etherStatsPkts1024Octetsto1522Octets;
230595d67482SBill Paul 	bge_hostaddr		etherStatsPkts1523Octetsto2047Octets;
230695d67482SBill Paul 	bge_hostaddr		etherStatsPkts2048Octetsto4095Octets;
230795d67482SBill Paul 	bge_hostaddr		etherStatsPkts4096Octetsto8191Octets;
230895d67482SBill Paul 	bge_hostaddr		etherStatsPkts8192Octetsto9022Octets;
23090434d1b8SBill Paul };
231095d67482SBill Paul 
231195d67482SBill Paul 
23120434d1b8SBill Paul /* Statistics maintained MAC Transmit block. */
23130434d1b8SBill Paul struct bge_tx_mac_stats {
231495d67482SBill Paul 	bge_hostaddr		ifHCOutOctets;
231595d67482SBill Paul 	bge_hostaddr		Reserved2;
231695d67482SBill Paul 	bge_hostaddr		etherStatsCollisions;
231795d67482SBill Paul 	bge_hostaddr		outXonSent;
231895d67482SBill Paul 	bge_hostaddr		outXoffSent;
231995d67482SBill Paul 	bge_hostaddr		flowControlDone;
232095d67482SBill Paul 	bge_hostaddr		dot3StatsInternalMacTransmitErrors;
232195d67482SBill Paul 	bge_hostaddr		dot3StatsSingleCollisionFrames;
232295d67482SBill Paul 	bge_hostaddr		dot3StatsMultipleCollisionFrames;
232395d67482SBill Paul 	bge_hostaddr		dot3StatsDeferredTransmissions;
232495d67482SBill Paul 	bge_hostaddr		Reserved3;
232595d67482SBill Paul 	bge_hostaddr		dot3StatsExcessiveCollisions;
232695d67482SBill Paul 	bge_hostaddr		dot3StatsLateCollisions;
232795d67482SBill Paul 	bge_hostaddr		dot3Collided2Times;
232895d67482SBill Paul 	bge_hostaddr		dot3Collided3Times;
232995d67482SBill Paul 	bge_hostaddr		dot3Collided4Times;
233095d67482SBill Paul 	bge_hostaddr		dot3Collided5Times;
233195d67482SBill Paul 	bge_hostaddr		dot3Collided6Times;
233295d67482SBill Paul 	bge_hostaddr		dot3Collided7Times;
233395d67482SBill Paul 	bge_hostaddr		dot3Collided8Times;
233495d67482SBill Paul 	bge_hostaddr		dot3Collided9Times;
233595d67482SBill Paul 	bge_hostaddr		dot3Collided10Times;
233695d67482SBill Paul 	bge_hostaddr		dot3Collided11Times;
233795d67482SBill Paul 	bge_hostaddr		dot3Collided12Times;
233895d67482SBill Paul 	bge_hostaddr		dot3Collided13Times;
233995d67482SBill Paul 	bge_hostaddr		dot3Collided14Times;
234095d67482SBill Paul 	bge_hostaddr		dot3Collided15Times;
234195d67482SBill Paul 	bge_hostaddr		ifHCOutUcastPkts;
234295d67482SBill Paul 	bge_hostaddr		ifHCOutMulticastPkts;
234395d67482SBill Paul 	bge_hostaddr		ifHCOutBroadcastPkts;
234495d67482SBill Paul 	bge_hostaddr		dot3StatsCarrierSenseErrors;
234595d67482SBill Paul 	bge_hostaddr		ifOutDiscards;
234695d67482SBill Paul 	bge_hostaddr		ifOutErrors;
23470434d1b8SBill Paul };
23480434d1b8SBill Paul 
23490434d1b8SBill Paul /* Stats counters access through registers */
23500434d1b8SBill Paul struct bge_mac_stats_regs {
2351a6c21371SGleb Smirnoff 	uint32_t		ifHCOutOctets;
2352a6c21371SGleb Smirnoff 	uint32_t		Reserved0;
2353a6c21371SGleb Smirnoff 	uint32_t		etherStatsCollisions;
2354a6c21371SGleb Smirnoff 	uint32_t		outXonSent;
2355a6c21371SGleb Smirnoff 	uint32_t		outXoffSent;
2356a6c21371SGleb Smirnoff 	uint32_t		Reserved1;
2357a6c21371SGleb Smirnoff 	uint32_t		dot3StatsInternalMacTransmitErrors;
2358a6c21371SGleb Smirnoff 	uint32_t		dot3StatsSingleCollisionFrames;
2359a6c21371SGleb Smirnoff 	uint32_t		dot3StatsMultipleCollisionFrames;
2360a6c21371SGleb Smirnoff 	uint32_t		dot3StatsDeferredTransmissions;
2361a6c21371SGleb Smirnoff 	uint32_t		Reserved2;
2362a6c21371SGleb Smirnoff 	uint32_t		dot3StatsExcessiveCollisions;
2363a6c21371SGleb Smirnoff 	uint32_t		dot3StatsLateCollisions;
2364a6c21371SGleb Smirnoff 	uint32_t		Reserved3[14];
2365a6c21371SGleb Smirnoff 	uint32_t		ifHCOutUcastPkts;
2366a6c21371SGleb Smirnoff 	uint32_t		ifHCOutMulticastPkts;
2367a6c21371SGleb Smirnoff 	uint32_t		ifHCOutBroadcastPkts;
2368a6c21371SGleb Smirnoff 	uint32_t		Reserved4[2];
2369a6c21371SGleb Smirnoff 	uint32_t		ifHCInOctets;
2370a6c21371SGleb Smirnoff 	uint32_t		Reserved5;
2371a6c21371SGleb Smirnoff 	uint32_t		etherStatsFragments;
2372a6c21371SGleb Smirnoff 	uint32_t		ifHCInUcastPkts;
2373a6c21371SGleb Smirnoff 	uint32_t		ifHCInMulticastPkts;
2374a6c21371SGleb Smirnoff 	uint32_t		ifHCInBroadcastPkts;
2375a6c21371SGleb Smirnoff 	uint32_t		dot3StatsFCSErrors;
2376a6c21371SGleb Smirnoff 	uint32_t		dot3StatsAlignmentErrors;
2377a6c21371SGleb Smirnoff 	uint32_t		xonPauseFramesReceived;
2378a6c21371SGleb Smirnoff 	uint32_t		xoffPauseFramesReceived;
2379a6c21371SGleb Smirnoff 	uint32_t		macControlFramesReceived;
2380a6c21371SGleb Smirnoff 	uint32_t		xoffStateEntered;
2381a6c21371SGleb Smirnoff 	uint32_t		dot3StatsFramesTooLong;
2382a6c21371SGleb Smirnoff 	uint32_t		etherStatsJabbers;
2383a6c21371SGleb Smirnoff 	uint32_t		etherStatsUndersizePkts;
23840434d1b8SBill Paul };
23850434d1b8SBill Paul 
23860434d1b8SBill Paul struct bge_stats {
2387a6c21371SGleb Smirnoff 	uint8_t		Reserved0[256];
23880434d1b8SBill Paul 
23890434d1b8SBill Paul 	/* Statistics maintained by Receive MAC. */
23900434d1b8SBill Paul 	struct bge_rx_mac_stats rxstats;
23910434d1b8SBill Paul 
23920434d1b8SBill Paul 	bge_hostaddr		Unused1[37];
23930434d1b8SBill Paul 
23940434d1b8SBill Paul 	/* Statistics maintained by Transmit MAC. */
23950434d1b8SBill Paul 	struct bge_tx_mac_stats txstats;
239695d67482SBill Paul 
239795d67482SBill Paul 	bge_hostaddr		Unused2[31];
239895d67482SBill Paul 
239995d67482SBill Paul 	/* Statistics maintained by Receive List Placement. */
240095d67482SBill Paul 	bge_hostaddr		COSIfHCInPkts[16];
240195d67482SBill Paul 	bge_hostaddr		COSFramesDroppedDueToFilters;
240295d67482SBill Paul 	bge_hostaddr		nicDmaWriteQueueFull;
240395d67482SBill Paul 	bge_hostaddr		nicDmaWriteHighPriQueueFull;
240495d67482SBill Paul 	bge_hostaddr		nicNoMoreRxBDs;
240595d67482SBill Paul 	bge_hostaddr		ifInDiscards;
240695d67482SBill Paul 	bge_hostaddr		ifInErrors;
240795d67482SBill Paul 	bge_hostaddr		nicRecvThresholdHit;
240895d67482SBill Paul 
240995d67482SBill Paul 	bge_hostaddr		Unused3[9];
241095d67482SBill Paul 
241195d67482SBill Paul 	/* Statistics maintained by Send Data Initiator. */
241295d67482SBill Paul 	bge_hostaddr		COSIfHCOutPkts[16];
241395d67482SBill Paul 	bge_hostaddr		nicDmaReadQueueFull;
241495d67482SBill Paul 	bge_hostaddr		nicDmaReadHighPriQueueFull;
241595d67482SBill Paul 	bge_hostaddr		nicSendDataCompQueueFull;
241695d67482SBill Paul 
241795d67482SBill Paul 	/* Statistics maintained by Host Coalescing. */
241895d67482SBill Paul 	bge_hostaddr		nicRingSetSendProdIndex;
241995d67482SBill Paul 	bge_hostaddr		nicRingStatusUpdate;
242095d67482SBill Paul 	bge_hostaddr		nicInterrupts;
242195d67482SBill Paul 	bge_hostaddr		nicAvoidedInterrupts;
242295d67482SBill Paul 	bge_hostaddr		nicSendThresholdHit;
242395d67482SBill Paul 
2424a6c21371SGleb Smirnoff 	uint8_t		Reserved4[320];
242595d67482SBill Paul };
242695d67482SBill Paul 
242795d67482SBill Paul /*
242895d67482SBill Paul  * Tigon general information block. This resides in host memory
242995d67482SBill Paul  * and contains the status counters, ring control blocks and
243095d67482SBill Paul  * producer pointers.
243195d67482SBill Paul  */
243295d67482SBill Paul 
243395d67482SBill Paul struct bge_gib {
243495d67482SBill Paul 	struct bge_stats	bge_stats;
243595d67482SBill Paul 	struct bge_rcb		bge_tx_rcb[16];
243695d67482SBill Paul 	struct bge_rcb		bge_std_rx_rcb;
243795d67482SBill Paul 	struct bge_rcb		bge_jumbo_rx_rcb;
243895d67482SBill Paul 	struct bge_rcb		bge_mini_rx_rcb;
243995d67482SBill Paul 	struct bge_rcb		bge_return_rcb;
244095d67482SBill Paul };
244195d67482SBill Paul 
244295d67482SBill Paul #define	BGE_FRAMELEN		1518
244395d67482SBill Paul #define	BGE_MAX_FRAMELEN	1536
244495d67482SBill Paul #define	BGE_JUMBO_FRAMELEN	9018
244595d67482SBill Paul #define	BGE_JUMBO_MTU		(BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
244695d67482SBill Paul #define	BGE_MIN_FRAMELEN		60
244795d67482SBill Paul 
244895d67482SBill Paul /*
244995d67482SBill Paul  * Other utility macros.
245095d67482SBill Paul  */
245195d67482SBill Paul #define	BGE_INC(x, y)	(x) = (x + 1) % y
245295d67482SBill Paul 
245395d67482SBill Paul /*
245495d67482SBill Paul  * Register access macros. The Tigon always uses memory mapped register
245595d67482SBill Paul  * accesses and all registers must be accessed with 32 bit operations.
245695d67482SBill Paul  */
245795d67482SBill Paul 
245895d67482SBill Paul #define	CSR_WRITE_4(sc, reg, val)	\
2459c00cf722SMarius Strobl 	bus_write_4(sc->bge_res, reg, val)
246095d67482SBill Paul 
246195d67482SBill Paul #define	CSR_READ_4(sc, reg)		\
2462c00cf722SMarius Strobl 	bus_read_4(sc->bge_res, reg)
246395d67482SBill Paul 
246495d67482SBill Paul #define	BGE_SETBIT(sc, reg, x)	\
246529f19445SAlfred Perlstein 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
246695d67482SBill Paul #define	BGE_CLRBIT(sc, reg, x)	\
246729f19445SAlfred Perlstein 	CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
246895d67482SBill Paul 
246995d67482SBill Paul #define	PCI_SETBIT(dev, reg, x, s)	\
247029f19445SAlfred Perlstein 	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
247195d67482SBill Paul #define	PCI_CLRBIT(dev, reg, x, s)	\
247229f19445SAlfred Perlstein 	pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
247395d67482SBill Paul 
247495d67482SBill Paul /*
2475*77982948SPyun YongHyeon  * Memory management stuff.
247695d67482SBill Paul  */
247795d67482SBill Paul 
24784e7ba1abSGleb Smirnoff #define	BGE_NSEG_JUMBO	4
24791be6acb7SGleb Smirnoff #define	BGE_NSEG_NEW	32
2480ca3f1187SPyun YongHyeon #define	BGE_TSOSEG_SZ	4096
24811be6acb7SGleb Smirnoff 
2482f681b29aSPyun YongHyeon /* Maximum DMA address for controllers that have 40bit DMA address bug. */
2483f681b29aSPyun YongHyeon #if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
2484f681b29aSPyun YongHyeon #define	BGE_DMA_MAXADDR		BUS_SPACE_MAXADDR
2485f681b29aSPyun YongHyeon #else
2486f681b29aSPyun YongHyeon #define	BGE_DMA_MAXADDR		0xFFFFFFFFFF
2487f681b29aSPyun YongHyeon #endif
2488f681b29aSPyun YongHyeon 
248995d67482SBill Paul /*
249095d67482SBill Paul  * Ring structures. Most of these reside in host memory and we tell
249195d67482SBill Paul  * the NIC where they are via the ring control blocks. The exceptions
249295d67482SBill Paul  * are the tx and command rings, which live in NIC memory and which
249395d67482SBill Paul  * we access via the shared memory window.
249495d67482SBill Paul  */
2495f41ac2beSBill Paul 
249695d67482SBill Paul struct bge_ring_data {
2497f41ac2beSBill Paul 	struct bge_rx_bd	*bge_rx_std_ring;
2498f41ac2beSBill Paul 	bus_addr_t		bge_rx_std_ring_paddr;
24991be6acb7SGleb Smirnoff 	struct bge_extrx_bd	*bge_rx_jumbo_ring;
2500f41ac2beSBill Paul 	bus_addr_t		bge_rx_jumbo_ring_paddr;
2501f41ac2beSBill Paul 	struct bge_rx_bd	*bge_rx_return_ring;
2502f41ac2beSBill Paul 	bus_addr_t		bge_rx_return_ring_paddr;
2503f41ac2beSBill Paul 	struct bge_tx_bd	*bge_tx_ring;
2504f41ac2beSBill Paul 	bus_addr_t		bge_tx_ring_paddr;
2505f41ac2beSBill Paul 	struct bge_status_block	*bge_status_block;
2506f41ac2beSBill Paul 	bus_addr_t		bge_status_block_paddr;
2507f41ac2beSBill Paul 	struct bge_stats	*bge_stats;
2508f41ac2beSBill Paul 	bus_addr_t		bge_stats_paddr;
250995d67482SBill Paul 	struct bge_gib		bge_info;
251095d67482SBill Paul };
251195d67482SBill Paul 
2512f41ac2beSBill Paul #define	BGE_STD_RX_RING_SZ	\
2513f41ac2beSBill Paul 	(sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2514f41ac2beSBill Paul #define	BGE_JUMBO_RX_RING_SZ	\
25151be6acb7SGleb Smirnoff 	(sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2516f41ac2beSBill Paul #define	BGE_TX_RING_SZ		\
2517f41ac2beSBill Paul 	(sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2518f41ac2beSBill Paul #define	BGE_RX_RTN_RING_SZ(x)	\
2519f41ac2beSBill Paul 	(sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2520f41ac2beSBill Paul 
2521f41ac2beSBill Paul #define	BGE_STATUS_BLK_SZ	sizeof (struct bge_status_block)
2522f41ac2beSBill Paul 
2523f41ac2beSBill Paul #define	BGE_STATS_SZ		sizeof (struct bge_stats)
2524f41ac2beSBill Paul 
252595d67482SBill Paul /*
252695d67482SBill Paul  * Mbuf pointers. We need these to keep track of the virtual addresses
252795d67482SBill Paul  * of our mbuf chains since we can only convert from physical to virtual,
252895d67482SBill Paul  * not the other way around.
252995d67482SBill Paul  */
253095d67482SBill Paul struct bge_chain_data {
2531f41ac2beSBill Paul 	bus_dma_tag_t		bge_parent_tag;
2532f41ac2beSBill Paul 	bus_dma_tag_t		bge_rx_std_ring_tag;
2533f41ac2beSBill Paul 	bus_dma_tag_t		bge_rx_jumbo_ring_tag;
2534f41ac2beSBill Paul 	bus_dma_tag_t		bge_rx_return_ring_tag;
2535f41ac2beSBill Paul 	bus_dma_tag_t		bge_tx_ring_tag;
2536f41ac2beSBill Paul 	bus_dma_tag_t		bge_status_tag;
2537f41ac2beSBill Paul 	bus_dma_tag_t		bge_stats_tag;
25380ac56796SPyun YongHyeon 	bus_dma_tag_t		bge_rx_mtag;	/* Rx mbuf mapping tag */
25390ac56796SPyun YongHyeon 	bus_dma_tag_t		bge_tx_mtag;	/* Tx mbuf mapping tag */
25400ac56796SPyun YongHyeon 	bus_dma_tag_t		bge_mtag_jumbo;	/* Jumbo mbuf mapping tag */
2541f41ac2beSBill Paul 	bus_dmamap_t		bge_tx_dmamap[BGE_TX_RING_CNT];
2542943787f3SPyun YongHyeon 	bus_dmamap_t		bge_rx_std_sparemap;
2543f41ac2beSBill Paul 	bus_dmamap_t		bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2544943787f3SPyun YongHyeon 	bus_dmamap_t		bge_rx_jumbo_sparemap;
2545f41ac2beSBill Paul 	bus_dmamap_t		bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2546f41ac2beSBill Paul 	bus_dmamap_t		bge_rx_std_ring_map;
2547f41ac2beSBill Paul 	bus_dmamap_t		bge_rx_jumbo_ring_map;
2548f41ac2beSBill Paul 	bus_dmamap_t		bge_tx_ring_map;
2549f41ac2beSBill Paul 	bus_dmamap_t		bge_rx_return_ring_map;
2550f41ac2beSBill Paul 	bus_dmamap_t		bge_status_map;
2551f41ac2beSBill Paul 	bus_dmamap_t		bge_stats_map;
255295d67482SBill Paul 	struct mbuf		*bge_tx_chain[BGE_TX_RING_CNT];
255395d67482SBill Paul 	struct mbuf		*bge_rx_std_chain[BGE_STD_RX_RING_CNT];
255495d67482SBill Paul 	struct mbuf		*bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2555e0b7b101SPyun YongHyeon 	int			bge_rx_std_seglen[BGE_STD_RX_RING_CNT];
2556e0b7b101SPyun YongHyeon 	int			bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4];
2557f41ac2beSBill Paul };
2558f41ac2beSBill Paul 
2559f41ac2beSBill Paul struct bge_dmamap_arg {
2560f41ac2beSBill Paul 	struct bge_softc	*sc;
2561f41ac2beSBill Paul 	bus_addr_t		bge_busaddr;
2562a6c21371SGleb Smirnoff 	uint16_t		bge_flags;
2563f41ac2beSBill Paul 	int			bge_idx;
2564f41ac2beSBill Paul 	int			bge_maxsegs;
2565f41ac2beSBill Paul 	struct bge_tx_bd	*bge_ring;
256695d67482SBill Paul };
256795d67482SBill Paul 
256895d67482SBill Paul #define	BGE_HWREV_TIGON		0x01
256995d67482SBill Paul #define	BGE_HWREV_TIGON_II	0x02
25700434d1b8SBill Paul #define	BGE_TIMEOUT		100000
257195d67482SBill Paul #define	BGE_TXCONS_UNSET		0xFFFF	/* impossible value */
257295d67482SBill Paul 
257395d67482SBill Paul struct bge_bcom_hack {
257495d67482SBill Paul 	int			reg;
257595d67482SBill Paul 	int			val;
257695d67482SBill Paul };
257795d67482SBill Paul 
25788cb1383cSDoug Ambrisko #define	ASF_ENABLE		1
25798cb1383cSDoug Ambrisko #define	ASF_NEW_HANDSHAKE	2
25808cb1383cSDoug Ambrisko #define	ASF_STACKUP		4
25818cb1383cSDoug Ambrisko 
258295d67482SBill Paul struct bge_softc {
2583fc74a9f9SBrooks Davis 	struct ifnet		*bge_ifp;	/* interface info */
258495d67482SBill Paul 	device_t		bge_dev;
25850f9bd73bSSam Leffler 	struct mtx		bge_mtx;
258695d67482SBill Paul 	device_t		bge_miibus;
258795d67482SBill Paul 	void			*bge_intrhand;
258895d67482SBill Paul 	struct resource		*bge_irq;
258995d67482SBill Paul 	struct resource		*bge_res;
259095d67482SBill Paul 	struct ifmedia		bge_ifmedia;	/* TBI media info */
25910aaf1057SPyun YongHyeon 	int			bge_expcap;
25920aaf1057SPyun YongHyeon 	int			bge_msicap;
25930aaf1057SPyun YongHyeon 	int			bge_pcixcap;
2594652ae483SGleb Smirnoff 	uint32_t		bge_flags;
25955ee49a3aSJung-uk Kim #define	BGE_FLAG_TBI		0x00000001
25965ee49a3aSJung-uk Kim #define	BGE_FLAG_JUMBO		0x00000002
259786543395SJung-uk Kim #define	BGE_FLAG_WIRESPEED	0x00000004
25985fea260fSMarius Strobl #define	BGE_FLAG_EADDR		0x00000008
2599ea3b4127SPyun YongHyeon #define	BGE_FLAG_MII_SERDES	0x00000010
26005ee49a3aSJung-uk Kim #define	BGE_FLAG_MSI		0x00000100
26015ee49a3aSJung-uk Kim #define	BGE_FLAG_PCIX		0x00000200
26025ee49a3aSJung-uk Kim #define	BGE_FLAG_PCIE		0x00000400
2603ca3f1187SPyun YongHyeon #define	BGE_FLAG_TSO		0x00000800
26045ee49a3aSJung-uk Kim #define	BGE_FLAG_5700_FAMILY	0x00001000
26055ee49a3aSJung-uk Kim #define	BGE_FLAG_5705_PLUS	0x00002000
26065ee49a3aSJung-uk Kim #define	BGE_FLAG_5714_FAMILY	0x00004000
26075ee49a3aSJung-uk Kim #define	BGE_FLAG_575X_PLUS	0x00008000
2608a5779553SStanislav Sedov #define	BGE_FLAG_5755_PLUS	0x00010000
2609f681b29aSPyun YongHyeon #define	BGE_FLAG_40BIT_BUG	0x00020000
2610f681b29aSPyun YongHyeon #define	BGE_FLAG_4G_BNDRY_BUG	0x00040000
26115ee49a3aSJung-uk Kim #define	BGE_FLAG_RX_ALIGNBUG	0x00100000
26125ee49a3aSJung-uk Kim #define	BGE_FLAG_NO_3LED	0x00200000
26135ee49a3aSJung-uk Kim #define	BGE_FLAG_ADC_BUG	0x00400000
26145ee49a3aSJung-uk Kim #define	BGE_FLAG_5704_A0_BUG	0x00800000
26155ee49a3aSJung-uk Kim #define	BGE_FLAG_JITTER_BUG	0x01000000
26165ee49a3aSJung-uk Kim #define	BGE_FLAG_BER_BUG	0x02000000
261708bf8bb7SJung-uk Kim #define	BGE_FLAG_ADJUST_TRIM	0x04000000
26181ec4c3a8SJung-uk Kim #define	BGE_FLAG_CRC_BUG	0x08000000
26194f0794ffSBjoern A. Zeeb #define	BGE_FLAG_5788		0x20000000
2620a6c21371SGleb Smirnoff 	uint32_t		bge_chipid;
2621a5779553SStanislav Sedov 	uint32_t		bge_asicrev;
2622a5779553SStanislav Sedov 	uint32_t		bge_chiprev;
26238cb1383cSDoug Ambrisko 	uint8_t			bge_asf_mode;
26248cb1383cSDoug Ambrisko 	uint8_t			bge_asf_count;
2625f41ac2beSBill Paul 	struct bge_ring_data	bge_ldata;	/* rings */
262695d67482SBill Paul 	struct bge_chain_data	bge_cdata;	/* mbufs */
2627a6c21371SGleb Smirnoff 	uint16_t		bge_tx_saved_considx;
2628a6c21371SGleb Smirnoff 	uint16_t		bge_rx_saved_considx;
2629a6c21371SGleb Smirnoff 	uint16_t		bge_ev_saved_considx;
2630a6c21371SGleb Smirnoff 	uint16_t		bge_return_ring_cnt;
2631a6c21371SGleb Smirnoff 	uint16_t		bge_std;	/* current std ring head */
2632a6c21371SGleb Smirnoff 	uint16_t		bge_jumbo;	/* current jumo ring head */
2633a6c21371SGleb Smirnoff 	uint32_t		bge_stat_ticks;
2634a6c21371SGleb Smirnoff 	uint32_t		bge_rx_coal_ticks;
2635a6c21371SGleb Smirnoff 	uint32_t		bge_tx_coal_ticks;
2636a6c21371SGleb Smirnoff 	uint32_t		bge_tx_prodidx;
2637a6c21371SGleb Smirnoff 	uint32_t		bge_rx_max_coal_bds;
2638a6c21371SGleb Smirnoff 	uint32_t		bge_tx_max_coal_bds;
2639a6c21371SGleb Smirnoff 	uint32_t		bge_tx_buf_ratio;
264095d67482SBill Paul 	int			bge_if_flags;
264195d67482SBill Paul 	int			bge_txcnt;
26427b97099dSOleg Bulyzhin 	int			bge_link;	/* link state */
26437b97099dSOleg Bulyzhin 	int			bge_link_evt;	/* pending link event */
2644b74e67fbSGleb Smirnoff 	int			bge_timer;
2645beaa2ae1SPyun YongHyeon 	int			bge_forced_collapse;
26460f9bd73bSSam Leffler 	struct callout		bge_stat_ch;
26477e6e2507SJung-uk Kim 	uint32_t		bge_rx_discards;
26487e6e2507SJung-uk Kim 	uint32_t		bge_tx_discards;
26497e6e2507SJung-uk Kim 	uint32_t		bge_tx_collisions;
265075719184SGleb Smirnoff #ifdef DEVICE_POLLING
265175719184SGleb Smirnoff 	int			rxcycles;
265275719184SGleb Smirnoff #endif /* DEVICE_POLLING */
2653dfe0df9aSPyun YongHyeon 	struct task		bge_intr_task;
2654dfe0df9aSPyun YongHyeon 	struct taskqueue	*bge_tq;
265595d67482SBill Paul };
26560f9bd73bSSam Leffler 
26570f9bd73bSSam Leffler #define	BGE_LOCK_INIT(_sc, _name) \
26580f9bd73bSSam Leffler 	mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
26590f9bd73bSSam Leffler #define	BGE_LOCK(_sc)		mtx_lock(&(_sc)->bge_mtx)
26600f9bd73bSSam Leffler #define	BGE_LOCK_ASSERT(_sc)	mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
26610f9bd73bSSam Leffler #define	BGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->bge_mtx)
26620f9bd73bSSam Leffler #define	BGE_LOCK_DESTROY(_sc)	mtx_destroy(&(_sc)->bge_mtx)
2663