xref: /freebsd/sys/dev/bge/if_bge.c (revision f976241773df2260e6170317080761d1c5814fe5)
1 /*-
2  * SPDX-License-Identifier: BSD-4-Clause
3  *
4  * Copyright (c) 2001 Wind River Systems
5  * Copyright (c) 1997, 1998, 1999, 2001
6  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *	This product includes software developed by Bill Paul.
19  * 4. Neither the name of the author nor the names of any co-contributors
20  *    may be used to endorse or promote products derived from this software
21  *    without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #include <sys/cdefs.h>
37 __FBSDID("$FreeBSD$");
38 
39 /*
40  * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver
41  *
42  * The Broadcom BCM5700 is based on technology originally developed by
43  * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet
44  * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
45  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
46  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
47  * frames, highly configurable RX filtering, and 16 RX and TX queues
48  * (which, along with RX filter rules, can be used for QOS applications).
49  * Other features, such as TCP segmentation, may be available as part
50  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
51  * firmware images can be stored in hardware and need not be compiled
52  * into the driver.
53  *
54  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
55  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
56  *
57  * The BCM5701 is a single-chip solution incorporating both the BCM5700
58  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
59  * does not support external SSRAM.
60  *
61  * Broadcom also produces a variation of the BCM5700 under the "Altima"
62  * brand name, which is functionally similar but lacks PCI-X support.
63  *
64  * Without external SSRAM, you can only have at most 4 TX rings,
65  * and the use of the mini RX ring is disabled. This seems to imply
66  * that these features are simply not available on the BCM5701. As a
67  * result, this driver does not implement any support for the mini RX
68  * ring.
69  */
70 
71 #ifdef HAVE_KERNEL_OPTION_HEADERS
72 #include "opt_device_polling.h"
73 #endif
74 
75 #include <sys/param.h>
76 #include <sys/endian.h>
77 #include <sys/systm.h>
78 #include <sys/sockio.h>
79 #include <sys/mbuf.h>
80 #include <sys/malloc.h>
81 #include <sys/kernel.h>
82 #include <sys/module.h>
83 #include <sys/socket.h>
84 #include <sys/sysctl.h>
85 #include <sys/taskqueue.h>
86 
87 #include <net/debugnet.h>
88 #include <net/if.h>
89 #include <net/if_var.h>
90 #include <net/if_arp.h>
91 #include <net/ethernet.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 
95 #include <net/bpf.h>
96 
97 #include <net/if_types.h>
98 #include <net/if_vlan_var.h>
99 
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 
105 #include <machine/bus.h>
106 #include <machine/resource.h>
107 #include <sys/bus.h>
108 #include <sys/rman.h>
109 
110 #include <dev/mii/mii.h>
111 #include <dev/mii/miivar.h>
112 #include "miidevs.h"
113 #include <dev/mii/brgphyreg.h>
114 
115 #include <dev/pci/pcireg.h>
116 #include <dev/pci/pcivar.h>
117 
118 #include <dev/bge/if_bgereg.h>
119 
120 #define	BGE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP)
121 #define	ETHER_MIN_NOPAD		(ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */
122 
123 MODULE_DEPEND(bge, pci, 1, 1, 1);
124 MODULE_DEPEND(bge, ether, 1, 1, 1);
125 MODULE_DEPEND(bge, miibus, 1, 1, 1);
126 
127 /* "device miibus" required.  See GENERIC if you get errors here. */
128 #include "miibus_if.h"
129 
130 /*
131  * Various supported device vendors/types and their names. Note: the
132  * spec seems to indicate that the hardware still has Alteon's vendor
133  * ID burned into it, though it will always be overriden by the vendor
134  * ID in the EEPROM. Just to be safe, we cover all possibilities.
135  */
136 static const struct bge_type {
137 	uint16_t	bge_vid;
138 	uint16_t	bge_did;
139 } bge_devs[] = {
140 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5700 },
141 	{ ALTEON_VENDORID,	ALTEON_DEVICEID_BCM5701 },
142 
143 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1000 },
144 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC1002 },
145 	{ ALTIMA_VENDORID,	ALTIMA_DEVICE_AC9100 },
146 
147 	{ APPLE_VENDORID,	APPLE_DEVICE_BCM5701 },
148 
149 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5700 },
150 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5701 },
151 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702 },
152 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702_ALT },
153 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5702X },
154 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703 },
155 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703_ALT },
156 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5703X },
157 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704C },
158 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S },
159 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5704S_ALT },
160 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705 },
161 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705F },
162 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705K },
163 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M },
164 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5705M_ALT },
165 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714C },
166 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5714S },
167 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715 },
168 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5715S },
169 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5717 },
170 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5717C },
171 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5718 },
172 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5719 },
173 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5720 },
174 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5721 },
175 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5722 },
176 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5723 },
177 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5725 },
178 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5727 },
179 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750 },
180 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5750M },
181 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751 },
182 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751F },
183 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5751M },
184 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752 },
185 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5752M },
186 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753 },
187 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753F },
188 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5753M },
189 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754 },
190 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5754M },
191 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755 },
192 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5755M },
193 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5756 },
194 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761 },
195 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761E },
196 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761S },
197 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5761SE },
198 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5762 },
199 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5764 },
200 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780 },
201 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5780S },
202 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5781 },
203 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5782 },
204 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5784 },
205 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5785F },
206 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5785G },
207 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5786 },
208 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787 },
209 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787F },
210 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5787M },
211 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5788 },
212 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5789 },
213 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901 },
214 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5901A2 },
215 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5903M },
216 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5906 },
217 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM5906M },
218 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57760 },
219 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57761 },
220 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57762 },
221 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57764 },
222 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57765 },
223 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57766 },
224 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57767 },
225 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57780 },
226 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57781 },
227 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57782 },
228 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57785 },
229 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57786 },
230 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57787 },
231 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57788 },
232 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57790 },
233 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57791 },
234 	{ BCOM_VENDORID,	BCOM_DEVICEID_BCM57795 },
235 
236 	{ SK_VENDORID,		SK_DEVICEID_ALTIMA },
237 
238 	{ TC_VENDORID,		TC_DEVICEID_3C996 },
239 
240 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PW008GE4 },
241 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PW008GE5 },
242 	{ FJTSU_VENDORID,	FJTSU_DEVICEID_PP250450 },
243 
244 	{ 0, 0 }
245 };
246 
247 static const struct bge_vendor {
248 	uint16_t	v_id;
249 	const char	*v_name;
250 } bge_vendors[] = {
251 	{ ALTEON_VENDORID,	"Alteon" },
252 	{ ALTIMA_VENDORID,	"Altima" },
253 	{ APPLE_VENDORID,	"Apple" },
254 	{ BCOM_VENDORID,	"Broadcom" },
255 	{ SK_VENDORID,		"SysKonnect" },
256 	{ TC_VENDORID,		"3Com" },
257 	{ FJTSU_VENDORID,	"Fujitsu" },
258 
259 	{ 0, NULL }
260 };
261 
262 static const struct bge_revision {
263 	uint32_t	br_chipid;
264 	const char	*br_name;
265 } bge_revisions[] = {
266 	{ BGE_CHIPID_BCM5700_A0,	"BCM5700 A0" },
267 	{ BGE_CHIPID_BCM5700_A1,	"BCM5700 A1" },
268 	{ BGE_CHIPID_BCM5700_B0,	"BCM5700 B0" },
269 	{ BGE_CHIPID_BCM5700_B1,	"BCM5700 B1" },
270 	{ BGE_CHIPID_BCM5700_B2,	"BCM5700 B2" },
271 	{ BGE_CHIPID_BCM5700_B3,	"BCM5700 B3" },
272 	{ BGE_CHIPID_BCM5700_ALTIMA,	"BCM5700 Altima" },
273 	{ BGE_CHIPID_BCM5700_C0,	"BCM5700 C0" },
274 	{ BGE_CHIPID_BCM5701_A0,	"BCM5701 A0" },
275 	{ BGE_CHIPID_BCM5701_B0,	"BCM5701 B0" },
276 	{ BGE_CHIPID_BCM5701_B2,	"BCM5701 B2" },
277 	{ BGE_CHIPID_BCM5701_B5,	"BCM5701 B5" },
278 	{ BGE_CHIPID_BCM5703_A0,	"BCM5703 A0" },
279 	{ BGE_CHIPID_BCM5703_A1,	"BCM5703 A1" },
280 	{ BGE_CHIPID_BCM5703_A2,	"BCM5703 A2" },
281 	{ BGE_CHIPID_BCM5703_A3,	"BCM5703 A3" },
282 	{ BGE_CHIPID_BCM5703_B0,	"BCM5703 B0" },
283 	{ BGE_CHIPID_BCM5704_A0,	"BCM5704 A0" },
284 	{ BGE_CHIPID_BCM5704_A1,	"BCM5704 A1" },
285 	{ BGE_CHIPID_BCM5704_A2,	"BCM5704 A2" },
286 	{ BGE_CHIPID_BCM5704_A3,	"BCM5704 A3" },
287 	{ BGE_CHIPID_BCM5704_B0,	"BCM5704 B0" },
288 	{ BGE_CHIPID_BCM5705_A0,	"BCM5705 A0" },
289 	{ BGE_CHIPID_BCM5705_A1,	"BCM5705 A1" },
290 	{ BGE_CHIPID_BCM5705_A2,	"BCM5705 A2" },
291 	{ BGE_CHIPID_BCM5705_A3,	"BCM5705 A3" },
292 	{ BGE_CHIPID_BCM5750_A0,	"BCM5750 A0" },
293 	{ BGE_CHIPID_BCM5750_A1,	"BCM5750 A1" },
294 	{ BGE_CHIPID_BCM5750_A3,	"BCM5750 A3" },
295 	{ BGE_CHIPID_BCM5750_B0,	"BCM5750 B0" },
296 	{ BGE_CHIPID_BCM5750_B1,	"BCM5750 B1" },
297 	{ BGE_CHIPID_BCM5750_C0,	"BCM5750 C0" },
298 	{ BGE_CHIPID_BCM5750_C1,	"BCM5750 C1" },
299 	{ BGE_CHIPID_BCM5750_C2,	"BCM5750 C2" },
300 	{ BGE_CHIPID_BCM5714_A0,	"BCM5714 A0" },
301 	{ BGE_CHIPID_BCM5752_A0,	"BCM5752 A0" },
302 	{ BGE_CHIPID_BCM5752_A1,	"BCM5752 A1" },
303 	{ BGE_CHIPID_BCM5752_A2,	"BCM5752 A2" },
304 	{ BGE_CHIPID_BCM5714_B0,	"BCM5714 B0" },
305 	{ BGE_CHIPID_BCM5714_B3,	"BCM5714 B3" },
306 	{ BGE_CHIPID_BCM5715_A0,	"BCM5715 A0" },
307 	{ BGE_CHIPID_BCM5715_A1,	"BCM5715 A1" },
308 	{ BGE_CHIPID_BCM5715_A3,	"BCM5715 A3" },
309 	{ BGE_CHIPID_BCM5717_A0,	"BCM5717 A0" },
310 	{ BGE_CHIPID_BCM5717_B0,	"BCM5717 B0" },
311 	{ BGE_CHIPID_BCM5717_C0,	"BCM5717 C0" },
312 	{ BGE_CHIPID_BCM5719_A0,	"BCM5719 A0" },
313 	{ BGE_CHIPID_BCM5720_A0,	"BCM5720 A0" },
314 	{ BGE_CHIPID_BCM5755_A0,	"BCM5755 A0" },
315 	{ BGE_CHIPID_BCM5755_A1,	"BCM5755 A1" },
316 	{ BGE_CHIPID_BCM5755_A2,	"BCM5755 A2" },
317 	{ BGE_CHIPID_BCM5722_A0,	"BCM5722 A0" },
318 	{ BGE_CHIPID_BCM5761_A0,	"BCM5761 A0" },
319 	{ BGE_CHIPID_BCM5761_A1,	"BCM5761 A1" },
320 	{ BGE_CHIPID_BCM5762_A0,	"BCM5762 A0" },
321 	{ BGE_CHIPID_BCM5784_A0,	"BCM5784 A0" },
322 	{ BGE_CHIPID_BCM5784_A1,	"BCM5784 A1" },
323 	/* 5754 and 5787 share the same ASIC ID */
324 	{ BGE_CHIPID_BCM5787_A0,	"BCM5754/5787 A0" },
325 	{ BGE_CHIPID_BCM5787_A1,	"BCM5754/5787 A1" },
326 	{ BGE_CHIPID_BCM5787_A2,	"BCM5754/5787 A2" },
327 	{ BGE_CHIPID_BCM5906_A1,	"BCM5906 A1" },
328 	{ BGE_CHIPID_BCM5906_A2,	"BCM5906 A2" },
329 	{ BGE_CHIPID_BCM57765_A0,	"BCM57765 A0" },
330 	{ BGE_CHIPID_BCM57765_B0,	"BCM57765 B0" },
331 	{ BGE_CHIPID_BCM57780_A0,	"BCM57780 A0" },
332 	{ BGE_CHIPID_BCM57780_A1,	"BCM57780 A1" },
333 
334 	{ 0, NULL }
335 };
336 
337 /*
338  * Some defaults for major revisions, so that newer steppings
339  * that we don't know about have a shot at working.
340  */
341 static const struct bge_revision bge_majorrevs[] = {
342 	{ BGE_ASICREV_BCM5700,		"unknown BCM5700" },
343 	{ BGE_ASICREV_BCM5701,		"unknown BCM5701" },
344 	{ BGE_ASICREV_BCM5703,		"unknown BCM5703" },
345 	{ BGE_ASICREV_BCM5704,		"unknown BCM5704" },
346 	{ BGE_ASICREV_BCM5705,		"unknown BCM5705" },
347 	{ BGE_ASICREV_BCM5750,		"unknown BCM5750" },
348 	{ BGE_ASICREV_BCM5714_A0,	"unknown BCM5714" },
349 	{ BGE_ASICREV_BCM5752,		"unknown BCM5752" },
350 	{ BGE_ASICREV_BCM5780,		"unknown BCM5780" },
351 	{ BGE_ASICREV_BCM5714,		"unknown BCM5714" },
352 	{ BGE_ASICREV_BCM5755,		"unknown BCM5755" },
353 	{ BGE_ASICREV_BCM5761,		"unknown BCM5761" },
354 	{ BGE_ASICREV_BCM5784,		"unknown BCM5784" },
355 	{ BGE_ASICREV_BCM5785,		"unknown BCM5785" },
356 	/* 5754 and 5787 share the same ASIC ID */
357 	{ BGE_ASICREV_BCM5787,		"unknown BCM5754/5787" },
358 	{ BGE_ASICREV_BCM5906,		"unknown BCM5906" },
359 	{ BGE_ASICREV_BCM57765,		"unknown BCM57765" },
360 	{ BGE_ASICREV_BCM57766,		"unknown BCM57766" },
361 	{ BGE_ASICREV_BCM57780,		"unknown BCM57780" },
362 	{ BGE_ASICREV_BCM5717,		"unknown BCM5717" },
363 	{ BGE_ASICREV_BCM5719,		"unknown BCM5719" },
364 	{ BGE_ASICREV_BCM5720,		"unknown BCM5720" },
365 	{ BGE_ASICREV_BCM5762,		"unknown BCM5762" },
366 
367 	{ 0, NULL }
368 };
369 
370 #define	BGE_IS_JUMBO_CAPABLE(sc)	((sc)->bge_flags & BGE_FLAG_JUMBO)
371 #define	BGE_IS_5700_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5700_FAMILY)
372 #define	BGE_IS_5705_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5705_PLUS)
373 #define	BGE_IS_5714_FAMILY(sc)		((sc)->bge_flags & BGE_FLAG_5714_FAMILY)
374 #define	BGE_IS_575X_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_575X_PLUS)
375 #define	BGE_IS_5755_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5755_PLUS)
376 #define	BGE_IS_5717_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_5717_PLUS)
377 #define	BGE_IS_57765_PLUS(sc)		((sc)->bge_flags & BGE_FLAG_57765_PLUS)
378 
379 static uint32_t bge_chipid(device_t);
380 static const struct bge_vendor * bge_lookup_vendor(uint16_t);
381 static const struct bge_revision * bge_lookup_rev(uint32_t);
382 
383 typedef int	(*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]);
384 
385 static int bge_probe(device_t);
386 static int bge_attach(device_t);
387 static int bge_detach(device_t);
388 static int bge_suspend(device_t);
389 static int bge_resume(device_t);
390 static void bge_release_resources(struct bge_softc *);
391 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int);
392 static int bge_dma_alloc(struct bge_softc *);
393 static void bge_dma_free(struct bge_softc *);
394 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t,
395     bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *);
396 
397 static void bge_devinfo(struct bge_softc *);
398 static int bge_mbox_reorder(struct bge_softc *);
399 
400 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]);
401 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]);
402 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]);
403 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]);
404 static int bge_get_eaddr(struct bge_softc *, uint8_t[]);
405 
406 static void bge_txeof(struct bge_softc *, uint16_t);
407 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *);
408 static int bge_rxeof(struct bge_softc *, uint16_t, int);
409 
410 static void bge_asf_driver_up (struct bge_softc *);
411 static void bge_tick(void *);
412 static void bge_stats_clear_regs(struct bge_softc *);
413 static void bge_stats_update(struct bge_softc *);
414 static void bge_stats_update_regs(struct bge_softc *);
415 static struct mbuf *bge_check_short_dma(struct mbuf *);
416 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *,
417     uint16_t *, uint16_t *);
418 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *);
419 
420 static void bge_intr(void *);
421 static int bge_msi_intr(void *);
422 static void bge_intr_task(void *, int);
423 static void bge_start(if_t);
424 static void bge_start_locked(if_t);
425 static void bge_start_tx(struct bge_softc *, uint32_t);
426 static int bge_ioctl(if_t, u_long, caddr_t);
427 static void bge_init_locked(struct bge_softc *);
428 static void bge_init(void *);
429 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t);
430 static void bge_stop(struct bge_softc *);
431 static void bge_watchdog(struct bge_softc *);
432 static int bge_shutdown(device_t);
433 static int bge_ifmedia_upd_locked(if_t);
434 static int bge_ifmedia_upd(if_t);
435 static void bge_ifmedia_sts(if_t, struct ifmediareq *);
436 static uint64_t bge_get_counter(if_t, ift_counter);
437 
438 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *);
439 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int);
440 
441 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *);
442 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int);
443 
444 static void bge_setpromisc(struct bge_softc *);
445 static void bge_setmulti(struct bge_softc *);
446 static void bge_setvlan(struct bge_softc *);
447 
448 static __inline void bge_rxreuse_std(struct bge_softc *, int);
449 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int);
450 static int bge_newbuf_std(struct bge_softc *, int);
451 static int bge_newbuf_jumbo(struct bge_softc *, int);
452 static int bge_init_rx_ring_std(struct bge_softc *);
453 static void bge_free_rx_ring_std(struct bge_softc *);
454 static int bge_init_rx_ring_jumbo(struct bge_softc *);
455 static void bge_free_rx_ring_jumbo(struct bge_softc *);
456 static void bge_free_tx_ring(struct bge_softc *);
457 static int bge_init_tx_ring(struct bge_softc *);
458 
459 static int bge_chipinit(struct bge_softc *);
460 static int bge_blockinit(struct bge_softc *);
461 static uint32_t bge_dma_swap_options(struct bge_softc *);
462 
463 static int bge_has_eaddr(struct bge_softc *);
464 static uint32_t bge_readmem_ind(struct bge_softc *, int);
465 static void bge_writemem_ind(struct bge_softc *, int, int);
466 static void bge_writembx(struct bge_softc *, int, int);
467 #ifdef notdef
468 static uint32_t bge_readreg_ind(struct bge_softc *, int);
469 #endif
470 static void bge_writemem_direct(struct bge_softc *, int, int);
471 static void bge_writereg_ind(struct bge_softc *, int, int);
472 
473 static int bge_miibus_readreg(device_t, int, int);
474 static int bge_miibus_writereg(device_t, int, int, int);
475 static void bge_miibus_statchg(device_t);
476 #ifdef DEVICE_POLLING
477 static int bge_poll(if_t ifp, enum poll_cmd cmd, int count);
478 #endif
479 
480 #define	BGE_RESET_SHUTDOWN	0
481 #define	BGE_RESET_START		1
482 #define	BGE_RESET_SUSPEND	2
483 static void bge_sig_post_reset(struct bge_softc *, int);
484 static void bge_sig_legacy(struct bge_softc *, int);
485 static void bge_sig_pre_reset(struct bge_softc *, int);
486 static void bge_stop_fw(struct bge_softc *);
487 static int bge_reset(struct bge_softc *);
488 static void bge_link_upd(struct bge_softc *);
489 
490 static void bge_ape_lock_init(struct bge_softc *);
491 static void bge_ape_read_fw_ver(struct bge_softc *);
492 static int bge_ape_lock(struct bge_softc *, int);
493 static void bge_ape_unlock(struct bge_softc *, int);
494 static void bge_ape_send_event(struct bge_softc *, uint32_t);
495 static void bge_ape_driver_state_change(struct bge_softc *, int);
496 
497 /*
498  * The BGE_REGISTER_DEBUG option is only for low-level debugging.  It may
499  * leak information to untrusted users.  It is also known to cause alignment
500  * traps on certain architectures.
501  */
502 #ifdef BGE_REGISTER_DEBUG
503 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
504 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS);
505 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS);
506 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS);
507 #endif
508 static void bge_add_sysctls(struct bge_softc *);
509 static void bge_add_sysctl_stats_regs(struct bge_softc *,
510     struct sysctl_ctx_list *, struct sysctl_oid_list *);
511 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *,
512     struct sysctl_oid_list *);
513 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS);
514 
515 DEBUGNET_DEFINE(bge);
516 
517 static device_method_t bge_methods[] = {
518 	/* Device interface */
519 	DEVMETHOD(device_probe,		bge_probe),
520 	DEVMETHOD(device_attach,	bge_attach),
521 	DEVMETHOD(device_detach,	bge_detach),
522 	DEVMETHOD(device_shutdown,	bge_shutdown),
523 	DEVMETHOD(device_suspend,	bge_suspend),
524 	DEVMETHOD(device_resume,	bge_resume),
525 
526 	/* MII interface */
527 	DEVMETHOD(miibus_readreg,	bge_miibus_readreg),
528 	DEVMETHOD(miibus_writereg,	bge_miibus_writereg),
529 	DEVMETHOD(miibus_statchg,	bge_miibus_statchg),
530 
531 	DEVMETHOD_END
532 };
533 
534 static driver_t bge_driver = {
535 	"bge",
536 	bge_methods,
537 	sizeof(struct bge_softc)
538 };
539 
540 static devclass_t bge_devclass;
541 
542 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0);
543 MODULE_PNP_INFO("U16:vendor;U16:device", pci, bge, bge_devs,
544     nitems(bge_devs) - 1);
545 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
546 
547 static int bge_allow_asf = 1;
548 
549 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters");
550 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RDTUN, &bge_allow_asf, 0,
551 	"Allow ASF mode if available");
552 
553 static int
554 bge_has_eaddr(struct bge_softc *sc)
555 {
556 	return (1);
557 }
558 
559 static uint32_t
560 bge_readmem_ind(struct bge_softc *sc, int off)
561 {
562 	device_t dev;
563 	uint32_t val;
564 
565 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
566 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
567 		return (0);
568 
569 	dev = sc->bge_dev;
570 
571 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
572 	val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4);
573 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
574 	return (val);
575 }
576 
577 static void
578 bge_writemem_ind(struct bge_softc *sc, int off, int val)
579 {
580 	device_t dev;
581 
582 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
583 	    off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4)
584 		return;
585 
586 	dev = sc->bge_dev;
587 
588 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
589 	pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
590 	pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
591 }
592 
593 #ifdef notdef
594 static uint32_t
595 bge_readreg_ind(struct bge_softc *sc, int off)
596 {
597 	device_t dev;
598 
599 	dev = sc->bge_dev;
600 
601 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
602 	return (pci_read_config(dev, BGE_PCI_REG_DATA, 4));
603 }
604 #endif
605 
606 static void
607 bge_writereg_ind(struct bge_softc *sc, int off, int val)
608 {
609 	device_t dev;
610 
611 	dev = sc->bge_dev;
612 
613 	pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
614 	pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
615 }
616 
617 static void
618 bge_writemem_direct(struct bge_softc *sc, int off, int val)
619 {
620 	CSR_WRITE_4(sc, off, val);
621 }
622 
623 static void
624 bge_writembx(struct bge_softc *sc, int off, int val)
625 {
626 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
627 		off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI;
628 
629 	CSR_WRITE_4(sc, off, val);
630 	if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0)
631 		CSR_READ_4(sc, off);
632 }
633 
634 /*
635  * Clear all stale locks and select the lock for this driver instance.
636  */
637 static void
638 bge_ape_lock_init(struct bge_softc *sc)
639 {
640 	uint32_t bit, regbase;
641 	int i;
642 
643 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
644 		regbase = BGE_APE_LOCK_GRANT;
645 	else
646 		regbase = BGE_APE_PER_LOCK_GRANT;
647 
648 	/* Clear any stale locks. */
649 	for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) {
650 		switch (i) {
651 		case BGE_APE_LOCK_PHY0:
652 		case BGE_APE_LOCK_PHY1:
653 		case BGE_APE_LOCK_PHY2:
654 		case BGE_APE_LOCK_PHY3:
655 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
656 			break;
657 		default:
658 			if (sc->bge_func_addr == 0)
659 				bit = BGE_APE_LOCK_GRANT_DRIVER0;
660 			else
661 				bit = (1 << sc->bge_func_addr);
662 		}
663 		APE_WRITE_4(sc, regbase + 4 * i, bit);
664 	}
665 
666 	/* Select the PHY lock based on the device's function number. */
667 	switch (sc->bge_func_addr) {
668 	case 0:
669 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0;
670 		break;
671 	case 1:
672 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1;
673 		break;
674 	case 2:
675 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2;
676 		break;
677 	case 3:
678 		sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3;
679 		break;
680 	default:
681 		device_printf(sc->bge_dev,
682 		    "PHY lock not supported on this function\n");
683 	}
684 }
685 
686 /*
687  * Check for APE firmware, set flags, and print version info.
688  */
689 static void
690 bge_ape_read_fw_ver(struct bge_softc *sc)
691 {
692 	const char *fwtype;
693 	uint32_t apedata, features;
694 
695 	/* Check for a valid APE signature in shared memory. */
696 	apedata = APE_READ_4(sc, BGE_APE_SEG_SIG);
697 	if (apedata != BGE_APE_SEG_SIG_MAGIC) {
698 		sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE;
699 		return;
700 	}
701 
702 	/* Check if APE firmware is running. */
703 	apedata = APE_READ_4(sc, BGE_APE_FW_STATUS);
704 	if ((apedata & BGE_APE_FW_STATUS_READY) == 0) {
705 		device_printf(sc->bge_dev, "APE signature found "
706 		    "but FW status not ready! 0x%08x\n", apedata);
707 		return;
708 	}
709 
710 	sc->bge_mfw_flags |= BGE_MFW_ON_APE;
711 
712 	/* Fetch the APE firwmare type and version. */
713 	apedata = APE_READ_4(sc, BGE_APE_FW_VERSION);
714 	features = APE_READ_4(sc, BGE_APE_FW_FEATURES);
715 	if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) {
716 		sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI;
717 		fwtype = "NCSI";
718 	} else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) {
719 		sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH;
720 		fwtype = "DASH";
721 	} else
722 		fwtype = "UNKN";
723 
724 	/* Print the APE firmware version. */
725 	device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n",
726 	    fwtype,
727 	    (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT,
728 	    (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT,
729 	    (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT,
730 	    (apedata & BGE_APE_FW_VERSION_BLDMSK));
731 }
732 
733 static int
734 bge_ape_lock(struct bge_softc *sc, int locknum)
735 {
736 	uint32_t bit, gnt, req, status;
737 	int i, off;
738 
739 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
740 		return (0);
741 
742 	/* Lock request/grant registers have different bases. */
743 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761) {
744 		req = BGE_APE_LOCK_REQ;
745 		gnt = BGE_APE_LOCK_GRANT;
746 	} else {
747 		req = BGE_APE_PER_LOCK_REQ;
748 		gnt = BGE_APE_PER_LOCK_GRANT;
749 	}
750 
751 	off = 4 * locknum;
752 
753 	switch (locknum) {
754 	case BGE_APE_LOCK_GPIO:
755 		/* Lock required when using GPIO. */
756 		if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
757 			return (0);
758 		if (sc->bge_func_addr == 0)
759 			bit = BGE_APE_LOCK_REQ_DRIVER0;
760 		else
761 			bit = (1 << sc->bge_func_addr);
762 		break;
763 	case BGE_APE_LOCK_GRC:
764 		/* Lock required to reset the device. */
765 		if (sc->bge_func_addr == 0)
766 			bit = BGE_APE_LOCK_REQ_DRIVER0;
767 		else
768 			bit = (1 << sc->bge_func_addr);
769 		break;
770 	case BGE_APE_LOCK_MEM:
771 		/* Lock required when accessing certain APE memory. */
772 		if (sc->bge_func_addr == 0)
773 			bit = BGE_APE_LOCK_REQ_DRIVER0;
774 		else
775 			bit = (1 << sc->bge_func_addr);
776 		break;
777 	case BGE_APE_LOCK_PHY0:
778 	case BGE_APE_LOCK_PHY1:
779 	case BGE_APE_LOCK_PHY2:
780 	case BGE_APE_LOCK_PHY3:
781 		/* Lock required when accessing PHYs. */
782 		bit = BGE_APE_LOCK_REQ_DRIVER0;
783 		break;
784 	default:
785 		return (EINVAL);
786 	}
787 
788 	/* Request a lock. */
789 	APE_WRITE_4(sc, req + off, bit);
790 
791 	/* Wait up to 1 second to acquire lock. */
792 	for (i = 0; i < 20000; i++) {
793 		status = APE_READ_4(sc, gnt + off);
794 		if (status == bit)
795 			break;
796 		DELAY(50);
797 	}
798 
799 	/* Handle any errors. */
800 	if (status != bit) {
801 		device_printf(sc->bge_dev, "APE lock %d request failed! "
802 		    "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n",
803 		    locknum, req + off, bit & 0xFFFF, gnt + off,
804 		    status & 0xFFFF);
805 		/* Revoke the lock request. */
806 		APE_WRITE_4(sc, gnt + off, bit);
807 		return (EBUSY);
808 	}
809 
810 	return (0);
811 }
812 
813 static void
814 bge_ape_unlock(struct bge_softc *sc, int locknum)
815 {
816 	uint32_t bit, gnt;
817 	int off;
818 
819 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
820 		return;
821 
822 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
823 		gnt = BGE_APE_LOCK_GRANT;
824 	else
825 		gnt = BGE_APE_PER_LOCK_GRANT;
826 
827 	off = 4 * locknum;
828 
829 	switch (locknum) {
830 	case BGE_APE_LOCK_GPIO:
831 		if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
832 			return;
833 		if (sc->bge_func_addr == 0)
834 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
835 		else
836 			bit = (1 << sc->bge_func_addr);
837 		break;
838 	case BGE_APE_LOCK_GRC:
839 		if (sc->bge_func_addr == 0)
840 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
841 		else
842 			bit = (1 << sc->bge_func_addr);
843 		break;
844 	case BGE_APE_LOCK_MEM:
845 		if (sc->bge_func_addr == 0)
846 			bit = BGE_APE_LOCK_GRANT_DRIVER0;
847 		else
848 			bit = (1 << sc->bge_func_addr);
849 		break;
850 	case BGE_APE_LOCK_PHY0:
851 	case BGE_APE_LOCK_PHY1:
852 	case BGE_APE_LOCK_PHY2:
853 	case BGE_APE_LOCK_PHY3:
854 		bit = BGE_APE_LOCK_GRANT_DRIVER0;
855 		break;
856 	default:
857 		return;
858 	}
859 
860 	APE_WRITE_4(sc, gnt + off, bit);
861 }
862 
863 /*
864  * Send an event to the APE firmware.
865  */
866 static void
867 bge_ape_send_event(struct bge_softc *sc, uint32_t event)
868 {
869 	uint32_t apedata;
870 	int i;
871 
872 	/* NCSI does not support APE events. */
873 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
874 		return;
875 
876 	/* Wait up to 1ms for APE to service previous event. */
877 	for (i = 10; i > 0; i--) {
878 		if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0)
879 			break;
880 		apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS);
881 		if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) {
882 			APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event |
883 			    BGE_APE_EVENT_STATUS_EVENT_PENDING);
884 			bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
885 			APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1);
886 			break;
887 		}
888 		bge_ape_unlock(sc, BGE_APE_LOCK_MEM);
889 		DELAY(100);
890 	}
891 	if (i == 0)
892 		device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n",
893 		    event);
894 }
895 
896 static void
897 bge_ape_driver_state_change(struct bge_softc *sc, int kind)
898 {
899 	uint32_t apedata, event;
900 
901 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0)
902 		return;
903 
904 	switch (kind) {
905 	case BGE_RESET_START:
906 		/* If this is the first load, clear the load counter. */
907 		apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG);
908 		if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC)
909 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0);
910 		else {
911 			apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT);
912 			APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata);
913 		}
914 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG,
915 		    BGE_APE_HOST_SEG_SIG_MAGIC);
916 		APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN,
917 		    BGE_APE_HOST_SEG_LEN_MAGIC);
918 
919 		/* Add some version info if bge(4) supports it. */
920 		APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID,
921 		    BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0));
922 		APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR,
923 		    BGE_APE_HOST_BEHAV_NO_PHYLOCK);
924 		APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS,
925 		    BGE_APE_HOST_HEARTBEAT_INT_DISABLE);
926 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
927 		    BGE_APE_HOST_DRVR_STATE_START);
928 		event = BGE_APE_EVENT_STATUS_STATE_START;
929 		break;
930 	case BGE_RESET_SHUTDOWN:
931 		APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE,
932 		    BGE_APE_HOST_DRVR_STATE_UNLOAD);
933 		event = BGE_APE_EVENT_STATUS_STATE_UNLOAD;
934 		break;
935 	case BGE_RESET_SUSPEND:
936 		event = BGE_APE_EVENT_STATUS_STATE_SUSPEND;
937 		break;
938 	default:
939 		return;
940 	}
941 
942 	bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT |
943 	    BGE_APE_EVENT_STATUS_STATE_CHNGE);
944 }
945 
946 /*
947  * Map a single buffer address.
948  */
949 
950 static void
951 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
952 {
953 	struct bge_dmamap_arg *ctx;
954 
955 	if (error)
956 		return;
957 
958 	KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg));
959 
960 	ctx = arg;
961 	ctx->bge_busaddr = segs->ds_addr;
962 }
963 
964 static uint8_t
965 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
966 {
967 	uint32_t access, byte = 0;
968 	int i;
969 
970 	/* Lock. */
971 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
972 	for (i = 0; i < 8000; i++) {
973 		if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1)
974 			break;
975 		DELAY(20);
976 	}
977 	if (i == 8000)
978 		return (1);
979 
980 	/* Enable access. */
981 	access = CSR_READ_4(sc, BGE_NVRAM_ACCESS);
982 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE);
983 
984 	CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc);
985 	CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD);
986 	for (i = 0; i < BGE_TIMEOUT * 10; i++) {
987 		DELAY(10);
988 		if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) {
989 			DELAY(10);
990 			break;
991 		}
992 	}
993 
994 	if (i == BGE_TIMEOUT * 10) {
995 		if_printf(sc->bge_ifp, "nvram read timed out\n");
996 		return (1);
997 	}
998 
999 	/* Get result. */
1000 	byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA);
1001 
1002 	*dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF;
1003 
1004 	/* Disable access. */
1005 	CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access);
1006 
1007 	/* Unlock. */
1008 	CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1);
1009 	CSR_READ_4(sc, BGE_NVRAM_SWARB);
1010 
1011 	return (0);
1012 }
1013 
1014 /*
1015  * Read a sequence of bytes from NVRAM.
1016  */
1017 static int
1018 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1019 {
1020 	int err = 0, i;
1021 	uint8_t byte = 0;
1022 
1023 	if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1024 		return (1);
1025 
1026 	for (i = 0; i < cnt; i++) {
1027 		err = bge_nvram_getbyte(sc, off + i, &byte);
1028 		if (err)
1029 			break;
1030 		*(dest + i) = byte;
1031 	}
1032 
1033 	return (err ? 1 : 0);
1034 }
1035 
1036 /*
1037  * Read a byte of data stored in the EEPROM at address 'addr.' The
1038  * BCM570x supports both the traditional bitbang interface and an
1039  * auto access interface for reading the EEPROM. We use the auto
1040  * access method.
1041  */
1042 static uint8_t
1043 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest)
1044 {
1045 	int i;
1046 	uint32_t byte = 0;
1047 
1048 	/*
1049 	 * Enable use of auto EEPROM access so we can avoid
1050 	 * having to use the bitbang method.
1051 	 */
1052 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
1053 
1054 	/* Reset the EEPROM, load the clock period. */
1055 	CSR_WRITE_4(sc, BGE_EE_ADDR,
1056 	    BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
1057 	DELAY(20);
1058 
1059 	/* Issue the read EEPROM command. */
1060 	CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
1061 
1062 	/* Wait for completion */
1063 	for(i = 0; i < BGE_TIMEOUT * 10; i++) {
1064 		DELAY(10);
1065 		if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
1066 			break;
1067 	}
1068 
1069 	if (i == BGE_TIMEOUT * 10) {
1070 		device_printf(sc->bge_dev, "EEPROM read timed out\n");
1071 		return (1);
1072 	}
1073 
1074 	/* Get result. */
1075 	byte = CSR_READ_4(sc, BGE_EE_DATA);
1076 
1077 	*dest = (byte >> ((addr % 4) * 8)) & 0xFF;
1078 
1079 	return (0);
1080 }
1081 
1082 /*
1083  * Read a sequence of bytes from the EEPROM.
1084  */
1085 static int
1086 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt)
1087 {
1088 	int i, error = 0;
1089 	uint8_t byte = 0;
1090 
1091 	for (i = 0; i < cnt; i++) {
1092 		error = bge_eeprom_getbyte(sc, off + i, &byte);
1093 		if (error)
1094 			break;
1095 		*(dest + i) = byte;
1096 	}
1097 
1098 	return (error ? 1 : 0);
1099 }
1100 
1101 static int
1102 bge_miibus_readreg(device_t dev, int phy, int reg)
1103 {
1104 	struct bge_softc *sc;
1105 	uint32_t val;
1106 	int i;
1107 
1108 	sc = device_get_softc(dev);
1109 
1110 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1111 		return (0);
1112 
1113 	/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1114 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1115 		CSR_WRITE_4(sc, BGE_MI_MODE,
1116 		    sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1117 		DELAY(80);
1118 	}
1119 
1120 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY |
1121 	    BGE_MIPHY(phy) | BGE_MIREG(reg));
1122 
1123 	/* Poll for the PHY register access to complete. */
1124 	for (i = 0; i < BGE_TIMEOUT; i++) {
1125 		DELAY(10);
1126 		val = CSR_READ_4(sc, BGE_MI_COMM);
1127 		if ((val & BGE_MICOMM_BUSY) == 0) {
1128 			DELAY(5);
1129 			val = CSR_READ_4(sc, BGE_MI_COMM);
1130 			break;
1131 		}
1132 	}
1133 
1134 	if (i == BGE_TIMEOUT) {
1135 		device_printf(sc->bge_dev,
1136 		    "PHY read timed out (phy %d, reg %d, val 0x%08x)\n",
1137 		    phy, reg, val);
1138 		val = 0;
1139 	}
1140 
1141 	/* Restore the autopoll bit if necessary. */
1142 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1143 		CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1144 		DELAY(80);
1145 	}
1146 
1147 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1148 
1149 	if (val & BGE_MICOMM_READFAIL)
1150 		return (0);
1151 
1152 	return (val & 0xFFFF);
1153 }
1154 
1155 static int
1156 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
1157 {
1158 	struct bge_softc *sc;
1159 	int i;
1160 
1161 	sc = device_get_softc(dev);
1162 
1163 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906 &&
1164 	    (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL))
1165 		return (0);
1166 
1167 	if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0)
1168 		return (0);
1169 
1170 	/* Clear the autopoll bit if set, otherwise may trigger PCI errors. */
1171 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1172 		CSR_WRITE_4(sc, BGE_MI_MODE,
1173 		    sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL);
1174 		DELAY(80);
1175 	}
1176 
1177 	CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY |
1178 	    BGE_MIPHY(phy) | BGE_MIREG(reg) | val);
1179 
1180 	for (i = 0; i < BGE_TIMEOUT; i++) {
1181 		DELAY(10);
1182 		if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) {
1183 			DELAY(5);
1184 			CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */
1185 			break;
1186 		}
1187 	}
1188 
1189 	/* Restore the autopoll bit if necessary. */
1190 	if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
1191 		CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
1192 		DELAY(80);
1193 	}
1194 
1195 	bge_ape_unlock(sc, sc->bge_phy_ape_lock);
1196 
1197 	if (i == BGE_TIMEOUT)
1198 		device_printf(sc->bge_dev,
1199 		    "PHY write timed out (phy %d, reg %d, val 0x%04x)\n",
1200 		    phy, reg, val);
1201 
1202 	return (0);
1203 }
1204 
1205 static void
1206 bge_miibus_statchg(device_t dev)
1207 {
1208 	struct bge_softc *sc;
1209 	struct mii_data *mii;
1210 	uint32_t mac_mode, rx_mode, tx_mode;
1211 
1212 	sc = device_get_softc(dev);
1213 	if ((if_getdrvflags(sc->bge_ifp) & IFF_DRV_RUNNING) == 0)
1214 		return;
1215 	mii = device_get_softc(sc->bge_miibus);
1216 
1217 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1218 	    (IFM_ACTIVE | IFM_AVALID)) {
1219 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
1220 		case IFM_10_T:
1221 		case IFM_100_TX:
1222 			sc->bge_link = 1;
1223 			break;
1224 		case IFM_1000_T:
1225 		case IFM_1000_SX:
1226 		case IFM_2500_SX:
1227 			if (sc->bge_asicrev != BGE_ASICREV_BCM5906)
1228 				sc->bge_link = 1;
1229 			else
1230 				sc->bge_link = 0;
1231 			break;
1232 		default:
1233 			sc->bge_link = 0;
1234 			break;
1235 		}
1236 	} else
1237 		sc->bge_link = 0;
1238 	if (sc->bge_link == 0)
1239 		return;
1240 
1241 	/*
1242 	 * APE firmware touches these registers to keep the MAC
1243 	 * connected to the outside world.  Try to keep the
1244 	 * accesses atomic.
1245 	 */
1246 
1247 	/* Set the port mode (MII/GMII) to match the link speed. */
1248 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) &
1249 	    ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX);
1250 	tx_mode = CSR_READ_4(sc, BGE_TX_MODE);
1251 	rx_mode = CSR_READ_4(sc, BGE_RX_MODE);
1252 
1253 	if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
1254 	    IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
1255 		mac_mode |= BGE_PORTMODE_GMII;
1256 	else
1257 		mac_mode |= BGE_PORTMODE_MII;
1258 
1259 	/* Set MAC flow control behavior to match link flow control settings. */
1260 	tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE;
1261 	rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE;
1262 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1263 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1264 			tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE;
1265 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1266 			rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE;
1267 	} else
1268 		mac_mode |= BGE_MACMODE_HALF_DUPLEX;
1269 
1270 	CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode);
1271 	DELAY(40);
1272 	CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode);
1273 	CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode);
1274 }
1275 
1276 /*
1277  * Intialize a standard receive ring descriptor.
1278  */
1279 static int
1280 bge_newbuf_std(struct bge_softc *sc, int i)
1281 {
1282 	struct mbuf *m;
1283 	struct bge_rx_bd *r;
1284 	bus_dma_segment_t segs[1];
1285 	bus_dmamap_t map;
1286 	int error, nsegs;
1287 
1288 	if (sc->bge_flags & BGE_FLAG_JUMBO_STD &&
1289 	    (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
1290 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) {
1291 		m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
1292 		if (m == NULL)
1293 			return (ENOBUFS);
1294 		m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1295 	} else {
1296 		m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1297 		if (m == NULL)
1298 			return (ENOBUFS);
1299 		m->m_len = m->m_pkthdr.len = MCLBYTES;
1300 	}
1301 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1302 		m_adj(m, ETHER_ALIGN);
1303 
1304 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag,
1305 	    sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0);
1306 	if (error != 0) {
1307 		m_freem(m);
1308 		return (error);
1309 	}
1310 	if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1311 		bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1312 		    sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD);
1313 		bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1314 		    sc->bge_cdata.bge_rx_std_dmamap[i]);
1315 	}
1316 	map = sc->bge_cdata.bge_rx_std_dmamap[i];
1317 	sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap;
1318 	sc->bge_cdata.bge_rx_std_sparemap = map;
1319 	sc->bge_cdata.bge_rx_std_chain[i] = m;
1320 	sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len;
1321 	r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
1322 	r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1323 	r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1324 	r->bge_flags = BGE_RXBDFLAG_END;
1325 	r->bge_len = segs[0].ds_len;
1326 	r->bge_idx = i;
1327 
1328 	bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1329 	    sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD);
1330 
1331 	return (0);
1332 }
1333 
1334 /*
1335  * Initialize a jumbo receive ring descriptor. This allocates
1336  * a jumbo buffer from the pool managed internally by the driver.
1337  */
1338 static int
1339 bge_newbuf_jumbo(struct bge_softc *sc, int i)
1340 {
1341 	bus_dma_segment_t segs[BGE_NSEG_JUMBO];
1342 	bus_dmamap_t map;
1343 	struct bge_extrx_bd *r;
1344 	struct mbuf *m;
1345 	int error, nsegs;
1346 
1347 	MGETHDR(m, M_NOWAIT, MT_DATA);
1348 	if (m == NULL)
1349 		return (ENOBUFS);
1350 
1351 	if (m_cljget(m, M_NOWAIT, MJUM9BYTES) == NULL) {
1352 		m_freem(m);
1353 		return (ENOBUFS);
1354 	}
1355 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
1356 	if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0)
1357 		m_adj(m, ETHER_ALIGN);
1358 
1359 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo,
1360 	    sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0);
1361 	if (error != 0) {
1362 		m_freem(m);
1363 		return (error);
1364 	}
1365 
1366 	if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1367 		bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1368 		    sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD);
1369 		bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1370 		    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1371 	}
1372 	map = sc->bge_cdata.bge_rx_jumbo_dmamap[i];
1373 	sc->bge_cdata.bge_rx_jumbo_dmamap[i] =
1374 	    sc->bge_cdata.bge_rx_jumbo_sparemap;
1375 	sc->bge_cdata.bge_rx_jumbo_sparemap = map;
1376 	sc->bge_cdata.bge_rx_jumbo_chain[i] = m;
1377 	sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0;
1378 	sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0;
1379 	sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0;
1380 	sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0;
1381 
1382 	/*
1383 	 * Fill in the extended RX buffer descriptor.
1384 	 */
1385 	r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
1386 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
1387 	r->bge_idx = i;
1388 	r->bge_len3 = r->bge_len2 = r->bge_len1 = 0;
1389 	switch (nsegs) {
1390 	case 4:
1391 		r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr);
1392 		r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr);
1393 		r->bge_len3 = segs[3].ds_len;
1394 		sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len;
1395 	case 3:
1396 		r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
1397 		r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
1398 		r->bge_len2 = segs[2].ds_len;
1399 		sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len;
1400 	case 2:
1401 		r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
1402 		r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
1403 		r->bge_len1 = segs[1].ds_len;
1404 		sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len;
1405 	case 1:
1406 		r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
1407 		r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
1408 		r->bge_len0 = segs[0].ds_len;
1409 		sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len;
1410 		break;
1411 	default:
1412 		panic("%s: %d segments\n", __func__, nsegs);
1413 	}
1414 
1415 	bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1416 	    sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD);
1417 
1418 	return (0);
1419 }
1420 
1421 static int
1422 bge_init_rx_ring_std(struct bge_softc *sc)
1423 {
1424 	int error, i;
1425 
1426 	bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ);
1427 	sc->bge_std = 0;
1428 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1429 		if ((error = bge_newbuf_std(sc, i)) != 0)
1430 			return (error);
1431 		BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1432 	}
1433 
1434 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
1435 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
1436 
1437 	sc->bge_std = 0;
1438 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1);
1439 
1440 	return (0);
1441 }
1442 
1443 static void
1444 bge_free_rx_ring_std(struct bge_softc *sc)
1445 {
1446 	int i;
1447 
1448 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
1449 		if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
1450 			bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag,
1451 			    sc->bge_cdata.bge_rx_std_dmamap[i],
1452 			    BUS_DMASYNC_POSTREAD);
1453 			bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag,
1454 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
1455 			m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
1456 			sc->bge_cdata.bge_rx_std_chain[i] = NULL;
1457 		}
1458 		bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i],
1459 		    sizeof(struct bge_rx_bd));
1460 	}
1461 }
1462 
1463 static int
1464 bge_init_rx_ring_jumbo(struct bge_softc *sc)
1465 {
1466 	struct bge_rcb *rcb;
1467 	int error, i;
1468 
1469 	bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ);
1470 	sc->bge_jumbo = 0;
1471 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1472 		if ((error = bge_newbuf_jumbo(sc, i)) != 0)
1473 			return (error);
1474 		BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1475 	}
1476 
1477 	bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
1478 	    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
1479 
1480 	sc->bge_jumbo = 0;
1481 
1482 	/* Enable the jumbo receive producer ring. */
1483 	rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
1484 	rcb->bge_maxlen_flags =
1485 	    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD);
1486 	CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1487 
1488 	bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1);
1489 
1490 	return (0);
1491 }
1492 
1493 static void
1494 bge_free_rx_ring_jumbo(struct bge_softc *sc)
1495 {
1496 	int i;
1497 
1498 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
1499 		if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
1500 			bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo,
1501 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i],
1502 			    BUS_DMASYNC_POSTREAD);
1503 			bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo,
1504 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
1505 			m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
1506 			sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
1507 		}
1508 		bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i],
1509 		    sizeof(struct bge_extrx_bd));
1510 	}
1511 }
1512 
1513 static void
1514 bge_free_tx_ring(struct bge_softc *sc)
1515 {
1516 	int i;
1517 
1518 	if (sc->bge_ldata.bge_tx_ring == NULL)
1519 		return;
1520 
1521 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
1522 		if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
1523 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
1524 			    sc->bge_cdata.bge_tx_dmamap[i],
1525 			    BUS_DMASYNC_POSTWRITE);
1526 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
1527 			    sc->bge_cdata.bge_tx_dmamap[i]);
1528 			m_freem(sc->bge_cdata.bge_tx_chain[i]);
1529 			sc->bge_cdata.bge_tx_chain[i] = NULL;
1530 		}
1531 		bzero((char *)&sc->bge_ldata.bge_tx_ring[i],
1532 		    sizeof(struct bge_tx_bd));
1533 	}
1534 }
1535 
1536 static int
1537 bge_init_tx_ring(struct bge_softc *sc)
1538 {
1539 	sc->bge_txcnt = 0;
1540 	sc->bge_tx_saved_considx = 0;
1541 
1542 	bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ);
1543 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
1544 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
1545 
1546 	/* Initialize transmit producer index for host-memory send ring. */
1547 	sc->bge_tx_prodidx = 0;
1548 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1549 
1550 	/* 5700 b2 errata */
1551 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1552 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx);
1553 
1554 	/* NIC-memory send ring not used; initialize to zero. */
1555 	bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1556 	/* 5700 b2 errata */
1557 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
1558 		bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
1559 
1560 	return (0);
1561 }
1562 
1563 static void
1564 bge_setpromisc(struct bge_softc *sc)
1565 {
1566 	if_t ifp;
1567 
1568 	BGE_LOCK_ASSERT(sc);
1569 
1570 	ifp = sc->bge_ifp;
1571 
1572 	/* Enable or disable promiscuous mode as needed. */
1573 	if (if_getflags(ifp) & IFF_PROMISC)
1574 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1575 	else
1576 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
1577 }
1578 
1579 static u_int
1580 bge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
1581 {
1582 	uint32_t *hashes = arg;
1583 	int h;
1584 
1585 	h = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN) & 0x7F;
1586 	hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
1587 
1588 	return (1);
1589 }
1590 
1591 static void
1592 bge_setmulti(struct bge_softc *sc)
1593 {
1594 	if_t ifp;
1595 	uint32_t hashes[4] = { 0, 0, 0, 0 };
1596 	int i;
1597 
1598 	BGE_LOCK_ASSERT(sc);
1599 
1600 	ifp = sc->bge_ifp;
1601 
1602 	if (if_getflags(ifp) & IFF_ALLMULTI || if_getflags(ifp) & IFF_PROMISC) {
1603 		for (i = 0; i < 4; i++)
1604 			CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
1605 		return;
1606 	}
1607 
1608 	/* First, zot all the existing filters. */
1609 	for (i = 0; i < 4; i++)
1610 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
1611 
1612 	if_foreach_llmaddr(ifp, bge_hash_maddr, hashes);
1613 
1614 	for (i = 0; i < 4; i++)
1615 		CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
1616 }
1617 
1618 static void
1619 bge_setvlan(struct bge_softc *sc)
1620 {
1621 	if_t ifp;
1622 
1623 	BGE_LOCK_ASSERT(sc);
1624 
1625 	ifp = sc->bge_ifp;
1626 
1627 	/* Enable or disable VLAN tag stripping as needed. */
1628 	if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING)
1629 		BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1630 	else
1631 		BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG);
1632 }
1633 
1634 static void
1635 bge_sig_pre_reset(struct bge_softc *sc, int type)
1636 {
1637 
1638 	/*
1639 	 * Some chips don't like this so only do this if ASF is enabled
1640 	 */
1641 	if (sc->bge_asf_mode)
1642 		bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
1643 
1644 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1645 		switch (type) {
1646 		case BGE_RESET_START:
1647 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1648 			    BGE_FW_DRV_STATE_START);
1649 			break;
1650 		case BGE_RESET_SHUTDOWN:
1651 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1652 			    BGE_FW_DRV_STATE_UNLOAD);
1653 			break;
1654 		case BGE_RESET_SUSPEND:
1655 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1656 			    BGE_FW_DRV_STATE_SUSPEND);
1657 			break;
1658 		}
1659 	}
1660 
1661 	if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND)
1662 		bge_ape_driver_state_change(sc, type);
1663 }
1664 
1665 static void
1666 bge_sig_post_reset(struct bge_softc *sc, int type)
1667 {
1668 
1669 	if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) {
1670 		switch (type) {
1671 		case BGE_RESET_START:
1672 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1673 			    BGE_FW_DRV_STATE_START_DONE);
1674 			/* START DONE */
1675 			break;
1676 		case BGE_RESET_SHUTDOWN:
1677 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1678 			    BGE_FW_DRV_STATE_UNLOAD_DONE);
1679 			break;
1680 		}
1681 	}
1682 	if (type == BGE_RESET_SHUTDOWN)
1683 		bge_ape_driver_state_change(sc, type);
1684 }
1685 
1686 static void
1687 bge_sig_legacy(struct bge_softc *sc, int type)
1688 {
1689 
1690 	if (sc->bge_asf_mode) {
1691 		switch (type) {
1692 		case BGE_RESET_START:
1693 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1694 			    BGE_FW_DRV_STATE_START);
1695 			break;
1696 		case BGE_RESET_SHUTDOWN:
1697 			bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB,
1698 			    BGE_FW_DRV_STATE_UNLOAD);
1699 			break;
1700 		}
1701 	}
1702 }
1703 
1704 static void
1705 bge_stop_fw(struct bge_softc *sc)
1706 {
1707 	int i;
1708 
1709 	if (sc->bge_asf_mode) {
1710 		bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE);
1711 		CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
1712 		    CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT);
1713 
1714 		for (i = 0; i < 100; i++ ) {
1715 			if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) &
1716 			    BGE_RX_CPU_DRV_EVENT))
1717 				break;
1718 			DELAY(10);
1719 		}
1720 	}
1721 }
1722 
1723 static uint32_t
1724 bge_dma_swap_options(struct bge_softc *sc)
1725 {
1726 	uint32_t dma_options;
1727 
1728 	dma_options = BGE_MODECTL_WORDSWAP_NONFRAME |
1729 	    BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA;
1730 #if BYTE_ORDER == BIG_ENDIAN
1731 	dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME;
1732 #endif
1733 	return (dma_options);
1734 }
1735 
1736 /*
1737  * Do endian, PCI and DMA initialization.
1738  */
1739 static int
1740 bge_chipinit(struct bge_softc *sc)
1741 {
1742 	uint32_t dma_rw_ctl, misc_ctl, mode_ctl;
1743 	uint16_t val;
1744 	int i;
1745 
1746 	/* Set endianness before we access any non-PCI registers. */
1747 	misc_ctl = BGE_INIT;
1748 	if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS)
1749 		misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS;
1750 	pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4);
1751 
1752 	/*
1753 	 * Clear the MAC statistics block in the NIC's
1754 	 * internal memory.
1755 	 */
1756 	for (i = BGE_STATS_BLOCK;
1757 	    i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1758 		BGE_MEMWIN_WRITE(sc, i, 0);
1759 
1760 	for (i = BGE_STATUS_BLOCK;
1761 	    i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1762 		BGE_MEMWIN_WRITE(sc, i, 0);
1763 
1764 	if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) {
1765 		/*
1766 		 *  Fix data corruption caused by non-qword write with WB.
1767 		 *  Fix master abort in PCI mode.
1768 		 *  Fix PCI latency timer.
1769 		 */
1770 		val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2);
1771 		val |= (1 << 10) | (1 << 12) | (1 << 13);
1772 		pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2);
1773 	}
1774 
1775 	if (sc->bge_asicrev == BGE_ASICREV_BCM57765 ||
1776 	    sc->bge_asicrev == BGE_ASICREV_BCM57766) {
1777 		/*
1778 		 * For the 57766 and non Ax versions of 57765, bootcode
1779 		 * needs to setup the PCIE Fast Training Sequence (FTS)
1780 		 * value to prevent transmit hangs.
1781 		 */
1782 		if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) {
1783 			CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL,
1784 			    CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) |
1785 			    BGE_CPMU_PADRNG_CTL_RDIV2);
1786 		}
1787 	}
1788 
1789 	/*
1790 	 * Set up the PCI DMA control register.
1791 	 */
1792 	dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1793 	    BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1794 	if (sc->bge_flags & BGE_FLAG_PCIE) {
1795 		if (sc->bge_mps >= 256)
1796 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1797 		else
1798 			dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1799 	} else if (sc->bge_flags & BGE_FLAG_PCIX) {
1800 		if (BGE_IS_5714_FAMILY(sc)) {
1801 			/* 256 bytes for read and write. */
1802 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1803 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1804 			dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1805 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1806 			    BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;
1807 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
1808 			/*
1809 			 * In the BCM5703, the DMA read watermark should
1810 			 * be set to less than or equal to the maximum
1811 			 * memory read byte count of the PCI-X command
1812 			 * register.
1813 			 */
1814 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) |
1815 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1816 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1817 			/* 1536 bytes for read, 384 bytes for write. */
1818 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1819 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1820 		} else {
1821 			/* 384 bytes for read and write. */
1822 			dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) |
1823 			    BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) |
1824 			    0x0F;
1825 		}
1826 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1827 		    sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1828 			uint32_t tmp;
1829 
1830 			/* Set ONE_DMA_AT_ONCE for hardware workaround. */
1831 			tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
1832 			if (tmp == 6 || tmp == 7)
1833 				dma_rw_ctl |=
1834 				    BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL;
1835 
1836 			/* Set PCI-X DMA write workaround. */
1837 			dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE;
1838 		}
1839 	} else {
1840 		/* Conventional PCI bus: 256 bytes for read and write. */
1841 		dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) |
1842 		    BGE_PCIDMARWCTL_WR_WAT_SHIFT(7);
1843 
1844 		if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1845 		    sc->bge_asicrev != BGE_ASICREV_BCM5750)
1846 			dma_rw_ctl |= 0x0F;
1847 	}
1848 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
1849 	    sc->bge_asicrev == BGE_ASICREV_BCM5701)
1850 		dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM |
1851 		    BGE_PCIDMARWCTL_ASRT_ALL_BE;
1852 	if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1853 	    sc->bge_asicrev == BGE_ASICREV_BCM5704)
1854 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1855 	if (BGE_IS_5717_PLUS(sc)) {
1856 		dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT;
1857 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
1858 			dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK;
1859 		/*
1860 		 * Enable HW workaround for controllers that misinterpret
1861 		 * a status tag update and leave interrupts permanently
1862 		 * disabled.
1863 		 */
1864 		if (!BGE_IS_57765_PLUS(sc) &&
1865 		    sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
1866 		    sc->bge_asicrev != BGE_ASICREV_BCM5762)
1867 			dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA;
1868 	}
1869 	pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1870 
1871 	/*
1872 	 * Set up general mode register.
1873 	 */
1874 	mode_ctl = bge_dma_swap_options(sc);
1875 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
1876 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
1877 		/* Retain Host-2-BMC settings written by APE firmware. */
1878 		mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) &
1879 		    (BGE_MODECTL_BYTESWAP_B2HRX_DATA |
1880 		    BGE_MODECTL_WORDSWAP_B2HRX_DATA |
1881 		    BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE);
1882 	}
1883 	mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS |
1884 	    BGE_MODECTL_TX_NO_PHDR_CSUM;
1885 
1886 	/*
1887 	 * BCM5701 B5 have a bug causing data corruption when using
1888 	 * 64-bit DMA reads, which can be terminated early and then
1889 	 * completed later as 32-bit accesses, in combination with
1890 	 * certain bridges.
1891 	 */
1892 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
1893 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B5)
1894 		mode_ctl |= BGE_MODECTL_FORCE_PCI32;
1895 
1896 	/*
1897 	 * Tell the firmware the driver is running
1898 	 */
1899 	if (sc->bge_asf_mode & ASF_STACKUP)
1900 		mode_ctl |= BGE_MODECTL_STACKUP;
1901 
1902 	CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl);
1903 
1904 	/*
1905 	 * Disable memory write invalidate.  Apparently it is not supported
1906 	 * properly by these devices.
1907 	 */
1908 	PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1909 
1910 	/* Set the timer prescaler (always 66 MHz). */
1911 	CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ);
1912 
1913 	/* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */
1914 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1915 		DELAY(40);	/* XXX */
1916 
1917 		/* Put PHY into ready state */
1918 		BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ);
1919 		CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */
1920 		DELAY(40);
1921 	}
1922 
1923 	return (0);
1924 }
1925 
1926 static int
1927 bge_blockinit(struct bge_softc *sc)
1928 {
1929 	struct bge_rcb *rcb;
1930 	bus_size_t vrcb;
1931 	bge_hostaddr taddr;
1932 	uint32_t dmactl, rdmareg, val;
1933 	int i, limit;
1934 
1935 	/*
1936 	 * Initialize the memory window pointer register so that
1937 	 * we can access the first 32K of internal NIC RAM. This will
1938 	 * allow us to set up the TX send ring RCBs and the RX return
1939 	 * ring RCBs, plus other things which live in NIC memory.
1940 	 */
1941 	CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1942 
1943 	/* Note: the BCM5704 has a smaller mbuf space than other chips. */
1944 
1945 	if (!(BGE_IS_5705_PLUS(sc))) {
1946 		/* Configure mbuf memory pool */
1947 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1);
1948 		if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1949 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1950 		else
1951 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1952 
1953 		/* Configure DMA resource pool */
1954 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1955 		    BGE_DMA_DESCRIPTORS);
1956 		CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1957 	}
1958 
1959 	/* Configure mbuf pool watermarks */
1960 	if (BGE_IS_5717_PLUS(sc)) {
1961 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1962 		if (if_getmtu(sc->bge_ifp) > ETHERMTU) {
1963 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e);
1964 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea);
1965 		} else {
1966 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a);
1967 			CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0);
1968 		}
1969 	} else if (!BGE_IS_5705_PLUS(sc)) {
1970 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1971 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1972 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1973 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
1974 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1975 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04);
1976 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10);
1977 	} else {
1978 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1979 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1980 		CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1981 	}
1982 
1983 	/* Configure DMA resource watermarks */
1984 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1985 	CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1986 
1987 	/* Enable buffer manager */
1988 	val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN;
1989 	/*
1990 	 * Change the arbitration algorithm of TXMBUF read request to
1991 	 * round-robin instead of priority based for BCM5719.  When
1992 	 * TXFIFO is almost empty, RDMA will hold its request until
1993 	 * TXFIFO is not almost empty.
1994 	 */
1995 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
1996 		val |= BGE_BMANMODE_NO_TX_UNDERRUN;
1997 	CSR_WRITE_4(sc, BGE_BMAN_MODE, val);
1998 
1999 	/* Poll for buffer manager start indication */
2000 	for (i = 0; i < BGE_TIMEOUT; i++) {
2001 		DELAY(10);
2002 		if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
2003 			break;
2004 	}
2005 
2006 	if (i == BGE_TIMEOUT) {
2007 		device_printf(sc->bge_dev, "buffer manager failed to start\n");
2008 		return (ENXIO);
2009 	}
2010 
2011 	/* Enable flow-through queues */
2012 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2013 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2014 
2015 	/* Wait until queue initialization is complete */
2016 	for (i = 0; i < BGE_TIMEOUT; i++) {
2017 		DELAY(10);
2018 		if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
2019 			break;
2020 	}
2021 
2022 	if (i == BGE_TIMEOUT) {
2023 		device_printf(sc->bge_dev, "flow-through queue init failed\n");
2024 		return (ENXIO);
2025 	}
2026 
2027 	/*
2028 	 * Summary of rings supported by the controller:
2029 	 *
2030 	 * Standard Receive Producer Ring
2031 	 * - This ring is used to feed receive buffers for "standard"
2032 	 *   sized frames (typically 1536 bytes) to the controller.
2033 	 *
2034 	 * Jumbo Receive Producer Ring
2035 	 * - This ring is used to feed receive buffers for jumbo sized
2036 	 *   frames (i.e. anything bigger than the "standard" frames)
2037 	 *   to the controller.
2038 	 *
2039 	 * Mini Receive Producer Ring
2040 	 * - This ring is used to feed receive buffers for "mini"
2041 	 *   sized frames to the controller.
2042 	 * - This feature required external memory for the controller
2043 	 *   but was never used in a production system.  Should always
2044 	 *   be disabled.
2045 	 *
2046 	 * Receive Return Ring
2047 	 * - After the controller has placed an incoming frame into a
2048 	 *   receive buffer that buffer is moved into a receive return
2049 	 *   ring.  The driver is then responsible to passing the
2050 	 *   buffer up to the stack.  Many versions of the controller
2051 	 *   support multiple RR rings.
2052 	 *
2053 	 * Send Ring
2054 	 * - This ring is used for outgoing frames.  Many versions of
2055 	 *   the controller support multiple send rings.
2056 	 */
2057 
2058 	/* Initialize the standard receive producer ring control block. */
2059 	rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb;
2060 	rcb->bge_hostaddr.bge_addr_lo =
2061 	    BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr);
2062 	rcb->bge_hostaddr.bge_addr_hi =
2063 	    BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr);
2064 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
2065 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD);
2066 	if (BGE_IS_5717_PLUS(sc)) {
2067 		/*
2068 		 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32)
2069 		 * Bits 15-2 : Maximum RX frame size
2070 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring ENabled
2071 		 * Bit 0     : Reserved
2072 		 */
2073 		rcb->bge_maxlen_flags =
2074 		    BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2);
2075 	} else if (BGE_IS_5705_PLUS(sc)) {
2076 		/*
2077 		 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32)
2078 		 * Bits 15-2 : Reserved (should be 0)
2079 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2080 		 * Bit 0     : Reserved
2081 		 */
2082 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
2083 	} else {
2084 		/*
2085 		 * Ring size is always XXX entries
2086 		 * Bits 31-16: Maximum RX frame size
2087 		 * Bits 15-2 : Reserved (should be 0)
2088 		 * Bit 1     : 1 = Ring Disabled, 0 = Ring Enabled
2089 		 * Bit 0     : Reserved
2090 		 */
2091 		rcb->bge_maxlen_flags =
2092 		    BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
2093 	}
2094 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2095 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2096 	    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2097 		rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717;
2098 	else
2099 		rcb->bge_nicaddr = BGE_STD_RX_RINGS;
2100 	/* Write the standard receive producer ring control block. */
2101 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
2102 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
2103 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
2104 	CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
2105 
2106 	/* Reset the standard receive producer ring producer index. */
2107 	bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0);
2108 
2109 	/*
2110 	 * Initialize the jumbo RX producer ring control
2111 	 * block.  We set the 'ring disabled' bit in the
2112 	 * flags field until we're actually ready to start
2113 	 * using this ring (i.e. once we set the MTU
2114 	 * high enough to require it).
2115 	 */
2116 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
2117 		rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb;
2118 		/* Get the jumbo receive producer ring RCB parameters. */
2119 		rcb->bge_hostaddr.bge_addr_lo =
2120 		    BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2121 		rcb->bge_hostaddr.bge_addr_hi =
2122 		    BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr);
2123 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2124 		    sc->bge_cdata.bge_rx_jumbo_ring_map,
2125 		    BUS_DMASYNC_PREREAD);
2126 		rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0,
2127 		    BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED);
2128 		if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2129 		    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2130 		    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2131 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717;
2132 		else
2133 			rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
2134 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
2135 		    rcb->bge_hostaddr.bge_addr_hi);
2136 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
2137 		    rcb->bge_hostaddr.bge_addr_lo);
2138 		/* Program the jumbo receive producer ring RCB parameters. */
2139 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
2140 		    rcb->bge_maxlen_flags);
2141 		CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
2142 		/* Reset the jumbo receive producer ring producer index. */
2143 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
2144 	}
2145 
2146 	/* Disable the mini receive producer ring RCB. */
2147 	if (BGE_IS_5700_FAMILY(sc)) {
2148 		rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb;
2149 		rcb->bge_maxlen_flags =
2150 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
2151 		CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
2152 		    rcb->bge_maxlen_flags);
2153 		/* Reset the mini receive producer ring producer index. */
2154 		bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
2155 	}
2156 
2157 	/* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */
2158 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
2159 		if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 ||
2160 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A1 ||
2161 		    sc->bge_chipid == BGE_CHIPID_BCM5906_A2)
2162 			CSR_WRITE_4(sc, BGE_ISO_PKT_TX,
2163 			    (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2);
2164 	}
2165 	/*
2166 	 * The BD ring replenish thresholds control how often the
2167 	 * hardware fetches new BD's from the producer rings in host
2168 	 * memory.  Setting the value too low on a busy system can
2169 	 * starve the hardware and recue the throughpout.
2170 	 *
2171 	 * Set the BD ring replentish thresholds. The recommended
2172 	 * values are 1/8th the number of descriptors allocated to
2173 	 * each ring.
2174 	 * XXX The 5754 requires a lower threshold, so it might be a
2175 	 * requirement of all 575x family chips.  The Linux driver sets
2176 	 * the lower threshold for all 5705 family chips as well, but there
2177 	 * are reports that it might not need to be so strict.
2178 	 *
2179 	 * XXX Linux does some extra fiddling here for the 5906 parts as
2180 	 * well.
2181 	 */
2182 	if (BGE_IS_5705_PLUS(sc))
2183 		val = 8;
2184 	else
2185 		val = BGE_STD_RX_RING_CNT / 8;
2186 	CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val);
2187 	if (BGE_IS_JUMBO_CAPABLE(sc))
2188 		CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH,
2189 		    BGE_JUMBO_RX_RING_CNT/8);
2190 	if (BGE_IS_5717_PLUS(sc)) {
2191 		CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32);
2192 		CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16);
2193 	}
2194 
2195 	/*
2196 	 * Disable all send rings by setting the 'ring disabled' bit
2197 	 * in the flags field of all the TX send ring control blocks,
2198 	 * located in NIC memory.
2199 	 */
2200 	if (!BGE_IS_5705_PLUS(sc))
2201 		/* 5700 to 5704 had 16 send rings. */
2202 		limit = BGE_TX_RINGS_EXTSSRAM_MAX;
2203 	else if (BGE_IS_57765_PLUS(sc) ||
2204 	    sc->bge_asicrev == BGE_ASICREV_BCM5762)
2205 		limit = 2;
2206 	else if (BGE_IS_5717_PLUS(sc))
2207 		limit = 4;
2208 	else
2209 		limit = 1;
2210 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2211 	for (i = 0; i < limit; i++) {
2212 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2213 		    BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
2214 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2215 		vrcb += sizeof(struct bge_rcb);
2216 	}
2217 
2218 	/* Configure send ring RCB 0 (we use only the first ring) */
2219 	vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
2220 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
2221 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2222 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2223 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2224 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2225 	    sc->bge_asicrev == BGE_ASICREV_BCM5720)
2226 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717);
2227 	else
2228 		RCB_WRITE_4(sc, vrcb, bge_nicaddr,
2229 		    BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
2230 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2231 	    BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
2232 
2233 	/*
2234 	 * Disable all receive return rings by setting the
2235 	 * 'ring diabled' bit in the flags field of all the receive
2236 	 * return ring control blocks, located in NIC memory.
2237 	 */
2238 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
2239 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
2240 	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2241 		/* Should be 17, use 16 until we get an SRAM map. */
2242 		limit = 16;
2243 	} else if (!BGE_IS_5705_PLUS(sc))
2244 		limit = BGE_RX_RINGS_MAX;
2245 	else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
2246 	    sc->bge_asicrev == BGE_ASICREV_BCM5762 ||
2247 	    BGE_IS_57765_PLUS(sc))
2248 		limit = 4;
2249 	else
2250 		limit = 1;
2251 	/* Disable all receive return rings. */
2252 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2253 	for (i = 0; i < limit; i++) {
2254 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
2255 		RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
2256 		RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2257 		    BGE_RCB_FLAG_RING_DISABLED);
2258 		RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2259 		bge_writembx(sc, BGE_MBX_RX_CONS0_LO +
2260 		    (i * (sizeof(uint64_t))), 0);
2261 		vrcb += sizeof(struct bge_rcb);
2262 	}
2263 
2264 	/*
2265 	 * Set up receive return ring 0.  Note that the NIC address
2266 	 * for RX return rings is 0x0.  The return rings live entirely
2267 	 * within the host, so the nicaddr field in the RCB isn't used.
2268 	 */
2269 	vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
2270 	BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
2271 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
2272 	RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
2273 	RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
2274 	RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
2275 	    BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
2276 
2277 	/* Set random backoff seed for TX */
2278 	CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
2279 	    (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
2280 	    IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
2281 	    IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) &
2282 	    BGE_TX_BACKOFF_SEED_MASK);
2283 
2284 	/* Set inter-packet gap */
2285 	val = 0x2620;
2286 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2287 	    sc->bge_asicrev == BGE_ASICREV_BCM5762)
2288 		val |= CSR_READ_4(sc, BGE_TX_LENGTHS) &
2289 		    (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK);
2290 	CSR_WRITE_4(sc, BGE_TX_LENGTHS, val);
2291 
2292 	/*
2293 	 * Specify which ring to use for packets that don't match
2294 	 * any RX rules.
2295 	 */
2296 	CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
2297 
2298 	/*
2299 	 * Configure number of RX lists. One interrupt distribution
2300 	 * list, sixteen active lists, one bad frames class.
2301 	 */
2302 	CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
2303 
2304 	/* Inialize RX list placement stats mask. */
2305 	CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
2306 	CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
2307 
2308 	/* Disable host coalescing until we get it set up */
2309 	CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
2310 
2311 	/* Poll to make sure it's shut down. */
2312 	for (i = 0; i < BGE_TIMEOUT; i++) {
2313 		DELAY(10);
2314 		if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
2315 			break;
2316 	}
2317 
2318 	if (i == BGE_TIMEOUT) {
2319 		device_printf(sc->bge_dev,
2320 		    "host coalescing engine failed to idle\n");
2321 		return (ENXIO);
2322 	}
2323 
2324 	/* Set up host coalescing defaults */
2325 	CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
2326 	CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
2327 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
2328 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
2329 	if (!(BGE_IS_5705_PLUS(sc))) {
2330 		CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
2331 		CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
2332 	}
2333 	CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1);
2334 	CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1);
2335 
2336 	/* Set up address of statistics block */
2337 	if (!(BGE_IS_5705_PLUS(sc))) {
2338 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI,
2339 		    BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr));
2340 		CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
2341 		    BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr));
2342 		CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
2343 		CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
2344 		CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
2345 	}
2346 
2347 	/* Set up address of status block */
2348 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI,
2349 	    BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr));
2350 	CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
2351 	    BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr));
2352 
2353 	/* Set up status block size. */
2354 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2355 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0) {
2356 		val = BGE_STATBLKSZ_FULL;
2357 		bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ);
2358 	} else {
2359 		val = BGE_STATBLKSZ_32BYTE;
2360 		bzero(sc->bge_ldata.bge_status_block, 32);
2361 	}
2362 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
2363 	    sc->bge_cdata.bge_status_map,
2364 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2365 
2366 	/* Turn on host coalescing state machine */
2367 	CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE);
2368 
2369 	/* Turn on RX BD completion state machine and enable attentions */
2370 	CSR_WRITE_4(sc, BGE_RBDC_MODE,
2371 	    BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN);
2372 
2373 	/* Turn on RX list placement state machine */
2374 	CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2375 
2376 	/* Turn on RX list selector state machine. */
2377 	if (!(BGE_IS_5705_PLUS(sc)))
2378 		CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2379 
2380 	/* Turn on DMA, clear stats. */
2381 	val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB |
2382 	    BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR |
2383 	    BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB |
2384 	    BGE_MACMODE_FRMHDR_DMA_ENB;
2385 
2386 	if (sc->bge_flags & BGE_FLAG_TBI)
2387 		val |= BGE_PORTMODE_TBI;
2388 	else if (sc->bge_flags & BGE_FLAG_MII_SERDES)
2389 		val |= BGE_PORTMODE_GMII;
2390 	else
2391 		val |= BGE_PORTMODE_MII;
2392 
2393 	/* Allow APE to send/receive frames. */
2394 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
2395 		val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
2396 
2397 	CSR_WRITE_4(sc, BGE_MAC_MODE, val);
2398 	DELAY(40);
2399 
2400 	/* Set misc. local control, enable interrupts on attentions */
2401 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
2402 
2403 #ifdef notdef
2404 	/* Assert GPIO pins for PHY reset */
2405 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 |
2406 	    BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2);
2407 	BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 |
2408 	    BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2);
2409 #endif
2410 
2411 	/* Turn on DMA completion state machine */
2412 	if (!(BGE_IS_5705_PLUS(sc)))
2413 		CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2414 
2415 	val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS;
2416 
2417 	/* Enable host coalescing bug fix. */
2418 	if (BGE_IS_5755_PLUS(sc))
2419 		val |= BGE_WDMAMODE_STATUS_TAG_FIX;
2420 
2421 	/* Request larger DMA burst size to get better performance. */
2422 	if (sc->bge_asicrev == BGE_ASICREV_BCM5785)
2423 		val |= BGE_WDMAMODE_BURST_ALL_DATA;
2424 
2425 	/* Turn on write DMA state machine */
2426 	CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
2427 	DELAY(40);
2428 
2429 	/* Turn on read DMA state machine */
2430 	val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
2431 
2432 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717)
2433 		val |= BGE_RDMAMODE_MULT_DMA_RD_DIS;
2434 
2435 	if (sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2436 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2437 	    sc->bge_asicrev == BGE_ASICREV_BCM57780)
2438 		val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN |
2439 		    BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN |
2440 		    BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN;
2441 	if (sc->bge_flags & BGE_FLAG_PCIE)
2442 		val |= BGE_RDMAMODE_FIFO_LONG_BURST;
2443 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
2444 		val |= BGE_RDMAMODE_TSO4_ENABLE;
2445 		if (sc->bge_flags & BGE_FLAG_TSO3 ||
2446 		    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2447 		    sc->bge_asicrev == BGE_ASICREV_BCM57780)
2448 			val |= BGE_RDMAMODE_TSO6_ENABLE;
2449 	}
2450 
2451 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
2452 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2453 		val |= CSR_READ_4(sc, BGE_RDMA_MODE) &
2454 			BGE_RDMAMODE_H2BNC_VLAN_DET;
2455 		/*
2456 		 * Allow multiple outstanding read requests from
2457 		 * non-LSO read DMA engine.
2458 		 */
2459 		val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS;
2460 	}
2461 
2462 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
2463 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
2464 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
2465 	    sc->bge_asicrev == BGE_ASICREV_BCM57780 ||
2466 	    BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) {
2467 		if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
2468 			rdmareg = BGE_RDMA_RSRVCTRL_REG2;
2469 		else
2470 			rdmareg = BGE_RDMA_RSRVCTRL;
2471 		dmactl = CSR_READ_4(sc, rdmareg);
2472 		/*
2473 		 * Adjust tx margin to prevent TX data corruption and
2474 		 * fix internal FIFO overflow.
2475 		 */
2476 		if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 ||
2477 		    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2478 			dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK |
2479 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK |
2480 			    BGE_RDMA_RSRVCTRL_TXMRGN_MASK);
2481 			dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K |
2482 			    BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K |
2483 			    BGE_RDMA_RSRVCTRL_TXMRGN_320B;
2484 		}
2485 		/*
2486 		 * Enable fix for read DMA FIFO overruns.
2487 		 * The fix is to limit the number of RX BDs
2488 		 * the hardware would fetch at a fime.
2489 		 */
2490 		CSR_WRITE_4(sc, rdmareg, dmactl |
2491 		    BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
2492 	}
2493 
2494 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719) {
2495 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2496 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2497 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2498 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2499 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) {
2500 		/*
2501 		 * Allow 4KB burst length reads for non-LSO frames.
2502 		 * Enable 512B burst length reads for buffer descriptors.
2503 		 */
2504 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL,
2505 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) |
2506 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 |
2507 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2508 	} else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) {
2509 		CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2,
2510 		    CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) |
2511 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K |
2512 		    BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K);
2513 	}
2514 
2515 	CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
2516 	DELAY(40);
2517 
2518 	if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
2519 		for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) {
2520 			val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4);
2521 			if ((val & 0xFFFF) > BGE_FRAMELEN)
2522 				break;
2523 			if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN)
2524 				break;
2525 		}
2526 		if (i != BGE_NUM_RDMA_CHANNELS / 2) {
2527 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
2528 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
2529 				val |= BGE_RDMA_TX_LENGTH_WA_5719;
2530 			else
2531 				val |= BGE_RDMA_TX_LENGTH_WA_5720;
2532 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
2533 		}
2534 	}
2535 
2536 	/* Turn on RX data completion state machine */
2537 	CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2538 
2539 	/* Turn on RX BD initiator state machine */
2540 	CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2541 
2542 	/* Turn on RX data and RX BD initiator state machine */
2543 	CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
2544 
2545 	/* Turn on Mbuf cluster free state machine */
2546 	if (!(BGE_IS_5705_PLUS(sc)))
2547 		CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2548 
2549 	/* Turn on send BD completion state machine */
2550 	CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2551 
2552 	/* Turn on send data completion state machine */
2553 	val = BGE_SDCMODE_ENABLE;
2554 	if (sc->bge_asicrev == BGE_ASICREV_BCM5761)
2555 		val |= BGE_SDCMODE_CDELAY;
2556 	CSR_WRITE_4(sc, BGE_SDC_MODE, val);
2557 
2558 	/* Turn on send data initiator state machine */
2559 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3))
2560 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE |
2561 		    BGE_SDIMODE_HW_LSO_PRE_DMA);
2562 	else
2563 		CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2564 
2565 	/* Turn on send BD initiator state machine */
2566 	CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2567 
2568 	/* Turn on send BD selector state machine */
2569 	CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2570 
2571 	CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
2572 	CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
2573 	    BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER);
2574 
2575 	/* ack/clear link change events */
2576 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2577 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2578 	    BGE_MACSTAT_LINK_CHANGED);
2579 	CSR_WRITE_4(sc, BGE_MI_STS, 0);
2580 
2581 	/*
2582 	 * Enable attention when the link has changed state for
2583 	 * devices that use auto polling.
2584 	 */
2585 	if (sc->bge_flags & BGE_FLAG_TBI) {
2586 		CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
2587 	} else {
2588 		if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) {
2589 			CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode);
2590 			DELAY(80);
2591 		}
2592 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2593 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2)
2594 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2595 			    BGE_EVTENB_MI_INTERRUPT);
2596 	}
2597 
2598 	/*
2599 	 * Clear any pending link state attention.
2600 	 * Otherwise some link state change events may be lost until attention
2601 	 * is cleared by bge_intr() -> bge_link_upd() sequence.
2602 	 * It's not necessary on newer BCM chips - perhaps enabling link
2603 	 * state change attentions implies clearing pending attention.
2604 	 */
2605 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
2606 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
2607 	    BGE_MACSTAT_LINK_CHANGED);
2608 
2609 	/* Enable link state change attentions. */
2610 	BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
2611 
2612 	return (0);
2613 }
2614 
2615 static const struct bge_revision *
2616 bge_lookup_rev(uint32_t chipid)
2617 {
2618 	const struct bge_revision *br;
2619 
2620 	for (br = bge_revisions; br->br_name != NULL; br++) {
2621 		if (br->br_chipid == chipid)
2622 			return (br);
2623 	}
2624 
2625 	for (br = bge_majorrevs; br->br_name != NULL; br++) {
2626 		if (br->br_chipid == BGE_ASICREV(chipid))
2627 			return (br);
2628 	}
2629 
2630 	return (NULL);
2631 }
2632 
2633 static const struct bge_vendor *
2634 bge_lookup_vendor(uint16_t vid)
2635 {
2636 	const struct bge_vendor *v;
2637 
2638 	for (v = bge_vendors; v->v_name != NULL; v++)
2639 		if (v->v_id == vid)
2640 			return (v);
2641 
2642 	return (NULL);
2643 }
2644 
2645 static uint32_t
2646 bge_chipid(device_t dev)
2647 {
2648 	uint32_t id;
2649 
2650 	id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >>
2651 	    BGE_PCIMISCCTL_ASICREV_SHIFT;
2652 	if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) {
2653 		/*
2654 		 * Find the ASCI revision.  Different chips use different
2655 		 * registers.
2656 		 */
2657 		switch (pci_get_device(dev)) {
2658 		case BCOM_DEVICEID_BCM5717C:
2659 			/* 5717 C0 seems to belong to 5720 line. */
2660 			id = BGE_CHIPID_BCM5720_A0;
2661 			break;
2662 		case BCOM_DEVICEID_BCM5717:
2663 		case BCOM_DEVICEID_BCM5718:
2664 		case BCOM_DEVICEID_BCM5719:
2665 		case BCOM_DEVICEID_BCM5720:
2666 		case BCOM_DEVICEID_BCM5725:
2667 		case BCOM_DEVICEID_BCM5727:
2668 		case BCOM_DEVICEID_BCM5762:
2669 		case BCOM_DEVICEID_BCM57764:
2670 		case BCOM_DEVICEID_BCM57767:
2671 		case BCOM_DEVICEID_BCM57787:
2672 			id = pci_read_config(dev,
2673 			    BGE_PCI_GEN2_PRODID_ASICREV, 4);
2674 			break;
2675 		case BCOM_DEVICEID_BCM57761:
2676 		case BCOM_DEVICEID_BCM57762:
2677 		case BCOM_DEVICEID_BCM57765:
2678 		case BCOM_DEVICEID_BCM57766:
2679 		case BCOM_DEVICEID_BCM57781:
2680 		case BCOM_DEVICEID_BCM57782:
2681 		case BCOM_DEVICEID_BCM57785:
2682 		case BCOM_DEVICEID_BCM57786:
2683 		case BCOM_DEVICEID_BCM57791:
2684 		case BCOM_DEVICEID_BCM57795:
2685 			id = pci_read_config(dev,
2686 			    BGE_PCI_GEN15_PRODID_ASICREV, 4);
2687 			break;
2688 		default:
2689 			id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4);
2690 		}
2691 	}
2692 	return (id);
2693 }
2694 
2695 /*
2696  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
2697  * against our list and return its name if we find a match.
2698  *
2699  * Note that since the Broadcom controller contains VPD support, we
2700  * try to get the device name string from the controller itself instead
2701  * of the compiled-in string. It guarantees we'll always announce the
2702  * right product name. We fall back to the compiled-in string when
2703  * VPD is unavailable or corrupt.
2704  */
2705 static int
2706 bge_probe(device_t dev)
2707 {
2708 	char buf[96];
2709 	char model[64];
2710 	const struct bge_revision *br;
2711 	const char *pname;
2712 	struct bge_softc *sc;
2713 	const struct bge_type *t = bge_devs;
2714 	const struct bge_vendor *v;
2715 	uint32_t id;
2716 	uint16_t did, vid;
2717 
2718 	sc = device_get_softc(dev);
2719 	sc->bge_dev = dev;
2720 	vid = pci_get_vendor(dev);
2721 	did = pci_get_device(dev);
2722 	while(t->bge_vid != 0) {
2723 		if ((vid == t->bge_vid) && (did == t->bge_did)) {
2724 			id = bge_chipid(dev);
2725 			br = bge_lookup_rev(id);
2726 			if (bge_has_eaddr(sc) &&
2727 			    pci_get_vpd_ident(dev, &pname) == 0)
2728 				snprintf(model, sizeof(model), "%s", pname);
2729 			else {
2730 				v = bge_lookup_vendor(vid);
2731 				snprintf(model, sizeof(model), "%s %s",
2732 				    v != NULL ? v->v_name : "Unknown",
2733 				    br != NULL ? br->br_name :
2734 				    "NetXtreme/NetLink Ethernet Controller");
2735 			}
2736 			snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x",
2737 			    model, br != NULL ? "" : "unknown ", id);
2738 			device_set_desc_copy(dev, buf);
2739 			return (BUS_PROBE_DEFAULT);
2740 		}
2741 		t++;
2742 	}
2743 
2744 	return (ENXIO);
2745 }
2746 
2747 static void
2748 bge_dma_free(struct bge_softc *sc)
2749 {
2750 	int i;
2751 
2752 	/* Destroy DMA maps for RX buffers. */
2753 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
2754 		if (sc->bge_cdata.bge_rx_std_dmamap[i])
2755 			bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2756 			    sc->bge_cdata.bge_rx_std_dmamap[i]);
2757 	}
2758 	if (sc->bge_cdata.bge_rx_std_sparemap)
2759 		bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag,
2760 		    sc->bge_cdata.bge_rx_std_sparemap);
2761 
2762 	/* Destroy DMA maps for jumbo RX buffers. */
2763 	for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
2764 		if (sc->bge_cdata.bge_rx_jumbo_dmamap[i])
2765 			bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2766 			    sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
2767 	}
2768 	if (sc->bge_cdata.bge_rx_jumbo_sparemap)
2769 		bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo,
2770 		    sc->bge_cdata.bge_rx_jumbo_sparemap);
2771 
2772 	/* Destroy DMA maps for TX buffers. */
2773 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
2774 		if (sc->bge_cdata.bge_tx_dmamap[i])
2775 			bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag,
2776 			    sc->bge_cdata.bge_tx_dmamap[i]);
2777 	}
2778 
2779 	if (sc->bge_cdata.bge_rx_mtag)
2780 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag);
2781 	if (sc->bge_cdata.bge_mtag_jumbo)
2782 		bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo);
2783 	if (sc->bge_cdata.bge_tx_mtag)
2784 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag);
2785 
2786 	/* Destroy standard RX ring. */
2787 	if (sc->bge_ldata.bge_rx_std_ring_paddr)
2788 		bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag,
2789 		    sc->bge_cdata.bge_rx_std_ring_map);
2790 	if (sc->bge_ldata.bge_rx_std_ring)
2791 		bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag,
2792 		    sc->bge_ldata.bge_rx_std_ring,
2793 		    sc->bge_cdata.bge_rx_std_ring_map);
2794 
2795 	if (sc->bge_cdata.bge_rx_std_ring_tag)
2796 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag);
2797 
2798 	/* Destroy jumbo RX ring. */
2799 	if (sc->bge_ldata.bge_rx_jumbo_ring_paddr)
2800 		bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2801 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
2802 
2803 	if (sc->bge_ldata.bge_rx_jumbo_ring)
2804 		bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag,
2805 		    sc->bge_ldata.bge_rx_jumbo_ring,
2806 		    sc->bge_cdata.bge_rx_jumbo_ring_map);
2807 
2808 	if (sc->bge_cdata.bge_rx_jumbo_ring_tag)
2809 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag);
2810 
2811 	/* Destroy RX return ring. */
2812 	if (sc->bge_ldata.bge_rx_return_ring_paddr)
2813 		bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag,
2814 		    sc->bge_cdata.bge_rx_return_ring_map);
2815 
2816 	if (sc->bge_ldata.bge_rx_return_ring)
2817 		bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag,
2818 		    sc->bge_ldata.bge_rx_return_ring,
2819 		    sc->bge_cdata.bge_rx_return_ring_map);
2820 
2821 	if (sc->bge_cdata.bge_rx_return_ring_tag)
2822 		bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag);
2823 
2824 	/* Destroy TX ring. */
2825 	if (sc->bge_ldata.bge_tx_ring_paddr)
2826 		bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag,
2827 		    sc->bge_cdata.bge_tx_ring_map);
2828 
2829 	if (sc->bge_ldata.bge_tx_ring)
2830 		bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag,
2831 		    sc->bge_ldata.bge_tx_ring,
2832 		    sc->bge_cdata.bge_tx_ring_map);
2833 
2834 	if (sc->bge_cdata.bge_tx_ring_tag)
2835 		bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag);
2836 
2837 	/* Destroy status block. */
2838 	if (sc->bge_ldata.bge_status_block_paddr)
2839 		bus_dmamap_unload(sc->bge_cdata.bge_status_tag,
2840 		    sc->bge_cdata.bge_status_map);
2841 
2842 	if (sc->bge_ldata.bge_status_block)
2843 		bus_dmamem_free(sc->bge_cdata.bge_status_tag,
2844 		    sc->bge_ldata.bge_status_block,
2845 		    sc->bge_cdata.bge_status_map);
2846 
2847 	if (sc->bge_cdata.bge_status_tag)
2848 		bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag);
2849 
2850 	/* Destroy statistics block. */
2851 	if (sc->bge_ldata.bge_stats_paddr)
2852 		bus_dmamap_unload(sc->bge_cdata.bge_stats_tag,
2853 		    sc->bge_cdata.bge_stats_map);
2854 
2855 	if (sc->bge_ldata.bge_stats)
2856 		bus_dmamem_free(sc->bge_cdata.bge_stats_tag,
2857 		    sc->bge_ldata.bge_stats,
2858 		    sc->bge_cdata.bge_stats_map);
2859 
2860 	if (sc->bge_cdata.bge_stats_tag)
2861 		bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag);
2862 
2863 	if (sc->bge_cdata.bge_buffer_tag)
2864 		bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag);
2865 
2866 	/* Destroy the parent tag. */
2867 	if (sc->bge_cdata.bge_parent_tag)
2868 		bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag);
2869 }
2870 
2871 static int
2872 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment,
2873     bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map,
2874     bus_addr_t *paddr, const char *msg)
2875 {
2876 	struct bge_dmamap_arg ctx;
2877 	bus_addr_t lowaddr;
2878 	bus_size_t ring_end;
2879 	int error;
2880 
2881 	lowaddr = BUS_SPACE_MAXADDR;
2882 again:
2883 	error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag,
2884 	    alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2885 	    NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag);
2886 	if (error != 0) {
2887 		device_printf(sc->bge_dev,
2888 		    "could not create %s dma tag\n", msg);
2889 		return (ENOMEM);
2890 	}
2891 	/* Allocate DMA'able memory for ring. */
2892 	error = bus_dmamem_alloc(*tag, (void **)ring,
2893 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map);
2894 	if (error != 0) {
2895 		device_printf(sc->bge_dev,
2896 		    "could not allocate DMA'able memory for %s\n", msg);
2897 		return (ENOMEM);
2898 	}
2899 	/* Load the address of the ring. */
2900 	ctx.bge_busaddr = 0;
2901 	error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr,
2902 	    &ctx, BUS_DMA_NOWAIT);
2903 	if (error != 0) {
2904 		device_printf(sc->bge_dev,
2905 		    "could not load DMA'able memory for %s\n", msg);
2906 		return (ENOMEM);
2907 	}
2908 	*paddr = ctx.bge_busaddr;
2909 	ring_end = *paddr + maxsize;
2910 	if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 &&
2911 	    BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) {
2912 		/*
2913 		 * 4GB boundary crossed.  Limit maximum allowable DMA
2914 		 * address space to 32bit and try again.
2915 		 */
2916 		bus_dmamap_unload(*tag, *map);
2917 		bus_dmamem_free(*tag, *ring, *map);
2918 		bus_dma_tag_destroy(*tag);
2919 		if (bootverbose)
2920 			device_printf(sc->bge_dev, "4GB boundary crossed, "
2921 			    "limit DMA address space to 32bit for %s\n", msg);
2922 		*ring = NULL;
2923 		*tag = NULL;
2924 		*map = NULL;
2925 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
2926 		goto again;
2927 	}
2928 	return (0);
2929 }
2930 
2931 static int
2932 bge_dma_alloc(struct bge_softc *sc)
2933 {
2934 	bus_addr_t lowaddr;
2935 	bus_size_t boundary, sbsz, rxmaxsegsz, txsegsz, txmaxsegsz;
2936 	int i, error;
2937 
2938 	lowaddr = BUS_SPACE_MAXADDR;
2939 	if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0)
2940 		lowaddr = BGE_DMA_MAXADDR;
2941 	/*
2942 	 * Allocate the parent bus DMA tag appropriate for PCI.
2943 	 */
2944 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
2945 	    1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL,
2946 	    NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
2947 	    0, NULL, NULL, &sc->bge_cdata.bge_parent_tag);
2948 	if (error != 0) {
2949 		device_printf(sc->bge_dev,
2950 		    "could not allocate parent dma tag\n");
2951 		return (ENOMEM);
2952 	}
2953 
2954 	/* Create tag for standard RX ring. */
2955 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ,
2956 	    &sc->bge_cdata.bge_rx_std_ring_tag,
2957 	    (uint8_t **)&sc->bge_ldata.bge_rx_std_ring,
2958 	    &sc->bge_cdata.bge_rx_std_ring_map,
2959 	    &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring");
2960 	if (error)
2961 		return (error);
2962 
2963 	/* Create tag for RX return ring. */
2964 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc),
2965 	    &sc->bge_cdata.bge_rx_return_ring_tag,
2966 	    (uint8_t **)&sc->bge_ldata.bge_rx_return_ring,
2967 	    &sc->bge_cdata.bge_rx_return_ring_map,
2968 	    &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring");
2969 	if (error)
2970 		return (error);
2971 
2972 	/* Create tag for TX ring. */
2973 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ,
2974 	    &sc->bge_cdata.bge_tx_ring_tag,
2975 	    (uint8_t **)&sc->bge_ldata.bge_tx_ring,
2976 	    &sc->bge_cdata.bge_tx_ring_map,
2977 	    &sc->bge_ldata.bge_tx_ring_paddr, "TX ring");
2978 	if (error)
2979 		return (error);
2980 
2981 	/*
2982 	 * Create tag for status block.
2983 	 * Because we only use single Tx/Rx/Rx return ring, use
2984 	 * minimum status block size except BCM5700 AX/BX which
2985 	 * seems to want to see full status block size regardless
2986 	 * of configured number of ring.
2987 	 */
2988 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
2989 	    sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
2990 		sbsz = BGE_STATUS_BLK_SZ;
2991 	else
2992 		sbsz = 32;
2993 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz,
2994 	    &sc->bge_cdata.bge_status_tag,
2995 	    (uint8_t **)&sc->bge_ldata.bge_status_block,
2996 	    &sc->bge_cdata.bge_status_map,
2997 	    &sc->bge_ldata.bge_status_block_paddr, "status block");
2998 	if (error)
2999 		return (error);
3000 
3001 	/* Create tag for statistics block. */
3002 	error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ,
3003 	    &sc->bge_cdata.bge_stats_tag,
3004 	    (uint8_t **)&sc->bge_ldata.bge_stats,
3005 	    &sc->bge_cdata.bge_stats_map,
3006 	    &sc->bge_ldata.bge_stats_paddr, "statistics block");
3007 	if (error)
3008 		return (error);
3009 
3010 	/* Create tag for jumbo RX ring. */
3011 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
3012 		error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ,
3013 		    &sc->bge_cdata.bge_rx_jumbo_ring_tag,
3014 		    (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring,
3015 		    &sc->bge_cdata.bge_rx_jumbo_ring_map,
3016 		    &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring");
3017 		if (error)
3018 			return (error);
3019 	}
3020 
3021 	/* Create parent tag for buffers. */
3022 	boundary = 0;
3023 	if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) {
3024 		boundary = BGE_DMA_BNDRY;
3025 		/*
3026 		 * XXX
3027 		 * watchdog timeout issue was observed on BCM5704 which
3028 		 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge).
3029 		 * Both limiting DMA address space to 32bits and flushing
3030 		 * mailbox write seem to address the issue.
3031 		 */
3032 		if (sc->bge_pcixcap != 0)
3033 			lowaddr = BUS_SPACE_MAXADDR_32BIT;
3034 	}
3035 	error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev),
3036 	    1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL,
3037 	    NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3038 	    0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag);
3039 	if (error != 0) {
3040 		device_printf(sc->bge_dev,
3041 		    "could not allocate buffer dma tag\n");
3042 		return (ENOMEM);
3043 	}
3044 	/* Create tag for Tx mbufs. */
3045 	if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) {
3046 		txsegsz = BGE_TSOSEG_SZ;
3047 		txmaxsegsz = 65535 + sizeof(struct ether_vlan_header);
3048 	} else {
3049 		txsegsz = MCLBYTES;
3050 		txmaxsegsz = MCLBYTES * BGE_NSEG_NEW;
3051 	}
3052 	error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1,
3053 	    0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
3054 	    txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL,
3055 	    &sc->bge_cdata.bge_tx_mtag);
3056 
3057 	if (error) {
3058 		device_printf(sc->bge_dev, "could not allocate TX dma tag\n");
3059 		return (ENOMEM);
3060 	}
3061 
3062 	/* Create tag for Rx mbufs. */
3063 	if (sc->bge_flags & BGE_FLAG_JUMBO_STD)
3064 		rxmaxsegsz = MJUM9BYTES;
3065 	else
3066 		rxmaxsegsz = MCLBYTES;
3067 	error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0,
3068 	    BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1,
3069 	    rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag);
3070 
3071 	if (error) {
3072 		device_printf(sc->bge_dev, "could not allocate RX dma tag\n");
3073 		return (ENOMEM);
3074 	}
3075 
3076 	/* Create DMA maps for RX buffers. */
3077 	error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3078 	    &sc->bge_cdata.bge_rx_std_sparemap);
3079 	if (error) {
3080 		device_printf(sc->bge_dev,
3081 		    "can't create spare DMA map for RX\n");
3082 		return (ENOMEM);
3083 	}
3084 	for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
3085 		error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0,
3086 			    &sc->bge_cdata.bge_rx_std_dmamap[i]);
3087 		if (error) {
3088 			device_printf(sc->bge_dev,
3089 			    "can't create DMA map for RX\n");
3090 			return (ENOMEM);
3091 		}
3092 	}
3093 
3094 	/* Create DMA maps for TX buffers. */
3095 	for (i = 0; i < BGE_TX_RING_CNT; i++) {
3096 		error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0,
3097 			    &sc->bge_cdata.bge_tx_dmamap[i]);
3098 		if (error) {
3099 			device_printf(sc->bge_dev,
3100 			    "can't create DMA map for TX\n");
3101 			return (ENOMEM);
3102 		}
3103 	}
3104 
3105 	/* Create tags for jumbo RX buffers. */
3106 	if (BGE_IS_JUMBO_CAPABLE(sc)) {
3107 		error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag,
3108 		    1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL,
3109 		    NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE,
3110 		    0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo);
3111 		if (error) {
3112 			device_printf(sc->bge_dev,
3113 			    "could not allocate jumbo dma tag\n");
3114 			return (ENOMEM);
3115 		}
3116 		/* Create DMA maps for jumbo RX buffers. */
3117 		error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3118 		    0, &sc->bge_cdata.bge_rx_jumbo_sparemap);
3119 		if (error) {
3120 			device_printf(sc->bge_dev,
3121 			    "can't create spare DMA map for jumbo RX\n");
3122 			return (ENOMEM);
3123 		}
3124 		for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
3125 			error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo,
3126 				    0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]);
3127 			if (error) {
3128 				device_printf(sc->bge_dev,
3129 				    "can't create DMA map for jumbo RX\n");
3130 				return (ENOMEM);
3131 			}
3132 		}
3133 	}
3134 
3135 	return (0);
3136 }
3137 
3138 /*
3139  * Return true if this device has more than one port.
3140  */
3141 static int
3142 bge_has_multiple_ports(struct bge_softc *sc)
3143 {
3144 	device_t dev = sc->bge_dev;
3145 	u_int b, d, f, fscan, s;
3146 
3147 	d = pci_get_domain(dev);
3148 	b = pci_get_bus(dev);
3149 	s = pci_get_slot(dev);
3150 	f = pci_get_function(dev);
3151 	for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++)
3152 		if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL)
3153 			return (1);
3154 	return (0);
3155 }
3156 
3157 /*
3158  * Return true if MSI can be used with this device.
3159  */
3160 static int
3161 bge_can_use_msi(struct bge_softc *sc)
3162 {
3163 	int can_use_msi = 0;
3164 
3165 	if (sc->bge_msi == 0)
3166 		return (0);
3167 
3168 	/* Disable MSI for polling(4). */
3169 #ifdef DEVICE_POLLING
3170 	return (0);
3171 #endif
3172 	switch (sc->bge_asicrev) {
3173 	case BGE_ASICREV_BCM5714_A0:
3174 	case BGE_ASICREV_BCM5714:
3175 		/*
3176 		 * Apparently, MSI doesn't work when these chips are
3177 		 * configured in single-port mode.
3178 		 */
3179 		if (bge_has_multiple_ports(sc))
3180 			can_use_msi = 1;
3181 		break;
3182 	case BGE_ASICREV_BCM5750:
3183 		if (sc->bge_chiprev != BGE_CHIPREV_5750_AX &&
3184 		    sc->bge_chiprev != BGE_CHIPREV_5750_BX)
3185 			can_use_msi = 1;
3186 		break;
3187 	case BGE_ASICREV_BCM5784:
3188 		/*
3189 		 * Prevent infinite "watchdog timeout" errors
3190 		 * in some MacBook Pro and make it work out-of-the-box.
3191 		 */
3192 		if (sc->bge_chiprev == BGE_CHIPREV_5784_AX)
3193 			break;
3194 		/* FALLTHROUGH */
3195 	default:
3196 		if (BGE_IS_575X_PLUS(sc))
3197 			can_use_msi = 1;
3198 	}
3199 	return (can_use_msi);
3200 }
3201 
3202 static int
3203 bge_mbox_reorder(struct bge_softc *sc)
3204 {
3205 	/* Lists of PCI bridges that are known to reorder mailbox writes. */
3206 	static const struct mbox_reorder {
3207 		const uint16_t vendor;
3208 		const uint16_t device;
3209 		const char *desc;
3210 	} mbox_reorder_lists[] = {
3211 		{ 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" },
3212 	};
3213 	devclass_t pci, pcib;
3214 	device_t bus, dev;
3215 	int i;
3216 
3217 	pci = devclass_find("pci");
3218 	pcib = devclass_find("pcib");
3219 	dev = sc->bge_dev;
3220 	bus = device_get_parent(dev);
3221 	for (;;) {
3222 		dev = device_get_parent(bus);
3223 		bus = device_get_parent(dev);
3224 		if (device_get_devclass(dev) != pcib)
3225 			break;
3226 		if (device_get_devclass(bus) != pci)
3227 			break;
3228 		for (i = 0; i < nitems(mbox_reorder_lists); i++) {
3229 			if (pci_get_vendor(dev) ==
3230 			    mbox_reorder_lists[i].vendor &&
3231 			    pci_get_device(dev) ==
3232 			    mbox_reorder_lists[i].device) {
3233 				device_printf(sc->bge_dev,
3234 				    "enabling MBOX workaround for %s\n",
3235 				    mbox_reorder_lists[i].desc);
3236 				return (1);
3237 			}
3238 		}
3239 	}
3240 	return (0);
3241 }
3242 
3243 static void
3244 bge_devinfo(struct bge_softc *sc)
3245 {
3246 	uint32_t cfg, clk;
3247 
3248 	device_printf(sc->bge_dev,
3249 	    "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ",
3250 	    sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev);
3251 	if (sc->bge_flags & BGE_FLAG_PCIE)
3252 		printf("PCI-E\n");
3253 	else if (sc->bge_flags & BGE_FLAG_PCIX) {
3254 		printf("PCI-X ");
3255 		cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3256 		if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE)
3257 			clk = 133;
3258 		else {
3259 			clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F;
3260 			switch (clk) {
3261 			case 0:
3262 				clk = 33;
3263 				break;
3264 			case 2:
3265 				clk = 50;
3266 				break;
3267 			case 4:
3268 				clk = 66;
3269 				break;
3270 			case 6:
3271 				clk = 100;
3272 				break;
3273 			case 7:
3274 				clk = 133;
3275 				break;
3276 			}
3277 		}
3278 		printf("%u MHz\n", clk);
3279 	} else {
3280 		if (sc->bge_pcixcap != 0)
3281 			printf("PCI on PCI-X ");
3282 		else
3283 			printf("PCI ");
3284 		cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4);
3285 		if (cfg & BGE_PCISTATE_PCI_BUSSPEED)
3286 			clk = 66;
3287 		else
3288 			clk = 33;
3289 		if (cfg & BGE_PCISTATE_32BIT_BUS)
3290 			printf("%u MHz; 32bit\n", clk);
3291 		else
3292 			printf("%u MHz; 64bit\n", clk);
3293 	}
3294 }
3295 
3296 static int
3297 bge_attach(device_t dev)
3298 {
3299 	if_t ifp;
3300 	struct bge_softc *sc;
3301 	uint32_t hwcfg = 0, misccfg, pcistate;
3302 	u_char eaddr[ETHER_ADDR_LEN];
3303 	int capmask, error, reg, rid, trys;
3304 
3305 	sc = device_get_softc(dev);
3306 	sc->bge_dev = dev;
3307 
3308 	BGE_LOCK_INIT(sc, device_get_nameunit(dev));
3309 	NET_TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc);
3310 	callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0);
3311 
3312 	pci_enable_busmaster(dev);
3313 
3314 	/*
3315 	 * Allocate control/status registers.
3316 	 */
3317 	rid = PCIR_BAR(0);
3318 	sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3319 	    RF_ACTIVE);
3320 
3321 	if (sc->bge_res == NULL) {
3322 		device_printf (sc->bge_dev, "couldn't map BAR0 memory\n");
3323 		error = ENXIO;
3324 		goto fail;
3325 	}
3326 
3327 	/* Save various chip information. */
3328 	sc->bge_func_addr = pci_get_function(dev);
3329 	sc->bge_chipid = bge_chipid(dev);
3330 	sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
3331 	sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
3332 
3333 	/* Set default PHY address. */
3334 	sc->bge_phy_addr = 1;
3335 	 /*
3336 	  * PHY address mapping for various devices.
3337 	  *
3338 	  *          | F0 Cu | F0 Sr | F1 Cu | F1 Sr |
3339 	  * ---------+-------+-------+-------+-------+
3340 	  * BCM57XX  |   1   |   X   |   X   |   X   |
3341 	  * BCM5704  |   1   |   X   |   1   |   X   |
3342 	  * BCM5717  |   1   |   8   |   2   |   9   |
3343 	  * BCM5719  |   1   |   8   |   2   |   9   |
3344 	  * BCM5720  |   1   |   8   |   2   |   9   |
3345 	  *
3346 	  *          | F2 Cu | F2 Sr | F3 Cu | F3 Sr |
3347 	  * ---------+-------+-------+-------+-------+
3348 	  * BCM57XX  |   X   |   X   |   X   |   X   |
3349 	  * BCM5704  |   X   |   X   |   X   |   X   |
3350 	  * BCM5717  |   X   |   X   |   X   |   X   |
3351 	  * BCM5719  |   3   |   10  |   4   |   11  |
3352 	  * BCM5720  |   X   |   X   |   X   |   X   |
3353 	  *
3354 	  * Other addresses may respond but they are not
3355 	  * IEEE compliant PHYs and should be ignored.
3356 	  */
3357 	if (sc->bge_asicrev == BGE_ASICREV_BCM5717 ||
3358 	    sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3359 	    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3360 		if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) {
3361 			if (CSR_READ_4(sc, BGE_SGDIG_STS) &
3362 			    BGE_SGDIGSTS_IS_SERDES)
3363 				sc->bge_phy_addr = sc->bge_func_addr + 8;
3364 			else
3365 				sc->bge_phy_addr = sc->bge_func_addr + 1;
3366 		} else {
3367 			if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) &
3368 			    BGE_CPMU_PHY_STRAP_IS_SERDES)
3369 				sc->bge_phy_addr = sc->bge_func_addr + 8;
3370 			else
3371 				sc->bge_phy_addr = sc->bge_func_addr + 1;
3372 		}
3373 	}
3374 
3375 	if (bge_has_eaddr(sc))
3376 		sc->bge_flags |= BGE_FLAG_EADDR;
3377 
3378 	/* Save chipset family. */
3379 	switch (sc->bge_asicrev) {
3380 	case BGE_ASICREV_BCM5762:
3381 	case BGE_ASICREV_BCM57765:
3382 	case BGE_ASICREV_BCM57766:
3383 		sc->bge_flags |= BGE_FLAG_57765_PLUS;
3384 		/* FALLTHROUGH */
3385 	case BGE_ASICREV_BCM5717:
3386 	case BGE_ASICREV_BCM5719:
3387 	case BGE_ASICREV_BCM5720:
3388 		sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS |
3389 		    BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO |
3390 		    BGE_FLAG_JUMBO_FRAME;
3391 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3392 		    sc->bge_asicrev == BGE_ASICREV_BCM5720) {
3393 			/*
3394 			 * Enable work around for DMA engine miscalculation
3395 			 * of TXMBUF available space.
3396 			 */
3397 			sc->bge_flags |= BGE_FLAG_RDMA_BUG;
3398 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3399 			    sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3400 				/* Jumbo frame on BCM5719 A0 does not work. */
3401 				sc->bge_flags &= ~BGE_FLAG_JUMBO;
3402 			}
3403 		}
3404 		break;
3405 	case BGE_ASICREV_BCM5755:
3406 	case BGE_ASICREV_BCM5761:
3407 	case BGE_ASICREV_BCM5784:
3408 	case BGE_ASICREV_BCM5785:
3409 	case BGE_ASICREV_BCM5787:
3410 	case BGE_ASICREV_BCM57780:
3411 		sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS |
3412 		    BGE_FLAG_5705_PLUS;
3413 		break;
3414 	case BGE_ASICREV_BCM5700:
3415 	case BGE_ASICREV_BCM5701:
3416 	case BGE_ASICREV_BCM5703:
3417 	case BGE_ASICREV_BCM5704:
3418 		sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO;
3419 		break;
3420 	case BGE_ASICREV_BCM5714_A0:
3421 	case BGE_ASICREV_BCM5780:
3422 	case BGE_ASICREV_BCM5714:
3423 		sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD;
3424 		/* FALLTHROUGH */
3425 	case BGE_ASICREV_BCM5750:
3426 	case BGE_ASICREV_BCM5752:
3427 	case BGE_ASICREV_BCM5906:
3428 		sc->bge_flags |= BGE_FLAG_575X_PLUS;
3429 		/* FALLTHROUGH */
3430 	case BGE_ASICREV_BCM5705:
3431 		sc->bge_flags |= BGE_FLAG_5705_PLUS;
3432 		break;
3433 	}
3434 
3435 	/* Identify chips with APE processor. */
3436 	switch (sc->bge_asicrev) {
3437 	case BGE_ASICREV_BCM5717:
3438 	case BGE_ASICREV_BCM5719:
3439 	case BGE_ASICREV_BCM5720:
3440 	case BGE_ASICREV_BCM5761:
3441 	case BGE_ASICREV_BCM5762:
3442 		sc->bge_flags |= BGE_FLAG_APE;
3443 		break;
3444 	}
3445 
3446 	/* Chips with APE need BAR2 access for APE registers/memory. */
3447 	if ((sc->bge_flags & BGE_FLAG_APE) != 0) {
3448 		rid = PCIR_BAR(2);
3449 		sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
3450 		    RF_ACTIVE);
3451 		if (sc->bge_res2 == NULL) {
3452 			device_printf (sc->bge_dev,
3453 			    "couldn't map BAR2 memory\n");
3454 			error = ENXIO;
3455 			goto fail;
3456 		}
3457 
3458 		/* Enable APE register/memory access by host driver. */
3459 		pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
3460 		pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
3461 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
3462 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
3463 		pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4);
3464 
3465 		bge_ape_lock_init(sc);
3466 		bge_ape_read_fw_ver(sc);
3467 	}
3468 
3469 	/* Add SYSCTLs, requires the chipset family to be set. */
3470 	bge_add_sysctls(sc);
3471 
3472 	/* Identify the chips that use an CPMU. */
3473 	if (BGE_IS_5717_PLUS(sc) ||
3474 	    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3475 	    sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3476 	    sc->bge_asicrev == BGE_ASICREV_BCM5785 ||
3477 	    sc->bge_asicrev == BGE_ASICREV_BCM57780)
3478 		sc->bge_flags |= BGE_FLAG_CPMU_PRESENT;
3479 	if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0)
3480 		sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST;
3481 	else
3482 		sc->bge_mi_mode = BGE_MIMODE_BASE;
3483 	/* Enable auto polling for BCM570[0-5]. */
3484 	if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705)
3485 		sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL;
3486 
3487 	/*
3488 	 * All Broadcom controllers have 4GB boundary DMA bug.
3489 	 * Whenever an address crosses a multiple of the 4GB boundary
3490 	 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition
3491 	 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA
3492 	 * state machine will lockup and cause the device to hang.
3493 	 */
3494 	sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG;
3495 
3496 	/* BCM5755 or higher and BCM5906 have short DMA bug. */
3497 	if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
3498 		sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG;
3499 
3500 	/*
3501 	 * BCM5719 cannot handle DMA requests for DMA segments that
3502 	 * have larger than 4KB in size.  However the maximum DMA
3503 	 * segment size created in DMA tag is 4KB for TSO, so we
3504 	 * wouldn't encounter the issue here.
3505 	 */
3506 	if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
3507 		sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG;
3508 
3509 	misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK;
3510 	if (sc->bge_asicrev == BGE_ASICREV_BCM5705) {
3511 		if (misccfg == BGE_MISCCFG_BOARD_ID_5788 ||
3512 		    misccfg == BGE_MISCCFG_BOARD_ID_5788M)
3513 			sc->bge_flags |= BGE_FLAG_5788;
3514 	}
3515 
3516 	capmask = BMSR_DEFCAPMASK;
3517 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 &&
3518 	    (misccfg == 0x4000 || misccfg == 0x8000)) ||
3519 	    (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3520 	    pci_get_vendor(dev) == BCOM_VENDORID &&
3521 	    (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 ||
3522 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 ||
3523 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) ||
3524 	    (pci_get_vendor(dev) == BCOM_VENDORID &&
3525 	    (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F ||
3526 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5753F ||
3527 	    pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) ||
3528 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57790 ||
3529 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57791 ||
3530 	    pci_get_device(dev) == BCOM_DEVICEID_BCM57795 ||
3531 	    sc->bge_asicrev == BGE_ASICREV_BCM5906) {
3532 		/* These chips are 10/100 only. */
3533 		capmask &= ~BMSR_EXTSTAT;
3534 		sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3535 	}
3536 
3537 	/*
3538 	 * Some controllers seem to require a special firmware to use
3539 	 * TSO. But the firmware is not available to FreeBSD and Linux
3540 	 * claims that the TSO performed by the firmware is slower than
3541 	 * hardware based TSO. Moreover the firmware based TSO has one
3542 	 * known bug which can't handle TSO if Ethernet header + IP/TCP
3543 	 * header is greater than 80 bytes. A workaround for the TSO
3544 	 * bug exist but it seems it's too expensive than not using
3545 	 * TSO at all. Some hardwares also have the TSO bug so limit
3546 	 * the TSO to the controllers that are not affected TSO issues
3547 	 * (e.g. 5755 or higher).
3548 	 */
3549 	if (BGE_IS_5717_PLUS(sc)) {
3550 		/* BCM5717 requires different TSO configuration. */
3551 		sc->bge_flags |= BGE_FLAG_TSO3;
3552 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 &&
3553 		    sc->bge_chipid == BGE_CHIPID_BCM5719_A0) {
3554 			/* TSO on BCM5719 A0 does not work. */
3555 			sc->bge_flags &= ~BGE_FLAG_TSO3;
3556 		}
3557 	} else if (BGE_IS_5755_PLUS(sc)) {
3558 		/*
3559 		 * BCM5754 and BCM5787 shares the same ASIC id so
3560 		 * explicit device id check is required.
3561 		 * Due to unknown reason TSO does not work on BCM5755M.
3562 		 */
3563 		if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 &&
3564 		    pci_get_device(dev) != BCOM_DEVICEID_BCM5754M &&
3565 		    pci_get_device(dev) != BCOM_DEVICEID_BCM5755M)
3566 			sc->bge_flags |= BGE_FLAG_TSO;
3567 	}
3568 
3569 	/*
3570 	 * Check if this is a PCI-X or PCI Express device.
3571 	 */
3572 	if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3573 		/*
3574 		 * Found a PCI Express capabilities register, this
3575 		 * must be a PCI Express device.
3576 		 */
3577 		sc->bge_flags |= BGE_FLAG_PCIE;
3578 		sc->bge_expcap = reg;
3579 		/* Extract supported maximum payload size. */
3580 		sc->bge_mps = pci_read_config(dev, sc->bge_expcap +
3581 		    PCIER_DEVICE_CAP, 2);
3582 		sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD);
3583 		if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3584 		    sc->bge_asicrev == BGE_ASICREV_BCM5720)
3585 			sc->bge_expmrq = 2048;
3586 		else
3587 			sc->bge_expmrq = 4096;
3588 		pci_set_max_read_req(dev, sc->bge_expmrq);
3589 	} else {
3590 		/*
3591 		 * Check if the device is in PCI-X Mode.
3592 		 * (This bit is not valid on PCI Express controllers.)
3593 		 */
3594 		if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3595 			sc->bge_pcixcap = reg;
3596 		if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
3597 		    BGE_PCISTATE_PCI_BUSMODE) == 0)
3598 			sc->bge_flags |= BGE_FLAG_PCIX;
3599 	}
3600 
3601 	/*
3602 	 * The 40bit DMA bug applies to the 5714/5715 controllers and is
3603 	 * not actually a MAC controller bug but an issue with the embedded
3604 	 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround.
3605 	 */
3606 	if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX))
3607 		sc->bge_flags |= BGE_FLAG_40BIT_BUG;
3608 	/*
3609 	 * Some PCI-X bridges are known to trigger write reordering to
3610 	 * the mailbox registers. Typical phenomena is watchdog timeouts
3611 	 * caused by out-of-order TX completions.  Enable workaround for
3612 	 * PCI-X devices that live behind these bridges.
3613 	 * Note, PCI-X controllers can run in PCI mode so we can't use
3614 	 * BGE_FLAG_PCIX flag to detect PCI-X controllers.
3615 	 */
3616 	if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0)
3617 		sc->bge_flags |= BGE_FLAG_MBOX_REORDER;
3618 	/*
3619 	 * Allocate the interrupt, using MSI if possible.  These devices
3620 	 * support 8 MSI messages, but only the first one is used in
3621 	 * normal operation.
3622 	 */
3623 	rid = 0;
3624 	if (pci_find_cap(sc->bge_dev, PCIY_MSI, &reg) == 0) {
3625 		sc->bge_msicap = reg;
3626 		reg = 1;
3627 		if (bge_can_use_msi(sc) && pci_alloc_msi(dev, &reg) == 0) {
3628 			rid = 1;
3629 			sc->bge_flags |= BGE_FLAG_MSI;
3630 		}
3631 	}
3632 
3633 	/*
3634 	 * All controllers except BCM5700 supports tagged status but
3635 	 * we use tagged status only for MSI case on BCM5717. Otherwise
3636 	 * MSI on BCM5717 does not work.
3637 	 */
3638 #ifndef DEVICE_POLLING
3639 	if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc))
3640 		sc->bge_flags |= BGE_FLAG_TAGGED_STATUS;
3641 #endif
3642 
3643 	sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
3644 	    RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
3645 
3646 	if (sc->bge_irq == NULL) {
3647 		device_printf(sc->bge_dev, "couldn't map interrupt\n");
3648 		error = ENXIO;
3649 		goto fail;
3650 	}
3651 
3652 	bge_devinfo(sc);
3653 
3654 	sc->bge_asf_mode = 0;
3655 	/* No ASF if APE present. */
3656 	if ((sc->bge_flags & BGE_FLAG_APE) == 0) {
3657 		if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) ==
3658 		    BGE_SRAM_DATA_SIG_MAGIC)) {
3659 			if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) &
3660 			    BGE_HWCFG_ASF) {
3661 				sc->bge_asf_mode |= ASF_ENABLE;
3662 				sc->bge_asf_mode |= ASF_STACKUP;
3663 				if (BGE_IS_575X_PLUS(sc))
3664 					sc->bge_asf_mode |= ASF_NEW_HANDSHAKE;
3665 			}
3666 		}
3667 	}
3668 
3669 	bge_stop_fw(sc);
3670 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
3671 	if (bge_reset(sc)) {
3672 		device_printf(sc->bge_dev, "chip reset failed\n");
3673 		error = ENXIO;
3674 		goto fail;
3675 	}
3676 
3677 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
3678 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
3679 
3680 	if (bge_chipinit(sc)) {
3681 		device_printf(sc->bge_dev, "chip initialization failed\n");
3682 		error = ENXIO;
3683 		goto fail;
3684 	}
3685 
3686 	error = bge_get_eaddr(sc, eaddr);
3687 	if (error) {
3688 		device_printf(sc->bge_dev,
3689 		    "failed to read station address\n");
3690 		error = ENXIO;
3691 		goto fail;
3692 	}
3693 
3694 	/* 5705 limits RX return ring to 512 entries. */
3695 	if (BGE_IS_5717_PLUS(sc))
3696 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3697 	else if (BGE_IS_5705_PLUS(sc))
3698 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
3699 	else
3700 		sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
3701 
3702 	if (bge_dma_alloc(sc)) {
3703 		device_printf(sc->bge_dev,
3704 		    "failed to allocate DMA resources\n");
3705 		error = ENXIO;
3706 		goto fail;
3707 	}
3708 
3709 	/* Set default tuneable values. */
3710 	sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
3711 	sc->bge_rx_coal_ticks = 150;
3712 	sc->bge_tx_coal_ticks = 150;
3713 	sc->bge_rx_max_coal_bds = 10;
3714 	sc->bge_tx_max_coal_bds = 10;
3715 
3716 	/* Initialize checksum features to use. */
3717 	sc->bge_csum_features = BGE_CSUM_FEATURES;
3718 	if (sc->bge_forced_udpcsum != 0)
3719 		sc->bge_csum_features |= CSUM_UDP;
3720 
3721 	/* Set up ifnet structure */
3722 	ifp = sc->bge_ifp = if_alloc(IFT_ETHER);
3723 	if (ifp == NULL) {
3724 		device_printf(sc->bge_dev, "failed to if_alloc()\n");
3725 		error = ENXIO;
3726 		goto fail;
3727 	}
3728 	if_setsoftc(ifp, sc);
3729 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
3730 	if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST);
3731 	if_setioctlfn(ifp, bge_ioctl);
3732 	if_setstartfn(ifp, bge_start);
3733 	if_setinitfn(ifp, bge_init);
3734 	if_setgetcounterfn(ifp, bge_get_counter);
3735 	if_setsendqlen(ifp, BGE_TX_RING_CNT - 1);
3736 	if_setsendqready(ifp);
3737 	if_sethwassist(ifp, sc->bge_csum_features);
3738 	if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
3739 	    IFCAP_VLAN_MTU);
3740 	if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) {
3741 		if_sethwassistbits(ifp, CSUM_TSO, 0);
3742 		if_setcapabilitiesbit(ifp, IFCAP_TSO4 | IFCAP_VLAN_HWTSO, 0);
3743 	}
3744 #ifdef IFCAP_VLAN_HWCSUM
3745 	if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM, 0);
3746 #endif
3747 	if_setcapenable(ifp, if_getcapabilities(ifp));
3748 #ifdef DEVICE_POLLING
3749 	if_setcapabilitiesbit(ifp, IFCAP_POLLING, 0);
3750 #endif
3751 
3752 	/*
3753 	 * 5700 B0 chips do not support checksumming correctly due
3754 	 * to hardware bugs.
3755 	 */
3756 	if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) {
3757 		if_setcapabilitiesbit(ifp, 0, IFCAP_HWCSUM);
3758 		if_setcapenablebit(ifp, 0, IFCAP_HWCSUM);
3759 		if_sethwassist(ifp, 0);
3760 	}
3761 
3762 	/*
3763 	 * Figure out what sort of media we have by checking the
3764 	 * hardware config word in the first 32k of NIC internal memory,
3765 	 * or fall back to examining the EEPROM if necessary.
3766 	 * Note: on some BCM5700 cards, this value appears to be unset.
3767 	 * If that's the case, we have to rely on identifying the NIC
3768 	 * by its PCI subsystem ID, as we do below for the SysKonnect
3769 	 * SK-9D41.
3770 	 */
3771 	if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC)
3772 		hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG);
3773 	else if ((sc->bge_flags & BGE_FLAG_EADDR) &&
3774 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
3775 		if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET,
3776 		    sizeof(hwcfg))) {
3777 			device_printf(sc->bge_dev, "failed to read EEPROM\n");
3778 			error = ENXIO;
3779 			goto fail;
3780 		}
3781 		hwcfg = ntohl(hwcfg);
3782 	}
3783 
3784 	/* The SysKonnect SK-9D41 is a 1000baseSX card. */
3785 	if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) ==
3786 	    SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) {
3787 		if (BGE_IS_5705_PLUS(sc)) {
3788 			sc->bge_flags |= BGE_FLAG_MII_SERDES;
3789 			sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3790 		} else
3791 			sc->bge_flags |= BGE_FLAG_TBI;
3792 	}
3793 
3794 	/* Set various PHY bug flags. */
3795 	if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 ||
3796 	    sc->bge_chipid == BGE_CHIPID_BCM5701_B0)
3797 		sc->bge_phy_flags |= BGE_PHY_CRC_BUG;
3798 	if (sc->bge_chiprev == BGE_CHIPREV_5703_AX ||
3799 	    sc->bge_chiprev == BGE_CHIPREV_5704_AX)
3800 		sc->bge_phy_flags |= BGE_PHY_ADC_BUG;
3801 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0)
3802 		sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG;
3803 	if (pci_get_subvendor(dev) == DELL_VENDORID)
3804 		sc->bge_phy_flags |= BGE_PHY_NO_3LED;
3805 	if ((BGE_IS_5705_PLUS(sc)) &&
3806 	    sc->bge_asicrev != BGE_ASICREV_BCM5906 &&
3807 	    sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
3808 	    sc->bge_asicrev != BGE_ASICREV_BCM57780 &&
3809 	    !BGE_IS_5717_PLUS(sc)) {
3810 		if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
3811 		    sc->bge_asicrev == BGE_ASICREV_BCM5761 ||
3812 		    sc->bge_asicrev == BGE_ASICREV_BCM5784 ||
3813 		    sc->bge_asicrev == BGE_ASICREV_BCM5787) {
3814 			if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 &&
3815 			    pci_get_device(dev) != BCOM_DEVICEID_BCM5756)
3816 				sc->bge_phy_flags |= BGE_PHY_JITTER_BUG;
3817 			if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M)
3818 				sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM;
3819 		} else
3820 			sc->bge_phy_flags |= BGE_PHY_BER_BUG;
3821 	}
3822 
3823 	/*
3824 	 * Don't enable Ethernet@WireSpeed for the 5700 or the
3825 	 * 5705 A0 and A1 chips.
3826 	 */
3827 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
3828 	    (sc->bge_asicrev == BGE_ASICREV_BCM5705 &&
3829 	    (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 &&
3830 	    sc->bge_chipid != BGE_CHIPID_BCM5705_A1)))
3831 		sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED;
3832 
3833 	if (sc->bge_flags & BGE_FLAG_TBI) {
3834 		ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd,
3835 		    bge_ifmedia_sts);
3836 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL);
3837 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX,
3838 		    0, NULL);
3839 		ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
3840 		ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO);
3841 		sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
3842 	} else {
3843 		/*
3844 		 * Do transceiver setup and tell the firmware the
3845 		 * driver is down so we can try to get access the
3846 		 * probe if ASF is running.  Retry a couple of times
3847 		 * if we get a conflict with the ASF firmware accessing
3848 		 * the PHY.
3849 		 */
3850 		trys = 0;
3851 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3852 again:
3853 		bge_asf_driver_up(sc);
3854 
3855 		error = mii_attach(dev, &sc->bge_miibus, ifp,
3856 		    (ifm_change_cb_t)bge_ifmedia_upd,
3857 		    (ifm_stat_cb_t)bge_ifmedia_sts, capmask, sc->bge_phy_addr,
3858 		    MII_OFFSET_ANY, MIIF_DOPAUSE);
3859 		if (error != 0) {
3860 			if (trys++ < 4) {
3861 				device_printf(sc->bge_dev, "Try again\n");
3862 				bge_miibus_writereg(sc->bge_dev,
3863 				    sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
3864 				goto again;
3865 			}
3866 			device_printf(sc->bge_dev, "attaching PHYs failed\n");
3867 			goto fail;
3868 		}
3869 
3870 		/*
3871 		 * Now tell the firmware we are going up after probing the PHY
3872 		 */
3873 		if (sc->bge_asf_mode & ASF_STACKUP)
3874 			BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
3875 	}
3876 
3877 	/*
3878 	 * When using the BCM5701 in PCI-X mode, data corruption has
3879 	 * been observed in the first few bytes of some received packets.
3880 	 * Aligning the packet buffer in memory eliminates the corruption.
3881 	 * Unfortunately, this misaligns the packet payloads.  On platforms
3882 	 * which do not support unaligned accesses, we will realign the
3883 	 * payloads by copying the received packets.
3884 	 */
3885 	if (sc->bge_asicrev == BGE_ASICREV_BCM5701 &&
3886 	    sc->bge_flags & BGE_FLAG_PCIX)
3887                 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG;
3888 
3889 	/*
3890 	 * Call MI attach routine.
3891 	 */
3892 	ether_ifattach(ifp, eaddr);
3893 
3894 	/* Tell upper layer we support long frames. */
3895 	if_setifheaderlen(ifp, sizeof(struct ether_vlan_header));
3896 
3897 	/*
3898 	 * Hookup IRQ last.
3899 	 */
3900 	if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) {
3901 		/* Take advantage of single-shot MSI. */
3902 		CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) &
3903 		    ~BGE_MSIMODE_ONE_SHOT_DISABLE);
3904 		sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK,
3905 		    taskqueue_thread_enqueue, &sc->bge_tq);
3906 		if (sc->bge_tq == NULL) {
3907 			device_printf(dev, "could not create taskqueue.\n");
3908 			ether_ifdetach(ifp);
3909 			error = ENOMEM;
3910 			goto fail;
3911 		}
3912 		error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET,
3913 		    "%s taskq", device_get_nameunit(sc->bge_dev));
3914 		if (error != 0) {
3915 			device_printf(dev, "could not start threads.\n");
3916 			ether_ifdetach(ifp);
3917 			goto fail;
3918 		}
3919 		error = bus_setup_intr(dev, sc->bge_irq,
3920 		    INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc,
3921 		    &sc->bge_intrhand);
3922 	} else
3923 		error = bus_setup_intr(dev, sc->bge_irq,
3924 		    INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc,
3925 		    &sc->bge_intrhand);
3926 
3927 	if (error) {
3928 		ether_ifdetach(ifp);
3929 		device_printf(sc->bge_dev, "couldn't set up irq\n");
3930 		goto fail;
3931 	}
3932 
3933 	/* Attach driver debugnet methods. */
3934 	DEBUGNET_SET(ifp, bge);
3935 
3936 fail:
3937 	if (error)
3938 		bge_detach(dev);
3939 	return (error);
3940 }
3941 
3942 static int
3943 bge_detach(device_t dev)
3944 {
3945 	struct bge_softc *sc;
3946 	if_t ifp;
3947 
3948 	sc = device_get_softc(dev);
3949 	ifp = sc->bge_ifp;
3950 
3951 #ifdef DEVICE_POLLING
3952 	if (if_getcapenable(ifp) & IFCAP_POLLING)
3953 		ether_poll_deregister(ifp);
3954 #endif
3955 
3956 	if (device_is_attached(dev)) {
3957 		ether_ifdetach(ifp);
3958 		BGE_LOCK(sc);
3959 		bge_stop(sc);
3960 		BGE_UNLOCK(sc);
3961 		callout_drain(&sc->bge_stat_ch);
3962 	}
3963 
3964 	if (sc->bge_tq)
3965 		taskqueue_drain(sc->bge_tq, &sc->bge_intr_task);
3966 
3967 	if (sc->bge_flags & BGE_FLAG_TBI)
3968 		ifmedia_removeall(&sc->bge_ifmedia);
3969 	else if (sc->bge_miibus != NULL) {
3970 		bus_generic_detach(dev);
3971 		device_delete_child(dev, sc->bge_miibus);
3972 	}
3973 
3974 	bge_release_resources(sc);
3975 
3976 	return (0);
3977 }
3978 
3979 static void
3980 bge_release_resources(struct bge_softc *sc)
3981 {
3982 	device_t dev;
3983 
3984 	dev = sc->bge_dev;
3985 
3986 	if (sc->bge_tq != NULL)
3987 		taskqueue_free(sc->bge_tq);
3988 
3989 	if (sc->bge_intrhand != NULL)
3990 		bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
3991 
3992 	if (sc->bge_irq != NULL) {
3993 		bus_release_resource(dev, SYS_RES_IRQ,
3994 		    rman_get_rid(sc->bge_irq), sc->bge_irq);
3995 		pci_release_msi(dev);
3996 	}
3997 
3998 	if (sc->bge_res != NULL)
3999 		bus_release_resource(dev, SYS_RES_MEMORY,
4000 		    rman_get_rid(sc->bge_res), sc->bge_res);
4001 
4002 	if (sc->bge_res2 != NULL)
4003 		bus_release_resource(dev, SYS_RES_MEMORY,
4004 		    rman_get_rid(sc->bge_res2), sc->bge_res2);
4005 
4006 	if (sc->bge_ifp != NULL)
4007 		if_free(sc->bge_ifp);
4008 
4009 	bge_dma_free(sc);
4010 
4011 	if (mtx_initialized(&sc->bge_mtx))	/* XXX */
4012 		BGE_LOCK_DESTROY(sc);
4013 }
4014 
4015 static int
4016 bge_reset(struct bge_softc *sc)
4017 {
4018 	device_t dev;
4019 	uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val;
4020 	void (*write_op)(struct bge_softc *, int, int);
4021 	uint16_t devctl;
4022 	int i;
4023 
4024 	dev = sc->bge_dev;
4025 
4026 	mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE;
4027 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4028 		mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN;
4029 	mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask;
4030 
4031 	if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) &&
4032 	    (sc->bge_asicrev != BGE_ASICREV_BCM5906)) {
4033 		if (sc->bge_flags & BGE_FLAG_PCIE)
4034 			write_op = bge_writemem_direct;
4035 		else
4036 			write_op = bge_writemem_ind;
4037 	} else
4038 		write_op = bge_writereg_ind;
4039 
4040 	if (sc->bge_asicrev != BGE_ASICREV_BCM5700 &&
4041 	    sc->bge_asicrev != BGE_ASICREV_BCM5701) {
4042 		CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1);
4043 		for (i = 0; i < 8000; i++) {
4044 			if (CSR_READ_4(sc, BGE_NVRAM_SWARB) &
4045 			    BGE_NVRAMSWARB_GNT1)
4046 				break;
4047 			DELAY(20);
4048 		}
4049 		if (i == 8000) {
4050 			if (bootverbose)
4051 				device_printf(dev, "NVRAM lock timedout!\n");
4052 		}
4053 	}
4054 	/* Take APE lock when performing reset. */
4055 	bge_ape_lock(sc, BGE_APE_LOCK_GRC);
4056 
4057 	/* Save some important PCI state. */
4058 	cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
4059 	command = pci_read_config(dev, BGE_PCI_CMD, 4);
4060 
4061 	pci_write_config(dev, BGE_PCI_MISC_CTL,
4062 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4063 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4064 
4065 	/* Disable fastboot on controllers that support it. */
4066 	if (sc->bge_asicrev == BGE_ASICREV_BCM5752 ||
4067 	    BGE_IS_5755_PLUS(sc)) {
4068 		if (bootverbose)
4069 			device_printf(dev, "Disabling fastboot\n");
4070 		CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0);
4071 	}
4072 
4073 	/*
4074 	 * Write the magic number to SRAM at offset 0xB50.
4075 	 * When firmware finishes its initialization it will
4076 	 * write ~BGE_SRAM_FW_MB_MAGIC to the same location.
4077 	 */
4078 	bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC);
4079 
4080 	reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ;
4081 
4082 	/* XXX: Broadcom Linux driver. */
4083 	if (sc->bge_flags & BGE_FLAG_PCIE) {
4084 		if (sc->bge_asicrev != BGE_ASICREV_BCM5785 &&
4085 		    (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) {
4086 			if (CSR_READ_4(sc, 0x7E2C) == 0x60)	/* PCIE 1.0 */
4087 				CSR_WRITE_4(sc, 0x7E2C, 0x20);
4088 		}
4089 		if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
4090 			/* Prevent PCIE link training during global reset */
4091 			CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29);
4092 			reset |= 1 << 29;
4093 		}
4094 	}
4095 
4096 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4097 		val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4098 		CSR_WRITE_4(sc, BGE_VCPU_STATUS,
4099 		    val | BGE_VCPU_STATUS_DRV_RESET);
4100 		val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL);
4101 		CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL,
4102 		    val & ~BGE_VCPU_EXT_CTRL_HALT_CPU);
4103 	}
4104 
4105 	/*
4106 	 * Set GPHY Power Down Override to leave GPHY
4107 	 * powered up in D0 uninitialized.
4108 	 */
4109 	if (BGE_IS_5705_PLUS(sc) &&
4110 	    (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0)
4111 		reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE;
4112 
4113 	/* Issue global reset */
4114 	write_op(sc, BGE_MISC_CFG, reset);
4115 
4116 	if (sc->bge_flags & BGE_FLAG_PCIE)
4117 		DELAY(100 * 1000);
4118 	else
4119 		DELAY(1000);
4120 
4121 	/* XXX: Broadcom Linux driver. */
4122 	if (sc->bge_flags & BGE_FLAG_PCIE) {
4123 		if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
4124 			DELAY(500000); /* wait for link training to complete */
4125 			val = pci_read_config(dev, 0xC4, 4);
4126 			pci_write_config(dev, 0xC4, val | (1 << 15), 4);
4127 		}
4128 		devctl = pci_read_config(dev,
4129 		    sc->bge_expcap + PCIER_DEVICE_CTL, 2);
4130 		/* Clear enable no snoop and disable relaxed ordering. */
4131 		devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
4132 		    PCIEM_CTL_NOSNOOP_ENABLE);
4133 		pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
4134 		    devctl, 2);
4135 		pci_set_max_read_req(dev, sc->bge_expmrq);
4136 		/* Clear error status. */
4137 		pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
4138 		    PCIEM_STA_CORRECTABLE_ERROR |
4139 		    PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
4140 		    PCIEM_STA_UNSUPPORTED_REQ, 2);
4141 	}
4142 
4143 	/* Reset some of the PCI state that got zapped by reset. */
4144 	pci_write_config(dev, BGE_PCI_MISC_CTL,
4145 	    BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR |
4146 	    BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4);
4147 	val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE;
4148 	if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 &&
4149 	    (sc->bge_flags & BGE_FLAG_PCIX) != 0)
4150 		val |= BGE_PCISTATE_RETRY_SAME_DMA;
4151 	if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0)
4152 		val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR |
4153 		    BGE_PCISTATE_ALLOW_APE_SHMEM_WR |
4154 		    BGE_PCISTATE_ALLOW_APE_PSPACE_WR;
4155 	pci_write_config(dev, BGE_PCI_PCISTATE, val, 4);
4156 	pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
4157 	pci_write_config(dev, BGE_PCI_CMD, command, 4);
4158 	/*
4159 	 * Disable PCI-X relaxed ordering to ensure status block update
4160 	 * comes first then packet buffer DMA. Otherwise driver may
4161 	 * read stale status block.
4162 	 */
4163 	if (sc->bge_flags & BGE_FLAG_PCIX) {
4164 		devctl = pci_read_config(dev,
4165 		    sc->bge_pcixcap + PCIXR_COMMAND, 2);
4166 		devctl &= ~PCIXM_COMMAND_ERO;
4167 		if (sc->bge_asicrev == BGE_ASICREV_BCM5703) {
4168 			devctl &= ~PCIXM_COMMAND_MAX_READ;
4169 			devctl |= PCIXM_COMMAND_MAX_READ_2048;
4170 		} else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
4171 			devctl &= ~(PCIXM_COMMAND_MAX_SPLITS |
4172 			    PCIXM_COMMAND_MAX_READ);
4173 			devctl |= PCIXM_COMMAND_MAX_READ_2048;
4174 		}
4175 		pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND,
4176 		    devctl, 2);
4177 	}
4178 	/* Re-enable MSI, if necessary, and enable the memory arbiter. */
4179 	if (BGE_IS_5714_FAMILY(sc)) {
4180 		/* This chip disables MSI on reset. */
4181 		if (sc->bge_flags & BGE_FLAG_MSI) {
4182 			val = pci_read_config(dev,
4183 			    sc->bge_msicap + PCIR_MSI_CTRL, 2);
4184 			pci_write_config(dev,
4185 			    sc->bge_msicap + PCIR_MSI_CTRL,
4186 			    val | PCIM_MSICTRL_MSI_ENABLE, 2);
4187 			val = CSR_READ_4(sc, BGE_MSI_MODE);
4188 			CSR_WRITE_4(sc, BGE_MSI_MODE,
4189 			    val | BGE_MSIMODE_ENABLE);
4190 		}
4191 		val = CSR_READ_4(sc, BGE_MARB_MODE);
4192 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val);
4193 	} else
4194 		CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
4195 
4196 	/* Fix up byte swapping. */
4197 	CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc));
4198 
4199 	val = CSR_READ_4(sc, BGE_MAC_MODE);
4200 	val = (val & ~mac_mode_mask) | mac_mode;
4201 	CSR_WRITE_4(sc, BGE_MAC_MODE, val);
4202 	DELAY(40);
4203 
4204 	bge_ape_unlock(sc, BGE_APE_LOCK_GRC);
4205 
4206 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906) {
4207 		for (i = 0; i < BGE_TIMEOUT; i++) {
4208 			val = CSR_READ_4(sc, BGE_VCPU_STATUS);
4209 			if (val & BGE_VCPU_STATUS_INIT_DONE)
4210 				break;
4211 			DELAY(100);
4212 		}
4213 		if (i == BGE_TIMEOUT) {
4214 			device_printf(dev, "reset timed out\n");
4215 			return (1);
4216 		}
4217 	} else {
4218 		/*
4219 		 * Poll until we see the 1's complement of the magic number.
4220 		 * This indicates that the firmware initialization is complete.
4221 		 * We expect this to fail if no chip containing the Ethernet
4222 		 * address is fitted though.
4223 		 */
4224 		for (i = 0; i < BGE_TIMEOUT; i++) {
4225 			DELAY(10);
4226 			val = bge_readmem_ind(sc, BGE_SRAM_FW_MB);
4227 			if (val == ~BGE_SRAM_FW_MB_MAGIC)
4228 				break;
4229 		}
4230 
4231 		if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT)
4232 			device_printf(dev,
4233 			    "firmware handshake timed out, found 0x%08x\n",
4234 			    val);
4235 		/* BCM57765 A0 needs additional time before accessing. */
4236 		if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0)
4237 			DELAY(10 * 1000);	/* XXX */
4238 	}
4239 
4240 	/*
4241 	 * The 5704 in TBI mode apparently needs some special
4242 	 * adjustment to insure the SERDES drive level is set
4243 	 * to 1.2V.
4244 	 */
4245 	if (sc->bge_asicrev == BGE_ASICREV_BCM5704 &&
4246 	    sc->bge_flags & BGE_FLAG_TBI) {
4247 		val = CSR_READ_4(sc, BGE_SERDES_CFG);
4248 		val = (val & ~0xFFF) | 0x880;
4249 		CSR_WRITE_4(sc, BGE_SERDES_CFG, val);
4250 	}
4251 
4252 	/* XXX: Broadcom Linux driver. */
4253 	if (sc->bge_flags & BGE_FLAG_PCIE &&
4254 	    !BGE_IS_5717_PLUS(sc) &&
4255 	    sc->bge_chipid != BGE_CHIPID_BCM5750_A0 &&
4256 	    sc->bge_asicrev != BGE_ASICREV_BCM5785) {
4257 		/* Enable Data FIFO protection. */
4258 		val = CSR_READ_4(sc, 0x7C00);
4259 		CSR_WRITE_4(sc, 0x7C00, val | (1 << 25));
4260 	}
4261 
4262 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720)
4263 		BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE,
4264 		    CPMU_CLCK_ORIDE_MAC_ORIDE_EN);
4265 
4266 	return (0);
4267 }
4268 
4269 static __inline void
4270 bge_rxreuse_std(struct bge_softc *sc, int i)
4271 {
4272 	struct bge_rx_bd *r;
4273 
4274 	r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std];
4275 	r->bge_flags = BGE_RXBDFLAG_END;
4276 	r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i];
4277 	r->bge_idx = i;
4278 	BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4279 }
4280 
4281 static __inline void
4282 bge_rxreuse_jumbo(struct bge_softc *sc, int i)
4283 {
4284 	struct bge_extrx_bd *r;
4285 
4286 	r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo];
4287 	r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END;
4288 	r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0];
4289 	r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1];
4290 	r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2];
4291 	r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3];
4292 	r->bge_idx = i;
4293 	BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4294 }
4295 
4296 /*
4297  * Frame reception handling. This is called if there's a frame
4298  * on the receive return list.
4299  *
4300  * Note: we have to be able to handle two possibilities here:
4301  * 1) the frame is from the jumbo receive ring
4302  * 2) the frame is from the standard receive ring
4303  */
4304 
4305 static int
4306 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck)
4307 {
4308 	if_t ifp;
4309 	int rx_npkts = 0, stdcnt = 0, jumbocnt = 0;
4310 	uint16_t rx_cons;
4311 
4312 	rx_cons = sc->bge_rx_saved_considx;
4313 
4314 	/* Nothing to do. */
4315 	if (rx_cons == rx_prod)
4316 		return (rx_npkts);
4317 
4318 	ifp = sc->bge_ifp;
4319 
4320 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4321 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD);
4322 	bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4323 	    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE);
4324 	if (BGE_IS_JUMBO_CAPABLE(sc) &&
4325 	    if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
4326 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))
4327 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4328 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE);
4329 
4330 	while (rx_cons != rx_prod) {
4331 		struct bge_rx_bd	*cur_rx;
4332 		uint32_t		rxidx;
4333 		struct mbuf		*m = NULL;
4334 		uint16_t		vlan_tag = 0;
4335 		int			have_tag = 0;
4336 
4337 #ifdef DEVICE_POLLING
4338 		if (if_getcapenable(ifp) & IFCAP_POLLING) {
4339 			if (sc->rxcycles <= 0)
4340 				break;
4341 			sc->rxcycles--;
4342 		}
4343 #endif
4344 
4345 		cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons];
4346 
4347 		rxidx = cur_rx->bge_idx;
4348 		BGE_INC(rx_cons, sc->bge_return_ring_cnt);
4349 
4350 		if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING &&
4351 		    cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
4352 			have_tag = 1;
4353 			vlan_tag = cur_rx->bge_vlan_tag;
4354 		}
4355 
4356 		if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
4357 			jumbocnt++;
4358 			m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
4359 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4360 				bge_rxreuse_jumbo(sc, rxidx);
4361 				continue;
4362 			}
4363 			if (bge_newbuf_jumbo(sc, rxidx) != 0) {
4364 				bge_rxreuse_jumbo(sc, rxidx);
4365 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4366 				continue;
4367 			}
4368 			BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
4369 		} else {
4370 			stdcnt++;
4371 			m = sc->bge_cdata.bge_rx_std_chain[rxidx];
4372 			if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
4373 				bge_rxreuse_std(sc, rxidx);
4374 				continue;
4375 			}
4376 			if (bge_newbuf_std(sc, rxidx) != 0) {
4377 				bge_rxreuse_std(sc, rxidx);
4378 				if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
4379 				continue;
4380 			}
4381 			BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
4382 		}
4383 
4384 		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
4385 #ifndef __NO_STRICT_ALIGNMENT
4386 		/*
4387 		 * For architectures with strict alignment we must make sure
4388 		 * the payload is aligned.
4389 		 */
4390 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) {
4391 			bcopy(m->m_data, m->m_data + ETHER_ALIGN,
4392 			    cur_rx->bge_len);
4393 			m->m_data += ETHER_ALIGN;
4394 		}
4395 #endif
4396 		m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
4397 		m->m_pkthdr.rcvif = ifp;
4398 
4399 		if (if_getcapenable(ifp) & IFCAP_RXCSUM)
4400 			bge_rxcsum(sc, cur_rx, m);
4401 
4402 		/*
4403 		 * If we received a packet with a vlan tag,
4404 		 * attach that information to the packet.
4405 		 */
4406 		if (have_tag) {
4407 			m->m_pkthdr.ether_vtag = vlan_tag;
4408 			m->m_flags |= M_VLANTAG;
4409 		}
4410 
4411 		if (holdlck != 0) {
4412 			BGE_UNLOCK(sc);
4413 			if_input(ifp, m);
4414 			BGE_LOCK(sc);
4415 		} else
4416 			if_input(ifp, m);
4417 		rx_npkts++;
4418 
4419 		if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING))
4420 			return (rx_npkts);
4421 	}
4422 
4423 	bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
4424 	    sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD);
4425 	if (stdcnt > 0)
4426 		bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag,
4427 		    sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE);
4428 
4429 	if (jumbocnt > 0)
4430 		bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag,
4431 		    sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE);
4432 
4433 	sc->bge_rx_saved_considx = rx_cons;
4434 	bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
4435 	if (stdcnt)
4436 		bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std +
4437 		    BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT);
4438 	if (jumbocnt)
4439 		bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo +
4440 		    BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT);
4441 #ifdef notyet
4442 	/*
4443 	 * This register wraps very quickly under heavy packet drops.
4444 	 * If you need correct statistics, you can enable this check.
4445 	 */
4446 	if (BGE_IS_5705_PLUS(sc))
4447 		if_incierrors(ifp, CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS));
4448 #endif
4449 	return (rx_npkts);
4450 }
4451 
4452 static void
4453 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m)
4454 {
4455 
4456 	if (BGE_IS_5717_PLUS(sc)) {
4457 		if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) {
4458 			if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4459 				m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4460 				if ((cur_rx->bge_error_flag &
4461 				    BGE_RXERRFLAG_IP_CSUM_NOK) == 0)
4462 					m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4463 			}
4464 			if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
4465 				m->m_pkthdr.csum_data =
4466 				    cur_rx->bge_tcp_udp_csum;
4467 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4468 				    CSUM_PSEUDO_HDR;
4469 			}
4470 		}
4471 	} else {
4472 		if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) {
4473 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
4474 			if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0)
4475 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
4476 		}
4477 		if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM &&
4478 		    m->m_pkthdr.len >= ETHER_MIN_NOPAD) {
4479 			m->m_pkthdr.csum_data =
4480 			    cur_rx->bge_tcp_udp_csum;
4481 			m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
4482 			    CSUM_PSEUDO_HDR;
4483 		}
4484 	}
4485 }
4486 
4487 static void
4488 bge_txeof(struct bge_softc *sc, uint16_t tx_cons)
4489 {
4490 	struct bge_tx_bd *cur_tx;
4491 	if_t ifp;
4492 
4493 	BGE_LOCK_ASSERT(sc);
4494 
4495 	/* Nothing to do. */
4496 	if (sc->bge_tx_saved_considx == tx_cons)
4497 		return;
4498 
4499 	ifp = sc->bge_ifp;
4500 
4501 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
4502 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE);
4503 	/*
4504 	 * Go through our tx ring and free mbufs for those
4505 	 * frames that have been sent.
4506 	 */
4507 	while (sc->bge_tx_saved_considx != tx_cons) {
4508 		uint32_t		idx;
4509 
4510 		idx = sc->bge_tx_saved_considx;
4511 		cur_tx = &sc->bge_ldata.bge_tx_ring[idx];
4512 		if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
4513 			if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
4514 		if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
4515 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag,
4516 			    sc->bge_cdata.bge_tx_dmamap[idx],
4517 			    BUS_DMASYNC_POSTWRITE);
4518 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag,
4519 			    sc->bge_cdata.bge_tx_dmamap[idx]);
4520 			m_freem(sc->bge_cdata.bge_tx_chain[idx]);
4521 			sc->bge_cdata.bge_tx_chain[idx] = NULL;
4522 		}
4523 		sc->bge_txcnt--;
4524 		BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
4525 	}
4526 
4527 	if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
4528 	if (sc->bge_txcnt == 0)
4529 		sc->bge_timer = 0;
4530 }
4531 
4532 #ifdef DEVICE_POLLING
4533 static int
4534 bge_poll(if_t ifp, enum poll_cmd cmd, int count)
4535 {
4536 	struct bge_softc *sc = if_getsoftc(ifp);
4537 	uint16_t rx_prod, tx_cons;
4538 	uint32_t statusword;
4539 	int rx_npkts = 0;
4540 
4541 	BGE_LOCK(sc);
4542 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4543 		BGE_UNLOCK(sc);
4544 		return (rx_npkts);
4545 	}
4546 
4547 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4548 	    sc->bge_cdata.bge_status_map,
4549 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4550 	/* Fetch updates from the status block. */
4551 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4552 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4553 
4554 	statusword = sc->bge_ldata.bge_status_block->bge_status;
4555 	/* Clear the status so the next pass only sees the changes. */
4556 	sc->bge_ldata.bge_status_block->bge_status = 0;
4557 
4558 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4559 	    sc->bge_cdata.bge_status_map,
4560 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4561 
4562 	/* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */
4563 	if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED)
4564 		sc->bge_link_evt++;
4565 
4566 	if (cmd == POLL_AND_CHECK_STATUS)
4567 		if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4568 		    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4569 		    sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI))
4570 			bge_link_upd(sc);
4571 
4572 	sc->rxcycles = count;
4573 	rx_npkts = bge_rxeof(sc, rx_prod, 1);
4574 	if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) {
4575 		BGE_UNLOCK(sc);
4576 		return (rx_npkts);
4577 	}
4578 	bge_txeof(sc, tx_cons);
4579 	if (!if_sendq_empty(ifp))
4580 		bge_start_locked(ifp);
4581 
4582 	BGE_UNLOCK(sc);
4583 	return (rx_npkts);
4584 }
4585 #endif /* DEVICE_POLLING */
4586 
4587 static int
4588 bge_msi_intr(void *arg)
4589 {
4590 	struct bge_softc *sc;
4591 
4592 	sc = (struct bge_softc *)arg;
4593 	/*
4594 	 * This interrupt is not shared and controller already
4595 	 * disabled further interrupt.
4596 	 */
4597 	taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task);
4598 	return (FILTER_HANDLED);
4599 }
4600 
4601 static void
4602 bge_intr_task(void *arg, int pending)
4603 {
4604 	struct bge_softc *sc;
4605 	if_t ifp;
4606 	uint32_t status, status_tag;
4607 	uint16_t rx_prod, tx_cons;
4608 
4609 	sc = (struct bge_softc *)arg;
4610 	ifp = sc->bge_ifp;
4611 
4612 	BGE_LOCK(sc);
4613 	if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) {
4614 		BGE_UNLOCK(sc);
4615 		return;
4616 	}
4617 
4618 	/* Get updated status block. */
4619 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4620 	    sc->bge_cdata.bge_status_map,
4621 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4622 
4623 	/* Save producer/consumer indices. */
4624 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4625 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4626 	status = sc->bge_ldata.bge_status_block->bge_status;
4627 	status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24;
4628 	/* Dirty the status flag. */
4629 	sc->bge_ldata.bge_status_block->bge_status = 0;
4630 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4631 	    sc->bge_cdata.bge_status_map,
4632 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4633 	if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0)
4634 		status_tag = 0;
4635 
4636 	if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0)
4637 		bge_link_upd(sc);
4638 
4639 	/* Let controller work. */
4640 	bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag);
4641 
4642 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4643 	    sc->bge_rx_saved_considx != rx_prod) {
4644 		/* Check RX return ring producer/consumer. */
4645 		BGE_UNLOCK(sc);
4646 		bge_rxeof(sc, rx_prod, 0);
4647 		BGE_LOCK(sc);
4648 	}
4649 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4650 		/* Check TX ring producer/consumer. */
4651 		bge_txeof(sc, tx_cons);
4652 		if (!if_sendq_empty(ifp))
4653 			bge_start_locked(ifp);
4654 	}
4655 	BGE_UNLOCK(sc);
4656 }
4657 
4658 static void
4659 bge_intr(void *xsc)
4660 {
4661 	struct bge_softc *sc;
4662 	if_t ifp;
4663 	uint32_t statusword;
4664 	uint16_t rx_prod, tx_cons;
4665 
4666 	sc = xsc;
4667 
4668 	BGE_LOCK(sc);
4669 
4670 	ifp = sc->bge_ifp;
4671 
4672 #ifdef DEVICE_POLLING
4673 	if (if_getcapenable(ifp) & IFCAP_POLLING) {
4674 		BGE_UNLOCK(sc);
4675 		return;
4676 	}
4677 #endif
4678 
4679 	/*
4680 	 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO.  Don't
4681 	 * disable interrupts by writing nonzero like we used to, since with
4682 	 * our current organization this just gives complications and
4683 	 * pessimizations for re-enabling interrupts.  We used to have races
4684 	 * instead of the necessary complications.  Disabling interrupts
4685 	 * would just reduce the chance of a status update while we are
4686 	 * running (by switching to the interrupt-mode coalescence
4687 	 * parameters), but this chance is already very low so it is more
4688 	 * efficient to get another interrupt than prevent it.
4689 	 *
4690 	 * We do the ack first to ensure another interrupt if there is a
4691 	 * status update after the ack.  We don't check for the status
4692 	 * changing later because it is more efficient to get another
4693 	 * interrupt than prevent it, not quite as above (not checking is
4694 	 * a smaller optimization than not toggling the interrupt enable,
4695 	 * since checking doesn't involve PCI accesses and toggling require
4696 	 * the status check).  So toggling would probably be a pessimization
4697 	 * even with MSI.  It would only be needed for using a task queue.
4698 	 */
4699 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
4700 
4701 	/*
4702 	 * Do the mandatory PCI flush as well as get the link status.
4703 	 */
4704 	statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED;
4705 
4706 	/* Make sure the descriptor ring indexes are coherent. */
4707 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4708 	    sc->bge_cdata.bge_status_map,
4709 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
4710 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
4711 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
4712 	sc->bge_ldata.bge_status_block->bge_status = 0;
4713 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
4714 	    sc->bge_cdata.bge_status_map,
4715 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4716 
4717 	if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
4718 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) ||
4719 	    statusword || sc->bge_link_evt)
4720 		bge_link_upd(sc);
4721 
4722 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4723 		/* Check RX return ring producer/consumer. */
4724 		bge_rxeof(sc, rx_prod, 1);
4725 	}
4726 
4727 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
4728 		/* Check TX ring producer/consumer. */
4729 		bge_txeof(sc, tx_cons);
4730 	}
4731 
4732 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING &&
4733 	    !if_sendq_empty(ifp))
4734 		bge_start_locked(ifp);
4735 
4736 	BGE_UNLOCK(sc);
4737 }
4738 
4739 static void
4740 bge_asf_driver_up(struct bge_softc *sc)
4741 {
4742 	if (sc->bge_asf_mode & ASF_STACKUP) {
4743 		/* Send ASF heartbeat aprox. every 2s */
4744 		if (sc->bge_asf_count)
4745 			sc->bge_asf_count --;
4746 		else {
4747 			sc->bge_asf_count = 2;
4748 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB,
4749 			    BGE_FW_CMD_DRV_ALIVE);
4750 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4);
4751 			bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB,
4752 			    BGE_FW_HB_TIMEOUT_SEC);
4753 			CSR_WRITE_4(sc, BGE_RX_CPU_EVENT,
4754 			    CSR_READ_4(sc, BGE_RX_CPU_EVENT) |
4755 			    BGE_RX_CPU_DRV_EVENT);
4756 		}
4757 	}
4758 }
4759 
4760 static void
4761 bge_tick(void *xsc)
4762 {
4763 	struct bge_softc *sc = xsc;
4764 	struct mii_data *mii = NULL;
4765 
4766 	BGE_LOCK_ASSERT(sc);
4767 
4768 	/* Synchronize with possible callout reset/stop. */
4769 	if (callout_pending(&sc->bge_stat_ch) ||
4770 	    !callout_active(&sc->bge_stat_ch))
4771 		return;
4772 
4773 	if (BGE_IS_5705_PLUS(sc))
4774 		bge_stats_update_regs(sc);
4775 	else
4776 		bge_stats_update(sc);
4777 
4778 	/* XXX Add APE heartbeat check here? */
4779 
4780 	if ((sc->bge_flags & BGE_FLAG_TBI) == 0) {
4781 		mii = device_get_softc(sc->bge_miibus);
4782 		/*
4783 		 * Do not touch PHY if we have link up. This could break
4784 		 * IPMI/ASF mode or produce extra input errors
4785 		 * (extra errors was reported for bcm5701 & bcm5704).
4786 		 */
4787 		if (!sc->bge_link)
4788 			mii_tick(mii);
4789 	} else {
4790 		/*
4791 		 * Since in TBI mode auto-polling can't be used we should poll
4792 		 * link status manually. Here we register pending link event
4793 		 * and trigger interrupt.
4794 		 */
4795 #ifdef DEVICE_POLLING
4796 		/* In polling mode we poll link state in bge_poll(). */
4797 		if (!(if_getcapenable(sc->bge_ifp) & IFCAP_POLLING))
4798 #endif
4799 		{
4800 		sc->bge_link_evt++;
4801 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
4802 		    sc->bge_flags & BGE_FLAG_5788)
4803 			BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
4804 		else
4805 			BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
4806 		}
4807 	}
4808 
4809 	bge_asf_driver_up(sc);
4810 	bge_watchdog(sc);
4811 
4812 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
4813 }
4814 
4815 static void
4816 bge_stats_update_regs(struct bge_softc *sc)
4817 {
4818 	if_t ifp;
4819 	struct bge_mac_stats *stats;
4820 	uint32_t val;
4821 
4822 	ifp = sc->bge_ifp;
4823 	stats = &sc->bge_mac_stats;
4824 
4825 	stats->ifHCOutOctets +=
4826 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4827 	stats->etherStatsCollisions +=
4828 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4829 	stats->outXonSent +=
4830 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4831 	stats->outXoffSent +=
4832 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4833 	stats->dot3StatsInternalMacTransmitErrors +=
4834 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4835 	stats->dot3StatsSingleCollisionFrames +=
4836 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4837 	stats->dot3StatsMultipleCollisionFrames +=
4838 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4839 	stats->dot3StatsDeferredTransmissions +=
4840 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4841 	stats->dot3StatsExcessiveCollisions +=
4842 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4843 	stats->dot3StatsLateCollisions +=
4844 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4845 	stats->ifHCOutUcastPkts +=
4846 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4847 	stats->ifHCOutMulticastPkts +=
4848 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4849 	stats->ifHCOutBroadcastPkts +=
4850 	    CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4851 
4852 	stats->ifHCInOctets +=
4853 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4854 	stats->etherStatsFragments +=
4855 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4856 	stats->ifHCInUcastPkts +=
4857 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4858 	stats->ifHCInMulticastPkts +=
4859 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4860 	stats->ifHCInBroadcastPkts +=
4861 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4862 	stats->dot3StatsFCSErrors +=
4863 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4864 	stats->dot3StatsAlignmentErrors +=
4865 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4866 	stats->xonPauseFramesReceived +=
4867 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4868 	stats->xoffPauseFramesReceived +=
4869 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4870 	stats->macControlFramesReceived +=
4871 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4872 	stats->xoffStateEntered +=
4873 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4874 	stats->dot3StatsFramesTooLong +=
4875 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4876 	stats->etherStatsJabbers +=
4877 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4878 	stats->etherStatsUndersizePkts +=
4879 	    CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4880 
4881 	stats->FramesDroppedDueToFilters +=
4882 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4883 	stats->DmaWriteQueueFull +=
4884 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4885 	stats->DmaWriteHighPriQueueFull +=
4886 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4887 	stats->NoMoreRxBDs +=
4888 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4889 	/*
4890 	 * XXX
4891 	 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS
4892 	 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0
4893 	 * includes number of unwanted multicast frames.  This comes
4894 	 * from silicon bug and known workaround to get rough(not
4895 	 * exact) counter is to enable interrupt on MBUF low water
4896 	 * attention.  This can be accomplished by setting
4897 	 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE,
4898 	 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and
4899 	 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL.
4900 	 * However that change would generate more interrupts and
4901 	 * there are still possibilities of losing multiple frames
4902 	 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling.
4903 	 * Given that the workaround still would not get correct
4904 	 * counter I don't think it's worth to implement it.  So
4905 	 * ignore reading the counter on controllers that have the
4906 	 * silicon bug.
4907 	 */
4908 	if (sc->bge_asicrev != BGE_ASICREV_BCM5717 &&
4909 	    sc->bge_chipid != BGE_CHIPID_BCM5719_A0 &&
4910 	    sc->bge_chipid != BGE_CHIPID_BCM5720_A0)
4911 		stats->InputDiscards +=
4912 		    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4913 	stats->InputErrors +=
4914 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4915 	stats->RecvThresholdHit +=
4916 	    CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4917 
4918 	if (sc->bge_flags & BGE_FLAG_RDMA_BUG) {
4919 		/*
4920 		 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS
4921 		 * frames, it's safe to disable workaround for DMA engine's
4922 		 * miscalculation of TXMBUF space.
4923 		 */
4924 		if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts +
4925 		    stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) {
4926 			val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL);
4927 			if (sc->bge_asicrev == BGE_ASICREV_BCM5719)
4928 				val &= ~BGE_RDMA_TX_LENGTH_WA_5719;
4929 			else
4930 				val &= ~BGE_RDMA_TX_LENGTH_WA_5720;
4931 			CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val);
4932 			sc->bge_flags &= ~BGE_FLAG_RDMA_BUG;
4933 		}
4934 	}
4935 }
4936 
4937 static void
4938 bge_stats_clear_regs(struct bge_softc *sc)
4939 {
4940 
4941 	CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS);
4942 	CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS);
4943 	CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT);
4944 	CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT);
4945 	CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS);
4946 	CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL);
4947 	CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL);
4948 	CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED);
4949 	CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL);
4950 	CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL);
4951 	CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST);
4952 	CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST);
4953 	CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST);
4954 
4955 	CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS);
4956 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS);
4957 	CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST);
4958 	CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST);
4959 	CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST);
4960 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS);
4961 	CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS);
4962 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD);
4963 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD);
4964 	CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD);
4965 	CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED);
4966 	CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG);
4967 	CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS);
4968 	CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE);
4969 
4970 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP);
4971 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL);
4972 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL);
4973 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS);
4974 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS);
4975 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS);
4976 	CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT);
4977 }
4978 
4979 static void
4980 bge_stats_update(struct bge_softc *sc)
4981 {
4982 	if_t ifp;
4983 	bus_size_t stats;
4984 	uint32_t cnt;	/* current register value */
4985 
4986 	ifp = sc->bge_ifp;
4987 
4988 	stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
4989 
4990 #define	READ_STAT(sc, stats, stat) \
4991 	CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
4992 
4993 	cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo);
4994 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, cnt - sc->bge_tx_collisions);
4995 	sc->bge_tx_collisions = cnt;
4996 
4997 	cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo);
4998 	if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_nobds);
4999 	sc->bge_rx_nobds = cnt;
5000 	cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo);
5001 	if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_inerrs);
5002 	sc->bge_rx_inerrs = cnt;
5003 	cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo);
5004 	if_inc_counter(ifp, IFCOUNTER_IERRORS, cnt - sc->bge_rx_discards);
5005 	sc->bge_rx_discards = cnt;
5006 
5007 	cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo);
5008 	if_inc_counter(ifp, IFCOUNTER_OERRORS, cnt - sc->bge_tx_discards);
5009 	sc->bge_tx_discards = cnt;
5010 
5011 #undef	READ_STAT
5012 }
5013 
5014 /*
5015  * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason.
5016  * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD,
5017  * but when such padded frames employ the bge IP/TCP checksum offload,
5018  * the hardware checksum assist gives incorrect results (possibly
5019  * from incorporating its own padding into the UDP/TCP checksum; who knows).
5020  * If we pad such runts with zeros, the onboard checksum comes out correct.
5021  */
5022 static __inline int
5023 bge_cksum_pad(struct mbuf *m)
5024 {
5025 	int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len;
5026 	struct mbuf *last;
5027 
5028 	/* If there's only the packet-header and we can pad there, use it. */
5029 	if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) &&
5030 	    M_TRAILINGSPACE(m) >= padlen) {
5031 		last = m;
5032 	} else {
5033 		/*
5034 		 * Walk packet chain to find last mbuf. We will either
5035 		 * pad there, or append a new mbuf and pad it.
5036 		 */
5037 		for (last = m; last->m_next != NULL; last = last->m_next);
5038 		if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) {
5039 			/* Allocate new empty mbuf, pad it. Compact later. */
5040 			struct mbuf *n;
5041 
5042 			MGET(n, M_NOWAIT, MT_DATA);
5043 			if (n == NULL)
5044 				return (ENOBUFS);
5045 			n->m_len = 0;
5046 			last->m_next = n;
5047 			last = n;
5048 		}
5049 	}
5050 
5051 	/* Now zero the pad area, to avoid the bge cksum-assist bug. */
5052 	memset(mtod(last, caddr_t) + last->m_len, 0, padlen);
5053 	last->m_len += padlen;
5054 	m->m_pkthdr.len += padlen;
5055 
5056 	return (0);
5057 }
5058 
5059 static struct mbuf *
5060 bge_check_short_dma(struct mbuf *m)
5061 {
5062 	struct mbuf *n;
5063 	int found;
5064 
5065 	/*
5066 	 * If device receive two back-to-back send BDs with less than
5067 	 * or equal to 8 total bytes then the device may hang.  The two
5068 	 * back-to-back send BDs must in the same frame for this failure
5069 	 * to occur.  Scan mbuf chains and see whether two back-to-back
5070 	 * send BDs are there. If this is the case, allocate new mbuf
5071 	 * and copy the frame to workaround the silicon bug.
5072 	 */
5073 	for (n = m, found = 0; n != NULL; n = n->m_next) {
5074 		if (n->m_len < 8) {
5075 			found++;
5076 			if (found > 1)
5077 				break;
5078 			continue;
5079 		}
5080 		found = 0;
5081 	}
5082 
5083 	if (found > 1) {
5084 		n = m_defrag(m, M_NOWAIT);
5085 		if (n == NULL)
5086 			m_freem(m);
5087 	} else
5088 		n = m;
5089 	return (n);
5090 }
5091 
5092 static struct mbuf *
5093 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss,
5094     uint16_t *flags)
5095 {
5096 	struct ip *ip;
5097 	struct tcphdr *tcp;
5098 	struct mbuf *n;
5099 	uint16_t hlen;
5100 	uint32_t poff;
5101 
5102 	if (M_WRITABLE(m) == 0) {
5103 		/* Get a writable copy. */
5104 		n = m_dup(m, M_NOWAIT);
5105 		m_freem(m);
5106 		if (n == NULL)
5107 			return (NULL);
5108 		m = n;
5109 	}
5110 	m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip));
5111 	if (m == NULL)
5112 		return (NULL);
5113 	ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5114 	poff = sizeof(struct ether_header) + (ip->ip_hl << 2);
5115 	m = m_pullup(m, poff + sizeof(struct tcphdr));
5116 	if (m == NULL)
5117 		return (NULL);
5118 	tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5119 	m = m_pullup(m, poff + (tcp->th_off << 2));
5120 	if (m == NULL)
5121 		return (NULL);
5122 	/*
5123 	 * It seems controller doesn't modify IP length and TCP pseudo
5124 	 * checksum. These checksum computed by upper stack should be 0.
5125 	 */
5126 	*mss = m->m_pkthdr.tso_segsz;
5127 	ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header));
5128 	ip->ip_sum = 0;
5129 	ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2));
5130 	/* Clear pseudo checksum computed by TCP stack. */
5131 	tcp = (struct tcphdr *)(mtod(m, char *) + poff);
5132 	tcp->th_sum = 0;
5133 	/*
5134 	 * Broadcom controllers uses different descriptor format for
5135 	 * TSO depending on ASIC revision. Due to TSO-capable firmware
5136 	 * license issue and lower performance of firmware based TSO
5137 	 * we only support hardware based TSO.
5138 	 */
5139 	/* Calculate header length, incl. TCP/IP options, in 32 bit units. */
5140 	hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2;
5141 	if (sc->bge_flags & BGE_FLAG_TSO3) {
5142 		/*
5143 		 * For BCM5717 and newer controllers, hardware based TSO
5144 		 * uses the 14 lower bits of the bge_mss field to store the
5145 		 * MSS and the upper 2 bits to store the lowest 2 bits of
5146 		 * the IP/TCP header length.  The upper 6 bits of the header
5147 		 * length are stored in the bge_flags[14:10,4] field.  Jumbo
5148 		 * frames are supported.
5149 		 */
5150 		*mss |= ((hlen & 0x3) << 14);
5151 		*flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2);
5152 	} else {
5153 		/*
5154 		 * For BCM5755 and newer controllers, hardware based TSO uses
5155 		 * the lower 11	bits to store the MSS and the upper 5 bits to
5156 		 * store the IP/TCP header length. Jumbo frames are not
5157 		 * supported.
5158 		 */
5159 		*mss |= (hlen << 11);
5160 	}
5161 	return (m);
5162 }
5163 
5164 /*
5165  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
5166  * pointers to descriptors.
5167  */
5168 static int
5169 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx)
5170 {
5171 	bus_dma_segment_t	segs[BGE_NSEG_NEW];
5172 	bus_dmamap_t		map;
5173 	struct bge_tx_bd	*d;
5174 	struct mbuf		*m = *m_head;
5175 	uint32_t		idx = *txidx;
5176 	uint16_t		csum_flags, mss, vlan_tag;
5177 	int			nsegs, i, error;
5178 
5179 	csum_flags = 0;
5180 	mss = 0;
5181 	vlan_tag = 0;
5182 	if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 &&
5183 	    m->m_next != NULL) {
5184 		*m_head = bge_check_short_dma(m);
5185 		if (*m_head == NULL)
5186 			return (ENOBUFS);
5187 		m = *m_head;
5188 	}
5189 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5190 		*m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags);
5191 		if (*m_head == NULL)
5192 			return (ENOBUFS);
5193 		csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA |
5194 		    BGE_TXBDFLAG_CPU_POST_DMA;
5195 	} else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) {
5196 		if (m->m_pkthdr.csum_flags & CSUM_IP)
5197 			csum_flags |= BGE_TXBDFLAG_IP_CSUM;
5198 		if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) {
5199 			csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
5200 			if (m->m_pkthdr.len < ETHER_MIN_NOPAD &&
5201 			    (error = bge_cksum_pad(m)) != 0) {
5202 				m_freem(m);
5203 				*m_head = NULL;
5204 				return (error);
5205 			}
5206 		}
5207 	}
5208 
5209 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) {
5210 		if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME &&
5211 		    m->m_pkthdr.len > ETHER_MAX_LEN)
5212 			csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME;
5213 		if (sc->bge_forced_collapse > 0 &&
5214 		    (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) {
5215 			/*
5216 			 * Forcedly collapse mbuf chains to overcome hardware
5217 			 * limitation which only support a single outstanding
5218 			 * DMA read operation.
5219 			 */
5220 			if (sc->bge_forced_collapse == 1)
5221 				m = m_defrag(m, M_NOWAIT);
5222 			else
5223 				m = m_collapse(m, M_NOWAIT,
5224 				    sc->bge_forced_collapse);
5225 			if (m == NULL)
5226 				m = *m_head;
5227 			*m_head = m;
5228 		}
5229 	}
5230 
5231 	map = sc->bge_cdata.bge_tx_dmamap[idx];
5232 	error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs,
5233 	    &nsegs, BUS_DMA_NOWAIT);
5234 	if (error == EFBIG) {
5235 		m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW);
5236 		if (m == NULL) {
5237 			m_freem(*m_head);
5238 			*m_head = NULL;
5239 			return (ENOBUFS);
5240 		}
5241 		*m_head = m;
5242 		error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map,
5243 		    m, segs, &nsegs, BUS_DMA_NOWAIT);
5244 		if (error) {
5245 			m_freem(m);
5246 			*m_head = NULL;
5247 			return (error);
5248 		}
5249 	} else if (error != 0)
5250 		return (error);
5251 
5252 	/* Check if we have enough free send BDs. */
5253 	if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) {
5254 		bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5255 		return (ENOBUFS);
5256 	}
5257 
5258 	bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE);
5259 
5260 	if (m->m_flags & M_VLANTAG) {
5261 		csum_flags |= BGE_TXBDFLAG_VLAN_TAG;
5262 		vlan_tag = m->m_pkthdr.ether_vtag;
5263 	}
5264 
5265 	if (sc->bge_asicrev == BGE_ASICREV_BCM5762 &&
5266 	    (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
5267 		/*
5268 		 * 5725 family of devices corrupts TSO packets when TSO DMA
5269 		 * buffers cross into regions which are within MSS bytes of
5270 		 * a 4GB boundary.  If we encounter the condition, drop the
5271 		 * packet.
5272 		 */
5273 		for (i = 0; ; i++) {
5274 			d = &sc->bge_ldata.bge_tx_ring[idx];
5275 			d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5276 			d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5277 			d->bge_len = segs[i].ds_len;
5278 			if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss <
5279 			    d->bge_addr.bge_addr_lo)
5280 				break;
5281 			d->bge_flags = csum_flags;
5282 			d->bge_vlan_tag = vlan_tag;
5283 			d->bge_mss = mss;
5284 			if (i == nsegs - 1)
5285 				break;
5286 			BGE_INC(idx, BGE_TX_RING_CNT);
5287 		}
5288 		if (i != nsegs - 1) {
5289 			bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map,
5290 			    BUS_DMASYNC_POSTWRITE);
5291 			bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map);
5292 			m_freem(*m_head);
5293 			*m_head = NULL;
5294 			return (EIO);
5295 		}
5296 	} else {
5297 		for (i = 0; ; i++) {
5298 			d = &sc->bge_ldata.bge_tx_ring[idx];
5299 			d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
5300 			d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
5301 			d->bge_len = segs[i].ds_len;
5302 			d->bge_flags = csum_flags;
5303 			d->bge_vlan_tag = vlan_tag;
5304 			d->bge_mss = mss;
5305 			if (i == nsegs - 1)
5306 				break;
5307 			BGE_INC(idx, BGE_TX_RING_CNT);
5308 		}
5309 	}
5310 
5311 	/* Mark the last segment as end of packet... */
5312 	d->bge_flags |= BGE_TXBDFLAG_END;
5313 
5314 	/*
5315 	 * Insure that the map for this transmission
5316 	 * is placed at the array index of the last descriptor
5317 	 * in this chain.
5318 	 */
5319 	sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx];
5320 	sc->bge_cdata.bge_tx_dmamap[idx] = map;
5321 	sc->bge_cdata.bge_tx_chain[idx] = m;
5322 	sc->bge_txcnt += nsegs;
5323 
5324 	BGE_INC(idx, BGE_TX_RING_CNT);
5325 	*txidx = idx;
5326 
5327 	return (0);
5328 }
5329 
5330 /*
5331  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5332  * to the mbuf data regions directly in the transmit descriptors.
5333  */
5334 static void
5335 bge_start_locked(if_t ifp)
5336 {
5337 	struct bge_softc *sc;
5338 	struct mbuf *m_head;
5339 	uint32_t prodidx;
5340 	int count;
5341 
5342 	sc = if_getsoftc(ifp);
5343 	BGE_LOCK_ASSERT(sc);
5344 
5345 	if (!sc->bge_link ||
5346 	    (if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
5347 	    IFF_DRV_RUNNING)
5348 		return;
5349 
5350 	prodidx = sc->bge_tx_prodidx;
5351 
5352 	for (count = 0; !if_sendq_empty(ifp);) {
5353 		if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) {
5354 			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5355 			break;
5356 		}
5357 		m_head = if_dequeue(ifp);
5358 		if (m_head == NULL)
5359 			break;
5360 
5361 		/*
5362 		 * Pack the data into the transmit ring. If we
5363 		 * don't have room, set the OACTIVE flag and wait
5364 		 * for the NIC to drain the ring.
5365 		 */
5366 		if (bge_encap(sc, &m_head, &prodidx)) {
5367 			if (m_head == NULL)
5368 				break;
5369 			if_sendq_prepend(ifp, m_head);
5370 			if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0);
5371 			break;
5372 		}
5373 		++count;
5374 
5375 		/*
5376 		 * If there's a BPF listener, bounce a copy of this frame
5377 		 * to him.
5378 		 */
5379 		if_bpfmtap(ifp, m_head);
5380 	}
5381 
5382 	if (count > 0)
5383 		bge_start_tx(sc, prodidx);
5384 }
5385 
5386 static void
5387 bge_start_tx(struct bge_softc *sc, uint32_t prodidx)
5388 {
5389 
5390 	bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag,
5391 	    sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE);
5392 	/* Transmit. */
5393 	bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5394 	/* 5700 b2 errata */
5395 	if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
5396 		bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
5397 
5398 	sc->bge_tx_prodidx = prodidx;
5399 
5400 	/* Set a timeout in case the chip goes out to lunch. */
5401 	sc->bge_timer = BGE_TX_TIMEOUT;
5402 }
5403 
5404 /*
5405  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
5406  * to the mbuf data regions directly in the transmit descriptors.
5407  */
5408 static void
5409 bge_start(if_t ifp)
5410 {
5411 	struct bge_softc *sc;
5412 
5413 	sc = if_getsoftc(ifp);
5414 	BGE_LOCK(sc);
5415 	bge_start_locked(ifp);
5416 	BGE_UNLOCK(sc);
5417 }
5418 
5419 static void
5420 bge_init_locked(struct bge_softc *sc)
5421 {
5422 	if_t ifp;
5423 	uint16_t *m;
5424 	uint32_t mode;
5425 
5426 	BGE_LOCK_ASSERT(sc);
5427 
5428 	ifp = sc->bge_ifp;
5429 
5430 	if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
5431 		return;
5432 
5433 	/* Cancel pending I/O and flush buffers. */
5434 	bge_stop(sc);
5435 
5436 	bge_stop_fw(sc);
5437 	bge_sig_pre_reset(sc, BGE_RESET_START);
5438 	bge_reset(sc);
5439 	bge_sig_legacy(sc, BGE_RESET_START);
5440 	bge_sig_post_reset(sc, BGE_RESET_START);
5441 
5442 	bge_chipinit(sc);
5443 
5444 	/*
5445 	 * Init the various state machines, ring
5446 	 * control blocks and firmware.
5447 	 */
5448 	if (bge_blockinit(sc)) {
5449 		device_printf(sc->bge_dev, "initialization failure\n");
5450 		return;
5451 	}
5452 
5453 	ifp = sc->bge_ifp;
5454 
5455 	/* Specify MTU. */
5456 	CSR_WRITE_4(sc, BGE_RX_MTU, if_getmtu(ifp) +
5457 	    ETHER_HDR_LEN + ETHER_CRC_LEN +
5458 	    (if_getcapenable(ifp) & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0));
5459 
5460 	/* Load our MAC address. */
5461 	m = (uint16_t *)IF_LLADDR(sc->bge_ifp);
5462 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
5463 	CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
5464 
5465 	/* Program promiscuous mode. */
5466 	bge_setpromisc(sc);
5467 
5468 	/* Program multicast filter. */
5469 	bge_setmulti(sc);
5470 
5471 	/* Program VLAN tag stripping. */
5472 	bge_setvlan(sc);
5473 
5474 	/* Override UDP checksum offloading. */
5475 	if (sc->bge_forced_udpcsum == 0)
5476 		sc->bge_csum_features &= ~CSUM_UDP;
5477 	else
5478 		sc->bge_csum_features |= CSUM_UDP;
5479 	if (if_getcapabilities(ifp) & IFCAP_TXCSUM &&
5480 	    if_getcapenable(ifp) & IFCAP_TXCSUM) {
5481 		if_sethwassistbits(ifp, 0, (BGE_CSUM_FEATURES | CSUM_UDP));
5482 		if_sethwassistbits(ifp, sc->bge_csum_features, 0);
5483 	}
5484 
5485 	/* Init RX ring. */
5486 	if (bge_init_rx_ring_std(sc) != 0) {
5487 		device_printf(sc->bge_dev, "no memory for std Rx buffers.\n");
5488 		bge_stop(sc);
5489 		return;
5490 	}
5491 
5492 	/*
5493 	 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
5494 	 * memory to insure that the chip has in fact read the first
5495 	 * entry of the ring.
5496 	 */
5497 	if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
5498 		uint32_t		v, i;
5499 		for (i = 0; i < 10; i++) {
5500 			DELAY(20);
5501 			v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
5502 			if (v == (MCLBYTES - ETHER_ALIGN))
5503 				break;
5504 		}
5505 		if (i == 10)
5506 			device_printf (sc->bge_dev,
5507 			    "5705 A0 chip failed to load RX ring\n");
5508 	}
5509 
5510 	/* Init jumbo RX ring. */
5511 	if (BGE_IS_JUMBO_CAPABLE(sc) &&
5512 	    if_getmtu(ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
5513      	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)) {
5514 		if (bge_init_rx_ring_jumbo(sc) != 0) {
5515 			device_printf(sc->bge_dev,
5516 			    "no memory for jumbo Rx buffers.\n");
5517 			bge_stop(sc);
5518 			return;
5519 		}
5520 	}
5521 
5522 	/* Init our RX return ring index. */
5523 	sc->bge_rx_saved_considx = 0;
5524 
5525 	/* Init our RX/TX stat counters. */
5526 	sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0;
5527 
5528 	/* Init TX ring. */
5529 	bge_init_tx_ring(sc);
5530 
5531 	/* Enable TX MAC state machine lockup fix. */
5532 	mode = CSR_READ_4(sc, BGE_TX_MODE);
5533 	if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906)
5534 		mode |= BGE_TXMODE_MBUF_LOCKUP_FIX;
5535 	if (sc->bge_asicrev == BGE_ASICREV_BCM5720 ||
5536 	    sc->bge_asicrev == BGE_ASICREV_BCM5762) {
5537 		mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5538 		mode |= CSR_READ_4(sc, BGE_TX_MODE) &
5539 		    (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE);
5540 	}
5541 	/* Turn on transmitter. */
5542 	CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE);
5543 	DELAY(100);
5544 
5545 	/* Turn on receiver. */
5546 	mode = CSR_READ_4(sc, BGE_RX_MODE);
5547 	if (BGE_IS_5755_PLUS(sc))
5548 		mode |= BGE_RXMODE_IPV6_ENABLE;
5549 	if (sc->bge_asicrev == BGE_ASICREV_BCM5762)
5550 		mode |= BGE_RXMODE_IPV4_FRAG_FIX;
5551 	CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE);
5552 	DELAY(10);
5553 
5554 	/*
5555 	 * Set the number of good frames to receive after RX MBUF
5556 	 * Low Watermark has been reached. After the RX MAC receives
5557 	 * this number of frames, it will drop subsequent incoming
5558 	 * frames until the MBUF High Watermark is reached.
5559 	 */
5560 	if (BGE_IS_57765_PLUS(sc))
5561 		CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1);
5562 	else
5563 		CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2);
5564 
5565 	/* Clear MAC statistics. */
5566 	if (BGE_IS_5705_PLUS(sc))
5567 		bge_stats_clear_regs(sc);
5568 
5569 	/* Tell firmware we're alive. */
5570 	BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
5571 
5572 #ifdef DEVICE_POLLING
5573 	/* Disable interrupts if we are polling. */
5574 	if (if_getcapenable(ifp) & IFCAP_POLLING) {
5575 		BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5576 		    BGE_PCIMISCCTL_MASK_PCI_INTR);
5577 		bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5578 	} else
5579 #endif
5580 
5581 	/* Enable host interrupts. */
5582 	{
5583 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
5584 	BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5585 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5586 	}
5587 
5588 	if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0);
5589 	if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE);
5590 
5591 	bge_ifmedia_upd_locked(ifp);
5592 
5593 	callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc);
5594 }
5595 
5596 static void
5597 bge_init(void *xsc)
5598 {
5599 	struct bge_softc *sc = xsc;
5600 
5601 	BGE_LOCK(sc);
5602 	bge_init_locked(sc);
5603 	BGE_UNLOCK(sc);
5604 }
5605 
5606 /*
5607  * Set media options.
5608  */
5609 static int
5610 bge_ifmedia_upd(if_t ifp)
5611 {
5612 	struct bge_softc *sc = if_getsoftc(ifp);
5613 	int res;
5614 
5615 	BGE_LOCK(sc);
5616 	res = bge_ifmedia_upd_locked(ifp);
5617 	BGE_UNLOCK(sc);
5618 
5619 	return (res);
5620 }
5621 
5622 static int
5623 bge_ifmedia_upd_locked(if_t ifp)
5624 {
5625 	struct bge_softc *sc = if_getsoftc(ifp);
5626 	struct mii_data *mii;
5627 	struct mii_softc *miisc;
5628 	struct ifmedia *ifm;
5629 
5630 	BGE_LOCK_ASSERT(sc);
5631 
5632 	ifm = &sc->bge_ifmedia;
5633 
5634 	/* If this is a 1000baseX NIC, enable the TBI port. */
5635 	if (sc->bge_flags & BGE_FLAG_TBI) {
5636 		if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
5637 			return (EINVAL);
5638 		switch(IFM_SUBTYPE(ifm->ifm_media)) {
5639 		case IFM_AUTO:
5640 			/*
5641 			 * The BCM5704 ASIC appears to have a special
5642 			 * mechanism for programming the autoneg
5643 			 * advertisement registers in TBI mode.
5644 			 */
5645 			if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
5646 				uint32_t sgdig;
5647 				sgdig = CSR_READ_4(sc, BGE_SGDIG_STS);
5648 				if (sgdig & BGE_SGDIGSTS_DONE) {
5649 					CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
5650 					sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
5651 					sgdig |= BGE_SGDIGCFG_AUTO |
5652 					    BGE_SGDIGCFG_PAUSE_CAP |
5653 					    BGE_SGDIGCFG_ASYM_PAUSE;
5654 					CSR_WRITE_4(sc, BGE_SGDIG_CFG,
5655 					    sgdig | BGE_SGDIGCFG_SEND);
5656 					DELAY(5);
5657 					CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
5658 				}
5659 			}
5660 			break;
5661 		case IFM_1000_SX:
5662 			if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
5663 				BGE_CLRBIT(sc, BGE_MAC_MODE,
5664 				    BGE_MACMODE_HALF_DUPLEX);
5665 			} else {
5666 				BGE_SETBIT(sc, BGE_MAC_MODE,
5667 				    BGE_MACMODE_HALF_DUPLEX);
5668 			}
5669 			DELAY(40);
5670 			break;
5671 		default:
5672 			return (EINVAL);
5673 		}
5674 		return (0);
5675 	}
5676 
5677 	sc->bge_link_evt++;
5678 	mii = device_get_softc(sc->bge_miibus);
5679 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5680 		PHY_RESET(miisc);
5681 	mii_mediachg(mii);
5682 
5683 	/*
5684 	 * Force an interrupt so that we will call bge_link_upd
5685 	 * if needed and clear any pending link state attention.
5686 	 * Without this we are not getting any further interrupts
5687 	 * for link state changes and thus will not UP the link and
5688 	 * not be able to send in bge_start_locked. The only
5689 	 * way to get things working was to receive a packet and
5690 	 * get an RX intr.
5691 	 * bge_tick should help for fiber cards and we might not
5692 	 * need to do this here if BGE_FLAG_TBI is set but as
5693 	 * we poll for fiber anyway it should not harm.
5694 	 */
5695 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 ||
5696 	    sc->bge_flags & BGE_FLAG_5788)
5697 		BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET);
5698 	else
5699 		BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW);
5700 
5701 	return (0);
5702 }
5703 
5704 /*
5705  * Report current media status.
5706  */
5707 static void
5708 bge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr)
5709 {
5710 	struct bge_softc *sc = if_getsoftc(ifp);
5711 	struct mii_data *mii;
5712 
5713 	BGE_LOCK(sc);
5714 
5715 	if ((if_getflags(ifp) & IFF_UP) == 0) {
5716 		BGE_UNLOCK(sc);
5717 		return;
5718 	}
5719 	if (sc->bge_flags & BGE_FLAG_TBI) {
5720 		ifmr->ifm_status = IFM_AVALID;
5721 		ifmr->ifm_active = IFM_ETHER;
5722 		if (CSR_READ_4(sc, BGE_MAC_STS) &
5723 		    BGE_MACSTAT_TBI_PCS_SYNCHED)
5724 			ifmr->ifm_status |= IFM_ACTIVE;
5725 		else {
5726 			ifmr->ifm_active |= IFM_NONE;
5727 			BGE_UNLOCK(sc);
5728 			return;
5729 		}
5730 		ifmr->ifm_active |= IFM_1000_SX;
5731 		if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
5732 			ifmr->ifm_active |= IFM_HDX;
5733 		else
5734 			ifmr->ifm_active |= IFM_FDX;
5735 		BGE_UNLOCK(sc);
5736 		return;
5737 	}
5738 
5739 	mii = device_get_softc(sc->bge_miibus);
5740 	mii_pollstat(mii);
5741 	ifmr->ifm_active = mii->mii_media_active;
5742 	ifmr->ifm_status = mii->mii_media_status;
5743 
5744 	BGE_UNLOCK(sc);
5745 }
5746 
5747 static int
5748 bge_ioctl(if_t ifp, u_long command, caddr_t data)
5749 {
5750 	struct bge_softc *sc = if_getsoftc(ifp);
5751 	struct ifreq *ifr = (struct ifreq *) data;
5752 	struct mii_data *mii;
5753 	int flags, mask, error = 0;
5754 
5755 	switch (command) {
5756 	case SIOCSIFMTU:
5757 		if (BGE_IS_JUMBO_CAPABLE(sc) ||
5758 		    (sc->bge_flags & BGE_FLAG_JUMBO_STD)) {
5759 			if (ifr->ifr_mtu < ETHERMIN ||
5760 			    ifr->ifr_mtu > BGE_JUMBO_MTU) {
5761 				error = EINVAL;
5762 				break;
5763 			}
5764 		} else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) {
5765 			error = EINVAL;
5766 			break;
5767 		}
5768 		BGE_LOCK(sc);
5769 		if (if_getmtu(ifp) != ifr->ifr_mtu) {
5770 			if_setmtu(ifp, ifr->ifr_mtu);
5771 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5772 				if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5773 				bge_init_locked(sc);
5774 			}
5775 		}
5776 		BGE_UNLOCK(sc);
5777 		break;
5778 	case SIOCSIFFLAGS:
5779 		BGE_LOCK(sc);
5780 		if (if_getflags(ifp) & IFF_UP) {
5781 			/*
5782 			 * If only the state of the PROMISC flag changed,
5783 			 * then just use the 'set promisc mode' command
5784 			 * instead of reinitializing the entire NIC. Doing
5785 			 * a full re-init means reloading the firmware and
5786 			 * waiting for it to start up, which may take a
5787 			 * second or two.  Similarly for ALLMULTI.
5788 			 */
5789 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5790 				flags = if_getflags(ifp) ^ sc->bge_if_flags;
5791 				if (flags & IFF_PROMISC)
5792 					bge_setpromisc(sc);
5793 				if (flags & IFF_ALLMULTI)
5794 					bge_setmulti(sc);
5795 			} else
5796 				bge_init_locked(sc);
5797 		} else {
5798 			if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5799 				bge_stop(sc);
5800 			}
5801 		}
5802 		sc->bge_if_flags = if_getflags(ifp);
5803 		BGE_UNLOCK(sc);
5804 		error = 0;
5805 		break;
5806 	case SIOCADDMULTI:
5807 	case SIOCDELMULTI:
5808 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) {
5809 			BGE_LOCK(sc);
5810 			bge_setmulti(sc);
5811 			BGE_UNLOCK(sc);
5812 			error = 0;
5813 		}
5814 		break;
5815 	case SIOCSIFMEDIA:
5816 	case SIOCGIFMEDIA:
5817 		if (sc->bge_flags & BGE_FLAG_TBI) {
5818 			error = ifmedia_ioctl(ifp, ifr,
5819 			    &sc->bge_ifmedia, command);
5820 		} else {
5821 			mii = device_get_softc(sc->bge_miibus);
5822 			error = ifmedia_ioctl(ifp, ifr,
5823 			    &mii->mii_media, command);
5824 		}
5825 		break;
5826 	case SIOCSIFCAP:
5827 		mask = ifr->ifr_reqcap ^ if_getcapenable(ifp);
5828 #ifdef DEVICE_POLLING
5829 		if (mask & IFCAP_POLLING) {
5830 			if (ifr->ifr_reqcap & IFCAP_POLLING) {
5831 				error = ether_poll_register(bge_poll, ifp);
5832 				if (error)
5833 					return (error);
5834 				BGE_LOCK(sc);
5835 				BGE_SETBIT(sc, BGE_PCI_MISC_CTL,
5836 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
5837 				bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5838 				if_setcapenablebit(ifp, IFCAP_POLLING, 0);
5839 				BGE_UNLOCK(sc);
5840 			} else {
5841 				error = ether_poll_deregister(ifp);
5842 				/* Enable interrupt even in error case */
5843 				BGE_LOCK(sc);
5844 				BGE_CLRBIT(sc, BGE_PCI_MISC_CTL,
5845 				    BGE_PCIMISCCTL_MASK_PCI_INTR);
5846 				bge_writembx(sc, BGE_MBX_IRQ0_LO, 0);
5847 				if_setcapenablebit(ifp, 0, IFCAP_POLLING);
5848 				BGE_UNLOCK(sc);
5849 			}
5850 		}
5851 #endif
5852 		if ((mask & IFCAP_TXCSUM) != 0 &&
5853 		    (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) {
5854 			if_togglecapenable(ifp, IFCAP_TXCSUM);
5855 			if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0)
5856 				if_sethwassistbits(ifp,
5857 				    sc->bge_csum_features, 0);
5858 			else
5859 				if_sethwassistbits(ifp, 0,
5860 				    sc->bge_csum_features);
5861 		}
5862 
5863 		if ((mask & IFCAP_RXCSUM) != 0 &&
5864 		    (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0)
5865 			if_togglecapenable(ifp, IFCAP_RXCSUM);
5866 
5867 		if ((mask & IFCAP_TSO4) != 0 &&
5868 		    (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) {
5869 			if_togglecapenable(ifp, IFCAP_TSO4);
5870 			if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0)
5871 				if_sethwassistbits(ifp, CSUM_TSO, 0);
5872 			else
5873 				if_sethwassistbits(ifp, 0, CSUM_TSO);
5874 		}
5875 
5876 		if (mask & IFCAP_VLAN_MTU) {
5877 			if_togglecapenable(ifp, IFCAP_VLAN_MTU);
5878 			if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5879 			bge_init(sc);
5880 		}
5881 
5882 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
5883 		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0)
5884 			if_togglecapenable(ifp, IFCAP_VLAN_HWTSO);
5885 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
5886 		    (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) {
5887 			if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING);
5888 			if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0)
5889 				if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO);
5890 			BGE_LOCK(sc);
5891 			bge_setvlan(sc);
5892 			BGE_UNLOCK(sc);
5893 		}
5894 #ifdef VLAN_CAPABILITIES
5895 		if_vlancap(ifp);
5896 #endif
5897 		break;
5898 	default:
5899 		error = ether_ioctl(ifp, command, data);
5900 		break;
5901 	}
5902 
5903 	return (error);
5904 }
5905 
5906 static void
5907 bge_watchdog(struct bge_softc *sc)
5908 {
5909 	if_t ifp;
5910 	uint32_t status;
5911 
5912 	BGE_LOCK_ASSERT(sc);
5913 
5914 	if (sc->bge_timer == 0 || --sc->bge_timer)
5915 		return;
5916 
5917 	/* If pause frames are active then don't reset the hardware. */
5918 	if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) {
5919 		status = CSR_READ_4(sc, BGE_RX_STS);
5920 		if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) {
5921 			/*
5922 			 * If link partner has us in XOFF state then wait for
5923 			 * the condition to clear.
5924 			 */
5925 			CSR_WRITE_4(sc, BGE_RX_STS, status);
5926 			sc->bge_timer = BGE_TX_TIMEOUT;
5927 			return;
5928 		} else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 &&
5929 		    (status & BGE_RXSTAT_RCVD_XON) != 0) {
5930 			/*
5931 			 * If link partner has us in XOFF state then wait for
5932 			 * the condition to clear.
5933 			 */
5934 			CSR_WRITE_4(sc, BGE_RX_STS, status);
5935 			sc->bge_timer = BGE_TX_TIMEOUT;
5936 			return;
5937 		}
5938 		/*
5939 		 * Any other condition is unexpected and the controller
5940 		 * should be reset.
5941 		 */
5942 	}
5943 
5944 	ifp = sc->bge_ifp;
5945 
5946 	if_printf(ifp, "watchdog timeout -- resetting\n");
5947 
5948 	if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING);
5949 	bge_init_locked(sc);
5950 
5951 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
5952 }
5953 
5954 static void
5955 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit)
5956 {
5957 	int i;
5958 
5959 	BGE_CLRBIT(sc, reg, bit);
5960 
5961 	for (i = 0; i < BGE_TIMEOUT; i++) {
5962 		if ((CSR_READ_4(sc, reg) & bit) == 0)
5963 			return;
5964 		DELAY(100);
5965         }
5966 }
5967 
5968 /*
5969  * Stop the adapter and free any mbufs allocated to the
5970  * RX and TX lists.
5971  */
5972 static void
5973 bge_stop(struct bge_softc *sc)
5974 {
5975 	if_t ifp;
5976 
5977 	BGE_LOCK_ASSERT(sc);
5978 
5979 	ifp = sc->bge_ifp;
5980 
5981 	callout_stop(&sc->bge_stat_ch);
5982 
5983 	/* Disable host interrupts. */
5984 	BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
5985 	bge_writembx(sc, BGE_MBX_IRQ0_LO, 1);
5986 
5987 	/*
5988 	 * Tell firmware we're shutting down.
5989 	 */
5990 	bge_stop_fw(sc);
5991 	bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN);
5992 
5993 	/*
5994 	 * Disable all of the receiver blocks.
5995 	 */
5996 	bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
5997 	bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
5998 	bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
5999 	if (BGE_IS_5700_FAMILY(sc))
6000 		bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
6001 	bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
6002 	bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
6003 	bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
6004 
6005 	/*
6006 	 * Disable all of the transmit blocks.
6007 	 */
6008 	bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
6009 	bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
6010 	bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
6011 	bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
6012 	bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
6013 	if (BGE_IS_5700_FAMILY(sc))
6014 		bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
6015 	bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
6016 
6017 	/*
6018 	 * Shut down all of the memory managers and related
6019 	 * state machines.
6020 	 */
6021 	bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
6022 	bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
6023 	if (BGE_IS_5700_FAMILY(sc))
6024 		bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
6025 
6026 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
6027 	CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
6028 	if (!(BGE_IS_5705_PLUS(sc))) {
6029 		BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
6030 		BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
6031 	}
6032 	/* Update MAC statistics. */
6033 	if (BGE_IS_5705_PLUS(sc))
6034 		bge_stats_update_regs(sc);
6035 
6036 	bge_reset(sc);
6037 	bge_sig_legacy(sc, BGE_RESET_SHUTDOWN);
6038 	bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN);
6039 
6040 	/*
6041 	 * Keep the ASF firmware running if up.
6042 	 */
6043 	if (sc->bge_asf_mode & ASF_STACKUP)
6044 		BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6045 	else
6046 		BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
6047 
6048 	/* Free the RX lists. */
6049 	bge_free_rx_ring_std(sc);
6050 
6051 	/* Free jumbo RX list. */
6052 	if (BGE_IS_JUMBO_CAPABLE(sc))
6053 		bge_free_rx_ring_jumbo(sc);
6054 
6055 	/* Free TX buffers. */
6056 	bge_free_tx_ring(sc);
6057 
6058 	sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
6059 
6060 	/* Clear MAC's link state (PHY may still have link UP). */
6061 	if (bootverbose && sc->bge_link)
6062 		if_printf(sc->bge_ifp, "link DOWN\n");
6063 	sc->bge_link = 0;
6064 
6065 	if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE));
6066 }
6067 
6068 /*
6069  * Stop all chip I/O so that the kernel's probe routines don't
6070  * get confused by errant DMAs when rebooting.
6071  */
6072 static int
6073 bge_shutdown(device_t dev)
6074 {
6075 	struct bge_softc *sc;
6076 
6077 	sc = device_get_softc(dev);
6078 	BGE_LOCK(sc);
6079 	bge_stop(sc);
6080 	BGE_UNLOCK(sc);
6081 
6082 	return (0);
6083 }
6084 
6085 static int
6086 bge_suspend(device_t dev)
6087 {
6088 	struct bge_softc *sc;
6089 
6090 	sc = device_get_softc(dev);
6091 	BGE_LOCK(sc);
6092 	bge_stop(sc);
6093 	BGE_UNLOCK(sc);
6094 
6095 	return (0);
6096 }
6097 
6098 static int
6099 bge_resume(device_t dev)
6100 {
6101 	struct bge_softc *sc;
6102 	if_t ifp;
6103 
6104 	sc = device_get_softc(dev);
6105 	BGE_LOCK(sc);
6106 	ifp = sc->bge_ifp;
6107 	if (if_getflags(ifp) & IFF_UP) {
6108 		bge_init_locked(sc);
6109 		if (if_getdrvflags(ifp) & IFF_DRV_RUNNING)
6110 			bge_start_locked(ifp);
6111 	}
6112 	BGE_UNLOCK(sc);
6113 
6114 	return (0);
6115 }
6116 
6117 static void
6118 bge_link_upd(struct bge_softc *sc)
6119 {
6120 	struct mii_data *mii;
6121 	uint32_t link, status;
6122 
6123 	BGE_LOCK_ASSERT(sc);
6124 
6125 	/* Clear 'pending link event' flag. */
6126 	sc->bge_link_evt = 0;
6127 
6128 	/*
6129 	 * Process link state changes.
6130 	 * Grrr. The link status word in the status block does
6131 	 * not work correctly on the BCM5700 rev AX and BX chips,
6132 	 * according to all available information. Hence, we have
6133 	 * to enable MII interrupts in order to properly obtain
6134 	 * async link changes. Unfortunately, this also means that
6135 	 * we have to read the MAC status register to detect link
6136 	 * changes, thereby adding an additional register access to
6137 	 * the interrupt handler.
6138 	 *
6139 	 * XXX: perhaps link state detection procedure used for
6140 	 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions.
6141 	 */
6142 
6143 	if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6144 	    sc->bge_chipid != BGE_CHIPID_BCM5700_B2) {
6145 		status = CSR_READ_4(sc, BGE_MAC_STS);
6146 		if (status & BGE_MACSTAT_MI_INTERRUPT) {
6147 			mii = device_get_softc(sc->bge_miibus);
6148 			mii_pollstat(mii);
6149 			if (!sc->bge_link &&
6150 			    mii->mii_media_status & IFM_ACTIVE &&
6151 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6152 				sc->bge_link++;
6153 				if (bootverbose)
6154 					if_printf(sc->bge_ifp, "link UP\n");
6155 			} else if (sc->bge_link &&
6156 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
6157 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6158 				sc->bge_link = 0;
6159 				if (bootverbose)
6160 					if_printf(sc->bge_ifp, "link DOWN\n");
6161 			}
6162 
6163 			/* Clear the interrupt. */
6164 			CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
6165 			    BGE_EVTENB_MI_INTERRUPT);
6166 			bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr,
6167 			    BRGPHY_MII_ISR);
6168 			bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr,
6169 			    BRGPHY_MII_IMR, BRGPHY_INTRS);
6170 		}
6171 		return;
6172 	}
6173 
6174 	if (sc->bge_flags & BGE_FLAG_TBI) {
6175 		status = CSR_READ_4(sc, BGE_MAC_STS);
6176 		if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) {
6177 			if (!sc->bge_link) {
6178 				sc->bge_link++;
6179 				if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
6180 					BGE_CLRBIT(sc, BGE_MAC_MODE,
6181 					    BGE_MACMODE_TBI_SEND_CFGS);
6182 					DELAY(40);
6183 				}
6184 				CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
6185 				if (bootverbose)
6186 					if_printf(sc->bge_ifp, "link UP\n");
6187 				if_link_state_change(sc->bge_ifp,
6188 				    LINK_STATE_UP);
6189 			}
6190 		} else if (sc->bge_link) {
6191 			sc->bge_link = 0;
6192 			if (bootverbose)
6193 				if_printf(sc->bge_ifp, "link DOWN\n");
6194 			if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN);
6195 		}
6196 	} else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) {
6197 		/*
6198 		 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit
6199 		 * in status word always set. Workaround this bug by reading
6200 		 * PHY link status directly.
6201 		 */
6202 		link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0;
6203 
6204 		if (link != sc->bge_link ||
6205 		    sc->bge_asicrev == BGE_ASICREV_BCM5700) {
6206 			mii = device_get_softc(sc->bge_miibus);
6207 			mii_pollstat(mii);
6208 			if (!sc->bge_link &&
6209 			    mii->mii_media_status & IFM_ACTIVE &&
6210 			    IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6211 				sc->bge_link++;
6212 				if (bootverbose)
6213 					if_printf(sc->bge_ifp, "link UP\n");
6214 			} else if (sc->bge_link &&
6215 			    (!(mii->mii_media_status & IFM_ACTIVE) ||
6216 			    IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) {
6217 				sc->bge_link = 0;
6218 				if (bootverbose)
6219 					if_printf(sc->bge_ifp, "link DOWN\n");
6220 			}
6221 		}
6222 	} else {
6223 		/*
6224 		 * For controllers that call mii_tick, we have to poll
6225 		 * link status.
6226 		 */
6227 		mii = device_get_softc(sc->bge_miibus);
6228 		mii_pollstat(mii);
6229 		bge_miibus_statchg(sc->bge_dev);
6230 	}
6231 
6232 	/* Disable MAC attention when link is up. */
6233 	CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED |
6234 	    BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE |
6235 	    BGE_MACSTAT_LINK_CHANGED);
6236 }
6237 
6238 static void
6239 bge_add_sysctls(struct bge_softc *sc)
6240 {
6241 	struct sysctl_ctx_list *ctx;
6242 	struct sysctl_oid_list *children;
6243 	int unit;
6244 
6245 	ctx = device_get_sysctl_ctx(sc->bge_dev);
6246 	children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev));
6247 
6248 #ifdef BGE_REGISTER_DEBUG
6249 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info",
6250 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I",
6251 	    "Debug Information");
6252 
6253 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read",
6254 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I",
6255 	    "MAC Register Read");
6256 
6257 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read",
6258 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I",
6259 	    "APE Register Read");
6260 
6261 	SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read",
6262 	    CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I",
6263 	    "Memory Read");
6264 
6265 #endif
6266 
6267 	unit = device_get_unit(sc->bge_dev);
6268 	/*
6269 	 * A common design characteristic for many Broadcom client controllers
6270 	 * is that they only support a single outstanding DMA read operation
6271 	 * on the PCIe bus. This means that it will take twice as long to fetch
6272 	 * a TX frame that is split into header and payload buffers as it does
6273 	 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For
6274 	 * these controllers, coalescing buffers to reduce the number of memory
6275 	 * reads is effective way to get maximum performance(about 940Mbps).
6276 	 * Without collapsing TX buffers the maximum TCP bulk transfer
6277 	 * performance is about 850Mbps. However forcing coalescing mbufs
6278 	 * consumes a lot of CPU cycles, so leave it off by default.
6279 	 */
6280 	sc->bge_forced_collapse = 0;
6281 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse",
6282 	    CTLFLAG_RWTUN, &sc->bge_forced_collapse, 0,
6283 	    "Number of fragmented TX buffers of a frame allowed before "
6284 	    "forced collapsing");
6285 
6286 	sc->bge_msi = 1;
6287 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi",
6288 	    CTLFLAG_RDTUN, &sc->bge_msi, 0, "Enable MSI");
6289 
6290 	/*
6291 	 * It seems all Broadcom controllers have a bug that can generate UDP
6292 	 * datagrams with checksum value 0 when TX UDP checksum offloading is
6293 	 * enabled.  Generating UDP checksum value 0 is RFC 768 violation.
6294 	 * Even though the probability of generating such UDP datagrams is
6295 	 * low, I don't want to see FreeBSD boxes to inject such datagrams
6296 	 * into network so disable UDP checksum offloading by default.  Users
6297 	 * still override this behavior by setting a sysctl variable,
6298 	 * dev.bge.0.forced_udpcsum.
6299 	 */
6300 	sc->bge_forced_udpcsum = 0;
6301 	SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum",
6302 	    CTLFLAG_RWTUN, &sc->bge_forced_udpcsum, 0,
6303 	    "Enable UDP checksum offloading even if controller can "
6304 	    "generate UDP checksum value 0");
6305 
6306 	if (BGE_IS_5705_PLUS(sc))
6307 		bge_add_sysctl_stats_regs(sc, ctx, children);
6308 	else
6309 		bge_add_sysctl_stats(sc, ctx, children);
6310 }
6311 
6312 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \
6313 	SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \
6314 	    sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \
6315 	    desc)
6316 
6317 static void
6318 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6319     struct sysctl_oid_list *parent)
6320 {
6321 	struct sysctl_oid *tree;
6322 	struct sysctl_oid_list *children, *schildren;
6323 
6324 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6325 	    NULL, "BGE Statistics");
6326 	schildren = children = SYSCTL_CHILDREN(tree);
6327 	BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters",
6328 	    children, COSFramesDroppedDueToFilters,
6329 	    "FramesDroppedDueToFilters");
6330 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full",
6331 	    children, nicDmaWriteQueueFull, "DmaWriteQueueFull");
6332 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full",
6333 	    children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull");
6334 	BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors",
6335 	    children, nicNoMoreRxBDs, "NoMoreRxBDs");
6336 	BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames",
6337 	    children, ifInDiscards, "InputDiscards");
6338 	BGE_SYSCTL_STAT(sc, ctx, "Input Errors",
6339 	    children, ifInErrors, "InputErrors");
6340 	BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit",
6341 	    children, nicRecvThresholdHit, "RecvThresholdHit");
6342 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full",
6343 	    children, nicDmaReadQueueFull, "DmaReadQueueFull");
6344 	BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full",
6345 	    children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull");
6346 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full",
6347 	    children, nicSendDataCompQueueFull, "SendDataCompQueueFull");
6348 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index",
6349 	    children, nicRingSetSendProdIndex, "RingSetSendProdIndex");
6350 	BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update",
6351 	    children, nicRingStatusUpdate, "RingStatusUpdate");
6352 	BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts",
6353 	    children, nicInterrupts, "Interrupts");
6354 	BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts",
6355 	    children, nicAvoidedInterrupts, "AvoidedInterrupts");
6356 	BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit",
6357 	    children, nicSendThresholdHit, "SendThresholdHit");
6358 
6359 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD,
6360 	    NULL, "BGE RX Statistics");
6361 	children = SYSCTL_CHILDREN(tree);
6362 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets",
6363 	    children, rxstats.ifHCInOctets, "ifHCInOctets");
6364 	BGE_SYSCTL_STAT(sc, ctx, "Fragments",
6365 	    children, rxstats.etherStatsFragments, "Fragments");
6366 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets",
6367 	    children, rxstats.ifHCInUcastPkts, "UnicastPkts");
6368 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets",
6369 	    children, rxstats.ifHCInMulticastPkts, "MulticastPkts");
6370 	BGE_SYSCTL_STAT(sc, ctx, "FCS Errors",
6371 	    children, rxstats.dot3StatsFCSErrors, "FCSErrors");
6372 	BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors",
6373 	    children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors");
6374 	BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received",
6375 	    children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived");
6376 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received",
6377 	    children, rxstats.xoffPauseFramesReceived,
6378 	    "xoffPauseFramesReceived");
6379 	BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received",
6380 	    children, rxstats.macControlFramesReceived,
6381 	    "ControlFramesReceived");
6382 	BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered",
6383 	    children, rxstats.xoffStateEntered, "xoffStateEntered");
6384 	BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long",
6385 	    children, rxstats.dot3StatsFramesTooLong, "FramesTooLong");
6386 	BGE_SYSCTL_STAT(sc, ctx, "Jabbers",
6387 	    children, rxstats.etherStatsJabbers, "Jabbers");
6388 	BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets",
6389 	    children, rxstats.etherStatsUndersizePkts, "UndersizePkts");
6390 	BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors",
6391 	    children, rxstats.inRangeLengthError, "inRangeLengthError");
6392 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors",
6393 	    children, rxstats.outRangeLengthError, "outRangeLengthError");
6394 
6395 	tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD,
6396 	    NULL, "BGE TX Statistics");
6397 	children = SYSCTL_CHILDREN(tree);
6398 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets",
6399 	    children, txstats.ifHCOutOctets, "ifHCOutOctets");
6400 	BGE_SYSCTL_STAT(sc, ctx, "TX Collisions",
6401 	    children, txstats.etherStatsCollisions, "Collisions");
6402 	BGE_SYSCTL_STAT(sc, ctx, "XON Sent",
6403 	    children, txstats.outXonSent, "XonSent");
6404 	BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent",
6405 	    children, txstats.outXoffSent, "XoffSent");
6406 	BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done",
6407 	    children, txstats.flowControlDone, "flowControlDone");
6408 	BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors",
6409 	    children, txstats.dot3StatsInternalMacTransmitErrors,
6410 	    "InternalMacTransmitErrors");
6411 	BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames",
6412 	    children, txstats.dot3StatsSingleCollisionFrames,
6413 	    "SingleCollisionFrames");
6414 	BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames",
6415 	    children, txstats.dot3StatsMultipleCollisionFrames,
6416 	    "MultipleCollisionFrames");
6417 	BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions",
6418 	    children, txstats.dot3StatsDeferredTransmissions,
6419 	    "DeferredTransmissions");
6420 	BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions",
6421 	    children, txstats.dot3StatsExcessiveCollisions,
6422 	    "ExcessiveCollisions");
6423 	BGE_SYSCTL_STAT(sc, ctx, "Late Collisions",
6424 	    children, txstats.dot3StatsLateCollisions,
6425 	    "LateCollisions");
6426 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets",
6427 	    children, txstats.ifHCOutUcastPkts, "UnicastPkts");
6428 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets",
6429 	    children, txstats.ifHCOutMulticastPkts, "MulticastPkts");
6430 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets",
6431 	    children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts");
6432 	BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors",
6433 	    children, txstats.dot3StatsCarrierSenseErrors,
6434 	    "CarrierSenseErrors");
6435 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards",
6436 	    children, txstats.ifOutDiscards, "Discards");
6437 	BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors",
6438 	    children, txstats.ifOutErrors, "Errors");
6439 }
6440 
6441 #undef BGE_SYSCTL_STAT
6442 
6443 #define	BGE_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
6444 	    SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
6445 
6446 static void
6447 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx,
6448     struct sysctl_oid_list *parent)
6449 {
6450 	struct sysctl_oid *tree;
6451 	struct sysctl_oid_list *child, *schild;
6452 	struct bge_mac_stats *stats;
6453 
6454 	stats = &sc->bge_mac_stats;
6455 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD,
6456 	    NULL, "BGE Statistics");
6457 	schild = child = SYSCTL_CHILDREN(tree);
6458 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters",
6459 	    &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters");
6460 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull",
6461 	    &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full");
6462 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull",
6463 	    &stats->DmaWriteHighPriQueueFull,
6464 	    "NIC DMA Write High Priority Queue Full");
6465 	BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs",
6466 	    &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors");
6467 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards",
6468 	    &stats->InputDiscards, "Discarded Input Frames");
6469 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors",
6470 	    &stats->InputErrors, "Input Errors");
6471 	BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit",
6472 	    &stats->RecvThresholdHit, "NIC Recv Threshold Hit");
6473 
6474 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
6475 	    NULL, "BGE RX Statistics");
6476 	child = SYSCTL_CHILDREN(tree);
6477 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets",
6478 	    &stats->ifHCInOctets, "Inbound Octets");
6479 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments",
6480 	    &stats->etherStatsFragments, "Fragments");
6481 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6482 	    &stats->ifHCInUcastPkts, "Inbound Unicast Packets");
6483 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6484 	    &stats->ifHCInMulticastPkts, "Inbound Multicast Packets");
6485 	BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6486 	    &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets");
6487 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors",
6488 	    &stats->dot3StatsFCSErrors, "FCS Errors");
6489 	BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors",
6490 	    &stats->dot3StatsAlignmentErrors, "Alignment Errors");
6491 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived",
6492 	    &stats->xonPauseFramesReceived, "XON Pause Frames Received");
6493 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived",
6494 	    &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received");
6495 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived",
6496 	    &stats->macControlFramesReceived, "MAC Control Frames Received");
6497 	BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered",
6498 	    &stats->xoffStateEntered, "XOFF State Entered");
6499 	BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong",
6500 	    &stats->dot3StatsFramesTooLong, "Frames Too Long");
6501 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers",
6502 	    &stats->etherStatsJabbers, "Jabbers");
6503 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts",
6504 	    &stats->etherStatsUndersizePkts, "Undersized Packets");
6505 
6506 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
6507 	    NULL, "BGE TX Statistics");
6508 	child = SYSCTL_CHILDREN(tree);
6509 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets",
6510 	    &stats->ifHCOutOctets, "Outbound Octets");
6511 	BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions",
6512 	    &stats->etherStatsCollisions, "TX Collisions");
6513 	BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent",
6514 	    &stats->outXonSent, "XON Sent");
6515 	BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent",
6516 	    &stats->outXoffSent, "XOFF Sent");
6517 	BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors",
6518 	    &stats->dot3StatsInternalMacTransmitErrors,
6519 	    "Internal MAC TX Errors");
6520 	BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames",
6521 	    &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames");
6522 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames",
6523 	    &stats->dot3StatsMultipleCollisionFrames,
6524 	    "Multiple Collision Frames");
6525 	BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions",
6526 	    &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions");
6527 	BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions",
6528 	    &stats->dot3StatsExcessiveCollisions, "Excessive Collisions");
6529 	BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions",
6530 	    &stats->dot3StatsLateCollisions, "Late Collisions");
6531 	BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts",
6532 	    &stats->ifHCOutUcastPkts, "Outbound Unicast Packets");
6533 	BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts",
6534 	    &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets");
6535 	BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts",
6536 	    &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets");
6537 }
6538 
6539 #undef	BGE_SYSCTL_STAT_ADD64
6540 
6541 static int
6542 bge_sysctl_stats(SYSCTL_HANDLER_ARGS)
6543 {
6544 	struct bge_softc *sc;
6545 	uint32_t result;
6546 	int offset;
6547 
6548 	sc = (struct bge_softc *)arg1;
6549 	offset = arg2;
6550 	result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset +
6551 	    offsetof(bge_hostaddr, bge_addr_lo));
6552 	return (sysctl_handle_int(oidp, &result, 0, req));
6553 }
6554 
6555 #ifdef BGE_REGISTER_DEBUG
6556 static int
6557 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
6558 {
6559 	struct bge_softc *sc;
6560 	uint16_t *sbdata;
6561 	int error, result, sbsz;
6562 	int i, j;
6563 
6564 	result = -1;
6565 	error = sysctl_handle_int(oidp, &result, 0, req);
6566 	if (error || (req->newptr == NULL))
6567 		return (error);
6568 
6569 	if (result == 1) {
6570 		sc = (struct bge_softc *)arg1;
6571 
6572 		if (sc->bge_asicrev == BGE_ASICREV_BCM5700 &&
6573 		    sc->bge_chipid != BGE_CHIPID_BCM5700_C0)
6574 			sbsz = BGE_STATUS_BLK_SZ;
6575 		else
6576 			sbsz = 32;
6577 		sbdata = (uint16_t *)sc->bge_ldata.bge_status_block;
6578 		printf("Status Block:\n");
6579 		BGE_LOCK(sc);
6580 		bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6581 		    sc->bge_cdata.bge_status_map,
6582 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6583 		for (i = 0x0; i < sbsz / sizeof(uint16_t); ) {
6584 			printf("%06x:", i);
6585 			for (j = 0; j < 8; j++)
6586 				printf(" %04x", sbdata[i++]);
6587 			printf("\n");
6588 		}
6589 
6590 		printf("Registers:\n");
6591 		for (i = 0x800; i < 0xA00; ) {
6592 			printf("%06x:", i);
6593 			for (j = 0; j < 8; j++) {
6594 				printf(" %08x", CSR_READ_4(sc, i));
6595 				i += 4;
6596 			}
6597 			printf("\n");
6598 		}
6599 		BGE_UNLOCK(sc);
6600 
6601 		printf("Hardware Flags:\n");
6602 		if (BGE_IS_5717_PLUS(sc))
6603 			printf(" - 5717 Plus\n");
6604 		if (BGE_IS_5755_PLUS(sc))
6605 			printf(" - 5755 Plus\n");
6606 		if (BGE_IS_575X_PLUS(sc))
6607 			printf(" - 575X Plus\n");
6608 		if (BGE_IS_5705_PLUS(sc))
6609 			printf(" - 5705 Plus\n");
6610 		if (BGE_IS_5714_FAMILY(sc))
6611 			printf(" - 5714 Family\n");
6612 		if (BGE_IS_5700_FAMILY(sc))
6613 			printf(" - 5700 Family\n");
6614 		if (sc->bge_flags & BGE_FLAG_JUMBO)
6615 			printf(" - Supports Jumbo Frames\n");
6616 		if (sc->bge_flags & BGE_FLAG_PCIX)
6617 			printf(" - PCI-X Bus\n");
6618 		if (sc->bge_flags & BGE_FLAG_PCIE)
6619 			printf(" - PCI Express Bus\n");
6620 		if (sc->bge_phy_flags & BGE_PHY_NO_3LED)
6621 			printf(" - No 3 LEDs\n");
6622 		if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG)
6623 			printf(" - RX Alignment Bug\n");
6624 	}
6625 
6626 	return (error);
6627 }
6628 
6629 static int
6630 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6631 {
6632 	struct bge_softc *sc;
6633 	int error;
6634 	uint16_t result;
6635 	uint32_t val;
6636 
6637 	result = -1;
6638 	error = sysctl_handle_int(oidp, &result, 0, req);
6639 	if (error || (req->newptr == NULL))
6640 		return (error);
6641 
6642 	if (result < 0x8000) {
6643 		sc = (struct bge_softc *)arg1;
6644 		val = CSR_READ_4(sc, result);
6645 		printf("reg 0x%06X = 0x%08X\n", result, val);
6646 	}
6647 
6648 	return (error);
6649 }
6650 
6651 static int
6652 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS)
6653 {
6654 	struct bge_softc *sc;
6655 	int error;
6656 	uint16_t result;
6657 	uint32_t val;
6658 
6659 	result = -1;
6660 	error = sysctl_handle_int(oidp, &result, 0, req);
6661 	if (error || (req->newptr == NULL))
6662 		return (error);
6663 
6664 	if (result < 0x8000) {
6665 		sc = (struct bge_softc *)arg1;
6666 		val = APE_READ_4(sc, result);
6667 		printf("reg 0x%06X = 0x%08X\n", result, val);
6668 	}
6669 
6670 	return (error);
6671 }
6672 
6673 static int
6674 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS)
6675 {
6676 	struct bge_softc *sc;
6677 	int error;
6678 	uint16_t result;
6679 	uint32_t val;
6680 
6681 	result = -1;
6682 	error = sysctl_handle_int(oidp, &result, 0, req);
6683 	if (error || (req->newptr == NULL))
6684 		return (error);
6685 
6686 	if (result < 0x8000) {
6687 		sc = (struct bge_softc *)arg1;
6688 		val = bge_readmem_ind(sc, result);
6689 		printf("mem 0x%06X = 0x%08X\n", result, val);
6690 	}
6691 
6692 	return (error);
6693 }
6694 #endif
6695 
6696 static int
6697 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[])
6698 {
6699 	return (1);
6700 }
6701 
6702 static int
6703 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[])
6704 {
6705 	uint32_t mac_addr;
6706 
6707 	mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB);
6708 	if ((mac_addr >> 16) == 0x484b) {
6709 		ether_addr[0] = (uint8_t)(mac_addr >> 8);
6710 		ether_addr[1] = (uint8_t)mac_addr;
6711 		mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB);
6712 		ether_addr[2] = (uint8_t)(mac_addr >> 24);
6713 		ether_addr[3] = (uint8_t)(mac_addr >> 16);
6714 		ether_addr[4] = (uint8_t)(mac_addr >> 8);
6715 		ether_addr[5] = (uint8_t)mac_addr;
6716 		return (0);
6717 	}
6718 	return (1);
6719 }
6720 
6721 static int
6722 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[])
6723 {
6724 	int mac_offset = BGE_EE_MAC_OFFSET;
6725 
6726 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6727 		mac_offset = BGE_EE_MAC_OFFSET_5906;
6728 
6729 	return (bge_read_nvram(sc, ether_addr, mac_offset + 2,
6730 	    ETHER_ADDR_LEN));
6731 }
6732 
6733 static int
6734 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[])
6735 {
6736 
6737 	if (sc->bge_asicrev == BGE_ASICREV_BCM5906)
6738 		return (1);
6739 
6740 	return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2,
6741 	   ETHER_ADDR_LEN));
6742 }
6743 
6744 static int
6745 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[])
6746 {
6747 	static const bge_eaddr_fcn_t bge_eaddr_funcs[] = {
6748 		/* NOTE: Order is critical */
6749 		bge_get_eaddr_fw,
6750 		bge_get_eaddr_mem,
6751 		bge_get_eaddr_nvram,
6752 		bge_get_eaddr_eeprom,
6753 		NULL
6754 	};
6755 	const bge_eaddr_fcn_t *func;
6756 
6757 	for (func = bge_eaddr_funcs; *func != NULL; ++func) {
6758 		if ((*func)(sc, eaddr) == 0)
6759 			break;
6760 	}
6761 	return (*func == NULL ? ENXIO : 0);
6762 }
6763 
6764 static uint64_t
6765 bge_get_counter(if_t ifp, ift_counter cnt)
6766 {
6767 	struct bge_softc *sc;
6768 	struct bge_mac_stats *stats;
6769 
6770 	sc = if_getsoftc(ifp);
6771 	if (!BGE_IS_5705_PLUS(sc))
6772 		return (if_get_counter_default(ifp, cnt));
6773 	stats = &sc->bge_mac_stats;
6774 
6775 	switch (cnt) {
6776 	case IFCOUNTER_IERRORS:
6777 		return (stats->NoMoreRxBDs + stats->InputDiscards +
6778 		    stats->InputErrors);
6779 	case IFCOUNTER_COLLISIONS:
6780 		return (stats->etherStatsCollisions);
6781 	default:
6782 		return (if_get_counter_default(ifp, cnt));
6783 	}
6784 }
6785 
6786 #ifdef DEBUGNET
6787 static void
6788 bge_debugnet_init(if_t ifp, int *nrxr, int *ncl, int *clsize)
6789 {
6790 	struct bge_softc *sc;
6791 
6792 	sc = if_getsoftc(ifp);
6793 	BGE_LOCK(sc);
6794 	*nrxr = sc->bge_return_ring_cnt;
6795 	*ncl = DEBUGNET_MAX_IN_FLIGHT;
6796 	if ((sc->bge_flags & BGE_FLAG_JUMBO_STD) != 0 &&
6797 	    (if_getmtu(sc->bge_ifp) + ETHER_HDR_LEN + ETHER_CRC_LEN +
6798 	    ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN)))
6799 		*clsize = MJUM9BYTES;
6800 	else
6801 		*clsize = MCLBYTES;
6802 	BGE_UNLOCK(sc);
6803 }
6804 
6805 static void
6806 bge_debugnet_event(if_t ifp __unused, enum debugnet_ev event __unused)
6807 {
6808 }
6809 
6810 static int
6811 bge_debugnet_transmit(if_t ifp, struct mbuf *m)
6812 {
6813 	struct bge_softc *sc;
6814 	uint32_t prodidx;
6815 	int error;
6816 
6817 	sc = if_getsoftc(ifp);
6818 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6819 	    IFF_DRV_RUNNING)
6820 		return (1);
6821 
6822 	prodidx = sc->bge_tx_prodidx;
6823 	error = bge_encap(sc, &m, &prodidx);
6824 	if (error == 0)
6825 		bge_start_tx(sc, prodidx);
6826 	return (error);
6827 }
6828 
6829 static int
6830 bge_debugnet_poll(if_t ifp, int count)
6831 {
6832 	struct bge_softc *sc;
6833 	uint32_t rx_prod, tx_cons;
6834 
6835 	sc = if_getsoftc(ifp);
6836 	if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
6837 	    IFF_DRV_RUNNING)
6838 		return (1);
6839 
6840 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6841 	    sc->bge_cdata.bge_status_map,
6842 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
6843 
6844 	rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx;
6845 	tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx;
6846 
6847 	bus_dmamap_sync(sc->bge_cdata.bge_status_tag,
6848 	    sc->bge_cdata.bge_status_map,
6849 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6850 
6851 	(void)bge_rxeof(sc, rx_prod, 0);
6852 	bge_txeof(sc, tx_cons);
6853 	return (0);
6854 }
6855 #endif /* DEBUGNET */
6856