1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 229 230 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 231 232 { TC_VENDORID, TC_DEVICEID_3C996 }, 233 234 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 235 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 236 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 237 238 { 0, 0 } 239 }; 240 241 static const struct bge_vendor { 242 uint16_t v_id; 243 const char *v_name; 244 } bge_vendors[] = { 245 { ALTEON_VENDORID, "Alteon" }, 246 { ALTIMA_VENDORID, "Altima" }, 247 { APPLE_VENDORID, "Apple" }, 248 { BCOM_VENDORID, "Broadcom" }, 249 { SK_VENDORID, "SysKonnect" }, 250 { TC_VENDORID, "3Com" }, 251 { FJTSU_VENDORID, "Fujitsu" }, 252 253 { 0, NULL } 254 }; 255 256 static const struct bge_revision { 257 uint32_t br_chipid; 258 const char *br_name; 259 } bge_revisions[] = { 260 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 261 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 262 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 263 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 264 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 265 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 266 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 267 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 268 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 269 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 270 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 271 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 272 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 273 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 274 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 275 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 276 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 277 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 278 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 279 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 280 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 281 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 282 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 283 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 284 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 285 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 286 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 287 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 288 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 289 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 290 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 291 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 292 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 293 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 294 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 295 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 296 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 297 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 298 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 299 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 300 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 301 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 302 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 303 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 304 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 305 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 306 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 307 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 308 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 309 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 310 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 311 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 312 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 313 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 314 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 315 /* 5754 and 5787 share the same ASIC ID */ 316 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 317 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 318 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 319 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 320 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 321 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 322 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 323 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 324 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 325 326 { 0, NULL } 327 }; 328 329 /* 330 * Some defaults for major revisions, so that newer steppings 331 * that we don't know about have a shot at working. 332 */ 333 static const struct bge_revision bge_majorrevs[] = { 334 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 335 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 336 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 337 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 338 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 339 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 340 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 341 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 342 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 343 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 344 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 345 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 346 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 347 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 348 /* 5754 and 5787 share the same ASIC ID */ 349 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 350 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 351 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 352 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 353 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 354 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 355 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 356 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 357 358 { 0, NULL } 359 }; 360 361 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 362 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 363 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 364 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 365 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 366 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 367 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 368 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 369 370 static uint32_t bge_chipid(device_t); 371 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 372 static const struct bge_revision * bge_lookup_rev(uint32_t); 373 374 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 375 376 static int bge_probe(device_t); 377 static int bge_attach(device_t); 378 static int bge_detach(device_t); 379 static int bge_suspend(device_t); 380 static int bge_resume(device_t); 381 static void bge_release_resources(struct bge_softc *); 382 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 383 static int bge_dma_alloc(struct bge_softc *); 384 static void bge_dma_free(struct bge_softc *); 385 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 386 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 387 388 static void bge_devinfo(struct bge_softc *); 389 static int bge_mbox_reorder(struct bge_softc *); 390 391 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 392 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 393 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 394 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 395 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 396 397 static void bge_txeof(struct bge_softc *, uint16_t); 398 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 399 static int bge_rxeof(struct bge_softc *, uint16_t, int); 400 401 static void bge_asf_driver_up (struct bge_softc *); 402 static void bge_tick(void *); 403 static void bge_stats_clear_regs(struct bge_softc *); 404 static void bge_stats_update(struct bge_softc *); 405 static void bge_stats_update_regs(struct bge_softc *); 406 static struct mbuf *bge_check_short_dma(struct mbuf *); 407 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 408 uint16_t *, uint16_t *); 409 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 410 411 static void bge_intr(void *); 412 static int bge_msi_intr(void *); 413 static void bge_intr_task(void *, int); 414 static void bge_start_locked(struct ifnet *); 415 static void bge_start(struct ifnet *); 416 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 417 static void bge_init_locked(struct bge_softc *); 418 static void bge_init(void *); 419 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 420 static void bge_stop(struct bge_softc *); 421 static void bge_watchdog(struct bge_softc *); 422 static int bge_shutdown(device_t); 423 static int bge_ifmedia_upd_locked(struct ifnet *); 424 static int bge_ifmedia_upd(struct ifnet *); 425 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 426 427 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 428 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 429 430 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 431 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 432 433 static void bge_setpromisc(struct bge_softc *); 434 static void bge_setmulti(struct bge_softc *); 435 static void bge_setvlan(struct bge_softc *); 436 437 static __inline void bge_rxreuse_std(struct bge_softc *, int); 438 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 439 static int bge_newbuf_std(struct bge_softc *, int); 440 static int bge_newbuf_jumbo(struct bge_softc *, int); 441 static int bge_init_rx_ring_std(struct bge_softc *); 442 static void bge_free_rx_ring_std(struct bge_softc *); 443 static int bge_init_rx_ring_jumbo(struct bge_softc *); 444 static void bge_free_rx_ring_jumbo(struct bge_softc *); 445 static void bge_free_tx_ring(struct bge_softc *); 446 static int bge_init_tx_ring(struct bge_softc *); 447 448 static int bge_chipinit(struct bge_softc *); 449 static int bge_blockinit(struct bge_softc *); 450 static uint32_t bge_dma_swap_options(struct bge_softc *); 451 452 static int bge_has_eaddr(struct bge_softc *); 453 static uint32_t bge_readmem_ind(struct bge_softc *, int); 454 static void bge_writemem_ind(struct bge_softc *, int, int); 455 static void bge_writembx(struct bge_softc *, int, int); 456 #ifdef notdef 457 static uint32_t bge_readreg_ind(struct bge_softc *, int); 458 #endif 459 static void bge_writemem_direct(struct bge_softc *, int, int); 460 static void bge_writereg_ind(struct bge_softc *, int, int); 461 462 static int bge_miibus_readreg(device_t, int, int); 463 static int bge_miibus_writereg(device_t, int, int, int); 464 static void bge_miibus_statchg(device_t); 465 #ifdef DEVICE_POLLING 466 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 467 #endif 468 469 #define BGE_RESET_SHUTDOWN 0 470 #define BGE_RESET_START 1 471 #define BGE_RESET_SUSPEND 2 472 static void bge_sig_post_reset(struct bge_softc *, int); 473 static void bge_sig_legacy(struct bge_softc *, int); 474 static void bge_sig_pre_reset(struct bge_softc *, int); 475 static void bge_stop_fw(struct bge_softc *); 476 static int bge_reset(struct bge_softc *); 477 static void bge_link_upd(struct bge_softc *); 478 479 static void bge_ape_lock_init(struct bge_softc *); 480 static void bge_ape_read_fw_ver(struct bge_softc *); 481 static int bge_ape_lock(struct bge_softc *, int); 482 static void bge_ape_unlock(struct bge_softc *, int); 483 static void bge_ape_send_event(struct bge_softc *, uint32_t); 484 static void bge_ape_driver_state_change(struct bge_softc *, int); 485 486 /* 487 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 488 * leak information to untrusted users. It is also known to cause alignment 489 * traps on certain architectures. 490 */ 491 #ifdef BGE_REGISTER_DEBUG 492 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 493 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 494 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 495 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 496 #endif 497 static void bge_add_sysctls(struct bge_softc *); 498 static void bge_add_sysctl_stats_regs(struct bge_softc *, 499 struct sysctl_ctx_list *, struct sysctl_oid_list *); 500 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 501 struct sysctl_oid_list *); 502 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 503 504 static device_method_t bge_methods[] = { 505 /* Device interface */ 506 DEVMETHOD(device_probe, bge_probe), 507 DEVMETHOD(device_attach, bge_attach), 508 DEVMETHOD(device_detach, bge_detach), 509 DEVMETHOD(device_shutdown, bge_shutdown), 510 DEVMETHOD(device_suspend, bge_suspend), 511 DEVMETHOD(device_resume, bge_resume), 512 513 /* MII interface */ 514 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 515 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 516 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 517 518 DEVMETHOD_END 519 }; 520 521 static driver_t bge_driver = { 522 "bge", 523 bge_methods, 524 sizeof(struct bge_softc) 525 }; 526 527 static devclass_t bge_devclass; 528 529 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 530 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 531 532 static int bge_allow_asf = 1; 533 534 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 535 536 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 537 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 538 "Allow ASF mode if available"); 539 540 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 541 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 542 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 543 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 544 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 545 546 static int 547 bge_has_eaddr(struct bge_softc *sc) 548 { 549 #ifdef __sparc64__ 550 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 551 device_t dev; 552 uint32_t subvendor; 553 554 dev = sc->bge_dev; 555 556 /* 557 * The on-board BGEs found in sun4u machines aren't fitted with 558 * an EEPROM which means that we have to obtain the MAC address 559 * via OFW and that some tests will always fail. We distinguish 560 * such BGEs by the subvendor ID, which also has to be obtained 561 * from OFW instead of the PCI configuration space as the latter 562 * indicates Broadcom as the subvendor of the netboot interface. 563 * For early Blade 1500 and 2500 we even have to check the OFW 564 * device path as the subvendor ID always defaults to Broadcom 565 * there. 566 */ 567 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 568 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 569 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 570 return (0); 571 memset(buf, 0, sizeof(buf)); 572 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 573 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 574 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 575 return (0); 576 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 577 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 578 return (0); 579 } 580 #endif 581 return (1); 582 } 583 584 static uint32_t 585 bge_readmem_ind(struct bge_softc *sc, int off) 586 { 587 device_t dev; 588 uint32_t val; 589 590 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 591 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 592 return (0); 593 594 dev = sc->bge_dev; 595 596 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 597 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 598 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 599 return (val); 600 } 601 602 static void 603 bge_writemem_ind(struct bge_softc *sc, int off, int val) 604 { 605 device_t dev; 606 607 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 608 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 609 return; 610 611 dev = sc->bge_dev; 612 613 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 614 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 615 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 616 } 617 618 #ifdef notdef 619 static uint32_t 620 bge_readreg_ind(struct bge_softc *sc, int off) 621 { 622 device_t dev; 623 624 dev = sc->bge_dev; 625 626 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 627 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 628 } 629 #endif 630 631 static void 632 bge_writereg_ind(struct bge_softc *sc, int off, int val) 633 { 634 device_t dev; 635 636 dev = sc->bge_dev; 637 638 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 639 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 640 } 641 642 static void 643 bge_writemem_direct(struct bge_softc *sc, int off, int val) 644 { 645 CSR_WRITE_4(sc, off, val); 646 } 647 648 static void 649 bge_writembx(struct bge_softc *sc, int off, int val) 650 { 651 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 652 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 653 654 CSR_WRITE_4(sc, off, val); 655 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 656 CSR_READ_4(sc, off); 657 } 658 659 /* 660 * Clear all stale locks and select the lock for this driver instance. 661 */ 662 static void 663 bge_ape_lock_init(struct bge_softc *sc) 664 { 665 uint32_t bit, regbase; 666 int i; 667 668 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 669 regbase = BGE_APE_LOCK_GRANT; 670 else 671 regbase = BGE_APE_PER_LOCK_GRANT; 672 673 /* Clear any stale locks. */ 674 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 675 switch (i) { 676 case BGE_APE_LOCK_PHY0: 677 case BGE_APE_LOCK_PHY1: 678 case BGE_APE_LOCK_PHY2: 679 case BGE_APE_LOCK_PHY3: 680 bit = BGE_APE_LOCK_GRANT_DRIVER0; 681 break; 682 default: 683 if (sc->bge_func_addr != 0) 684 bit = BGE_APE_LOCK_GRANT_DRIVER0; 685 else 686 bit = (1 << sc->bge_func_addr); 687 } 688 APE_WRITE_4(sc, regbase + 4 * i, bit); 689 } 690 691 /* Select the PHY lock based on the device's function number. */ 692 switch (sc->bge_func_addr) { 693 case 0: 694 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 695 break; 696 case 1: 697 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 698 break; 699 case 2: 700 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 701 break; 702 case 3: 703 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 704 break; 705 default: 706 device_printf(sc->bge_dev, 707 "PHY lock not supported on this function\n"); 708 } 709 } 710 711 /* 712 * Check for APE firmware, set flags, and print version info. 713 */ 714 static void 715 bge_ape_read_fw_ver(struct bge_softc *sc) 716 { 717 const char *fwtype; 718 uint32_t apedata, features; 719 720 /* Check for a valid APE signature in shared memory. */ 721 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 722 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 723 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 724 return; 725 } 726 727 /* Check if APE firmware is running. */ 728 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 729 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 730 device_printf(sc->bge_dev, "APE signature found " 731 "but FW status not ready! 0x%08x\n", apedata); 732 return; 733 } 734 735 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 736 737 /* Fetch the APE firwmare type and version. */ 738 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 739 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 740 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 741 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 742 fwtype = "NCSI"; 743 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 744 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 745 fwtype = "DASH"; 746 } else 747 fwtype = "UNKN"; 748 749 /* Print the APE firmware version. */ 750 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 751 fwtype, 752 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 753 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 754 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 755 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 756 } 757 758 static int 759 bge_ape_lock(struct bge_softc *sc, int locknum) 760 { 761 uint32_t bit, gnt, req, status; 762 int i, off; 763 764 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 765 return (0); 766 767 /* Lock request/grant registers have different bases. */ 768 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 769 req = BGE_APE_LOCK_REQ; 770 gnt = BGE_APE_LOCK_GRANT; 771 } else { 772 req = BGE_APE_PER_LOCK_REQ; 773 gnt = BGE_APE_PER_LOCK_GRANT; 774 } 775 776 off = 4 * locknum; 777 778 switch (locknum) { 779 case BGE_APE_LOCK_GPIO: 780 /* Lock required when using GPIO. */ 781 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 782 return (0); 783 if (sc->bge_func_addr == 0) 784 bit = BGE_APE_LOCK_REQ_DRIVER0; 785 else 786 bit = (1 << sc->bge_func_addr); 787 break; 788 case BGE_APE_LOCK_GRC: 789 /* Lock required to reset the device. */ 790 if (sc->bge_func_addr == 0) 791 bit = BGE_APE_LOCK_REQ_DRIVER0; 792 else 793 bit = (1 << sc->bge_func_addr); 794 break; 795 case BGE_APE_LOCK_MEM: 796 /* Lock required when accessing certain APE memory. */ 797 if (sc->bge_func_addr == 0) 798 bit = BGE_APE_LOCK_REQ_DRIVER0; 799 else 800 bit = (1 << sc->bge_func_addr); 801 break; 802 case BGE_APE_LOCK_PHY0: 803 case BGE_APE_LOCK_PHY1: 804 case BGE_APE_LOCK_PHY2: 805 case BGE_APE_LOCK_PHY3: 806 /* Lock required when accessing PHYs. */ 807 bit = BGE_APE_LOCK_REQ_DRIVER0; 808 break; 809 default: 810 return (EINVAL); 811 } 812 813 /* Request a lock. */ 814 APE_WRITE_4(sc, req + off, bit); 815 816 /* Wait up to 1 second to acquire lock. */ 817 for (i = 0; i < 20000; i++) { 818 status = APE_READ_4(sc, gnt + off); 819 if (status == bit) 820 break; 821 DELAY(50); 822 } 823 824 /* Handle any errors. */ 825 if (status != bit) { 826 device_printf(sc->bge_dev, "APE lock %d request failed! " 827 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 828 locknum, req + off, bit & 0xFFFF, gnt + off, 829 status & 0xFFFF); 830 /* Revoke the lock request. */ 831 APE_WRITE_4(sc, gnt + off, bit); 832 return (EBUSY); 833 } 834 835 return (0); 836 } 837 838 static void 839 bge_ape_unlock(struct bge_softc *sc, int locknum) 840 { 841 uint32_t bit, gnt; 842 int off; 843 844 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 845 return; 846 847 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 848 gnt = BGE_APE_LOCK_GRANT; 849 else 850 gnt = BGE_APE_PER_LOCK_GRANT; 851 852 off = 4 * locknum; 853 854 switch (locknum) { 855 case BGE_APE_LOCK_GPIO: 856 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 857 return; 858 if (sc->bge_func_addr == 0) 859 bit = BGE_APE_LOCK_GRANT_DRIVER0; 860 else 861 bit = (1 << sc->bge_func_addr); 862 break; 863 case BGE_APE_LOCK_GRC: 864 if (sc->bge_func_addr == 0) 865 bit = BGE_APE_LOCK_GRANT_DRIVER0; 866 else 867 bit = (1 << sc->bge_func_addr); 868 break; 869 case BGE_APE_LOCK_MEM: 870 if (sc->bge_func_addr == 0) 871 bit = BGE_APE_LOCK_GRANT_DRIVER0; 872 else 873 bit = (1 << sc->bge_func_addr); 874 break; 875 case BGE_APE_LOCK_PHY0: 876 case BGE_APE_LOCK_PHY1: 877 case BGE_APE_LOCK_PHY2: 878 case BGE_APE_LOCK_PHY3: 879 bit = BGE_APE_LOCK_GRANT_DRIVER0; 880 break; 881 default: 882 return; 883 } 884 885 APE_WRITE_4(sc, gnt + off, bit); 886 } 887 888 /* 889 * Send an event to the APE firmware. 890 */ 891 static void 892 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 893 { 894 uint32_t apedata; 895 int i; 896 897 /* NCSI does not support APE events. */ 898 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 899 return; 900 901 /* Wait up to 1ms for APE to service previous event. */ 902 for (i = 10; i > 0; i--) { 903 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 904 break; 905 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 906 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 907 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 908 BGE_APE_EVENT_STATUS_EVENT_PENDING); 909 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 910 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 911 break; 912 } 913 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 914 DELAY(100); 915 } 916 if (i == 0) 917 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 918 event); 919 } 920 921 static void 922 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 923 { 924 uint32_t apedata, event; 925 926 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 927 return; 928 929 switch (kind) { 930 case BGE_RESET_START: 931 /* If this is the first load, clear the load counter. */ 932 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 933 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 934 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 935 else { 936 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 937 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 938 } 939 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 940 BGE_APE_HOST_SEG_SIG_MAGIC); 941 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 942 BGE_APE_HOST_SEG_LEN_MAGIC); 943 944 /* Add some version info if bge(4) supports it. */ 945 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 946 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 947 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 948 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 949 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 950 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 951 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 952 BGE_APE_HOST_DRVR_STATE_START); 953 event = BGE_APE_EVENT_STATUS_STATE_START; 954 break; 955 case BGE_RESET_SHUTDOWN: 956 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 957 BGE_APE_HOST_DRVR_STATE_UNLOAD); 958 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 959 break; 960 case BGE_RESET_SUSPEND: 961 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 962 break; 963 default: 964 return; 965 } 966 967 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 968 BGE_APE_EVENT_STATUS_STATE_CHNGE); 969 } 970 971 /* 972 * Map a single buffer address. 973 */ 974 975 static void 976 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 977 { 978 struct bge_dmamap_arg *ctx; 979 980 if (error) 981 return; 982 983 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 984 985 ctx = arg; 986 ctx->bge_busaddr = segs->ds_addr; 987 } 988 989 static uint8_t 990 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 991 { 992 uint32_t access, byte = 0; 993 int i; 994 995 /* Lock. */ 996 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 997 for (i = 0; i < 8000; i++) { 998 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 999 break; 1000 DELAY(20); 1001 } 1002 if (i == 8000) 1003 return (1); 1004 1005 /* Enable access. */ 1006 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1007 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1008 1009 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1010 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1011 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1012 DELAY(10); 1013 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1014 DELAY(10); 1015 break; 1016 } 1017 } 1018 1019 if (i == BGE_TIMEOUT * 10) { 1020 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1021 return (1); 1022 } 1023 1024 /* Get result. */ 1025 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1026 1027 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1028 1029 /* Disable access. */ 1030 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1031 1032 /* Unlock. */ 1033 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1034 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1035 1036 return (0); 1037 } 1038 1039 /* 1040 * Read a sequence of bytes from NVRAM. 1041 */ 1042 static int 1043 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1044 { 1045 int err = 0, i; 1046 uint8_t byte = 0; 1047 1048 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1049 return (1); 1050 1051 for (i = 0; i < cnt; i++) { 1052 err = bge_nvram_getbyte(sc, off + i, &byte); 1053 if (err) 1054 break; 1055 *(dest + i) = byte; 1056 } 1057 1058 return (err ? 1 : 0); 1059 } 1060 1061 /* 1062 * Read a byte of data stored in the EEPROM at address 'addr.' The 1063 * BCM570x supports both the traditional bitbang interface and an 1064 * auto access interface for reading the EEPROM. We use the auto 1065 * access method. 1066 */ 1067 static uint8_t 1068 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1069 { 1070 int i; 1071 uint32_t byte = 0; 1072 1073 /* 1074 * Enable use of auto EEPROM access so we can avoid 1075 * having to use the bitbang method. 1076 */ 1077 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1078 1079 /* Reset the EEPROM, load the clock period. */ 1080 CSR_WRITE_4(sc, BGE_EE_ADDR, 1081 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1082 DELAY(20); 1083 1084 /* Issue the read EEPROM command. */ 1085 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1086 1087 /* Wait for completion */ 1088 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1089 DELAY(10); 1090 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1091 break; 1092 } 1093 1094 if (i == BGE_TIMEOUT * 10) { 1095 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1096 return (1); 1097 } 1098 1099 /* Get result. */ 1100 byte = CSR_READ_4(sc, BGE_EE_DATA); 1101 1102 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1103 1104 return (0); 1105 } 1106 1107 /* 1108 * Read a sequence of bytes from the EEPROM. 1109 */ 1110 static int 1111 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1112 { 1113 int i, error = 0; 1114 uint8_t byte = 0; 1115 1116 for (i = 0; i < cnt; i++) { 1117 error = bge_eeprom_getbyte(sc, off + i, &byte); 1118 if (error) 1119 break; 1120 *(dest + i) = byte; 1121 } 1122 1123 return (error ? 1 : 0); 1124 } 1125 1126 static int 1127 bge_miibus_readreg(device_t dev, int phy, int reg) 1128 { 1129 struct bge_softc *sc; 1130 uint32_t val; 1131 int i; 1132 1133 sc = device_get_softc(dev); 1134 1135 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1136 return (0); 1137 1138 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1139 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1140 CSR_WRITE_4(sc, BGE_MI_MODE, 1141 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1142 DELAY(80); 1143 } 1144 1145 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1146 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1147 1148 /* Poll for the PHY register access to complete. */ 1149 for (i = 0; i < BGE_TIMEOUT; i++) { 1150 DELAY(10); 1151 val = CSR_READ_4(sc, BGE_MI_COMM); 1152 if ((val & BGE_MICOMM_BUSY) == 0) { 1153 DELAY(5); 1154 val = CSR_READ_4(sc, BGE_MI_COMM); 1155 break; 1156 } 1157 } 1158 1159 if (i == BGE_TIMEOUT) { 1160 device_printf(sc->bge_dev, 1161 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1162 phy, reg, val); 1163 val = 0; 1164 } 1165 1166 /* Restore the autopoll bit if necessary. */ 1167 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1168 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1169 DELAY(80); 1170 } 1171 1172 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1173 1174 if (val & BGE_MICOMM_READFAIL) 1175 return (0); 1176 1177 return (val & 0xFFFF); 1178 } 1179 1180 static int 1181 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1182 { 1183 struct bge_softc *sc; 1184 int i; 1185 1186 sc = device_get_softc(dev); 1187 1188 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1189 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1190 return (0); 1191 1192 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1193 return (0); 1194 1195 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1196 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1197 CSR_WRITE_4(sc, BGE_MI_MODE, 1198 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1199 DELAY(80); 1200 } 1201 1202 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1203 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1204 1205 for (i = 0; i < BGE_TIMEOUT; i++) { 1206 DELAY(10); 1207 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1208 DELAY(5); 1209 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1210 break; 1211 } 1212 } 1213 1214 /* Restore the autopoll bit if necessary. */ 1215 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1216 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1217 DELAY(80); 1218 } 1219 1220 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1221 1222 if (i == BGE_TIMEOUT) 1223 device_printf(sc->bge_dev, 1224 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1225 phy, reg, val); 1226 1227 return (0); 1228 } 1229 1230 static void 1231 bge_miibus_statchg(device_t dev) 1232 { 1233 struct bge_softc *sc; 1234 struct mii_data *mii; 1235 uint32_t mac_mode, rx_mode, tx_mode; 1236 1237 sc = device_get_softc(dev); 1238 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1239 return; 1240 mii = device_get_softc(sc->bge_miibus); 1241 1242 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1243 (IFM_ACTIVE | IFM_AVALID)) { 1244 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1245 case IFM_10_T: 1246 case IFM_100_TX: 1247 sc->bge_link = 1; 1248 break; 1249 case IFM_1000_T: 1250 case IFM_1000_SX: 1251 case IFM_2500_SX: 1252 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1253 sc->bge_link = 1; 1254 else 1255 sc->bge_link = 0; 1256 break; 1257 default: 1258 sc->bge_link = 0; 1259 break; 1260 } 1261 } else 1262 sc->bge_link = 0; 1263 if (sc->bge_link == 0) 1264 return; 1265 1266 /* 1267 * APE firmware touches these registers to keep the MAC 1268 * connected to the outside world. Try to keep the 1269 * accesses atomic. 1270 */ 1271 1272 /* Set the port mode (MII/GMII) to match the link speed. */ 1273 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1274 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1275 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1276 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1277 1278 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1279 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1280 mac_mode |= BGE_PORTMODE_GMII; 1281 else 1282 mac_mode |= BGE_PORTMODE_MII; 1283 1284 /* Set MAC flow control behavior to match link flow control settings. */ 1285 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1286 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1287 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 1288 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1289 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1290 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1291 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1292 } else 1293 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1294 1295 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1296 DELAY(40); 1297 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1298 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1299 } 1300 1301 /* 1302 * Intialize a standard receive ring descriptor. 1303 */ 1304 static int 1305 bge_newbuf_std(struct bge_softc *sc, int i) 1306 { 1307 struct mbuf *m; 1308 struct bge_rx_bd *r; 1309 bus_dma_segment_t segs[1]; 1310 bus_dmamap_t map; 1311 int error, nsegs; 1312 1313 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1314 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1315 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1316 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1317 if (m == NULL) 1318 return (ENOBUFS); 1319 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1320 } else { 1321 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1322 if (m == NULL) 1323 return (ENOBUFS); 1324 m->m_len = m->m_pkthdr.len = MCLBYTES; 1325 } 1326 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1327 m_adj(m, ETHER_ALIGN); 1328 1329 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1330 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1331 if (error != 0) { 1332 m_freem(m); 1333 return (error); 1334 } 1335 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1336 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1337 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1338 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1339 sc->bge_cdata.bge_rx_std_dmamap[i]); 1340 } 1341 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1342 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1343 sc->bge_cdata.bge_rx_std_sparemap = map; 1344 sc->bge_cdata.bge_rx_std_chain[i] = m; 1345 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1346 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1347 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1348 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1349 r->bge_flags = BGE_RXBDFLAG_END; 1350 r->bge_len = segs[0].ds_len; 1351 r->bge_idx = i; 1352 1353 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1354 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1355 1356 return (0); 1357 } 1358 1359 /* 1360 * Initialize a jumbo receive ring descriptor. This allocates 1361 * a jumbo buffer from the pool managed internally by the driver. 1362 */ 1363 static int 1364 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1365 { 1366 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1367 bus_dmamap_t map; 1368 struct bge_extrx_bd *r; 1369 struct mbuf *m; 1370 int error, nsegs; 1371 1372 MGETHDR(m, M_NOWAIT, MT_DATA); 1373 if (m == NULL) 1374 return (ENOBUFS); 1375 1376 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1377 if (!(m->m_flags & M_EXT)) { 1378 m_freem(m); 1379 return (ENOBUFS); 1380 } 1381 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1382 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1383 m_adj(m, ETHER_ALIGN); 1384 1385 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1386 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1387 if (error != 0) { 1388 m_freem(m); 1389 return (error); 1390 } 1391 1392 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1393 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1394 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1395 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1396 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1397 } 1398 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1399 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1400 sc->bge_cdata.bge_rx_jumbo_sparemap; 1401 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1402 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1403 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1404 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1405 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1406 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1407 1408 /* 1409 * Fill in the extended RX buffer descriptor. 1410 */ 1411 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1412 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1413 r->bge_idx = i; 1414 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1415 switch (nsegs) { 1416 case 4: 1417 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1418 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1419 r->bge_len3 = segs[3].ds_len; 1420 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1421 case 3: 1422 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1423 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1424 r->bge_len2 = segs[2].ds_len; 1425 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1426 case 2: 1427 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1428 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1429 r->bge_len1 = segs[1].ds_len; 1430 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1431 case 1: 1432 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1433 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1434 r->bge_len0 = segs[0].ds_len; 1435 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1436 break; 1437 default: 1438 panic("%s: %d segments\n", __func__, nsegs); 1439 } 1440 1441 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1442 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1443 1444 return (0); 1445 } 1446 1447 static int 1448 bge_init_rx_ring_std(struct bge_softc *sc) 1449 { 1450 int error, i; 1451 1452 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1453 sc->bge_std = 0; 1454 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1455 if ((error = bge_newbuf_std(sc, i)) != 0) 1456 return (error); 1457 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1458 } 1459 1460 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1461 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1462 1463 sc->bge_std = 0; 1464 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1465 1466 return (0); 1467 } 1468 1469 static void 1470 bge_free_rx_ring_std(struct bge_softc *sc) 1471 { 1472 int i; 1473 1474 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1475 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1476 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1477 sc->bge_cdata.bge_rx_std_dmamap[i], 1478 BUS_DMASYNC_POSTREAD); 1479 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1480 sc->bge_cdata.bge_rx_std_dmamap[i]); 1481 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1482 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1483 } 1484 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1485 sizeof(struct bge_rx_bd)); 1486 } 1487 } 1488 1489 static int 1490 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1491 { 1492 struct bge_rcb *rcb; 1493 int error, i; 1494 1495 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1496 sc->bge_jumbo = 0; 1497 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1498 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1499 return (error); 1500 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1501 } 1502 1503 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1504 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1505 1506 sc->bge_jumbo = 0; 1507 1508 /* Enable the jumbo receive producer ring. */ 1509 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1510 rcb->bge_maxlen_flags = 1511 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1512 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1513 1514 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1515 1516 return (0); 1517 } 1518 1519 static void 1520 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1521 { 1522 int i; 1523 1524 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1525 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1526 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1527 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1528 BUS_DMASYNC_POSTREAD); 1529 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1530 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1531 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1532 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1533 } 1534 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1535 sizeof(struct bge_extrx_bd)); 1536 } 1537 } 1538 1539 static void 1540 bge_free_tx_ring(struct bge_softc *sc) 1541 { 1542 int i; 1543 1544 if (sc->bge_ldata.bge_tx_ring == NULL) 1545 return; 1546 1547 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1548 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1549 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1550 sc->bge_cdata.bge_tx_dmamap[i], 1551 BUS_DMASYNC_POSTWRITE); 1552 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1553 sc->bge_cdata.bge_tx_dmamap[i]); 1554 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1555 sc->bge_cdata.bge_tx_chain[i] = NULL; 1556 } 1557 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1558 sizeof(struct bge_tx_bd)); 1559 } 1560 } 1561 1562 static int 1563 bge_init_tx_ring(struct bge_softc *sc) 1564 { 1565 sc->bge_txcnt = 0; 1566 sc->bge_tx_saved_considx = 0; 1567 1568 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1569 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1570 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1571 1572 /* Initialize transmit producer index for host-memory send ring. */ 1573 sc->bge_tx_prodidx = 0; 1574 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1575 1576 /* 5700 b2 errata */ 1577 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1578 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1579 1580 /* NIC-memory send ring not used; initialize to zero. */ 1581 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1582 /* 5700 b2 errata */ 1583 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1584 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1585 1586 return (0); 1587 } 1588 1589 static void 1590 bge_setpromisc(struct bge_softc *sc) 1591 { 1592 struct ifnet *ifp; 1593 1594 BGE_LOCK_ASSERT(sc); 1595 1596 ifp = sc->bge_ifp; 1597 1598 /* Enable or disable promiscuous mode as needed. */ 1599 if (ifp->if_flags & IFF_PROMISC) 1600 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1601 else 1602 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1603 } 1604 1605 static void 1606 bge_setmulti(struct bge_softc *sc) 1607 { 1608 struct ifnet *ifp; 1609 struct ifmultiaddr *ifma; 1610 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1611 int h, i; 1612 1613 BGE_LOCK_ASSERT(sc); 1614 1615 ifp = sc->bge_ifp; 1616 1617 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1618 for (i = 0; i < 4; i++) 1619 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1620 return; 1621 } 1622 1623 /* First, zot all the existing filters. */ 1624 for (i = 0; i < 4; i++) 1625 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1626 1627 /* Now program new ones. */ 1628 if_maddr_rlock(ifp); 1629 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1630 if (ifma->ifma_addr->sa_family != AF_LINK) 1631 continue; 1632 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1633 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1634 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1635 } 1636 if_maddr_runlock(ifp); 1637 1638 for (i = 0; i < 4; i++) 1639 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1640 } 1641 1642 static void 1643 bge_setvlan(struct bge_softc *sc) 1644 { 1645 struct ifnet *ifp; 1646 1647 BGE_LOCK_ASSERT(sc); 1648 1649 ifp = sc->bge_ifp; 1650 1651 /* Enable or disable VLAN tag stripping as needed. */ 1652 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1653 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1654 else 1655 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1656 } 1657 1658 static void 1659 bge_sig_pre_reset(struct bge_softc *sc, int type) 1660 { 1661 1662 /* 1663 * Some chips don't like this so only do this if ASF is enabled 1664 */ 1665 if (sc->bge_asf_mode) 1666 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1667 1668 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1669 switch (type) { 1670 case BGE_RESET_START: 1671 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1672 BGE_FW_DRV_STATE_START); 1673 break; 1674 case BGE_RESET_SHUTDOWN: 1675 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1676 BGE_FW_DRV_STATE_UNLOAD); 1677 break; 1678 case BGE_RESET_SUSPEND: 1679 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1680 BGE_FW_DRV_STATE_SUSPEND); 1681 break; 1682 } 1683 } 1684 1685 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1686 bge_ape_driver_state_change(sc, type); 1687 } 1688 1689 static void 1690 bge_sig_post_reset(struct bge_softc *sc, int type) 1691 { 1692 1693 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1694 switch (type) { 1695 case BGE_RESET_START: 1696 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1697 BGE_FW_DRV_STATE_START_DONE); 1698 /* START DONE */ 1699 break; 1700 case BGE_RESET_SHUTDOWN: 1701 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1702 BGE_FW_DRV_STATE_UNLOAD_DONE); 1703 break; 1704 } 1705 } 1706 if (type == BGE_RESET_SHUTDOWN) 1707 bge_ape_driver_state_change(sc, type); 1708 } 1709 1710 static void 1711 bge_sig_legacy(struct bge_softc *sc, int type) 1712 { 1713 1714 if (sc->bge_asf_mode) { 1715 switch (type) { 1716 case BGE_RESET_START: 1717 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1718 BGE_FW_DRV_STATE_START); 1719 break; 1720 case BGE_RESET_SHUTDOWN: 1721 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1722 BGE_FW_DRV_STATE_UNLOAD); 1723 break; 1724 } 1725 } 1726 } 1727 1728 static void 1729 bge_stop_fw(struct bge_softc *sc) 1730 { 1731 int i; 1732 1733 if (sc->bge_asf_mode) { 1734 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1735 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1736 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1737 1738 for (i = 0; i < 100; i++ ) { 1739 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1740 BGE_RX_CPU_DRV_EVENT)) 1741 break; 1742 DELAY(10); 1743 } 1744 } 1745 } 1746 1747 static uint32_t 1748 bge_dma_swap_options(struct bge_softc *sc) 1749 { 1750 uint32_t dma_options; 1751 1752 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1753 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1754 #if BYTE_ORDER == BIG_ENDIAN 1755 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1756 #endif 1757 return (dma_options); 1758 } 1759 1760 /* 1761 * Do endian, PCI and DMA initialization. 1762 */ 1763 static int 1764 bge_chipinit(struct bge_softc *sc) 1765 { 1766 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1767 uint16_t val; 1768 int i; 1769 1770 /* Set endianness before we access any non-PCI registers. */ 1771 misc_ctl = BGE_INIT; 1772 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1773 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1774 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1775 1776 /* 1777 * Clear the MAC statistics block in the NIC's 1778 * internal memory. 1779 */ 1780 for (i = BGE_STATS_BLOCK; 1781 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1782 BGE_MEMWIN_WRITE(sc, i, 0); 1783 1784 for (i = BGE_STATUS_BLOCK; 1785 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1786 BGE_MEMWIN_WRITE(sc, i, 0); 1787 1788 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1789 /* 1790 * Fix data corruption caused by non-qword write with WB. 1791 * Fix master abort in PCI mode. 1792 * Fix PCI latency timer. 1793 */ 1794 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1795 val |= (1 << 10) | (1 << 12) | (1 << 13); 1796 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1797 } 1798 1799 /* 1800 * Set up the PCI DMA control register. 1801 */ 1802 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1803 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1804 if (sc->bge_flags & BGE_FLAG_PCIE) { 1805 if (sc->bge_mps >= 256) 1806 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1807 else 1808 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1809 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1810 if (BGE_IS_5714_FAMILY(sc)) { 1811 /* 256 bytes for read and write. */ 1812 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1813 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1814 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1815 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1816 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1817 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1818 /* 1819 * In the BCM5703, the DMA read watermark should 1820 * be set to less than or equal to the maximum 1821 * memory read byte count of the PCI-X command 1822 * register. 1823 */ 1824 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1825 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1826 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1827 /* 1536 bytes for read, 384 bytes for write. */ 1828 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1829 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1830 } else { 1831 /* 384 bytes for read and write. */ 1832 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1833 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1834 0x0F; 1835 } 1836 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1837 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1838 uint32_t tmp; 1839 1840 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1841 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1842 if (tmp == 6 || tmp == 7) 1843 dma_rw_ctl |= 1844 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1845 1846 /* Set PCI-X DMA write workaround. */ 1847 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1848 } 1849 } else { 1850 /* Conventional PCI bus: 256 bytes for read and write. */ 1851 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1852 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1853 1854 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1855 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1856 dma_rw_ctl |= 0x0F; 1857 } 1858 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1859 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1860 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1861 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1862 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1863 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1864 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1865 if (BGE_IS_5717_PLUS(sc)) { 1866 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1867 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1868 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1869 /* 1870 * Enable HW workaround for controllers that misinterpret 1871 * a status tag update and leave interrupts permanently 1872 * disabled. 1873 */ 1874 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1875 sc->bge_asicrev != BGE_ASICREV_BCM57765) 1876 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1877 } 1878 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1879 1880 /* 1881 * Set up general mode register. 1882 */ 1883 mode_ctl = bge_dma_swap_options(sc); 1884 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 1885 /* Retain Host-2-BMC settings written by APE firmware. */ 1886 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1887 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1888 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1889 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1890 } 1891 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1892 BGE_MODECTL_TX_NO_PHDR_CSUM; 1893 1894 /* 1895 * BCM5701 B5 have a bug causing data corruption when using 1896 * 64-bit DMA reads, which can be terminated early and then 1897 * completed later as 32-bit accesses, in combination with 1898 * certain bridges. 1899 */ 1900 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1901 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1902 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1903 1904 /* 1905 * Tell the firmware the driver is running 1906 */ 1907 if (sc->bge_asf_mode & ASF_STACKUP) 1908 mode_ctl |= BGE_MODECTL_STACKUP; 1909 1910 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1911 1912 /* 1913 * Disable memory write invalidate. Apparently it is not supported 1914 * properly by these devices. Also ensure that INTx isn't disabled, 1915 * as these chips need it even when using MSI. 1916 */ 1917 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1918 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1919 1920 /* Set the timer prescaler (always 66 MHz). */ 1921 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1922 1923 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1924 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1925 DELAY(40); /* XXX */ 1926 1927 /* Put PHY into ready state */ 1928 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1929 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1930 DELAY(40); 1931 } 1932 1933 return (0); 1934 } 1935 1936 static int 1937 bge_blockinit(struct bge_softc *sc) 1938 { 1939 struct bge_rcb *rcb; 1940 bus_size_t vrcb; 1941 bge_hostaddr taddr; 1942 uint32_t dmactl, val; 1943 int i, limit; 1944 1945 /* 1946 * Initialize the memory window pointer register so that 1947 * we can access the first 32K of internal NIC RAM. This will 1948 * allow us to set up the TX send ring RCBs and the RX return 1949 * ring RCBs, plus other things which live in NIC memory. 1950 */ 1951 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1952 1953 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1954 1955 if (!(BGE_IS_5705_PLUS(sc))) { 1956 /* Configure mbuf memory pool */ 1957 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1958 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1959 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1960 else 1961 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1962 1963 /* Configure DMA resource pool */ 1964 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1965 BGE_DMA_DESCRIPTORS); 1966 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1967 } 1968 1969 /* Configure mbuf pool watermarks */ 1970 if (BGE_IS_5717_PLUS(sc)) { 1971 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1972 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1973 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1974 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1975 } else { 1976 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1977 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1978 } 1979 } else if (!BGE_IS_5705_PLUS(sc)) { 1980 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1981 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1982 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1983 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1985 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1986 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1987 } else { 1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1989 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1990 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1991 } 1992 1993 /* Configure DMA resource watermarks */ 1994 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1995 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1996 1997 /* Enable buffer manager */ 1998 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1999 /* 2000 * Change the arbitration algorithm of TXMBUF read request to 2001 * round-robin instead of priority based for BCM5719. When 2002 * TXFIFO is almost empty, RDMA will hold its request until 2003 * TXFIFO is not almost empty. 2004 */ 2005 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2006 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2007 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2008 2009 /* Poll for buffer manager start indication */ 2010 for (i = 0; i < BGE_TIMEOUT; i++) { 2011 DELAY(10); 2012 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2013 break; 2014 } 2015 2016 if (i == BGE_TIMEOUT) { 2017 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2018 return (ENXIO); 2019 } 2020 2021 /* Enable flow-through queues */ 2022 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2024 2025 /* Wait until queue initialization is complete */ 2026 for (i = 0; i < BGE_TIMEOUT; i++) { 2027 DELAY(10); 2028 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2029 break; 2030 } 2031 2032 if (i == BGE_TIMEOUT) { 2033 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2034 return (ENXIO); 2035 } 2036 2037 /* 2038 * Summary of rings supported by the controller: 2039 * 2040 * Standard Receive Producer Ring 2041 * - This ring is used to feed receive buffers for "standard" 2042 * sized frames (typically 1536 bytes) to the controller. 2043 * 2044 * Jumbo Receive Producer Ring 2045 * - This ring is used to feed receive buffers for jumbo sized 2046 * frames (i.e. anything bigger than the "standard" frames) 2047 * to the controller. 2048 * 2049 * Mini Receive Producer Ring 2050 * - This ring is used to feed receive buffers for "mini" 2051 * sized frames to the controller. 2052 * - This feature required external memory for the controller 2053 * but was never used in a production system. Should always 2054 * be disabled. 2055 * 2056 * Receive Return Ring 2057 * - After the controller has placed an incoming frame into a 2058 * receive buffer that buffer is moved into a receive return 2059 * ring. The driver is then responsible to passing the 2060 * buffer up to the stack. Many versions of the controller 2061 * support multiple RR rings. 2062 * 2063 * Send Ring 2064 * - This ring is used for outgoing frames. Many versions of 2065 * the controller support multiple send rings. 2066 */ 2067 2068 /* Initialize the standard receive producer ring control block. */ 2069 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2070 rcb->bge_hostaddr.bge_addr_lo = 2071 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2072 rcb->bge_hostaddr.bge_addr_hi = 2073 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2074 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2075 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2076 if (BGE_IS_5717_PLUS(sc)) { 2077 /* 2078 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2079 * Bits 15-2 : Maximum RX frame size 2080 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2081 * Bit 0 : Reserved 2082 */ 2083 rcb->bge_maxlen_flags = 2084 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2085 } else if (BGE_IS_5705_PLUS(sc)) { 2086 /* 2087 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2088 * Bits 15-2 : Reserved (should be 0) 2089 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2090 * Bit 0 : Reserved 2091 */ 2092 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2093 } else { 2094 /* 2095 * Ring size is always XXX entries 2096 * Bits 31-16: Maximum RX frame size 2097 * Bits 15-2 : Reserved (should be 0) 2098 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2099 * Bit 0 : Reserved 2100 */ 2101 rcb->bge_maxlen_flags = 2102 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2103 } 2104 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2105 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2106 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2107 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2108 else 2109 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2110 /* Write the standard receive producer ring control block. */ 2111 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2112 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2113 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2114 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2115 2116 /* Reset the standard receive producer ring producer index. */ 2117 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2118 2119 /* 2120 * Initialize the jumbo RX producer ring control 2121 * block. We set the 'ring disabled' bit in the 2122 * flags field until we're actually ready to start 2123 * using this ring (i.e. once we set the MTU 2124 * high enough to require it). 2125 */ 2126 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2127 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2128 /* Get the jumbo receive producer ring RCB parameters. */ 2129 rcb->bge_hostaddr.bge_addr_lo = 2130 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2131 rcb->bge_hostaddr.bge_addr_hi = 2132 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2133 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2134 sc->bge_cdata.bge_rx_jumbo_ring_map, 2135 BUS_DMASYNC_PREREAD); 2136 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2137 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2138 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2139 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2140 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2141 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2142 else 2143 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2144 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2145 rcb->bge_hostaddr.bge_addr_hi); 2146 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2147 rcb->bge_hostaddr.bge_addr_lo); 2148 /* Program the jumbo receive producer ring RCB parameters. */ 2149 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2150 rcb->bge_maxlen_flags); 2151 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2152 /* Reset the jumbo receive producer ring producer index. */ 2153 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2154 } 2155 2156 /* Disable the mini receive producer ring RCB. */ 2157 if (BGE_IS_5700_FAMILY(sc)) { 2158 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2159 rcb->bge_maxlen_flags = 2160 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2161 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2162 rcb->bge_maxlen_flags); 2163 /* Reset the mini receive producer ring producer index. */ 2164 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2165 } 2166 2167 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2168 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2169 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2170 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2171 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2172 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2173 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2174 } 2175 /* 2176 * The BD ring replenish thresholds control how often the 2177 * hardware fetches new BD's from the producer rings in host 2178 * memory. Setting the value too low on a busy system can 2179 * starve the hardware and recue the throughpout. 2180 * 2181 * Set the BD ring replentish thresholds. The recommended 2182 * values are 1/8th the number of descriptors allocated to 2183 * each ring. 2184 * XXX The 5754 requires a lower threshold, so it might be a 2185 * requirement of all 575x family chips. The Linux driver sets 2186 * the lower threshold for all 5705 family chips as well, but there 2187 * are reports that it might not need to be so strict. 2188 * 2189 * XXX Linux does some extra fiddling here for the 5906 parts as 2190 * well. 2191 */ 2192 if (BGE_IS_5705_PLUS(sc)) 2193 val = 8; 2194 else 2195 val = BGE_STD_RX_RING_CNT / 8; 2196 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2197 if (BGE_IS_JUMBO_CAPABLE(sc)) 2198 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2199 BGE_JUMBO_RX_RING_CNT/8); 2200 if (BGE_IS_5717_PLUS(sc)) { 2201 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2202 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2203 } 2204 2205 /* 2206 * Disable all send rings by setting the 'ring disabled' bit 2207 * in the flags field of all the TX send ring control blocks, 2208 * located in NIC memory. 2209 */ 2210 if (!BGE_IS_5705_PLUS(sc)) 2211 /* 5700 to 5704 had 16 send rings. */ 2212 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2213 else 2214 limit = 1; 2215 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2216 for (i = 0; i < limit; i++) { 2217 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2218 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2219 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2220 vrcb += sizeof(struct bge_rcb); 2221 } 2222 2223 /* Configure send ring RCB 0 (we use only the first ring) */ 2224 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2225 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2226 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2227 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2228 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2229 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2230 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2231 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2232 else 2233 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2234 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2235 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2236 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2237 2238 /* 2239 * Disable all receive return rings by setting the 2240 * 'ring diabled' bit in the flags field of all the receive 2241 * return ring control blocks, located in NIC memory. 2242 */ 2243 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2244 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2245 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2246 /* Should be 17, use 16 until we get an SRAM map. */ 2247 limit = 16; 2248 } else if (!BGE_IS_5705_PLUS(sc)) 2249 limit = BGE_RX_RINGS_MAX; 2250 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2251 BGE_IS_57765_PLUS(sc)) 2252 limit = 4; 2253 else 2254 limit = 1; 2255 /* Disable all receive return rings. */ 2256 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2257 for (i = 0; i < limit; i++) { 2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2259 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2260 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2261 BGE_RCB_FLAG_RING_DISABLED); 2262 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2263 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2264 (i * (sizeof(uint64_t))), 0); 2265 vrcb += sizeof(struct bge_rcb); 2266 } 2267 2268 /* 2269 * Set up receive return ring 0. Note that the NIC address 2270 * for RX return rings is 0x0. The return rings live entirely 2271 * within the host, so the nicaddr field in the RCB isn't used. 2272 */ 2273 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2274 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2275 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2276 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2277 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2278 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2279 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2280 2281 /* Set random backoff seed for TX */ 2282 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2283 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2284 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2285 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 2286 BGE_TX_BACKOFF_SEED_MASK); 2287 2288 /* Set inter-packet gap */ 2289 val = 0x2620; 2290 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 2291 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2292 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2293 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2294 2295 /* 2296 * Specify which ring to use for packets that don't match 2297 * any RX rules. 2298 */ 2299 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2300 2301 /* 2302 * Configure number of RX lists. One interrupt distribution 2303 * list, sixteen active lists, one bad frames class. 2304 */ 2305 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2306 2307 /* Inialize RX list placement stats mask. */ 2308 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2309 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2310 2311 /* Disable host coalescing until we get it set up */ 2312 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2313 2314 /* Poll to make sure it's shut down. */ 2315 for (i = 0; i < BGE_TIMEOUT; i++) { 2316 DELAY(10); 2317 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2318 break; 2319 } 2320 2321 if (i == BGE_TIMEOUT) { 2322 device_printf(sc->bge_dev, 2323 "host coalescing engine failed to idle\n"); 2324 return (ENXIO); 2325 } 2326 2327 /* Set up host coalescing defaults */ 2328 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2329 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2330 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2331 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2332 if (!(BGE_IS_5705_PLUS(sc))) { 2333 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2334 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2335 } 2336 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2337 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2338 2339 /* Set up address of statistics block */ 2340 if (!(BGE_IS_5705_PLUS(sc))) { 2341 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2342 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2343 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2344 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2345 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2346 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2347 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2348 } 2349 2350 /* Set up address of status block */ 2351 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2352 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2353 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2354 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2355 2356 /* Set up status block size. */ 2357 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2358 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2359 val = BGE_STATBLKSZ_FULL; 2360 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2361 } else { 2362 val = BGE_STATBLKSZ_32BYTE; 2363 bzero(sc->bge_ldata.bge_status_block, 32); 2364 } 2365 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2366 sc->bge_cdata.bge_status_map, 2367 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2368 2369 /* Turn on host coalescing state machine */ 2370 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2371 2372 /* Turn on RX BD completion state machine and enable attentions */ 2373 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2374 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2375 2376 /* Turn on RX list placement state machine */ 2377 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2378 2379 /* Turn on RX list selector state machine. */ 2380 if (!(BGE_IS_5705_PLUS(sc))) 2381 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2382 2383 /* Turn on DMA, clear stats. */ 2384 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2385 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2386 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2387 BGE_MACMODE_FRMHDR_DMA_ENB; 2388 2389 if (sc->bge_flags & BGE_FLAG_TBI) 2390 val |= BGE_PORTMODE_TBI; 2391 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2392 val |= BGE_PORTMODE_GMII; 2393 else 2394 val |= BGE_PORTMODE_MII; 2395 2396 /* Allow APE to send/receive frames. */ 2397 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2398 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2399 2400 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2401 DELAY(40); 2402 2403 /* Set misc. local control, enable interrupts on attentions */ 2404 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2405 2406 #ifdef notdef 2407 /* Assert GPIO pins for PHY reset */ 2408 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2409 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2410 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2411 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2412 #endif 2413 2414 /* Turn on DMA completion state machine */ 2415 if (!(BGE_IS_5705_PLUS(sc))) 2416 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2417 2418 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2419 2420 /* Enable host coalescing bug fix. */ 2421 if (BGE_IS_5755_PLUS(sc)) 2422 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2423 2424 /* Request larger DMA burst size to get better performance. */ 2425 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2426 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2427 2428 /* Turn on write DMA state machine */ 2429 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2430 DELAY(40); 2431 2432 /* Turn on read DMA state machine */ 2433 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2434 2435 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2436 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2437 2438 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2439 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2440 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2441 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2442 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2443 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2444 if (sc->bge_flags & BGE_FLAG_PCIE) 2445 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2446 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2447 val |= BGE_RDMAMODE_TSO4_ENABLE; 2448 if (sc->bge_flags & BGE_FLAG_TSO3 || 2449 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2450 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2451 val |= BGE_RDMAMODE_TSO6_ENABLE; 2452 } 2453 2454 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2455 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2456 BGE_RDMAMODE_H2BNC_VLAN_DET; 2457 /* 2458 * Allow multiple outstanding read requests from 2459 * non-LSO read DMA engine. 2460 */ 2461 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2462 } 2463 2464 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2465 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2466 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2467 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2468 BGE_IS_5717_PLUS(sc)) { 2469 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2470 /* 2471 * Adjust tx margin to prevent TX data corruption and 2472 * fix internal FIFO overflow. 2473 */ 2474 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 2475 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2476 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2477 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2478 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2479 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2480 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2481 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2482 } 2483 /* 2484 * Enable fix for read DMA FIFO overruns. 2485 * The fix is to limit the number of RX BDs 2486 * the hardware would fetch at a fime. 2487 */ 2488 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2489 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2490 } 2491 2492 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2493 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2494 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2495 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2496 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2497 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2498 /* 2499 * Allow 4KB burst length reads for non-LSO frames. 2500 * Enable 512B burst length reads for buffer descriptors. 2501 */ 2502 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2503 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2504 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2505 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2506 } 2507 2508 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2509 DELAY(40); 2510 2511 /* Turn on RX data completion state machine */ 2512 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2513 2514 /* Turn on RX BD initiator state machine */ 2515 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2516 2517 /* Turn on RX data and RX BD initiator state machine */ 2518 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2519 2520 /* Turn on Mbuf cluster free state machine */ 2521 if (!(BGE_IS_5705_PLUS(sc))) 2522 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2523 2524 /* Turn on send BD completion state machine */ 2525 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2526 2527 /* Turn on send data completion state machine */ 2528 val = BGE_SDCMODE_ENABLE; 2529 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2530 val |= BGE_SDCMODE_CDELAY; 2531 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2532 2533 /* Turn on send data initiator state machine */ 2534 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2535 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2536 BGE_SDIMODE_HW_LSO_PRE_DMA); 2537 else 2538 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2539 2540 /* Turn on send BD initiator state machine */ 2541 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2542 2543 /* Turn on send BD selector state machine */ 2544 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2545 2546 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2547 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2548 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2549 2550 /* ack/clear link change events */ 2551 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2552 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2553 BGE_MACSTAT_LINK_CHANGED); 2554 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2555 2556 /* 2557 * Enable attention when the link has changed state for 2558 * devices that use auto polling. 2559 */ 2560 if (sc->bge_flags & BGE_FLAG_TBI) { 2561 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2562 } else { 2563 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2564 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2565 DELAY(80); 2566 } 2567 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2568 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2569 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2570 BGE_EVTENB_MI_INTERRUPT); 2571 } 2572 2573 /* 2574 * Clear any pending link state attention. 2575 * Otherwise some link state change events may be lost until attention 2576 * is cleared by bge_intr() -> bge_link_upd() sequence. 2577 * It's not necessary on newer BCM chips - perhaps enabling link 2578 * state change attentions implies clearing pending attention. 2579 */ 2580 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2581 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2582 BGE_MACSTAT_LINK_CHANGED); 2583 2584 /* Enable link state change attentions. */ 2585 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2586 2587 return (0); 2588 } 2589 2590 static const struct bge_revision * 2591 bge_lookup_rev(uint32_t chipid) 2592 { 2593 const struct bge_revision *br; 2594 2595 for (br = bge_revisions; br->br_name != NULL; br++) { 2596 if (br->br_chipid == chipid) 2597 return (br); 2598 } 2599 2600 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2601 if (br->br_chipid == BGE_ASICREV(chipid)) 2602 return (br); 2603 } 2604 2605 return (NULL); 2606 } 2607 2608 static const struct bge_vendor * 2609 bge_lookup_vendor(uint16_t vid) 2610 { 2611 const struct bge_vendor *v; 2612 2613 for (v = bge_vendors; v->v_name != NULL; v++) 2614 if (v->v_id == vid) 2615 return (v); 2616 2617 return (NULL); 2618 } 2619 2620 static uint32_t 2621 bge_chipid(device_t dev) 2622 { 2623 uint32_t id; 2624 2625 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2626 BGE_PCIMISCCTL_ASICREV_SHIFT; 2627 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2628 /* 2629 * Find the ASCI revision. Different chips use different 2630 * registers. 2631 */ 2632 switch (pci_get_device(dev)) { 2633 case BCOM_DEVICEID_BCM5717: 2634 case BCOM_DEVICEID_BCM5718: 2635 case BCOM_DEVICEID_BCM5719: 2636 case BCOM_DEVICEID_BCM5720: 2637 id = pci_read_config(dev, 2638 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2639 break; 2640 case BCOM_DEVICEID_BCM57761: 2641 case BCOM_DEVICEID_BCM57762: 2642 case BCOM_DEVICEID_BCM57765: 2643 case BCOM_DEVICEID_BCM57766: 2644 case BCOM_DEVICEID_BCM57781: 2645 case BCOM_DEVICEID_BCM57785: 2646 case BCOM_DEVICEID_BCM57791: 2647 case BCOM_DEVICEID_BCM57795: 2648 id = pci_read_config(dev, 2649 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2650 break; 2651 default: 2652 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2653 } 2654 } 2655 return (id); 2656 } 2657 2658 /* 2659 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2660 * against our list and return its name if we find a match. 2661 * 2662 * Note that since the Broadcom controller contains VPD support, we 2663 * try to get the device name string from the controller itself instead 2664 * of the compiled-in string. It guarantees we'll always announce the 2665 * right product name. We fall back to the compiled-in string when 2666 * VPD is unavailable or corrupt. 2667 */ 2668 static int 2669 bge_probe(device_t dev) 2670 { 2671 char buf[96]; 2672 char model[64]; 2673 const struct bge_revision *br; 2674 const char *pname; 2675 struct bge_softc *sc; 2676 const struct bge_type *t = bge_devs; 2677 const struct bge_vendor *v; 2678 uint32_t id; 2679 uint16_t did, vid; 2680 2681 sc = device_get_softc(dev); 2682 sc->bge_dev = dev; 2683 vid = pci_get_vendor(dev); 2684 did = pci_get_device(dev); 2685 while(t->bge_vid != 0) { 2686 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2687 id = bge_chipid(dev); 2688 br = bge_lookup_rev(id); 2689 if (bge_has_eaddr(sc) && 2690 pci_get_vpd_ident(dev, &pname) == 0) 2691 snprintf(model, sizeof(model), "%s", pname); 2692 else { 2693 v = bge_lookup_vendor(vid); 2694 snprintf(model, sizeof(model), "%s %s", 2695 v != NULL ? v->v_name : "Unknown", 2696 br != NULL ? br->br_name : 2697 "NetXtreme/NetLink Ethernet Controller"); 2698 } 2699 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2700 model, br != NULL ? "" : "unknown ", id); 2701 device_set_desc_copy(dev, buf); 2702 return (BUS_PROBE_DEFAULT); 2703 } 2704 t++; 2705 } 2706 2707 return (ENXIO); 2708 } 2709 2710 static void 2711 bge_dma_free(struct bge_softc *sc) 2712 { 2713 int i; 2714 2715 /* Destroy DMA maps for RX buffers. */ 2716 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2717 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2718 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2719 sc->bge_cdata.bge_rx_std_dmamap[i]); 2720 } 2721 if (sc->bge_cdata.bge_rx_std_sparemap) 2722 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2723 sc->bge_cdata.bge_rx_std_sparemap); 2724 2725 /* Destroy DMA maps for jumbo RX buffers. */ 2726 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2727 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2728 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2729 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2730 } 2731 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2732 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2733 sc->bge_cdata.bge_rx_jumbo_sparemap); 2734 2735 /* Destroy DMA maps for TX buffers. */ 2736 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2737 if (sc->bge_cdata.bge_tx_dmamap[i]) 2738 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2739 sc->bge_cdata.bge_tx_dmamap[i]); 2740 } 2741 2742 if (sc->bge_cdata.bge_rx_mtag) 2743 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2744 if (sc->bge_cdata.bge_mtag_jumbo) 2745 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2746 if (sc->bge_cdata.bge_tx_mtag) 2747 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2748 2749 /* Destroy standard RX ring. */ 2750 if (sc->bge_cdata.bge_rx_std_ring_map) 2751 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2752 sc->bge_cdata.bge_rx_std_ring_map); 2753 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2754 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2755 sc->bge_ldata.bge_rx_std_ring, 2756 sc->bge_cdata.bge_rx_std_ring_map); 2757 2758 if (sc->bge_cdata.bge_rx_std_ring_tag) 2759 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2760 2761 /* Destroy jumbo RX ring. */ 2762 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2763 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2764 sc->bge_cdata.bge_rx_jumbo_ring_map); 2765 2766 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2767 sc->bge_ldata.bge_rx_jumbo_ring) 2768 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2769 sc->bge_ldata.bge_rx_jumbo_ring, 2770 sc->bge_cdata.bge_rx_jumbo_ring_map); 2771 2772 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2773 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2774 2775 /* Destroy RX return ring. */ 2776 if (sc->bge_cdata.bge_rx_return_ring_map) 2777 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2778 sc->bge_cdata.bge_rx_return_ring_map); 2779 2780 if (sc->bge_cdata.bge_rx_return_ring_map && 2781 sc->bge_ldata.bge_rx_return_ring) 2782 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2783 sc->bge_ldata.bge_rx_return_ring, 2784 sc->bge_cdata.bge_rx_return_ring_map); 2785 2786 if (sc->bge_cdata.bge_rx_return_ring_tag) 2787 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2788 2789 /* Destroy TX ring. */ 2790 if (sc->bge_cdata.bge_tx_ring_map) 2791 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2792 sc->bge_cdata.bge_tx_ring_map); 2793 2794 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2795 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2796 sc->bge_ldata.bge_tx_ring, 2797 sc->bge_cdata.bge_tx_ring_map); 2798 2799 if (sc->bge_cdata.bge_tx_ring_tag) 2800 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2801 2802 /* Destroy status block. */ 2803 if (sc->bge_cdata.bge_status_map) 2804 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2805 sc->bge_cdata.bge_status_map); 2806 2807 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2808 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2809 sc->bge_ldata.bge_status_block, 2810 sc->bge_cdata.bge_status_map); 2811 2812 if (sc->bge_cdata.bge_status_tag) 2813 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2814 2815 /* Destroy statistics block. */ 2816 if (sc->bge_cdata.bge_stats_map) 2817 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2818 sc->bge_cdata.bge_stats_map); 2819 2820 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2821 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2822 sc->bge_ldata.bge_stats, 2823 sc->bge_cdata.bge_stats_map); 2824 2825 if (sc->bge_cdata.bge_stats_tag) 2826 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2827 2828 if (sc->bge_cdata.bge_buffer_tag) 2829 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2830 2831 /* Destroy the parent tag. */ 2832 if (sc->bge_cdata.bge_parent_tag) 2833 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2834 } 2835 2836 static int 2837 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2838 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2839 bus_addr_t *paddr, const char *msg) 2840 { 2841 struct bge_dmamap_arg ctx; 2842 int error; 2843 2844 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2845 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2846 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2847 if (error != 0) { 2848 device_printf(sc->bge_dev, 2849 "could not create %s dma tag\n", msg); 2850 return (ENOMEM); 2851 } 2852 /* Allocate DMA'able memory for ring. */ 2853 error = bus_dmamem_alloc(*tag, (void **)ring, 2854 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2855 if (error != 0) { 2856 device_printf(sc->bge_dev, 2857 "could not allocate DMA'able memory for %s\n", msg); 2858 return (ENOMEM); 2859 } 2860 /* Load the address of the ring. */ 2861 ctx.bge_busaddr = 0; 2862 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2863 &ctx, BUS_DMA_NOWAIT); 2864 if (error != 0) { 2865 device_printf(sc->bge_dev, 2866 "could not load DMA'able memory for %s\n", msg); 2867 return (ENOMEM); 2868 } 2869 *paddr = ctx.bge_busaddr; 2870 return (0); 2871 } 2872 2873 static int 2874 bge_dma_alloc(struct bge_softc *sc) 2875 { 2876 bus_addr_t lowaddr; 2877 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2878 int i, error; 2879 2880 lowaddr = BUS_SPACE_MAXADDR; 2881 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2882 lowaddr = BGE_DMA_MAXADDR; 2883 /* 2884 * Allocate the parent bus DMA tag appropriate for PCI. 2885 */ 2886 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2887 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2888 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2889 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2890 if (error != 0) { 2891 device_printf(sc->bge_dev, 2892 "could not allocate parent dma tag\n"); 2893 return (ENOMEM); 2894 } 2895 2896 /* Create tag for standard RX ring. */ 2897 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2898 &sc->bge_cdata.bge_rx_std_ring_tag, 2899 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2900 &sc->bge_cdata.bge_rx_std_ring_map, 2901 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2902 if (error) 2903 return (error); 2904 2905 /* Create tag for RX return ring. */ 2906 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2907 &sc->bge_cdata.bge_rx_return_ring_tag, 2908 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2909 &sc->bge_cdata.bge_rx_return_ring_map, 2910 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2911 if (error) 2912 return (error); 2913 2914 /* Create tag for TX ring. */ 2915 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2916 &sc->bge_cdata.bge_tx_ring_tag, 2917 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2918 &sc->bge_cdata.bge_tx_ring_map, 2919 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2920 if (error) 2921 return (error); 2922 2923 /* 2924 * Create tag for status block. 2925 * Because we only use single Tx/Rx/Rx return ring, use 2926 * minimum status block size except BCM5700 AX/BX which 2927 * seems to want to see full status block size regardless 2928 * of configured number of ring. 2929 */ 2930 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2931 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2932 sbsz = BGE_STATUS_BLK_SZ; 2933 else 2934 sbsz = 32; 2935 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2936 &sc->bge_cdata.bge_status_tag, 2937 (uint8_t **)&sc->bge_ldata.bge_status_block, 2938 &sc->bge_cdata.bge_status_map, 2939 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2940 if (error) 2941 return (error); 2942 2943 /* Create tag for statistics block. */ 2944 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2945 &sc->bge_cdata.bge_stats_tag, 2946 (uint8_t **)&sc->bge_ldata.bge_stats, 2947 &sc->bge_cdata.bge_stats_map, 2948 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2949 if (error) 2950 return (error); 2951 2952 /* Create tag for jumbo RX ring. */ 2953 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2954 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2955 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2956 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2957 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2958 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2959 if (error) 2960 return (error); 2961 } 2962 2963 /* Create parent tag for buffers. */ 2964 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 2965 /* 2966 * XXX 2967 * watchdog timeout issue was observed on BCM5704 which 2968 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 2969 * Both limiting DMA address space to 32bits and flushing 2970 * mailbox write seem to address the issue. 2971 */ 2972 if (sc->bge_pcixcap != 0) 2973 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2974 } 2975 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 2976 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 2977 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 2978 &sc->bge_cdata.bge_buffer_tag); 2979 if (error != 0) { 2980 device_printf(sc->bge_dev, 2981 "could not allocate buffer dma tag\n"); 2982 return (ENOMEM); 2983 } 2984 /* Create tag for Tx mbufs. */ 2985 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2986 txsegsz = BGE_TSOSEG_SZ; 2987 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2988 } else { 2989 txsegsz = MCLBYTES; 2990 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2991 } 2992 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2993 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2994 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2995 &sc->bge_cdata.bge_tx_mtag); 2996 2997 if (error) { 2998 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2999 return (ENOMEM); 3000 } 3001 3002 /* Create tag for Rx mbufs. */ 3003 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3004 rxmaxsegsz = MJUM9BYTES; 3005 else 3006 rxmaxsegsz = MCLBYTES; 3007 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3008 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3009 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3010 3011 if (error) { 3012 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3013 return (ENOMEM); 3014 } 3015 3016 /* Create DMA maps for RX buffers. */ 3017 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3018 &sc->bge_cdata.bge_rx_std_sparemap); 3019 if (error) { 3020 device_printf(sc->bge_dev, 3021 "can't create spare DMA map for RX\n"); 3022 return (ENOMEM); 3023 } 3024 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3025 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3026 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3027 if (error) { 3028 device_printf(sc->bge_dev, 3029 "can't create DMA map for RX\n"); 3030 return (ENOMEM); 3031 } 3032 } 3033 3034 /* Create DMA maps for TX buffers. */ 3035 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3036 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3037 &sc->bge_cdata.bge_tx_dmamap[i]); 3038 if (error) { 3039 device_printf(sc->bge_dev, 3040 "can't create DMA map for TX\n"); 3041 return (ENOMEM); 3042 } 3043 } 3044 3045 /* Create tags for jumbo RX buffers. */ 3046 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3047 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3048 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3049 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3050 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3051 if (error) { 3052 device_printf(sc->bge_dev, 3053 "could not allocate jumbo dma tag\n"); 3054 return (ENOMEM); 3055 } 3056 /* Create DMA maps for jumbo RX buffers. */ 3057 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3058 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3059 if (error) { 3060 device_printf(sc->bge_dev, 3061 "can't create spare DMA map for jumbo RX\n"); 3062 return (ENOMEM); 3063 } 3064 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3065 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3066 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3067 if (error) { 3068 device_printf(sc->bge_dev, 3069 "can't create DMA map for jumbo RX\n"); 3070 return (ENOMEM); 3071 } 3072 } 3073 } 3074 3075 return (0); 3076 } 3077 3078 /* 3079 * Return true if this device has more than one port. 3080 */ 3081 static int 3082 bge_has_multiple_ports(struct bge_softc *sc) 3083 { 3084 device_t dev = sc->bge_dev; 3085 u_int b, d, f, fscan, s; 3086 3087 d = pci_get_domain(dev); 3088 b = pci_get_bus(dev); 3089 s = pci_get_slot(dev); 3090 f = pci_get_function(dev); 3091 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3092 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3093 return (1); 3094 return (0); 3095 } 3096 3097 /* 3098 * Return true if MSI can be used with this device. 3099 */ 3100 static int 3101 bge_can_use_msi(struct bge_softc *sc) 3102 { 3103 int can_use_msi = 0; 3104 3105 if (sc->bge_msi == 0) 3106 return (0); 3107 3108 /* Disable MSI for polling(4). */ 3109 #ifdef DEVICE_POLLING 3110 return (0); 3111 #endif 3112 switch (sc->bge_asicrev) { 3113 case BGE_ASICREV_BCM5714_A0: 3114 case BGE_ASICREV_BCM5714: 3115 /* 3116 * Apparently, MSI doesn't work when these chips are 3117 * configured in single-port mode. 3118 */ 3119 if (bge_has_multiple_ports(sc)) 3120 can_use_msi = 1; 3121 break; 3122 case BGE_ASICREV_BCM5750: 3123 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3124 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3125 can_use_msi = 1; 3126 break; 3127 default: 3128 if (BGE_IS_575X_PLUS(sc)) 3129 can_use_msi = 1; 3130 } 3131 return (can_use_msi); 3132 } 3133 3134 static int 3135 bge_mbox_reorder(struct bge_softc *sc) 3136 { 3137 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3138 static const struct mbox_reorder { 3139 const uint16_t vendor; 3140 const uint16_t device; 3141 const char *desc; 3142 } mbox_reorder_lists[] = { 3143 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3144 }; 3145 devclass_t pci, pcib; 3146 device_t bus, dev; 3147 int i; 3148 3149 pci = devclass_find("pci"); 3150 pcib = devclass_find("pcib"); 3151 dev = sc->bge_dev; 3152 bus = device_get_parent(dev); 3153 for (;;) { 3154 dev = device_get_parent(bus); 3155 bus = device_get_parent(dev); 3156 if (device_get_devclass(dev) != pcib) 3157 break; 3158 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3159 if (pci_get_vendor(dev) == 3160 mbox_reorder_lists[i].vendor && 3161 pci_get_device(dev) == 3162 mbox_reorder_lists[i].device) { 3163 device_printf(sc->bge_dev, 3164 "enabling MBOX workaround for %s\n", 3165 mbox_reorder_lists[i].desc); 3166 return (1); 3167 } 3168 } 3169 if (device_get_devclass(bus) != pci) 3170 break; 3171 } 3172 return (0); 3173 } 3174 3175 static void 3176 bge_devinfo(struct bge_softc *sc) 3177 { 3178 uint32_t cfg, clk; 3179 3180 device_printf(sc->bge_dev, 3181 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3182 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3183 if (sc->bge_flags & BGE_FLAG_PCIE) 3184 printf("PCI-E\n"); 3185 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3186 printf("PCI-X "); 3187 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3188 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3189 clk = 133; 3190 else { 3191 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3192 switch (clk) { 3193 case 0: 3194 clk = 33; 3195 break; 3196 case 2: 3197 clk = 50; 3198 break; 3199 case 4: 3200 clk = 66; 3201 break; 3202 case 6: 3203 clk = 100; 3204 break; 3205 case 7: 3206 clk = 133; 3207 break; 3208 } 3209 } 3210 printf("%u MHz\n", clk); 3211 } else { 3212 if (sc->bge_pcixcap != 0) 3213 printf("PCI on PCI-X "); 3214 else 3215 printf("PCI "); 3216 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3217 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3218 clk = 66; 3219 else 3220 clk = 33; 3221 if (cfg & BGE_PCISTATE_32BIT_BUS) 3222 printf("%u MHz; 32bit\n", clk); 3223 else 3224 printf("%u MHz; 64bit\n", clk); 3225 } 3226 } 3227 3228 static int 3229 bge_attach(device_t dev) 3230 { 3231 struct ifnet *ifp; 3232 struct bge_softc *sc; 3233 uint32_t hwcfg = 0, misccfg, pcistate; 3234 u_char eaddr[ETHER_ADDR_LEN]; 3235 int capmask, error, msicount, reg, rid, trys; 3236 3237 sc = device_get_softc(dev); 3238 sc->bge_dev = dev; 3239 3240 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3241 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3242 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3243 3244 /* 3245 * Map control/status registers. 3246 */ 3247 pci_enable_busmaster(dev); 3248 3249 rid = PCIR_BAR(0); 3250 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3251 RF_ACTIVE); 3252 3253 if (sc->bge_res == NULL) { 3254 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3255 error = ENXIO; 3256 goto fail; 3257 } 3258 3259 /* Save various chip information. */ 3260 sc->bge_func_addr = pci_get_function(dev); 3261 sc->bge_chipid = bge_chipid(dev); 3262 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3263 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3264 3265 /* Set default PHY address. */ 3266 sc->bge_phy_addr = 1; 3267 /* 3268 * PHY address mapping for various devices. 3269 * 3270 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3271 * ---------+-------+-------+-------+-------+ 3272 * BCM57XX | 1 | X | X | X | 3273 * BCM5704 | 1 | X | 1 | X | 3274 * BCM5717 | 1 | 8 | 2 | 9 | 3275 * BCM5719 | 1 | 8 | 2 | 9 | 3276 * BCM5720 | 1 | 8 | 2 | 9 | 3277 * 3278 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3279 * ---------+-------+-------+-------+-------+ 3280 * BCM57XX | X | X | X | X | 3281 * BCM5704 | X | X | X | X | 3282 * BCM5717 | X | X | X | X | 3283 * BCM5719 | 3 | 10 | 4 | 11 | 3284 * BCM5720 | X | X | X | X | 3285 * 3286 * Other addresses may respond but they are not 3287 * IEEE compliant PHYs and should be ignored. 3288 */ 3289 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3290 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3291 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3292 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3293 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3294 BGE_SGDIGSTS_IS_SERDES) 3295 sc->bge_phy_addr = sc->bge_func_addr + 8; 3296 else 3297 sc->bge_phy_addr = sc->bge_func_addr + 1; 3298 } else { 3299 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3300 BGE_CPMU_PHY_STRAP_IS_SERDES) 3301 sc->bge_phy_addr = sc->bge_func_addr + 8; 3302 else 3303 sc->bge_phy_addr = sc->bge_func_addr + 1; 3304 } 3305 } 3306 3307 if (bge_has_eaddr(sc)) 3308 sc->bge_flags |= BGE_FLAG_EADDR; 3309 3310 /* Save chipset family. */ 3311 switch (sc->bge_asicrev) { 3312 case BGE_ASICREV_BCM57765: 3313 case BGE_ASICREV_BCM57766: 3314 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3315 /* FALLTHROUGH */ 3316 case BGE_ASICREV_BCM5717: 3317 case BGE_ASICREV_BCM5719: 3318 case BGE_ASICREV_BCM5720: 3319 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3320 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3321 BGE_FLAG_JUMBO_FRAME; 3322 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3323 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3324 /* Jumbo frame on BCM5719 A0 does not work. */ 3325 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3326 } 3327 break; 3328 case BGE_ASICREV_BCM5755: 3329 case BGE_ASICREV_BCM5761: 3330 case BGE_ASICREV_BCM5784: 3331 case BGE_ASICREV_BCM5785: 3332 case BGE_ASICREV_BCM5787: 3333 case BGE_ASICREV_BCM57780: 3334 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3335 BGE_FLAG_5705_PLUS; 3336 break; 3337 case BGE_ASICREV_BCM5700: 3338 case BGE_ASICREV_BCM5701: 3339 case BGE_ASICREV_BCM5703: 3340 case BGE_ASICREV_BCM5704: 3341 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3342 break; 3343 case BGE_ASICREV_BCM5714_A0: 3344 case BGE_ASICREV_BCM5780: 3345 case BGE_ASICREV_BCM5714: 3346 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3347 /* FALLTHROUGH */ 3348 case BGE_ASICREV_BCM5750: 3349 case BGE_ASICREV_BCM5752: 3350 case BGE_ASICREV_BCM5906: 3351 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3352 /* FALLTHROUGH */ 3353 case BGE_ASICREV_BCM5705: 3354 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3355 break; 3356 } 3357 3358 /* Identify chips with APE processor. */ 3359 switch (sc->bge_asicrev) { 3360 case BGE_ASICREV_BCM5717: 3361 case BGE_ASICREV_BCM5719: 3362 case BGE_ASICREV_BCM5720: 3363 case BGE_ASICREV_BCM5761: 3364 sc->bge_flags |= BGE_FLAG_APE; 3365 break; 3366 } 3367 3368 /* Chips with APE need BAR2 access for APE registers/memory. */ 3369 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3370 rid = PCIR_BAR(2); 3371 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3372 RF_ACTIVE); 3373 if (sc->bge_res2 == NULL) { 3374 device_printf (sc->bge_dev, 3375 "couldn't map BAR2 memory\n"); 3376 error = ENXIO; 3377 goto fail; 3378 } 3379 3380 /* Enable APE register/memory access by host driver. */ 3381 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3382 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3383 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3384 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3385 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3386 3387 bge_ape_lock_init(sc); 3388 bge_ape_read_fw_ver(sc); 3389 } 3390 3391 /* Add SYSCTLs, requires the chipset family to be set. */ 3392 bge_add_sysctls(sc); 3393 3394 /* Identify the chips that use an CPMU. */ 3395 if (BGE_IS_5717_PLUS(sc) || 3396 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3397 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3398 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3399 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3400 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3401 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3402 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3403 else 3404 sc->bge_mi_mode = BGE_MIMODE_BASE; 3405 /* Enable auto polling for BCM570[0-5]. */ 3406 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3407 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3408 3409 /* 3410 * All Broadcom controllers have 4GB boundary DMA bug. 3411 * Whenever an address crosses a multiple of the 4GB boundary 3412 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3413 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3414 * state machine will lockup and cause the device to hang. 3415 */ 3416 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3417 3418 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3419 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3420 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3421 3422 /* 3423 * BCM5719 cannot handle DMA requests for DMA segments that 3424 * have larger than 4KB in size. However the maximum DMA 3425 * segment size created in DMA tag is 4KB for TSO, so we 3426 * wouldn't encounter the issue here. 3427 */ 3428 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3429 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3430 3431 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3432 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3433 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3434 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3435 sc->bge_flags |= BGE_FLAG_5788; 3436 } 3437 3438 capmask = BMSR_DEFCAPMASK; 3439 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3440 (misccfg == 0x4000 || misccfg == 0x8000)) || 3441 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3442 pci_get_vendor(dev) == BCOM_VENDORID && 3443 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3444 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3445 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3446 (pci_get_vendor(dev) == BCOM_VENDORID && 3447 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3448 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3449 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3450 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3451 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3452 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3453 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3454 /* These chips are 10/100 only. */ 3455 capmask &= ~BMSR_EXTSTAT; 3456 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3457 } 3458 3459 /* 3460 * Some controllers seem to require a special firmware to use 3461 * TSO. But the firmware is not available to FreeBSD and Linux 3462 * claims that the TSO performed by the firmware is slower than 3463 * hardware based TSO. Moreover the firmware based TSO has one 3464 * known bug which can't handle TSO if Ethernet header + IP/TCP 3465 * header is greater than 80 bytes. A workaround for the TSO 3466 * bug exist but it seems it's too expensive than not using 3467 * TSO at all. Some hardwares also have the TSO bug so limit 3468 * the TSO to the controllers that are not affected TSO issues 3469 * (e.g. 5755 or higher). 3470 */ 3471 if (BGE_IS_5717_PLUS(sc)) { 3472 /* BCM5717 requires different TSO configuration. */ 3473 sc->bge_flags |= BGE_FLAG_TSO3; 3474 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3475 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3476 /* TSO on BCM5719 A0 does not work. */ 3477 sc->bge_flags &= ~BGE_FLAG_TSO3; 3478 } 3479 } else if (BGE_IS_5755_PLUS(sc)) { 3480 /* 3481 * BCM5754 and BCM5787 shares the same ASIC id so 3482 * explicit device id check is required. 3483 * Due to unknown reason TSO does not work on BCM5755M. 3484 */ 3485 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3486 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3487 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3488 sc->bge_flags |= BGE_FLAG_TSO; 3489 } 3490 3491 /* 3492 * Check if this is a PCI-X or PCI Express device. 3493 */ 3494 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3495 /* 3496 * Found a PCI Express capabilities register, this 3497 * must be a PCI Express device. 3498 */ 3499 sc->bge_flags |= BGE_FLAG_PCIE; 3500 sc->bge_expcap = reg; 3501 /* Extract supported maximum payload size. */ 3502 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3503 PCIER_DEVICE_CAP, 2); 3504 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3505 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3506 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3507 sc->bge_expmrq = 2048; 3508 else 3509 sc->bge_expmrq = 4096; 3510 pci_set_max_read_req(dev, sc->bge_expmrq); 3511 } else { 3512 /* 3513 * Check if the device is in PCI-X Mode. 3514 * (This bit is not valid on PCI Express controllers.) 3515 */ 3516 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3517 sc->bge_pcixcap = reg; 3518 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3519 BGE_PCISTATE_PCI_BUSMODE) == 0) 3520 sc->bge_flags |= BGE_FLAG_PCIX; 3521 } 3522 3523 /* 3524 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3525 * not actually a MAC controller bug but an issue with the embedded 3526 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3527 */ 3528 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3529 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3530 /* 3531 * Some PCI-X bridges are known to trigger write reordering to 3532 * the mailbox registers. Typical phenomena is watchdog timeouts 3533 * caused by out-of-order TX completions. Enable workaround for 3534 * PCI-X devices that live behind these bridges. 3535 * Note, PCI-X controllers can run in PCI mode so we can't use 3536 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3537 */ 3538 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3539 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3540 /* 3541 * Allocate the interrupt, using MSI if possible. These devices 3542 * support 8 MSI messages, but only the first one is used in 3543 * normal operation. 3544 */ 3545 rid = 0; 3546 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3547 sc->bge_msicap = reg; 3548 if (bge_can_use_msi(sc)) { 3549 msicount = pci_msi_count(dev); 3550 if (msicount > 1) 3551 msicount = 1; 3552 } else 3553 msicount = 0; 3554 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 3555 rid = 1; 3556 sc->bge_flags |= BGE_FLAG_MSI; 3557 } 3558 } 3559 3560 /* 3561 * All controllers except BCM5700 supports tagged status but 3562 * we use tagged status only for MSI case on BCM5717. Otherwise 3563 * MSI on BCM5717 does not work. 3564 */ 3565 #ifndef DEVICE_POLLING 3566 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3567 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3568 #endif 3569 3570 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3571 RF_SHAREABLE | RF_ACTIVE); 3572 3573 if (sc->bge_irq == NULL) { 3574 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3575 error = ENXIO; 3576 goto fail; 3577 } 3578 3579 bge_devinfo(sc); 3580 3581 sc->bge_asf_mode = 0; 3582 /* No ASF if APE present. */ 3583 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3584 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3585 BGE_SRAM_DATA_SIG_MAGIC)) { 3586 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3587 BGE_HWCFG_ASF) { 3588 sc->bge_asf_mode |= ASF_ENABLE; 3589 sc->bge_asf_mode |= ASF_STACKUP; 3590 if (BGE_IS_575X_PLUS(sc)) 3591 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3592 } 3593 } 3594 } 3595 3596 bge_stop_fw(sc); 3597 bge_sig_pre_reset(sc, BGE_RESET_START); 3598 if (bge_reset(sc)) { 3599 device_printf(sc->bge_dev, "chip reset failed\n"); 3600 error = ENXIO; 3601 goto fail; 3602 } 3603 3604 bge_sig_legacy(sc, BGE_RESET_START); 3605 bge_sig_post_reset(sc, BGE_RESET_START); 3606 3607 if (bge_chipinit(sc)) { 3608 device_printf(sc->bge_dev, "chip initialization failed\n"); 3609 error = ENXIO; 3610 goto fail; 3611 } 3612 3613 error = bge_get_eaddr(sc, eaddr); 3614 if (error) { 3615 device_printf(sc->bge_dev, 3616 "failed to read station address\n"); 3617 error = ENXIO; 3618 goto fail; 3619 } 3620 3621 /* 5705 limits RX return ring to 512 entries. */ 3622 if (BGE_IS_5717_PLUS(sc)) 3623 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3624 else if (BGE_IS_5705_PLUS(sc)) 3625 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3626 else 3627 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3628 3629 if (bge_dma_alloc(sc)) { 3630 device_printf(sc->bge_dev, 3631 "failed to allocate DMA resources\n"); 3632 error = ENXIO; 3633 goto fail; 3634 } 3635 3636 /* Set default tuneable values. */ 3637 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3638 sc->bge_rx_coal_ticks = 150; 3639 sc->bge_tx_coal_ticks = 150; 3640 sc->bge_rx_max_coal_bds = 10; 3641 sc->bge_tx_max_coal_bds = 10; 3642 3643 /* Initialize checksum features to use. */ 3644 sc->bge_csum_features = BGE_CSUM_FEATURES; 3645 if (sc->bge_forced_udpcsum != 0) 3646 sc->bge_csum_features |= CSUM_UDP; 3647 3648 /* Set up ifnet structure */ 3649 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3650 if (ifp == NULL) { 3651 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3652 error = ENXIO; 3653 goto fail; 3654 } 3655 ifp->if_softc = sc; 3656 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3657 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3658 ifp->if_ioctl = bge_ioctl; 3659 ifp->if_start = bge_start; 3660 ifp->if_init = bge_init; 3661 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3662 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3663 IFQ_SET_READY(&ifp->if_snd); 3664 ifp->if_hwassist = sc->bge_csum_features; 3665 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3666 IFCAP_VLAN_MTU; 3667 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3668 ifp->if_hwassist |= CSUM_TSO; 3669 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3670 } 3671 #ifdef IFCAP_VLAN_HWCSUM 3672 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3673 #endif 3674 ifp->if_capenable = ifp->if_capabilities; 3675 #ifdef DEVICE_POLLING 3676 ifp->if_capabilities |= IFCAP_POLLING; 3677 #endif 3678 3679 /* 3680 * 5700 B0 chips do not support checksumming correctly due 3681 * to hardware bugs. 3682 */ 3683 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3684 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3685 ifp->if_capenable &= ~IFCAP_HWCSUM; 3686 ifp->if_hwassist = 0; 3687 } 3688 3689 /* 3690 * Figure out what sort of media we have by checking the 3691 * hardware config word in the first 32k of NIC internal memory, 3692 * or fall back to examining the EEPROM if necessary. 3693 * Note: on some BCM5700 cards, this value appears to be unset. 3694 * If that's the case, we have to rely on identifying the NIC 3695 * by its PCI subsystem ID, as we do below for the SysKonnect 3696 * SK-9D41. 3697 */ 3698 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3699 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3700 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3701 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3702 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3703 sizeof(hwcfg))) { 3704 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3705 error = ENXIO; 3706 goto fail; 3707 } 3708 hwcfg = ntohl(hwcfg); 3709 } 3710 3711 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3712 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3713 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3714 if (BGE_IS_5705_PLUS(sc)) { 3715 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3716 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3717 } else 3718 sc->bge_flags |= BGE_FLAG_TBI; 3719 } 3720 3721 /* Set various PHY bug flags. */ 3722 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3723 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3724 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3725 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3726 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3727 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3728 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3729 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3730 if (pci_get_subvendor(dev) == DELL_VENDORID) 3731 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3732 if ((BGE_IS_5705_PLUS(sc)) && 3733 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3734 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3735 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3736 !BGE_IS_5717_PLUS(sc)) { 3737 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3738 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3739 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3740 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3741 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3742 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3743 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3744 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3745 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3746 } else 3747 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3748 } 3749 3750 /* 3751 * Don't enable Ethernet@WireSpeed for the 5700 or the 3752 * 5705 A0 and A1 chips. 3753 */ 3754 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3755 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3756 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3757 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3758 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3759 3760 if (sc->bge_flags & BGE_FLAG_TBI) { 3761 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3762 bge_ifmedia_sts); 3763 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3764 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3765 0, NULL); 3766 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3767 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3768 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3769 } else { 3770 /* 3771 * Do transceiver setup and tell the firmware the 3772 * driver is down so we can try to get access the 3773 * probe if ASF is running. Retry a couple of times 3774 * if we get a conflict with the ASF firmware accessing 3775 * the PHY. 3776 */ 3777 trys = 0; 3778 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3779 again: 3780 bge_asf_driver_up(sc); 3781 3782 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3783 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, 3784 MIIF_DOPAUSE); 3785 if (error != 0) { 3786 if (trys++ < 4) { 3787 device_printf(sc->bge_dev, "Try again\n"); 3788 bge_miibus_writereg(sc->bge_dev, 3789 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3790 goto again; 3791 } 3792 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3793 goto fail; 3794 } 3795 3796 /* 3797 * Now tell the firmware we are going up after probing the PHY 3798 */ 3799 if (sc->bge_asf_mode & ASF_STACKUP) 3800 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3801 } 3802 3803 /* 3804 * When using the BCM5701 in PCI-X mode, data corruption has 3805 * been observed in the first few bytes of some received packets. 3806 * Aligning the packet buffer in memory eliminates the corruption. 3807 * Unfortunately, this misaligns the packet payloads. On platforms 3808 * which do not support unaligned accesses, we will realign the 3809 * payloads by copying the received packets. 3810 */ 3811 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3812 sc->bge_flags & BGE_FLAG_PCIX) 3813 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3814 3815 /* 3816 * Call MI attach routine. 3817 */ 3818 ether_ifattach(ifp, eaddr); 3819 3820 /* Tell upper layer we support long frames. */ 3821 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3822 3823 /* 3824 * Hookup IRQ last. 3825 */ 3826 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3827 /* Take advantage of single-shot MSI. */ 3828 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3829 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3830 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3831 taskqueue_thread_enqueue, &sc->bge_tq); 3832 if (sc->bge_tq == NULL) { 3833 device_printf(dev, "could not create taskqueue.\n"); 3834 ether_ifdetach(ifp); 3835 error = ENOMEM; 3836 goto fail; 3837 } 3838 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3839 "%s taskq", device_get_nameunit(sc->bge_dev)); 3840 if (error != 0) { 3841 device_printf(dev, "could not start threads.\n"); 3842 ether_ifdetach(ifp); 3843 goto fail; 3844 } 3845 error = bus_setup_intr(dev, sc->bge_irq, 3846 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3847 &sc->bge_intrhand); 3848 } else 3849 error = bus_setup_intr(dev, sc->bge_irq, 3850 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3851 &sc->bge_intrhand); 3852 3853 if (error) { 3854 ether_ifdetach(ifp); 3855 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3856 } 3857 3858 fail: 3859 if (error) 3860 bge_detach(dev); 3861 return (error); 3862 } 3863 3864 static int 3865 bge_detach(device_t dev) 3866 { 3867 struct bge_softc *sc; 3868 struct ifnet *ifp; 3869 3870 sc = device_get_softc(dev); 3871 ifp = sc->bge_ifp; 3872 3873 #ifdef DEVICE_POLLING 3874 if (ifp->if_capenable & IFCAP_POLLING) 3875 ether_poll_deregister(ifp); 3876 #endif 3877 3878 if (device_is_attached(dev)) { 3879 ether_ifdetach(ifp); 3880 BGE_LOCK(sc); 3881 bge_stop(sc); 3882 BGE_UNLOCK(sc); 3883 callout_drain(&sc->bge_stat_ch); 3884 } 3885 3886 if (sc->bge_tq) 3887 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3888 3889 if (sc->bge_flags & BGE_FLAG_TBI) 3890 ifmedia_removeall(&sc->bge_ifmedia); 3891 else if (sc->bge_miibus != NULL) { 3892 bus_generic_detach(dev); 3893 device_delete_child(dev, sc->bge_miibus); 3894 } 3895 3896 bge_release_resources(sc); 3897 3898 return (0); 3899 } 3900 3901 static void 3902 bge_release_resources(struct bge_softc *sc) 3903 { 3904 device_t dev; 3905 3906 dev = sc->bge_dev; 3907 3908 if (sc->bge_tq != NULL) 3909 taskqueue_free(sc->bge_tq); 3910 3911 if (sc->bge_intrhand != NULL) 3912 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3913 3914 if (sc->bge_irq != NULL) 3915 bus_release_resource(dev, SYS_RES_IRQ, 3916 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3917 3918 if (sc->bge_flags & BGE_FLAG_MSI) 3919 pci_release_msi(dev); 3920 3921 if (sc->bge_res != NULL) 3922 bus_release_resource(dev, SYS_RES_MEMORY, 3923 PCIR_BAR(0), sc->bge_res); 3924 3925 if (sc->bge_res2 != NULL) 3926 bus_release_resource(dev, SYS_RES_MEMORY, 3927 PCIR_BAR(2), sc->bge_res2); 3928 3929 if (sc->bge_ifp != NULL) 3930 if_free(sc->bge_ifp); 3931 3932 bge_dma_free(sc); 3933 3934 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3935 BGE_LOCK_DESTROY(sc); 3936 } 3937 3938 static int 3939 bge_reset(struct bge_softc *sc) 3940 { 3941 device_t dev; 3942 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 3943 void (*write_op)(struct bge_softc *, int, int); 3944 uint16_t devctl; 3945 int i; 3946 3947 dev = sc->bge_dev; 3948 3949 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 3950 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 3951 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 3952 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 3953 3954 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3955 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3956 if (sc->bge_flags & BGE_FLAG_PCIE) 3957 write_op = bge_writemem_direct; 3958 else 3959 write_op = bge_writemem_ind; 3960 } else 3961 write_op = bge_writereg_ind; 3962 3963 /* Take APE lock when performing reset. */ 3964 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 3965 3966 /* Save some important PCI state. */ 3967 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3968 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3969 3970 pci_write_config(dev, BGE_PCI_MISC_CTL, 3971 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3972 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3973 3974 /* Disable fastboot on controllers that support it. */ 3975 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3976 BGE_IS_5755_PLUS(sc)) { 3977 if (bootverbose) 3978 device_printf(dev, "Disabling fastboot\n"); 3979 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3980 } 3981 3982 /* 3983 * Write the magic number to SRAM at offset 0xB50. 3984 * When firmware finishes its initialization it will 3985 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 3986 */ 3987 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3988 3989 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3990 3991 /* XXX: Broadcom Linux driver. */ 3992 if (sc->bge_flags & BGE_FLAG_PCIE) { 3993 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3994 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 3995 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3996 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3997 } 3998 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3999 /* Prevent PCIE link training during global reset */ 4000 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4001 reset |= 1 << 29; 4002 } 4003 } 4004 4005 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4006 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4007 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4008 val | BGE_VCPU_STATUS_DRV_RESET); 4009 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4010 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4011 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4012 } 4013 4014 /* 4015 * Set GPHY Power Down Override to leave GPHY 4016 * powered up in D0 uninitialized. 4017 */ 4018 if (BGE_IS_5705_PLUS(sc) && 4019 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4020 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4021 4022 /* Issue global reset */ 4023 write_op(sc, BGE_MISC_CFG, reset); 4024 4025 if (sc->bge_flags & BGE_FLAG_PCIE) 4026 DELAY(100 * 1000); 4027 else 4028 DELAY(1000); 4029 4030 /* XXX: Broadcom Linux driver. */ 4031 if (sc->bge_flags & BGE_FLAG_PCIE) { 4032 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4033 DELAY(500000); /* wait for link training to complete */ 4034 val = pci_read_config(dev, 0xC4, 4); 4035 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4036 } 4037 devctl = pci_read_config(dev, 4038 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4039 /* Clear enable no snoop and disable relaxed ordering. */ 4040 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4041 PCIEM_CTL_NOSNOOP_ENABLE); 4042 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4043 devctl, 2); 4044 pci_set_max_read_req(dev, sc->bge_expmrq); 4045 /* Clear error status. */ 4046 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4047 PCIEM_STA_CORRECTABLE_ERROR | 4048 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4049 PCIEM_STA_UNSUPPORTED_REQ, 2); 4050 } 4051 4052 /* Reset some of the PCI state that got zapped by reset. */ 4053 pci_write_config(dev, BGE_PCI_MISC_CTL, 4054 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4055 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4056 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4057 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4058 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4059 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4060 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4061 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4062 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4063 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4064 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4065 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4066 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4067 /* 4068 * Disable PCI-X relaxed ordering to ensure status block update 4069 * comes first then packet buffer DMA. Otherwise driver may 4070 * read stale status block. 4071 */ 4072 if (sc->bge_flags & BGE_FLAG_PCIX) { 4073 devctl = pci_read_config(dev, 4074 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4075 devctl &= ~PCIXM_COMMAND_ERO; 4076 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4077 devctl &= ~PCIXM_COMMAND_MAX_READ; 4078 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4079 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4080 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4081 PCIXM_COMMAND_MAX_READ); 4082 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4083 } 4084 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4085 devctl, 2); 4086 } 4087 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4088 if (BGE_IS_5714_FAMILY(sc)) { 4089 /* This chip disables MSI on reset. */ 4090 if (sc->bge_flags & BGE_FLAG_MSI) { 4091 val = pci_read_config(dev, 4092 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4093 pci_write_config(dev, 4094 sc->bge_msicap + PCIR_MSI_CTRL, 4095 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4096 val = CSR_READ_4(sc, BGE_MSI_MODE); 4097 CSR_WRITE_4(sc, BGE_MSI_MODE, 4098 val | BGE_MSIMODE_ENABLE); 4099 } 4100 val = CSR_READ_4(sc, BGE_MARB_MODE); 4101 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4102 } else 4103 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4104 4105 /* Fix up byte swapping. */ 4106 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4107 4108 val = CSR_READ_4(sc, BGE_MAC_MODE); 4109 val = (val & ~mac_mode_mask) | mac_mode; 4110 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4111 DELAY(40); 4112 4113 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4114 4115 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4116 for (i = 0; i < BGE_TIMEOUT; i++) { 4117 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4118 if (val & BGE_VCPU_STATUS_INIT_DONE) 4119 break; 4120 DELAY(100); 4121 } 4122 if (i == BGE_TIMEOUT) { 4123 device_printf(dev, "reset timed out\n"); 4124 return (1); 4125 } 4126 } else { 4127 /* 4128 * Poll until we see the 1's complement of the magic number. 4129 * This indicates that the firmware initialization is complete. 4130 * We expect this to fail if no chip containing the Ethernet 4131 * address is fitted though. 4132 */ 4133 for (i = 0; i < BGE_TIMEOUT; i++) { 4134 DELAY(10); 4135 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4136 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4137 break; 4138 } 4139 4140 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4141 device_printf(dev, 4142 "firmware handshake timed out, found 0x%08x\n", 4143 val); 4144 /* BCM57765 A0 needs additional time before accessing. */ 4145 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4146 DELAY(10 * 1000); /* XXX */ 4147 } 4148 4149 /* 4150 * The 5704 in TBI mode apparently needs some special 4151 * adjustment to insure the SERDES drive level is set 4152 * to 1.2V. 4153 */ 4154 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4155 sc->bge_flags & BGE_FLAG_TBI) { 4156 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4157 val = (val & ~0xFFF) | 0x880; 4158 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4159 } 4160 4161 /* XXX: Broadcom Linux driver. */ 4162 if (sc->bge_flags & BGE_FLAG_PCIE && 4163 !BGE_IS_5717_PLUS(sc) && 4164 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4165 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4166 /* Enable Data FIFO protection. */ 4167 val = CSR_READ_4(sc, 0x7C00); 4168 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4169 } 4170 4171 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4172 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4173 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4174 4175 return (0); 4176 } 4177 4178 static __inline void 4179 bge_rxreuse_std(struct bge_softc *sc, int i) 4180 { 4181 struct bge_rx_bd *r; 4182 4183 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4184 r->bge_flags = BGE_RXBDFLAG_END; 4185 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4186 r->bge_idx = i; 4187 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4188 } 4189 4190 static __inline void 4191 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4192 { 4193 struct bge_extrx_bd *r; 4194 4195 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4196 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4197 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4198 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4199 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4200 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4201 r->bge_idx = i; 4202 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4203 } 4204 4205 /* 4206 * Frame reception handling. This is called if there's a frame 4207 * on the receive return list. 4208 * 4209 * Note: we have to be able to handle two possibilities here: 4210 * 1) the frame is from the jumbo receive ring 4211 * 2) the frame is from the standard receive ring 4212 */ 4213 4214 static int 4215 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4216 { 4217 struct ifnet *ifp; 4218 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4219 uint16_t rx_cons; 4220 4221 rx_cons = sc->bge_rx_saved_considx; 4222 4223 /* Nothing to do. */ 4224 if (rx_cons == rx_prod) 4225 return (rx_npkts); 4226 4227 ifp = sc->bge_ifp; 4228 4229 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4230 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4231 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4232 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4233 if (BGE_IS_JUMBO_CAPABLE(sc) && 4234 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4235 (MCLBYTES - ETHER_ALIGN)) 4236 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4237 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4238 4239 while (rx_cons != rx_prod) { 4240 struct bge_rx_bd *cur_rx; 4241 uint32_t rxidx; 4242 struct mbuf *m = NULL; 4243 uint16_t vlan_tag = 0; 4244 int have_tag = 0; 4245 4246 #ifdef DEVICE_POLLING 4247 if (ifp->if_capenable & IFCAP_POLLING) { 4248 if (sc->rxcycles <= 0) 4249 break; 4250 sc->rxcycles--; 4251 } 4252 #endif 4253 4254 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4255 4256 rxidx = cur_rx->bge_idx; 4257 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4258 4259 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 4260 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4261 have_tag = 1; 4262 vlan_tag = cur_rx->bge_vlan_tag; 4263 } 4264 4265 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4266 jumbocnt++; 4267 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4268 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4269 bge_rxreuse_jumbo(sc, rxidx); 4270 continue; 4271 } 4272 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4273 bge_rxreuse_jumbo(sc, rxidx); 4274 ifp->if_iqdrops++; 4275 continue; 4276 } 4277 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4278 } else { 4279 stdcnt++; 4280 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4281 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4282 bge_rxreuse_std(sc, rxidx); 4283 continue; 4284 } 4285 if (bge_newbuf_std(sc, rxidx) != 0) { 4286 bge_rxreuse_std(sc, rxidx); 4287 ifp->if_iqdrops++; 4288 continue; 4289 } 4290 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4291 } 4292 4293 ifp->if_ipackets++; 4294 #ifndef __NO_STRICT_ALIGNMENT 4295 /* 4296 * For architectures with strict alignment we must make sure 4297 * the payload is aligned. 4298 */ 4299 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4300 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4301 cur_rx->bge_len); 4302 m->m_data += ETHER_ALIGN; 4303 } 4304 #endif 4305 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4306 m->m_pkthdr.rcvif = ifp; 4307 4308 if (ifp->if_capenable & IFCAP_RXCSUM) 4309 bge_rxcsum(sc, cur_rx, m); 4310 4311 /* 4312 * If we received a packet with a vlan tag, 4313 * attach that information to the packet. 4314 */ 4315 if (have_tag) { 4316 m->m_pkthdr.ether_vtag = vlan_tag; 4317 m->m_flags |= M_VLANTAG; 4318 } 4319 4320 if (holdlck != 0) { 4321 BGE_UNLOCK(sc); 4322 (*ifp->if_input)(ifp, m); 4323 BGE_LOCK(sc); 4324 } else 4325 (*ifp->if_input)(ifp, m); 4326 rx_npkts++; 4327 4328 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 4329 return (rx_npkts); 4330 } 4331 4332 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4333 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4334 if (stdcnt > 0) 4335 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4336 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4337 4338 if (jumbocnt > 0) 4339 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4340 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4341 4342 sc->bge_rx_saved_considx = rx_cons; 4343 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4344 if (stdcnt) 4345 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4346 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4347 if (jumbocnt) 4348 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4349 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4350 #ifdef notyet 4351 /* 4352 * This register wraps very quickly under heavy packet drops. 4353 * If you need correct statistics, you can enable this check. 4354 */ 4355 if (BGE_IS_5705_PLUS(sc)) 4356 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4357 #endif 4358 return (rx_npkts); 4359 } 4360 4361 static void 4362 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4363 { 4364 4365 if (BGE_IS_5717_PLUS(sc)) { 4366 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4367 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4368 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4369 if ((cur_rx->bge_error_flag & 4370 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4371 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4372 } 4373 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4374 m->m_pkthdr.csum_data = 4375 cur_rx->bge_tcp_udp_csum; 4376 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4377 CSUM_PSEUDO_HDR; 4378 } 4379 } 4380 } else { 4381 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4382 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4383 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4384 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4385 } 4386 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4387 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4388 m->m_pkthdr.csum_data = 4389 cur_rx->bge_tcp_udp_csum; 4390 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4391 CSUM_PSEUDO_HDR; 4392 } 4393 } 4394 } 4395 4396 static void 4397 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4398 { 4399 struct bge_tx_bd *cur_tx; 4400 struct ifnet *ifp; 4401 4402 BGE_LOCK_ASSERT(sc); 4403 4404 /* Nothing to do. */ 4405 if (sc->bge_tx_saved_considx == tx_cons) 4406 return; 4407 4408 ifp = sc->bge_ifp; 4409 4410 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4411 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4412 /* 4413 * Go through our tx ring and free mbufs for those 4414 * frames that have been sent. 4415 */ 4416 while (sc->bge_tx_saved_considx != tx_cons) { 4417 uint32_t idx; 4418 4419 idx = sc->bge_tx_saved_considx; 4420 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4421 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4422 ifp->if_opackets++; 4423 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4424 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4425 sc->bge_cdata.bge_tx_dmamap[idx], 4426 BUS_DMASYNC_POSTWRITE); 4427 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4428 sc->bge_cdata.bge_tx_dmamap[idx]); 4429 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4430 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4431 } 4432 sc->bge_txcnt--; 4433 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4434 } 4435 4436 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4437 if (sc->bge_txcnt == 0) 4438 sc->bge_timer = 0; 4439 } 4440 4441 #ifdef DEVICE_POLLING 4442 static int 4443 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4444 { 4445 struct bge_softc *sc = ifp->if_softc; 4446 uint16_t rx_prod, tx_cons; 4447 uint32_t statusword; 4448 int rx_npkts = 0; 4449 4450 BGE_LOCK(sc); 4451 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4452 BGE_UNLOCK(sc); 4453 return (rx_npkts); 4454 } 4455 4456 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4457 sc->bge_cdata.bge_status_map, 4458 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4459 /* Fetch updates from the status block. */ 4460 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4461 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4462 4463 statusword = sc->bge_ldata.bge_status_block->bge_status; 4464 /* Clear the status so the next pass only sees the changes. */ 4465 sc->bge_ldata.bge_status_block->bge_status = 0; 4466 4467 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4468 sc->bge_cdata.bge_status_map, 4469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4470 4471 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4472 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4473 sc->bge_link_evt++; 4474 4475 if (cmd == POLL_AND_CHECK_STATUS) 4476 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4477 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4478 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4479 bge_link_upd(sc); 4480 4481 sc->rxcycles = count; 4482 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4483 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4484 BGE_UNLOCK(sc); 4485 return (rx_npkts); 4486 } 4487 bge_txeof(sc, tx_cons); 4488 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4489 bge_start_locked(ifp); 4490 4491 BGE_UNLOCK(sc); 4492 return (rx_npkts); 4493 } 4494 #endif /* DEVICE_POLLING */ 4495 4496 static int 4497 bge_msi_intr(void *arg) 4498 { 4499 struct bge_softc *sc; 4500 4501 sc = (struct bge_softc *)arg; 4502 /* 4503 * This interrupt is not shared and controller already 4504 * disabled further interrupt. 4505 */ 4506 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4507 return (FILTER_HANDLED); 4508 } 4509 4510 static void 4511 bge_intr_task(void *arg, int pending) 4512 { 4513 struct bge_softc *sc; 4514 struct ifnet *ifp; 4515 uint32_t status, status_tag; 4516 uint16_t rx_prod, tx_cons; 4517 4518 sc = (struct bge_softc *)arg; 4519 ifp = sc->bge_ifp; 4520 4521 BGE_LOCK(sc); 4522 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4523 BGE_UNLOCK(sc); 4524 return; 4525 } 4526 4527 /* Get updated status block. */ 4528 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4529 sc->bge_cdata.bge_status_map, 4530 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4531 4532 /* Save producer/consumer indices. */ 4533 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4534 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4535 status = sc->bge_ldata.bge_status_block->bge_status; 4536 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4537 /* Dirty the status flag. */ 4538 sc->bge_ldata.bge_status_block->bge_status = 0; 4539 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4540 sc->bge_cdata.bge_status_map, 4541 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4542 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4543 status_tag = 0; 4544 4545 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4546 bge_link_upd(sc); 4547 4548 /* Let controller work. */ 4549 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4550 4551 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4552 sc->bge_rx_saved_considx != rx_prod) { 4553 /* Check RX return ring producer/consumer. */ 4554 BGE_UNLOCK(sc); 4555 bge_rxeof(sc, rx_prod, 0); 4556 BGE_LOCK(sc); 4557 } 4558 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4559 /* Check TX ring producer/consumer. */ 4560 bge_txeof(sc, tx_cons); 4561 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4562 bge_start_locked(ifp); 4563 } 4564 BGE_UNLOCK(sc); 4565 } 4566 4567 static void 4568 bge_intr(void *xsc) 4569 { 4570 struct bge_softc *sc; 4571 struct ifnet *ifp; 4572 uint32_t statusword; 4573 uint16_t rx_prod, tx_cons; 4574 4575 sc = xsc; 4576 4577 BGE_LOCK(sc); 4578 4579 ifp = sc->bge_ifp; 4580 4581 #ifdef DEVICE_POLLING 4582 if (ifp->if_capenable & IFCAP_POLLING) { 4583 BGE_UNLOCK(sc); 4584 return; 4585 } 4586 #endif 4587 4588 /* 4589 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4590 * disable interrupts by writing nonzero like we used to, since with 4591 * our current organization this just gives complications and 4592 * pessimizations for re-enabling interrupts. We used to have races 4593 * instead of the necessary complications. Disabling interrupts 4594 * would just reduce the chance of a status update while we are 4595 * running (by switching to the interrupt-mode coalescence 4596 * parameters), but this chance is already very low so it is more 4597 * efficient to get another interrupt than prevent it. 4598 * 4599 * We do the ack first to ensure another interrupt if there is a 4600 * status update after the ack. We don't check for the status 4601 * changing later because it is more efficient to get another 4602 * interrupt than prevent it, not quite as above (not checking is 4603 * a smaller optimization than not toggling the interrupt enable, 4604 * since checking doesn't involve PCI accesses and toggling require 4605 * the status check). So toggling would probably be a pessimization 4606 * even with MSI. It would only be needed for using a task queue. 4607 */ 4608 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4609 4610 /* 4611 * Do the mandatory PCI flush as well as get the link status. 4612 */ 4613 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4614 4615 /* Make sure the descriptor ring indexes are coherent. */ 4616 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4617 sc->bge_cdata.bge_status_map, 4618 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4619 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4620 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4621 sc->bge_ldata.bge_status_block->bge_status = 0; 4622 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4623 sc->bge_cdata.bge_status_map, 4624 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4625 4626 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4627 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4628 statusword || sc->bge_link_evt) 4629 bge_link_upd(sc); 4630 4631 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4632 /* Check RX return ring producer/consumer. */ 4633 bge_rxeof(sc, rx_prod, 1); 4634 } 4635 4636 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4637 /* Check TX ring producer/consumer. */ 4638 bge_txeof(sc, tx_cons); 4639 } 4640 4641 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4642 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4643 bge_start_locked(ifp); 4644 4645 BGE_UNLOCK(sc); 4646 } 4647 4648 static void 4649 bge_asf_driver_up(struct bge_softc *sc) 4650 { 4651 if (sc->bge_asf_mode & ASF_STACKUP) { 4652 /* Send ASF heartbeat aprox. every 2s */ 4653 if (sc->bge_asf_count) 4654 sc->bge_asf_count --; 4655 else { 4656 sc->bge_asf_count = 2; 4657 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4658 BGE_FW_CMD_DRV_ALIVE); 4659 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4660 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4661 BGE_FW_HB_TIMEOUT_SEC); 4662 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4663 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4664 BGE_RX_CPU_DRV_EVENT); 4665 } 4666 } 4667 } 4668 4669 static void 4670 bge_tick(void *xsc) 4671 { 4672 struct bge_softc *sc = xsc; 4673 struct mii_data *mii = NULL; 4674 4675 BGE_LOCK_ASSERT(sc); 4676 4677 /* Synchronize with possible callout reset/stop. */ 4678 if (callout_pending(&sc->bge_stat_ch) || 4679 !callout_active(&sc->bge_stat_ch)) 4680 return; 4681 4682 if (BGE_IS_5705_PLUS(sc)) 4683 bge_stats_update_regs(sc); 4684 else 4685 bge_stats_update(sc); 4686 4687 /* XXX Add APE heartbeat check here? */ 4688 4689 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4690 mii = device_get_softc(sc->bge_miibus); 4691 /* 4692 * Do not touch PHY if we have link up. This could break 4693 * IPMI/ASF mode or produce extra input errors 4694 * (extra errors was reported for bcm5701 & bcm5704). 4695 */ 4696 if (!sc->bge_link) 4697 mii_tick(mii); 4698 } else { 4699 /* 4700 * Since in TBI mode auto-polling can't be used we should poll 4701 * link status manually. Here we register pending link event 4702 * and trigger interrupt. 4703 */ 4704 #ifdef DEVICE_POLLING 4705 /* In polling mode we poll link state in bge_poll(). */ 4706 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4707 #endif 4708 { 4709 sc->bge_link_evt++; 4710 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4711 sc->bge_flags & BGE_FLAG_5788) 4712 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4713 else 4714 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4715 } 4716 } 4717 4718 bge_asf_driver_up(sc); 4719 bge_watchdog(sc); 4720 4721 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4722 } 4723 4724 static void 4725 bge_stats_update_regs(struct bge_softc *sc) 4726 { 4727 struct ifnet *ifp; 4728 struct bge_mac_stats *stats; 4729 4730 ifp = sc->bge_ifp; 4731 stats = &sc->bge_mac_stats; 4732 4733 stats->ifHCOutOctets += 4734 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4735 stats->etherStatsCollisions += 4736 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4737 stats->outXonSent += 4738 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4739 stats->outXoffSent += 4740 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4741 stats->dot3StatsInternalMacTransmitErrors += 4742 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4743 stats->dot3StatsSingleCollisionFrames += 4744 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4745 stats->dot3StatsMultipleCollisionFrames += 4746 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4747 stats->dot3StatsDeferredTransmissions += 4748 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4749 stats->dot3StatsExcessiveCollisions += 4750 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4751 stats->dot3StatsLateCollisions += 4752 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4753 stats->ifHCOutUcastPkts += 4754 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4755 stats->ifHCOutMulticastPkts += 4756 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4757 stats->ifHCOutBroadcastPkts += 4758 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4759 4760 stats->ifHCInOctets += 4761 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4762 stats->etherStatsFragments += 4763 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4764 stats->ifHCInUcastPkts += 4765 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4766 stats->ifHCInMulticastPkts += 4767 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4768 stats->ifHCInBroadcastPkts += 4769 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4770 stats->dot3StatsFCSErrors += 4771 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4772 stats->dot3StatsAlignmentErrors += 4773 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4774 stats->xonPauseFramesReceived += 4775 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4776 stats->xoffPauseFramesReceived += 4777 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4778 stats->macControlFramesReceived += 4779 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4780 stats->xoffStateEntered += 4781 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4782 stats->dot3StatsFramesTooLong += 4783 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4784 stats->etherStatsJabbers += 4785 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4786 stats->etherStatsUndersizePkts += 4787 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4788 4789 stats->FramesDroppedDueToFilters += 4790 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4791 stats->DmaWriteQueueFull += 4792 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4793 stats->DmaWriteHighPriQueueFull += 4794 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4795 stats->NoMoreRxBDs += 4796 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4797 /* 4798 * XXX 4799 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4800 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4801 * includes number of unwanted multicast frames. This comes 4802 * from silicon bug and known workaround to get rough(not 4803 * exact) counter is to enable interrupt on MBUF low water 4804 * attention. This can be accomplished by setting 4805 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4806 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4807 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4808 * However that change would generate more interrupts and 4809 * there are still possibilities of losing multiple frames 4810 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4811 * Given that the workaround still would not get correct 4812 * counter I don't think it's worth to implement it. So 4813 * ignore reading the counter on controllers that have the 4814 * silicon bug. 4815 */ 4816 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4817 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4818 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4819 stats->InputDiscards += 4820 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4821 stats->InputErrors += 4822 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4823 stats->RecvThresholdHit += 4824 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4825 4826 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4827 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4828 stats->InputErrors); 4829 } 4830 4831 static void 4832 bge_stats_clear_regs(struct bge_softc *sc) 4833 { 4834 4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4836 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4837 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4838 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4839 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4840 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4841 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4842 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4843 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4844 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4845 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4846 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4847 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4848 4849 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4850 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4851 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4852 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4853 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4855 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4857 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4859 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4861 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4863 4864 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4865 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4866 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4867 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4868 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4869 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4870 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4871 } 4872 4873 static void 4874 bge_stats_update(struct bge_softc *sc) 4875 { 4876 struct ifnet *ifp; 4877 bus_size_t stats; 4878 uint32_t cnt; /* current register value */ 4879 4880 ifp = sc->bge_ifp; 4881 4882 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4883 4884 #define READ_STAT(sc, stats, stat) \ 4885 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4886 4887 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4888 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4889 sc->bge_tx_collisions = cnt; 4890 4891 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4892 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4893 sc->bge_rx_nobds = cnt; 4894 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4895 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 4896 sc->bge_rx_inerrs = cnt; 4897 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4898 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4899 sc->bge_rx_discards = cnt; 4900 4901 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4902 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4903 sc->bge_tx_discards = cnt; 4904 4905 #undef READ_STAT 4906 } 4907 4908 /* 4909 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4910 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4911 * but when such padded frames employ the bge IP/TCP checksum offload, 4912 * the hardware checksum assist gives incorrect results (possibly 4913 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4914 * If we pad such runts with zeros, the onboard checksum comes out correct. 4915 */ 4916 static __inline int 4917 bge_cksum_pad(struct mbuf *m) 4918 { 4919 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4920 struct mbuf *last; 4921 4922 /* If there's only the packet-header and we can pad there, use it. */ 4923 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4924 M_TRAILINGSPACE(m) >= padlen) { 4925 last = m; 4926 } else { 4927 /* 4928 * Walk packet chain to find last mbuf. We will either 4929 * pad there, or append a new mbuf and pad it. 4930 */ 4931 for (last = m; last->m_next != NULL; last = last->m_next); 4932 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4933 /* Allocate new empty mbuf, pad it. Compact later. */ 4934 struct mbuf *n; 4935 4936 MGET(n, M_NOWAIT, MT_DATA); 4937 if (n == NULL) 4938 return (ENOBUFS); 4939 n->m_len = 0; 4940 last->m_next = n; 4941 last = n; 4942 } 4943 } 4944 4945 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4946 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4947 last->m_len += padlen; 4948 m->m_pkthdr.len += padlen; 4949 4950 return (0); 4951 } 4952 4953 static struct mbuf * 4954 bge_check_short_dma(struct mbuf *m) 4955 { 4956 struct mbuf *n; 4957 int found; 4958 4959 /* 4960 * If device receive two back-to-back send BDs with less than 4961 * or equal to 8 total bytes then the device may hang. The two 4962 * back-to-back send BDs must in the same frame for this failure 4963 * to occur. Scan mbuf chains and see whether two back-to-back 4964 * send BDs are there. If this is the case, allocate new mbuf 4965 * and copy the frame to workaround the silicon bug. 4966 */ 4967 for (n = m, found = 0; n != NULL; n = n->m_next) { 4968 if (n->m_len < 8) { 4969 found++; 4970 if (found > 1) 4971 break; 4972 continue; 4973 } 4974 found = 0; 4975 } 4976 4977 if (found > 1) { 4978 n = m_defrag(m, M_NOWAIT); 4979 if (n == NULL) 4980 m_freem(m); 4981 } else 4982 n = m; 4983 return (n); 4984 } 4985 4986 static struct mbuf * 4987 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 4988 uint16_t *flags) 4989 { 4990 struct ip *ip; 4991 struct tcphdr *tcp; 4992 struct mbuf *n; 4993 uint16_t hlen; 4994 uint32_t poff; 4995 4996 if (M_WRITABLE(m) == 0) { 4997 /* Get a writable copy. */ 4998 n = m_dup(m, M_NOWAIT); 4999 m_freem(m); 5000 if (n == NULL) 5001 return (NULL); 5002 m = n; 5003 } 5004 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5005 if (m == NULL) 5006 return (NULL); 5007 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5008 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5009 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5010 if (m == NULL) 5011 return (NULL); 5012 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5013 m = m_pullup(m, poff + (tcp->th_off << 2)); 5014 if (m == NULL) 5015 return (NULL); 5016 /* 5017 * It seems controller doesn't modify IP length and TCP pseudo 5018 * checksum. These checksum computed by upper stack should be 0. 5019 */ 5020 *mss = m->m_pkthdr.tso_segsz; 5021 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5022 ip->ip_sum = 0; 5023 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5024 /* Clear pseudo checksum computed by TCP stack. */ 5025 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5026 tcp->th_sum = 0; 5027 /* 5028 * Broadcom controllers uses different descriptor format for 5029 * TSO depending on ASIC revision. Due to TSO-capable firmware 5030 * license issue and lower performance of firmware based TSO 5031 * we only support hardware based TSO. 5032 */ 5033 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5034 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5035 if (sc->bge_flags & BGE_FLAG_TSO3) { 5036 /* 5037 * For BCM5717 and newer controllers, hardware based TSO 5038 * uses the 14 lower bits of the bge_mss field to store the 5039 * MSS and the upper 2 bits to store the lowest 2 bits of 5040 * the IP/TCP header length. The upper 6 bits of the header 5041 * length are stored in the bge_flags[14:10,4] field. Jumbo 5042 * frames are supported. 5043 */ 5044 *mss |= ((hlen & 0x3) << 14); 5045 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5046 } else { 5047 /* 5048 * For BCM5755 and newer controllers, hardware based TSO uses 5049 * the lower 11 bits to store the MSS and the upper 5 bits to 5050 * store the IP/TCP header length. Jumbo frames are not 5051 * supported. 5052 */ 5053 *mss |= (hlen << 11); 5054 } 5055 return (m); 5056 } 5057 5058 /* 5059 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5060 * pointers to descriptors. 5061 */ 5062 static int 5063 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5064 { 5065 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5066 bus_dmamap_t map; 5067 struct bge_tx_bd *d; 5068 struct mbuf *m = *m_head; 5069 uint32_t idx = *txidx; 5070 uint16_t csum_flags, mss, vlan_tag; 5071 int nsegs, i, error; 5072 5073 csum_flags = 0; 5074 mss = 0; 5075 vlan_tag = 0; 5076 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5077 m->m_next != NULL) { 5078 *m_head = bge_check_short_dma(m); 5079 if (*m_head == NULL) 5080 return (ENOBUFS); 5081 m = *m_head; 5082 } 5083 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5084 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5085 if (*m_head == NULL) 5086 return (ENOBUFS); 5087 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5088 BGE_TXBDFLAG_CPU_POST_DMA; 5089 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5090 if (m->m_pkthdr.csum_flags & CSUM_IP) 5091 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5092 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5093 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5094 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5095 (error = bge_cksum_pad(m)) != 0) { 5096 m_freem(m); 5097 *m_head = NULL; 5098 return (error); 5099 } 5100 } 5101 } 5102 5103 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5104 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5105 m->m_pkthdr.len > ETHER_MAX_LEN) 5106 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5107 if (sc->bge_forced_collapse > 0 && 5108 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5109 /* 5110 * Forcedly collapse mbuf chains to overcome hardware 5111 * limitation which only support a single outstanding 5112 * DMA read operation. 5113 */ 5114 if (sc->bge_forced_collapse == 1) 5115 m = m_defrag(m, M_NOWAIT); 5116 else 5117 m = m_collapse(m, M_NOWAIT, 5118 sc->bge_forced_collapse); 5119 if (m == NULL) 5120 m = *m_head; 5121 *m_head = m; 5122 } 5123 } 5124 5125 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5126 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5127 &nsegs, BUS_DMA_NOWAIT); 5128 if (error == EFBIG) { 5129 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5130 if (m == NULL) { 5131 m_freem(*m_head); 5132 *m_head = NULL; 5133 return (ENOBUFS); 5134 } 5135 *m_head = m; 5136 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5137 m, segs, &nsegs, BUS_DMA_NOWAIT); 5138 if (error) { 5139 m_freem(m); 5140 *m_head = NULL; 5141 return (error); 5142 } 5143 } else if (error != 0) 5144 return (error); 5145 5146 /* Check if we have enough free send BDs. */ 5147 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5148 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5149 return (ENOBUFS); 5150 } 5151 5152 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5153 5154 if (m->m_flags & M_VLANTAG) { 5155 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5156 vlan_tag = m->m_pkthdr.ether_vtag; 5157 } 5158 for (i = 0; ; i++) { 5159 d = &sc->bge_ldata.bge_tx_ring[idx]; 5160 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5161 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5162 d->bge_len = segs[i].ds_len; 5163 d->bge_flags = csum_flags; 5164 d->bge_vlan_tag = vlan_tag; 5165 d->bge_mss = mss; 5166 if (i == nsegs - 1) 5167 break; 5168 BGE_INC(idx, BGE_TX_RING_CNT); 5169 } 5170 5171 /* Mark the last segment as end of packet... */ 5172 d->bge_flags |= BGE_TXBDFLAG_END; 5173 5174 /* 5175 * Insure that the map for this transmission 5176 * is placed at the array index of the last descriptor 5177 * in this chain. 5178 */ 5179 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5180 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5181 sc->bge_cdata.bge_tx_chain[idx] = m; 5182 sc->bge_txcnt += nsegs; 5183 5184 BGE_INC(idx, BGE_TX_RING_CNT); 5185 *txidx = idx; 5186 5187 return (0); 5188 } 5189 5190 /* 5191 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5192 * to the mbuf data regions directly in the transmit descriptors. 5193 */ 5194 static void 5195 bge_start_locked(struct ifnet *ifp) 5196 { 5197 struct bge_softc *sc; 5198 struct mbuf *m_head; 5199 uint32_t prodidx; 5200 int count; 5201 5202 sc = ifp->if_softc; 5203 BGE_LOCK_ASSERT(sc); 5204 5205 if (!sc->bge_link || 5206 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5207 IFF_DRV_RUNNING) 5208 return; 5209 5210 prodidx = sc->bge_tx_prodidx; 5211 5212 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 5213 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5214 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5215 break; 5216 } 5217 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 5218 if (m_head == NULL) 5219 break; 5220 5221 /* 5222 * Pack the data into the transmit ring. If we 5223 * don't have room, set the OACTIVE flag and wait 5224 * for the NIC to drain the ring. 5225 */ 5226 if (bge_encap(sc, &m_head, &prodidx)) { 5227 if (m_head == NULL) 5228 break; 5229 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 5230 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5231 break; 5232 } 5233 ++count; 5234 5235 /* 5236 * If there's a BPF listener, bounce a copy of this frame 5237 * to him. 5238 */ 5239 #ifdef ETHER_BPF_MTAP 5240 ETHER_BPF_MTAP(ifp, m_head); 5241 #else 5242 BPF_MTAP(ifp, m_head); 5243 #endif 5244 } 5245 5246 if (count > 0) { 5247 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5248 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5249 /* Transmit. */ 5250 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5251 /* 5700 b2 errata */ 5252 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5253 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5254 5255 sc->bge_tx_prodidx = prodidx; 5256 5257 /* 5258 * Set a timeout in case the chip goes out to lunch. 5259 */ 5260 sc->bge_timer = 5; 5261 } 5262 } 5263 5264 /* 5265 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5266 * to the mbuf data regions directly in the transmit descriptors. 5267 */ 5268 static void 5269 bge_start(struct ifnet *ifp) 5270 { 5271 struct bge_softc *sc; 5272 5273 sc = ifp->if_softc; 5274 BGE_LOCK(sc); 5275 bge_start_locked(ifp); 5276 BGE_UNLOCK(sc); 5277 } 5278 5279 static void 5280 bge_init_locked(struct bge_softc *sc) 5281 { 5282 struct ifnet *ifp; 5283 uint16_t *m; 5284 uint32_t mode; 5285 5286 BGE_LOCK_ASSERT(sc); 5287 5288 ifp = sc->bge_ifp; 5289 5290 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5291 return; 5292 5293 /* Cancel pending I/O and flush buffers. */ 5294 bge_stop(sc); 5295 5296 bge_stop_fw(sc); 5297 bge_sig_pre_reset(sc, BGE_RESET_START); 5298 bge_reset(sc); 5299 bge_sig_legacy(sc, BGE_RESET_START); 5300 bge_sig_post_reset(sc, BGE_RESET_START); 5301 5302 bge_chipinit(sc); 5303 5304 /* 5305 * Init the various state machines, ring 5306 * control blocks and firmware. 5307 */ 5308 if (bge_blockinit(sc)) { 5309 device_printf(sc->bge_dev, "initialization failure\n"); 5310 return; 5311 } 5312 5313 ifp = sc->bge_ifp; 5314 5315 /* Specify MTU. */ 5316 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5317 ETHER_HDR_LEN + ETHER_CRC_LEN + 5318 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5319 5320 /* Load our MAC address. */ 5321 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5322 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5323 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5324 5325 /* Program promiscuous mode. */ 5326 bge_setpromisc(sc); 5327 5328 /* Program multicast filter. */ 5329 bge_setmulti(sc); 5330 5331 /* Program VLAN tag stripping. */ 5332 bge_setvlan(sc); 5333 5334 /* Override UDP checksum offloading. */ 5335 if (sc->bge_forced_udpcsum == 0) 5336 sc->bge_csum_features &= ~CSUM_UDP; 5337 else 5338 sc->bge_csum_features |= CSUM_UDP; 5339 if (ifp->if_capabilities & IFCAP_TXCSUM && 5340 ifp->if_capenable & IFCAP_TXCSUM) { 5341 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 5342 ifp->if_hwassist |= sc->bge_csum_features; 5343 } 5344 5345 /* Init RX ring. */ 5346 if (bge_init_rx_ring_std(sc) != 0) { 5347 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5348 bge_stop(sc); 5349 return; 5350 } 5351 5352 /* 5353 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5354 * memory to insure that the chip has in fact read the first 5355 * entry of the ring. 5356 */ 5357 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5358 uint32_t v, i; 5359 for (i = 0; i < 10; i++) { 5360 DELAY(20); 5361 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5362 if (v == (MCLBYTES - ETHER_ALIGN)) 5363 break; 5364 } 5365 if (i == 10) 5366 device_printf (sc->bge_dev, 5367 "5705 A0 chip failed to load RX ring\n"); 5368 } 5369 5370 /* Init jumbo RX ring. */ 5371 if (BGE_IS_JUMBO_CAPABLE(sc) && 5372 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5373 (MCLBYTES - ETHER_ALIGN)) { 5374 if (bge_init_rx_ring_jumbo(sc) != 0) { 5375 device_printf(sc->bge_dev, 5376 "no memory for jumbo Rx buffers.\n"); 5377 bge_stop(sc); 5378 return; 5379 } 5380 } 5381 5382 /* Init our RX return ring index. */ 5383 sc->bge_rx_saved_considx = 0; 5384 5385 /* Init our RX/TX stat counters. */ 5386 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5387 5388 /* Init TX ring. */ 5389 bge_init_tx_ring(sc); 5390 5391 /* Enable TX MAC state machine lockup fix. */ 5392 mode = CSR_READ_4(sc, BGE_TX_MODE); 5393 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5394 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5395 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 5396 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5397 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5398 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5399 } 5400 /* Turn on transmitter. */ 5401 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5402 DELAY(100); 5403 5404 /* Turn on receiver. */ 5405 mode = CSR_READ_4(sc, BGE_RX_MODE); 5406 if (BGE_IS_5755_PLUS(sc)) 5407 mode |= BGE_RXMODE_IPV6_ENABLE; 5408 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5409 DELAY(10); 5410 5411 /* 5412 * Set the number of good frames to receive after RX MBUF 5413 * Low Watermark has been reached. After the RX MAC receives 5414 * this number of frames, it will drop subsequent incoming 5415 * frames until the MBUF High Watermark is reached. 5416 */ 5417 if (BGE_IS_57765_PLUS(sc)) 5418 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5419 else 5420 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5421 5422 /* Clear MAC statistics. */ 5423 if (BGE_IS_5705_PLUS(sc)) 5424 bge_stats_clear_regs(sc); 5425 5426 /* Tell firmware we're alive. */ 5427 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5428 5429 #ifdef DEVICE_POLLING 5430 /* Disable interrupts if we are polling. */ 5431 if (ifp->if_capenable & IFCAP_POLLING) { 5432 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5433 BGE_PCIMISCCTL_MASK_PCI_INTR); 5434 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5435 } else 5436 #endif 5437 5438 /* Enable host interrupts. */ 5439 { 5440 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5441 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5442 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5443 } 5444 5445 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5446 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5447 5448 bge_ifmedia_upd_locked(ifp); 5449 5450 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5451 } 5452 5453 static void 5454 bge_init(void *xsc) 5455 { 5456 struct bge_softc *sc = xsc; 5457 5458 BGE_LOCK(sc); 5459 bge_init_locked(sc); 5460 BGE_UNLOCK(sc); 5461 } 5462 5463 /* 5464 * Set media options. 5465 */ 5466 static int 5467 bge_ifmedia_upd(struct ifnet *ifp) 5468 { 5469 struct bge_softc *sc = ifp->if_softc; 5470 int res; 5471 5472 BGE_LOCK(sc); 5473 res = bge_ifmedia_upd_locked(ifp); 5474 BGE_UNLOCK(sc); 5475 5476 return (res); 5477 } 5478 5479 static int 5480 bge_ifmedia_upd_locked(struct ifnet *ifp) 5481 { 5482 struct bge_softc *sc = ifp->if_softc; 5483 struct mii_data *mii; 5484 struct mii_softc *miisc; 5485 struct ifmedia *ifm; 5486 5487 BGE_LOCK_ASSERT(sc); 5488 5489 ifm = &sc->bge_ifmedia; 5490 5491 /* If this is a 1000baseX NIC, enable the TBI port. */ 5492 if (sc->bge_flags & BGE_FLAG_TBI) { 5493 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5494 return (EINVAL); 5495 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5496 case IFM_AUTO: 5497 /* 5498 * The BCM5704 ASIC appears to have a special 5499 * mechanism for programming the autoneg 5500 * advertisement registers in TBI mode. 5501 */ 5502 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5503 uint32_t sgdig; 5504 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5505 if (sgdig & BGE_SGDIGSTS_DONE) { 5506 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5507 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5508 sgdig |= BGE_SGDIGCFG_AUTO | 5509 BGE_SGDIGCFG_PAUSE_CAP | 5510 BGE_SGDIGCFG_ASYM_PAUSE; 5511 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5512 sgdig | BGE_SGDIGCFG_SEND); 5513 DELAY(5); 5514 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5515 } 5516 } 5517 break; 5518 case IFM_1000_SX: 5519 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5520 BGE_CLRBIT(sc, BGE_MAC_MODE, 5521 BGE_MACMODE_HALF_DUPLEX); 5522 } else { 5523 BGE_SETBIT(sc, BGE_MAC_MODE, 5524 BGE_MACMODE_HALF_DUPLEX); 5525 } 5526 DELAY(40); 5527 break; 5528 default: 5529 return (EINVAL); 5530 } 5531 return (0); 5532 } 5533 5534 sc->bge_link_evt++; 5535 mii = device_get_softc(sc->bge_miibus); 5536 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5537 PHY_RESET(miisc); 5538 mii_mediachg(mii); 5539 5540 /* 5541 * Force an interrupt so that we will call bge_link_upd 5542 * if needed and clear any pending link state attention. 5543 * Without this we are not getting any further interrupts 5544 * for link state changes and thus will not UP the link and 5545 * not be able to send in bge_start_locked. The only 5546 * way to get things working was to receive a packet and 5547 * get an RX intr. 5548 * bge_tick should help for fiber cards and we might not 5549 * need to do this here if BGE_FLAG_TBI is set but as 5550 * we poll for fiber anyway it should not harm. 5551 */ 5552 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5553 sc->bge_flags & BGE_FLAG_5788) 5554 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5555 else 5556 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5557 5558 return (0); 5559 } 5560 5561 /* 5562 * Report current media status. 5563 */ 5564 static void 5565 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5566 { 5567 struct bge_softc *sc = ifp->if_softc; 5568 struct mii_data *mii; 5569 5570 BGE_LOCK(sc); 5571 5572 if (sc->bge_flags & BGE_FLAG_TBI) { 5573 ifmr->ifm_status = IFM_AVALID; 5574 ifmr->ifm_active = IFM_ETHER; 5575 if (CSR_READ_4(sc, BGE_MAC_STS) & 5576 BGE_MACSTAT_TBI_PCS_SYNCHED) 5577 ifmr->ifm_status |= IFM_ACTIVE; 5578 else { 5579 ifmr->ifm_active |= IFM_NONE; 5580 BGE_UNLOCK(sc); 5581 return; 5582 } 5583 ifmr->ifm_active |= IFM_1000_SX; 5584 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5585 ifmr->ifm_active |= IFM_HDX; 5586 else 5587 ifmr->ifm_active |= IFM_FDX; 5588 BGE_UNLOCK(sc); 5589 return; 5590 } 5591 5592 mii = device_get_softc(sc->bge_miibus); 5593 mii_pollstat(mii); 5594 ifmr->ifm_active = mii->mii_media_active; 5595 ifmr->ifm_status = mii->mii_media_status; 5596 5597 BGE_UNLOCK(sc); 5598 } 5599 5600 static int 5601 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5602 { 5603 struct bge_softc *sc = ifp->if_softc; 5604 struct ifreq *ifr = (struct ifreq *) data; 5605 struct mii_data *mii; 5606 int flags, mask, error = 0; 5607 5608 switch (command) { 5609 case SIOCSIFMTU: 5610 if (BGE_IS_JUMBO_CAPABLE(sc) || 5611 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5612 if (ifr->ifr_mtu < ETHERMIN || 5613 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5614 error = EINVAL; 5615 break; 5616 } 5617 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5618 error = EINVAL; 5619 break; 5620 } 5621 BGE_LOCK(sc); 5622 if (ifp->if_mtu != ifr->ifr_mtu) { 5623 ifp->if_mtu = ifr->ifr_mtu; 5624 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5625 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5626 bge_init_locked(sc); 5627 } 5628 } 5629 BGE_UNLOCK(sc); 5630 break; 5631 case SIOCSIFFLAGS: 5632 BGE_LOCK(sc); 5633 if (ifp->if_flags & IFF_UP) { 5634 /* 5635 * If only the state of the PROMISC flag changed, 5636 * then just use the 'set promisc mode' command 5637 * instead of reinitializing the entire NIC. Doing 5638 * a full re-init means reloading the firmware and 5639 * waiting for it to start up, which may take a 5640 * second or two. Similarly for ALLMULTI. 5641 */ 5642 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5643 flags = ifp->if_flags ^ sc->bge_if_flags; 5644 if (flags & IFF_PROMISC) 5645 bge_setpromisc(sc); 5646 if (flags & IFF_ALLMULTI) 5647 bge_setmulti(sc); 5648 } else 5649 bge_init_locked(sc); 5650 } else { 5651 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5652 bge_stop(sc); 5653 } 5654 } 5655 sc->bge_if_flags = ifp->if_flags; 5656 BGE_UNLOCK(sc); 5657 error = 0; 5658 break; 5659 case SIOCADDMULTI: 5660 case SIOCDELMULTI: 5661 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5662 BGE_LOCK(sc); 5663 bge_setmulti(sc); 5664 BGE_UNLOCK(sc); 5665 error = 0; 5666 } 5667 break; 5668 case SIOCSIFMEDIA: 5669 case SIOCGIFMEDIA: 5670 if (sc->bge_flags & BGE_FLAG_TBI) { 5671 error = ifmedia_ioctl(ifp, ifr, 5672 &sc->bge_ifmedia, command); 5673 } else { 5674 mii = device_get_softc(sc->bge_miibus); 5675 error = ifmedia_ioctl(ifp, ifr, 5676 &mii->mii_media, command); 5677 } 5678 break; 5679 case SIOCSIFCAP: 5680 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5681 #ifdef DEVICE_POLLING 5682 if (mask & IFCAP_POLLING) { 5683 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5684 error = ether_poll_register(bge_poll, ifp); 5685 if (error) 5686 return (error); 5687 BGE_LOCK(sc); 5688 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5689 BGE_PCIMISCCTL_MASK_PCI_INTR); 5690 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5691 ifp->if_capenable |= IFCAP_POLLING; 5692 BGE_UNLOCK(sc); 5693 } else { 5694 error = ether_poll_deregister(ifp); 5695 /* Enable interrupt even in error case */ 5696 BGE_LOCK(sc); 5697 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5698 BGE_PCIMISCCTL_MASK_PCI_INTR); 5699 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5700 ifp->if_capenable &= ~IFCAP_POLLING; 5701 BGE_UNLOCK(sc); 5702 } 5703 } 5704 #endif 5705 if ((mask & IFCAP_TXCSUM) != 0 && 5706 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5707 ifp->if_capenable ^= IFCAP_TXCSUM; 5708 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5709 ifp->if_hwassist |= sc->bge_csum_features; 5710 else 5711 ifp->if_hwassist &= ~sc->bge_csum_features; 5712 } 5713 5714 if ((mask & IFCAP_RXCSUM) != 0 && 5715 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5716 ifp->if_capenable ^= IFCAP_RXCSUM; 5717 5718 if ((mask & IFCAP_TSO4) != 0 && 5719 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5720 ifp->if_capenable ^= IFCAP_TSO4; 5721 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5722 ifp->if_hwassist |= CSUM_TSO; 5723 else 5724 ifp->if_hwassist &= ~CSUM_TSO; 5725 } 5726 5727 if (mask & IFCAP_VLAN_MTU) { 5728 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5729 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5730 bge_init(sc); 5731 } 5732 5733 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5734 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5735 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5736 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5737 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5738 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5739 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5740 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5741 BGE_LOCK(sc); 5742 bge_setvlan(sc); 5743 BGE_UNLOCK(sc); 5744 } 5745 #ifdef VLAN_CAPABILITIES 5746 VLAN_CAPABILITIES(ifp); 5747 #endif 5748 break; 5749 default: 5750 error = ether_ioctl(ifp, command, data); 5751 break; 5752 } 5753 5754 return (error); 5755 } 5756 5757 static void 5758 bge_watchdog(struct bge_softc *sc) 5759 { 5760 struct ifnet *ifp; 5761 5762 BGE_LOCK_ASSERT(sc); 5763 5764 if (sc->bge_timer == 0 || --sc->bge_timer) 5765 return; 5766 5767 ifp = sc->bge_ifp; 5768 5769 if_printf(ifp, "watchdog timeout -- resetting\n"); 5770 5771 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5772 bge_init_locked(sc); 5773 5774 ifp->if_oerrors++; 5775 } 5776 5777 static void 5778 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5779 { 5780 int i; 5781 5782 BGE_CLRBIT(sc, reg, bit); 5783 5784 for (i = 0; i < BGE_TIMEOUT; i++) { 5785 if ((CSR_READ_4(sc, reg) & bit) == 0) 5786 return; 5787 DELAY(100); 5788 } 5789 } 5790 5791 /* 5792 * Stop the adapter and free any mbufs allocated to the 5793 * RX and TX lists. 5794 */ 5795 static void 5796 bge_stop(struct bge_softc *sc) 5797 { 5798 struct ifnet *ifp; 5799 5800 BGE_LOCK_ASSERT(sc); 5801 5802 ifp = sc->bge_ifp; 5803 5804 callout_stop(&sc->bge_stat_ch); 5805 5806 /* Disable host interrupts. */ 5807 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5808 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5809 5810 /* 5811 * Tell firmware we're shutting down. 5812 */ 5813 bge_stop_fw(sc); 5814 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5815 5816 /* 5817 * Disable all of the receiver blocks. 5818 */ 5819 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5820 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5821 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5822 if (BGE_IS_5700_FAMILY(sc)) 5823 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5824 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5825 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5826 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5827 5828 /* 5829 * Disable all of the transmit blocks. 5830 */ 5831 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5832 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5833 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5834 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5835 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5836 if (BGE_IS_5700_FAMILY(sc)) 5837 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5838 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5839 5840 /* 5841 * Shut down all of the memory managers and related 5842 * state machines. 5843 */ 5844 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5845 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5846 if (BGE_IS_5700_FAMILY(sc)) 5847 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5848 5849 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5850 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5851 if (!(BGE_IS_5705_PLUS(sc))) { 5852 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5853 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5854 } 5855 /* Update MAC statistics. */ 5856 if (BGE_IS_5705_PLUS(sc)) 5857 bge_stats_update_regs(sc); 5858 5859 bge_reset(sc); 5860 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 5861 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 5862 5863 /* 5864 * Keep the ASF firmware running if up. 5865 */ 5866 if (sc->bge_asf_mode & ASF_STACKUP) 5867 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5868 else 5869 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5870 5871 /* Free the RX lists. */ 5872 bge_free_rx_ring_std(sc); 5873 5874 /* Free jumbo RX list. */ 5875 if (BGE_IS_JUMBO_CAPABLE(sc)) 5876 bge_free_rx_ring_jumbo(sc); 5877 5878 /* Free TX buffers. */ 5879 bge_free_tx_ring(sc); 5880 5881 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5882 5883 /* Clear MAC's link state (PHY may still have link UP). */ 5884 if (bootverbose && sc->bge_link) 5885 if_printf(sc->bge_ifp, "link DOWN\n"); 5886 sc->bge_link = 0; 5887 5888 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5889 } 5890 5891 /* 5892 * Stop all chip I/O so that the kernel's probe routines don't 5893 * get confused by errant DMAs when rebooting. 5894 */ 5895 static int 5896 bge_shutdown(device_t dev) 5897 { 5898 struct bge_softc *sc; 5899 5900 sc = device_get_softc(dev); 5901 BGE_LOCK(sc); 5902 bge_stop(sc); 5903 BGE_UNLOCK(sc); 5904 5905 return (0); 5906 } 5907 5908 static int 5909 bge_suspend(device_t dev) 5910 { 5911 struct bge_softc *sc; 5912 5913 sc = device_get_softc(dev); 5914 BGE_LOCK(sc); 5915 bge_stop(sc); 5916 BGE_UNLOCK(sc); 5917 5918 return (0); 5919 } 5920 5921 static int 5922 bge_resume(device_t dev) 5923 { 5924 struct bge_softc *sc; 5925 struct ifnet *ifp; 5926 5927 sc = device_get_softc(dev); 5928 BGE_LOCK(sc); 5929 ifp = sc->bge_ifp; 5930 if (ifp->if_flags & IFF_UP) { 5931 bge_init_locked(sc); 5932 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5933 bge_start_locked(ifp); 5934 } 5935 BGE_UNLOCK(sc); 5936 5937 return (0); 5938 } 5939 5940 static void 5941 bge_link_upd(struct bge_softc *sc) 5942 { 5943 struct mii_data *mii; 5944 uint32_t link, status; 5945 5946 BGE_LOCK_ASSERT(sc); 5947 5948 /* Clear 'pending link event' flag. */ 5949 sc->bge_link_evt = 0; 5950 5951 /* 5952 * Process link state changes. 5953 * Grrr. The link status word in the status block does 5954 * not work correctly on the BCM5700 rev AX and BX chips, 5955 * according to all available information. Hence, we have 5956 * to enable MII interrupts in order to properly obtain 5957 * async link changes. Unfortunately, this also means that 5958 * we have to read the MAC status register to detect link 5959 * changes, thereby adding an additional register access to 5960 * the interrupt handler. 5961 * 5962 * XXX: perhaps link state detection procedure used for 5963 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5964 */ 5965 5966 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5967 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5968 status = CSR_READ_4(sc, BGE_MAC_STS); 5969 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5970 mii = device_get_softc(sc->bge_miibus); 5971 mii_pollstat(mii); 5972 if (!sc->bge_link && 5973 mii->mii_media_status & IFM_ACTIVE && 5974 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5975 sc->bge_link++; 5976 if (bootverbose) 5977 if_printf(sc->bge_ifp, "link UP\n"); 5978 } else if (sc->bge_link && 5979 (!(mii->mii_media_status & IFM_ACTIVE) || 5980 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5981 sc->bge_link = 0; 5982 if (bootverbose) 5983 if_printf(sc->bge_ifp, "link DOWN\n"); 5984 } 5985 5986 /* Clear the interrupt. */ 5987 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5988 BGE_EVTENB_MI_INTERRUPT); 5989 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 5990 BRGPHY_MII_ISR); 5991 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 5992 BRGPHY_MII_IMR, BRGPHY_INTRS); 5993 } 5994 return; 5995 } 5996 5997 if (sc->bge_flags & BGE_FLAG_TBI) { 5998 status = CSR_READ_4(sc, BGE_MAC_STS); 5999 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6000 if (!sc->bge_link) { 6001 sc->bge_link++; 6002 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6003 BGE_CLRBIT(sc, BGE_MAC_MODE, 6004 BGE_MACMODE_TBI_SEND_CFGS); 6005 DELAY(40); 6006 } 6007 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6008 if (bootverbose) 6009 if_printf(sc->bge_ifp, "link UP\n"); 6010 if_link_state_change(sc->bge_ifp, 6011 LINK_STATE_UP); 6012 } 6013 } else if (sc->bge_link) { 6014 sc->bge_link = 0; 6015 if (bootverbose) 6016 if_printf(sc->bge_ifp, "link DOWN\n"); 6017 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6018 } 6019 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6020 /* 6021 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6022 * in status word always set. Workaround this bug by reading 6023 * PHY link status directly. 6024 */ 6025 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6026 6027 if (link != sc->bge_link || 6028 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6029 mii = device_get_softc(sc->bge_miibus); 6030 mii_pollstat(mii); 6031 if (!sc->bge_link && 6032 mii->mii_media_status & IFM_ACTIVE && 6033 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6034 sc->bge_link++; 6035 if (bootverbose) 6036 if_printf(sc->bge_ifp, "link UP\n"); 6037 } else if (sc->bge_link && 6038 (!(mii->mii_media_status & IFM_ACTIVE) || 6039 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6040 sc->bge_link = 0; 6041 if (bootverbose) 6042 if_printf(sc->bge_ifp, "link DOWN\n"); 6043 } 6044 } 6045 } else { 6046 /* 6047 * For controllers that call mii_tick, we have to poll 6048 * link status. 6049 */ 6050 mii = device_get_softc(sc->bge_miibus); 6051 mii_pollstat(mii); 6052 bge_miibus_statchg(sc->bge_dev); 6053 } 6054 6055 /* Disable MAC attention when link is up. */ 6056 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6057 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6058 BGE_MACSTAT_LINK_CHANGED); 6059 } 6060 6061 static void 6062 bge_add_sysctls(struct bge_softc *sc) 6063 { 6064 struct sysctl_ctx_list *ctx; 6065 struct sysctl_oid_list *children; 6066 char tn[32]; 6067 int unit; 6068 6069 ctx = device_get_sysctl_ctx(sc->bge_dev); 6070 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6071 6072 #ifdef BGE_REGISTER_DEBUG 6073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6074 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6075 "Debug Information"); 6076 6077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6078 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6079 "MAC Register Read"); 6080 6081 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6082 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6083 "APE Register Read"); 6084 6085 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6086 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6087 "Memory Read"); 6088 6089 #endif 6090 6091 unit = device_get_unit(sc->bge_dev); 6092 /* 6093 * A common design characteristic for many Broadcom client controllers 6094 * is that they only support a single outstanding DMA read operation 6095 * on the PCIe bus. This means that it will take twice as long to fetch 6096 * a TX frame that is split into header and payload buffers as it does 6097 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6098 * these controllers, coalescing buffers to reduce the number of memory 6099 * reads is effective way to get maximum performance(about 940Mbps). 6100 * Without collapsing TX buffers the maximum TCP bulk transfer 6101 * performance is about 850Mbps. However forcing coalescing mbufs 6102 * consumes a lot of CPU cycles, so leave it off by default. 6103 */ 6104 sc->bge_forced_collapse = 0; 6105 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 6106 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 6107 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6108 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 6109 "Number of fragmented TX buffers of a frame allowed before " 6110 "forced collapsing"); 6111 6112 sc->bge_msi = 1; 6113 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 6114 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 6115 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6116 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 6117 6118 /* 6119 * It seems all Broadcom controllers have a bug that can generate UDP 6120 * datagrams with checksum value 0 when TX UDP checksum offloading is 6121 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6122 * Even though the probability of generating such UDP datagrams is 6123 * low, I don't want to see FreeBSD boxes to inject such datagrams 6124 * into network so disable UDP checksum offloading by default. Users 6125 * still override this behavior by setting a sysctl variable, 6126 * dev.bge.0.forced_udpcsum. 6127 */ 6128 sc->bge_forced_udpcsum = 0; 6129 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 6130 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 6131 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6132 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 6133 "Enable UDP checksum offloading even if controller can " 6134 "generate UDP checksum value 0"); 6135 6136 if (BGE_IS_5705_PLUS(sc)) 6137 bge_add_sysctl_stats_regs(sc, ctx, children); 6138 else 6139 bge_add_sysctl_stats(sc, ctx, children); 6140 } 6141 6142 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6143 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6144 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6145 desc) 6146 6147 static void 6148 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6149 struct sysctl_oid_list *parent) 6150 { 6151 struct sysctl_oid *tree; 6152 struct sysctl_oid_list *children, *schildren; 6153 6154 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6155 NULL, "BGE Statistics"); 6156 schildren = children = SYSCTL_CHILDREN(tree); 6157 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6158 children, COSFramesDroppedDueToFilters, 6159 "FramesDroppedDueToFilters"); 6160 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6161 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6162 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6163 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6164 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6165 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6166 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6167 children, ifInDiscards, "InputDiscards"); 6168 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6169 children, ifInErrors, "InputErrors"); 6170 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6171 children, nicRecvThresholdHit, "RecvThresholdHit"); 6172 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6173 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6174 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6175 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6176 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6177 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6178 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6179 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6180 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6181 children, nicRingStatusUpdate, "RingStatusUpdate"); 6182 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6183 children, nicInterrupts, "Interrupts"); 6184 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6185 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6186 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6187 children, nicSendThresholdHit, "SendThresholdHit"); 6188 6189 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6190 NULL, "BGE RX Statistics"); 6191 children = SYSCTL_CHILDREN(tree); 6192 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6193 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6194 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6195 children, rxstats.etherStatsFragments, "Fragments"); 6196 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6197 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6198 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6199 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6200 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6201 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6202 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6203 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6204 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6205 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6206 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6207 children, rxstats.xoffPauseFramesReceived, 6208 "xoffPauseFramesReceived"); 6209 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6210 children, rxstats.macControlFramesReceived, 6211 "ControlFramesReceived"); 6212 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6213 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6214 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6215 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6216 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6217 children, rxstats.etherStatsJabbers, "Jabbers"); 6218 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6219 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6220 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6221 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6222 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6223 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6224 6225 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6226 NULL, "BGE TX Statistics"); 6227 children = SYSCTL_CHILDREN(tree); 6228 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6229 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6230 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6231 children, txstats.etherStatsCollisions, "Collisions"); 6232 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6233 children, txstats.outXonSent, "XonSent"); 6234 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6235 children, txstats.outXoffSent, "XoffSent"); 6236 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6237 children, txstats.flowControlDone, "flowControlDone"); 6238 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6239 children, txstats.dot3StatsInternalMacTransmitErrors, 6240 "InternalMacTransmitErrors"); 6241 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6242 children, txstats.dot3StatsSingleCollisionFrames, 6243 "SingleCollisionFrames"); 6244 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6245 children, txstats.dot3StatsMultipleCollisionFrames, 6246 "MultipleCollisionFrames"); 6247 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6248 children, txstats.dot3StatsDeferredTransmissions, 6249 "DeferredTransmissions"); 6250 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6251 children, txstats.dot3StatsExcessiveCollisions, 6252 "ExcessiveCollisions"); 6253 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6254 children, txstats.dot3StatsLateCollisions, 6255 "LateCollisions"); 6256 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6257 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6258 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6259 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6260 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6261 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6262 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6263 children, txstats.dot3StatsCarrierSenseErrors, 6264 "CarrierSenseErrors"); 6265 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6266 children, txstats.ifOutDiscards, "Discards"); 6267 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6268 children, txstats.ifOutErrors, "Errors"); 6269 } 6270 6271 #undef BGE_SYSCTL_STAT 6272 6273 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6274 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6275 6276 static void 6277 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6278 struct sysctl_oid_list *parent) 6279 { 6280 struct sysctl_oid *tree; 6281 struct sysctl_oid_list *child, *schild; 6282 struct bge_mac_stats *stats; 6283 6284 stats = &sc->bge_mac_stats; 6285 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6286 NULL, "BGE Statistics"); 6287 schild = child = SYSCTL_CHILDREN(tree); 6288 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6289 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6290 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6291 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6292 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6293 &stats->DmaWriteHighPriQueueFull, 6294 "NIC DMA Write High Priority Queue Full"); 6295 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6296 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6297 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6298 &stats->InputDiscards, "Discarded Input Frames"); 6299 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6300 &stats->InputErrors, "Input Errors"); 6301 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6302 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6303 6304 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6305 NULL, "BGE RX Statistics"); 6306 child = SYSCTL_CHILDREN(tree); 6307 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6308 &stats->ifHCInOctets, "Inbound Octets"); 6309 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6310 &stats->etherStatsFragments, "Fragments"); 6311 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6312 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6313 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6314 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6315 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6316 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6317 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6318 &stats->dot3StatsFCSErrors, "FCS Errors"); 6319 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6320 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6321 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6322 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6323 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6324 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6325 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6326 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6327 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6328 &stats->xoffStateEntered, "XOFF State Entered"); 6329 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6330 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6331 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6332 &stats->etherStatsJabbers, "Jabbers"); 6333 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6334 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6335 6336 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6337 NULL, "BGE TX Statistics"); 6338 child = SYSCTL_CHILDREN(tree); 6339 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6340 &stats->ifHCOutOctets, "Outbound Octets"); 6341 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6342 &stats->etherStatsCollisions, "TX Collisions"); 6343 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6344 &stats->outXonSent, "XON Sent"); 6345 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6346 &stats->outXoffSent, "XOFF Sent"); 6347 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6348 &stats->dot3StatsInternalMacTransmitErrors, 6349 "Internal MAC TX Errors"); 6350 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6351 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6352 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6353 &stats->dot3StatsMultipleCollisionFrames, 6354 "Multiple Collision Frames"); 6355 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6356 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6357 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6358 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6359 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6360 &stats->dot3StatsLateCollisions, "Late Collisions"); 6361 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6362 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6363 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6364 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6365 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6366 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6367 } 6368 6369 #undef BGE_SYSCTL_STAT_ADD64 6370 6371 static int 6372 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6373 { 6374 struct bge_softc *sc; 6375 uint32_t result; 6376 int offset; 6377 6378 sc = (struct bge_softc *)arg1; 6379 offset = arg2; 6380 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6381 offsetof(bge_hostaddr, bge_addr_lo)); 6382 return (sysctl_handle_int(oidp, &result, 0, req)); 6383 } 6384 6385 #ifdef BGE_REGISTER_DEBUG 6386 static int 6387 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6388 { 6389 struct bge_softc *sc; 6390 uint16_t *sbdata; 6391 int error, result, sbsz; 6392 int i, j; 6393 6394 result = -1; 6395 error = sysctl_handle_int(oidp, &result, 0, req); 6396 if (error || (req->newptr == NULL)) 6397 return (error); 6398 6399 if (result == 1) { 6400 sc = (struct bge_softc *)arg1; 6401 6402 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6403 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6404 sbsz = BGE_STATUS_BLK_SZ; 6405 else 6406 sbsz = 32; 6407 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6408 printf("Status Block:\n"); 6409 BGE_LOCK(sc); 6410 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6411 sc->bge_cdata.bge_status_map, 6412 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6413 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6414 printf("%06x:", i); 6415 for (j = 0; j < 8; j++) 6416 printf(" %04x", sbdata[i++]); 6417 printf("\n"); 6418 } 6419 6420 printf("Registers:\n"); 6421 for (i = 0x800; i < 0xA00; ) { 6422 printf("%06x:", i); 6423 for (j = 0; j < 8; j++) { 6424 printf(" %08x", CSR_READ_4(sc, i)); 6425 i += 4; 6426 } 6427 printf("\n"); 6428 } 6429 BGE_UNLOCK(sc); 6430 6431 printf("Hardware Flags:\n"); 6432 if (BGE_IS_5717_PLUS(sc)) 6433 printf(" - 5717 Plus\n"); 6434 if (BGE_IS_5755_PLUS(sc)) 6435 printf(" - 5755 Plus\n"); 6436 if (BGE_IS_575X_PLUS(sc)) 6437 printf(" - 575X Plus\n"); 6438 if (BGE_IS_5705_PLUS(sc)) 6439 printf(" - 5705 Plus\n"); 6440 if (BGE_IS_5714_FAMILY(sc)) 6441 printf(" - 5714 Family\n"); 6442 if (BGE_IS_5700_FAMILY(sc)) 6443 printf(" - 5700 Family\n"); 6444 if (sc->bge_flags & BGE_FLAG_JUMBO) 6445 printf(" - Supports Jumbo Frames\n"); 6446 if (sc->bge_flags & BGE_FLAG_PCIX) 6447 printf(" - PCI-X Bus\n"); 6448 if (sc->bge_flags & BGE_FLAG_PCIE) 6449 printf(" - PCI Express Bus\n"); 6450 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6451 printf(" - No 3 LEDs\n"); 6452 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6453 printf(" - RX Alignment Bug\n"); 6454 } 6455 6456 return (error); 6457 } 6458 6459 static int 6460 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6461 { 6462 struct bge_softc *sc; 6463 int error; 6464 uint16_t result; 6465 uint32_t val; 6466 6467 result = -1; 6468 error = sysctl_handle_int(oidp, &result, 0, req); 6469 if (error || (req->newptr == NULL)) 6470 return (error); 6471 6472 if (result < 0x8000) { 6473 sc = (struct bge_softc *)arg1; 6474 val = CSR_READ_4(sc, result); 6475 printf("reg 0x%06X = 0x%08X\n", result, val); 6476 } 6477 6478 return (error); 6479 } 6480 6481 static int 6482 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6483 { 6484 struct bge_softc *sc; 6485 int error; 6486 uint16_t result; 6487 uint32_t val; 6488 6489 result = -1; 6490 error = sysctl_handle_int(oidp, &result, 0, req); 6491 if (error || (req->newptr == NULL)) 6492 return (error); 6493 6494 if (result < 0x8000) { 6495 sc = (struct bge_softc *)arg1; 6496 val = APE_READ_4(sc, result); 6497 printf("reg 0x%06X = 0x%08X\n", result, val); 6498 } 6499 6500 return (error); 6501 } 6502 6503 static int 6504 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6505 { 6506 struct bge_softc *sc; 6507 int error; 6508 uint16_t result; 6509 uint32_t val; 6510 6511 result = -1; 6512 error = sysctl_handle_int(oidp, &result, 0, req); 6513 if (error || (req->newptr == NULL)) 6514 return (error); 6515 6516 if (result < 0x8000) { 6517 sc = (struct bge_softc *)arg1; 6518 val = bge_readmem_ind(sc, result); 6519 printf("mem 0x%06X = 0x%08X\n", result, val); 6520 } 6521 6522 return (error); 6523 } 6524 #endif 6525 6526 static int 6527 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6528 { 6529 6530 if (sc->bge_flags & BGE_FLAG_EADDR) 6531 return (1); 6532 6533 #ifdef __sparc64__ 6534 OF_getetheraddr(sc->bge_dev, ether_addr); 6535 return (0); 6536 #endif 6537 return (1); 6538 } 6539 6540 static int 6541 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6542 { 6543 uint32_t mac_addr; 6544 6545 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6546 if ((mac_addr >> 16) == 0x484b) { 6547 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6548 ether_addr[1] = (uint8_t)mac_addr; 6549 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6550 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6551 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6552 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6553 ether_addr[5] = (uint8_t)mac_addr; 6554 return (0); 6555 } 6556 return (1); 6557 } 6558 6559 static int 6560 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6561 { 6562 int mac_offset = BGE_EE_MAC_OFFSET; 6563 6564 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6565 mac_offset = BGE_EE_MAC_OFFSET_5906; 6566 6567 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6568 ETHER_ADDR_LEN)); 6569 } 6570 6571 static int 6572 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6573 { 6574 6575 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6576 return (1); 6577 6578 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6579 ETHER_ADDR_LEN)); 6580 } 6581 6582 static int 6583 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6584 { 6585 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6586 /* NOTE: Order is critical */ 6587 bge_get_eaddr_fw, 6588 bge_get_eaddr_mem, 6589 bge_get_eaddr_nvram, 6590 bge_get_eaddr_eeprom, 6591 NULL 6592 }; 6593 const bge_eaddr_fcn_t *func; 6594 6595 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6596 if ((*func)(sc, eaddr) == 0) 6597 break; 6598 } 6599 return (*func == NULL ? ENXIO : 0); 6600 } 6601