1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 84 #include <net/if.h> 85 #include <net/if_arp.h> 86 #include <net/ethernet.h> 87 #include <net/if_dl.h> 88 #include <net/if_media.h> 89 90 #include <net/bpf.h> 91 92 #include <net/if_types.h> 93 #include <net/if_vlan_var.h> 94 95 #include <netinet/in_systm.h> 96 #include <netinet/in.h> 97 #include <netinet/ip.h> 98 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 112 #include <dev/bge/if_bgereg.h> 113 114 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 115 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 116 117 MODULE_DEPEND(bge, pci, 1, 1, 1); 118 MODULE_DEPEND(bge, ether, 1, 1, 1); 119 MODULE_DEPEND(bge, miibus, 1, 1, 1); 120 121 /* "device miibus" required. See GENERIC if you get errors here. */ 122 #include "miibus_if.h" 123 124 /* 125 * Various supported device vendors/types and their names. Note: the 126 * spec seems to indicate that the hardware still has Alteon's vendor 127 * ID burned into it, though it will always be overriden by the vendor 128 * ID in the EEPROM. Just to be safe, we cover all possibilities. 129 */ 130 static struct bge_type { 131 uint16_t bge_vid; 132 uint16_t bge_did; 133 } bge_devs[] = { 134 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 135 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 136 137 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 138 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 139 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 140 141 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 142 143 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 145 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 191 192 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 193 194 { TC_VENDORID, TC_DEVICEID_3C996 }, 195 196 { 0, 0 } 197 }; 198 199 static const struct bge_vendor { 200 uint16_t v_id; 201 const char *v_name; 202 } bge_vendors[] = { 203 { ALTEON_VENDORID, "Alteon" }, 204 { ALTIMA_VENDORID, "Altima" }, 205 { APPLE_VENDORID, "Apple" }, 206 { BCOM_VENDORID, "Broadcom" }, 207 { SK_VENDORID, "SysKonnect" }, 208 { TC_VENDORID, "3Com" }, 209 210 { 0, NULL } 211 }; 212 213 static const struct bge_revision { 214 uint32_t br_chipid; 215 const char *br_name; 216 } bge_revisions[] = { 217 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 218 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 219 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 220 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 221 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 222 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 223 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 224 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 225 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 226 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 227 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 228 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 229 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 230 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 231 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 232 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 233 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 234 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 235 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 236 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 237 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 238 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 239 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 240 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 241 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 242 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 243 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 244 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 245 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 246 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 247 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 248 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 249 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 250 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 251 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 252 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 253 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 254 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 255 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 256 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 257 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 258 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 259 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 260 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 261 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 262 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 263 /* 5754 and 5787 share the same ASIC ID */ 264 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 265 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 266 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 267 268 { 0, NULL } 269 }; 270 271 /* 272 * Some defaults for major revisions, so that newer steppings 273 * that we don't know about have a shot at working. 274 */ 275 static const struct bge_revision bge_majorrevs[] = { 276 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 277 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 278 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 279 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 280 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 281 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 282 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 283 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 284 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 285 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 286 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 287 /* 5754 and 5787 share the same ASIC ID */ 288 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 289 290 { 0, NULL } 291 }; 292 293 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 294 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 295 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 296 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 297 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 298 299 const struct bge_revision * bge_lookup_rev(uint32_t); 300 const struct bge_vendor * bge_lookup_vendor(uint16_t); 301 static int bge_probe(device_t); 302 static int bge_attach(device_t); 303 static int bge_detach(device_t); 304 static int bge_suspend(device_t); 305 static int bge_resume(device_t); 306 static void bge_release_resources(struct bge_softc *); 307 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 308 static int bge_dma_alloc(device_t); 309 static void bge_dma_free(struct bge_softc *); 310 311 static void bge_txeof(struct bge_softc *); 312 static void bge_rxeof(struct bge_softc *); 313 314 static void bge_asf_driver_up (struct bge_softc *); 315 static void bge_tick(void *); 316 static void bge_stats_update(struct bge_softc *); 317 static void bge_stats_update_regs(struct bge_softc *); 318 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 319 320 static void bge_intr(void *); 321 static void bge_start_locked(struct ifnet *); 322 static void bge_start(struct ifnet *); 323 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 324 static void bge_init_locked(struct bge_softc *); 325 static void bge_init(void *); 326 static void bge_stop(struct bge_softc *); 327 static void bge_watchdog(struct bge_softc *); 328 static void bge_shutdown(device_t); 329 static int bge_ifmedia_upd_locked(struct ifnet *); 330 static int bge_ifmedia_upd(struct ifnet *); 331 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 332 333 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 334 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 335 336 static void bge_setpromisc(struct bge_softc *); 337 static void bge_setmulti(struct bge_softc *); 338 339 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *); 340 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *); 341 static int bge_init_rx_ring_std(struct bge_softc *); 342 static void bge_free_rx_ring_std(struct bge_softc *); 343 static int bge_init_rx_ring_jumbo(struct bge_softc *); 344 static void bge_free_rx_ring_jumbo(struct bge_softc *); 345 static void bge_free_tx_ring(struct bge_softc *); 346 static int bge_init_tx_ring(struct bge_softc *); 347 348 static int bge_chipinit(struct bge_softc *); 349 static int bge_blockinit(struct bge_softc *); 350 351 static uint32_t bge_readmem_ind(struct bge_softc *, int); 352 static void bge_writemem_ind(struct bge_softc *, int, int); 353 #ifdef notdef 354 static uint32_t bge_readreg_ind(struct bge_softc *, int); 355 #endif 356 static void bge_writemem_direct(struct bge_softc *, int, int); 357 static void bge_writereg_ind(struct bge_softc *, int, int); 358 359 static int bge_miibus_readreg(device_t, int, int); 360 static int bge_miibus_writereg(device_t, int, int, int); 361 static void bge_miibus_statchg(device_t); 362 #ifdef DEVICE_POLLING 363 static void bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 364 #endif 365 366 #define BGE_RESET_START 1 367 #define BGE_RESET_STOP 2 368 static void bge_sig_post_reset(struct bge_softc *, int); 369 static void bge_sig_legacy(struct bge_softc *, int); 370 static void bge_sig_pre_reset(struct bge_softc *, int); 371 static int bge_reset(struct bge_softc *); 372 static void bge_link_upd(struct bge_softc *); 373 374 /* 375 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 376 * leak information to untrusted users. It is also known to cause alignment 377 * traps on certain architectures. 378 */ 379 #ifdef BGE_REGISTER_DEBUG 380 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 381 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 382 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 383 #endif 384 static void bge_add_sysctls(struct bge_softc *); 385 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 386 387 static device_method_t bge_methods[] = { 388 /* Device interface */ 389 DEVMETHOD(device_probe, bge_probe), 390 DEVMETHOD(device_attach, bge_attach), 391 DEVMETHOD(device_detach, bge_detach), 392 DEVMETHOD(device_shutdown, bge_shutdown), 393 DEVMETHOD(device_suspend, bge_suspend), 394 DEVMETHOD(device_resume, bge_resume), 395 396 /* bus interface */ 397 DEVMETHOD(bus_print_child, bus_generic_print_child), 398 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 399 400 /* MII interface */ 401 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 402 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 403 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 404 405 { 0, 0 } 406 }; 407 408 static driver_t bge_driver = { 409 "bge", 410 bge_methods, 411 sizeof(struct bge_softc) 412 }; 413 414 static devclass_t bge_devclass; 415 416 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 417 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 418 419 static int bge_fake_autoneg = 0; 420 static int bge_allow_asf = 1; 421 422 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg); 423 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 424 425 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 426 SYSCTL_INT(_hw_bge, OID_AUTO, fake_autoneg, CTLFLAG_RD, &bge_fake_autoneg, 0, 427 "Enable fake autonegotiation for certain blade systems"); 428 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 429 "Allow ASF mode if available"); 430 431 static uint32_t 432 bge_readmem_ind(struct bge_softc *sc, int off) 433 { 434 device_t dev; 435 uint32_t val; 436 437 dev = sc->bge_dev; 438 439 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 440 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 441 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 442 return (val); 443 } 444 445 static void 446 bge_writemem_ind(struct bge_softc *sc, int off, int val) 447 { 448 device_t dev; 449 450 dev = sc->bge_dev; 451 452 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 453 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 454 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 455 } 456 457 #ifdef notdef 458 static uint32_t 459 bge_readreg_ind(struct bge_softc *sc, int off) 460 { 461 device_t dev; 462 463 dev = sc->bge_dev; 464 465 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 466 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 467 } 468 #endif 469 470 static void 471 bge_writereg_ind(struct bge_softc *sc, int off, int val) 472 { 473 device_t dev; 474 475 dev = sc->bge_dev; 476 477 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 478 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 479 } 480 481 static void 482 bge_writemem_direct(struct bge_softc *sc, int off, int val) 483 { 484 CSR_WRITE_4(sc, off, val); 485 } 486 487 /* 488 * Map a single buffer address. 489 */ 490 491 static void 492 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 493 { 494 struct bge_dmamap_arg *ctx; 495 496 if (error) 497 return; 498 499 ctx = arg; 500 501 if (nseg > ctx->bge_maxsegs) { 502 ctx->bge_maxsegs = 0; 503 return; 504 } 505 506 ctx->bge_busaddr = segs->ds_addr; 507 } 508 509 /* 510 * Read a byte of data stored in the EEPROM at address 'addr.' The 511 * BCM570x supports both the traditional bitbang interface and an 512 * auto access interface for reading the EEPROM. We use the auto 513 * access method. 514 */ 515 static uint8_t 516 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 517 { 518 int i; 519 uint32_t byte = 0; 520 521 /* 522 * Enable use of auto EEPROM access so we can avoid 523 * having to use the bitbang method. 524 */ 525 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 526 527 /* Reset the EEPROM, load the clock period. */ 528 CSR_WRITE_4(sc, BGE_EE_ADDR, 529 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 530 DELAY(20); 531 532 /* Issue the read EEPROM command. */ 533 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 534 535 /* Wait for completion */ 536 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 537 DELAY(10); 538 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 539 break; 540 } 541 542 if (i == BGE_TIMEOUT) { 543 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 544 return (1); 545 } 546 547 /* Get result. */ 548 byte = CSR_READ_4(sc, BGE_EE_DATA); 549 550 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 551 552 return (0); 553 } 554 555 /* 556 * Read a sequence of bytes from the EEPROM. 557 */ 558 static int 559 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 560 { 561 int i, error = 0; 562 uint8_t byte = 0; 563 564 for (i = 0; i < cnt; i++) { 565 error = bge_eeprom_getbyte(sc, off + i, &byte); 566 if (error) 567 break; 568 *(dest + i) = byte; 569 } 570 571 return (error ? 1 : 0); 572 } 573 574 static int 575 bge_miibus_readreg(device_t dev, int phy, int reg) 576 { 577 struct bge_softc *sc; 578 uint32_t val, autopoll; 579 int i; 580 581 sc = device_get_softc(dev); 582 583 /* 584 * Broadcom's own driver always assumes the internal 585 * PHY is at GMII address 1. On some chips, the PHY responds 586 * to accesses at all addresses, which could cause us to 587 * bogusly attach the PHY 32 times at probe type. Always 588 * restricting the lookup to address 1 is simpler than 589 * trying to figure out which chips revisions should be 590 * special-cased. 591 */ 592 if (phy != 1) 593 return (0); 594 595 /* Reading with autopolling on may trigger PCI errors */ 596 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 597 if (autopoll & BGE_MIMODE_AUTOPOLL) { 598 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 599 DELAY(40); 600 } 601 602 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 603 BGE_MIPHY(phy) | BGE_MIREG(reg)); 604 605 for (i = 0; i < BGE_TIMEOUT; i++) { 606 val = CSR_READ_4(sc, BGE_MI_COMM); 607 if (!(val & BGE_MICOMM_BUSY)) 608 break; 609 } 610 611 if (i == BGE_TIMEOUT) { 612 device_printf(sc->bge_dev, "PHY read timed out\n"); 613 val = 0; 614 goto done; 615 } 616 617 val = CSR_READ_4(sc, BGE_MI_COMM); 618 619 done: 620 if (autopoll & BGE_MIMODE_AUTOPOLL) { 621 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 622 DELAY(40); 623 } 624 625 if (val & BGE_MICOMM_READFAIL) 626 return (0); 627 628 return (val & 0xFFFF); 629 } 630 631 static int 632 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 633 { 634 struct bge_softc *sc; 635 uint32_t autopoll; 636 int i; 637 638 sc = device_get_softc(dev); 639 640 /* Reading with autopolling on may trigger PCI errors */ 641 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 642 if (autopoll & BGE_MIMODE_AUTOPOLL) { 643 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 644 DELAY(40); 645 } 646 647 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 648 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 649 650 for (i = 0; i < BGE_TIMEOUT; i++) { 651 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 652 break; 653 } 654 655 if (autopoll & BGE_MIMODE_AUTOPOLL) { 656 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 657 DELAY(40); 658 } 659 660 if (i == BGE_TIMEOUT) { 661 device_printf(sc->bge_dev, "PHY read timed out\n"); 662 return (0); 663 } 664 665 return (0); 666 } 667 668 static void 669 bge_miibus_statchg(device_t dev) 670 { 671 struct bge_softc *sc; 672 struct mii_data *mii; 673 sc = device_get_softc(dev); 674 mii = device_get_softc(sc->bge_miibus); 675 676 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 677 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 678 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 679 else 680 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 681 682 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 683 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 684 else 685 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 686 } 687 688 /* 689 * Intialize a standard receive ring descriptor. 690 */ 691 static int 692 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m) 693 { 694 struct mbuf *m_new = NULL; 695 struct bge_rx_bd *r; 696 struct bge_dmamap_arg ctx; 697 int error; 698 699 if (m == NULL) { 700 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 701 if (m_new == NULL) 702 return (ENOBUFS); 703 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 704 } else { 705 m_new = m; 706 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 707 m_new->m_data = m_new->m_ext.ext_buf; 708 } 709 710 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 711 m_adj(m_new, ETHER_ALIGN); 712 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 713 r = &sc->bge_ldata.bge_rx_std_ring[i]; 714 ctx.bge_maxsegs = 1; 715 ctx.sc = sc; 716 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 717 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 718 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 719 if (error || ctx.bge_maxsegs == 0) { 720 if (m == NULL) { 721 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 722 m_freem(m_new); 723 } 724 return (ENOMEM); 725 } 726 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr); 727 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr); 728 r->bge_flags = BGE_RXBDFLAG_END; 729 r->bge_len = m_new->m_len; 730 r->bge_idx = i; 731 732 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 733 sc->bge_cdata.bge_rx_std_dmamap[i], 734 BUS_DMASYNC_PREREAD); 735 736 return (0); 737 } 738 739 /* 740 * Initialize a jumbo receive ring descriptor. This allocates 741 * a jumbo buffer from the pool managed internally by the driver. 742 */ 743 static int 744 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m) 745 { 746 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 747 struct bge_extrx_bd *r; 748 struct mbuf *m_new = NULL; 749 int nsegs; 750 int error; 751 752 if (m == NULL) { 753 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 754 if (m_new == NULL) 755 return (ENOBUFS); 756 757 m_cljget(m_new, M_DONTWAIT, MJUM9BYTES); 758 if (!(m_new->m_flags & M_EXT)) { 759 m_freem(m_new); 760 return (ENOBUFS); 761 } 762 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 763 } else { 764 m_new = m; 765 m_new->m_len = m_new->m_pkthdr.len = MJUM9BYTES; 766 m_new->m_data = m_new->m_ext.ext_buf; 767 } 768 769 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 770 m_adj(m_new, ETHER_ALIGN); 771 772 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 773 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 774 m_new, segs, &nsegs, BUS_DMA_NOWAIT); 775 if (error) { 776 if (m == NULL) 777 m_freem(m_new); 778 return (error); 779 } 780 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 781 782 /* 783 * Fill in the extended RX buffer descriptor. 784 */ 785 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 786 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 787 r->bge_idx = i; 788 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 789 switch (nsegs) { 790 case 4: 791 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 792 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 793 r->bge_len3 = segs[3].ds_len; 794 case 3: 795 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 796 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 797 r->bge_len2 = segs[2].ds_len; 798 case 2: 799 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 800 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 801 r->bge_len1 = segs[1].ds_len; 802 case 1: 803 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 804 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 805 r->bge_len0 = segs[0].ds_len; 806 break; 807 default: 808 panic("%s: %d segments\n", __func__, nsegs); 809 } 810 811 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 812 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 813 BUS_DMASYNC_PREREAD); 814 815 return (0); 816 } 817 818 /* 819 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 820 * that's 1MB or memory, which is a lot. For now, we fill only the first 821 * 256 ring entries and hope that our CPU is fast enough to keep up with 822 * the NIC. 823 */ 824 static int 825 bge_init_rx_ring_std(struct bge_softc *sc) 826 { 827 int i; 828 829 for (i = 0; i < BGE_SSLOTS; i++) { 830 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 831 return (ENOBUFS); 832 }; 833 834 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 835 sc->bge_cdata.bge_rx_std_ring_map, 836 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 837 838 sc->bge_std = i - 1; 839 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 840 841 return (0); 842 } 843 844 static void 845 bge_free_rx_ring_std(struct bge_softc *sc) 846 { 847 int i; 848 849 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 850 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 851 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 852 sc->bge_cdata.bge_rx_std_dmamap[i], 853 BUS_DMASYNC_POSTREAD); 854 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 855 sc->bge_cdata.bge_rx_std_dmamap[i]); 856 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 857 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 858 } 859 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 860 sizeof(struct bge_rx_bd)); 861 } 862 } 863 864 static int 865 bge_init_rx_ring_jumbo(struct bge_softc *sc) 866 { 867 struct bge_rcb *rcb; 868 int i; 869 870 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 871 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 872 return (ENOBUFS); 873 }; 874 875 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 876 sc->bge_cdata.bge_rx_jumbo_ring_map, 877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 878 879 sc->bge_jumbo = i - 1; 880 881 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 882 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 883 BGE_RCB_FLAG_USE_EXT_RX_BD); 884 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 885 886 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 887 888 return (0); 889 } 890 891 static void 892 bge_free_rx_ring_jumbo(struct bge_softc *sc) 893 { 894 int i; 895 896 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 897 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 898 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 899 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 900 BUS_DMASYNC_POSTREAD); 901 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 902 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 903 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 904 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 905 } 906 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 907 sizeof(struct bge_extrx_bd)); 908 } 909 } 910 911 static void 912 bge_free_tx_ring(struct bge_softc *sc) 913 { 914 int i; 915 916 if (sc->bge_ldata.bge_tx_ring == NULL) 917 return; 918 919 for (i = 0; i < BGE_TX_RING_CNT; i++) { 920 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 921 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 922 sc->bge_cdata.bge_tx_dmamap[i], 923 BUS_DMASYNC_POSTWRITE); 924 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 925 sc->bge_cdata.bge_tx_dmamap[i]); 926 m_freem(sc->bge_cdata.bge_tx_chain[i]); 927 sc->bge_cdata.bge_tx_chain[i] = NULL; 928 } 929 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 930 sizeof(struct bge_tx_bd)); 931 } 932 } 933 934 static int 935 bge_init_tx_ring(struct bge_softc *sc) 936 { 937 sc->bge_txcnt = 0; 938 sc->bge_tx_saved_considx = 0; 939 940 /* Initialize transmit producer index for host-memory send ring. */ 941 sc->bge_tx_prodidx = 0; 942 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 943 944 /* 5700 b2 errata */ 945 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 946 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 947 948 /* NIC-memory send ring not used; initialize to zero. */ 949 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 950 /* 5700 b2 errata */ 951 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 952 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 953 954 return (0); 955 } 956 957 static void 958 bge_setpromisc(struct bge_softc *sc) 959 { 960 struct ifnet *ifp; 961 962 BGE_LOCK_ASSERT(sc); 963 964 ifp = sc->bge_ifp; 965 966 /* Enable or disable promiscuous mode as needed. */ 967 if (ifp->if_flags & IFF_PROMISC) 968 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 969 else 970 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 971 } 972 973 static void 974 bge_setmulti(struct bge_softc *sc) 975 { 976 struct ifnet *ifp; 977 struct ifmultiaddr *ifma; 978 uint32_t hashes[4] = { 0, 0, 0, 0 }; 979 int h, i; 980 981 BGE_LOCK_ASSERT(sc); 982 983 ifp = sc->bge_ifp; 984 985 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 986 for (i = 0; i < 4; i++) 987 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 988 return; 989 } 990 991 /* First, zot all the existing filters. */ 992 for (i = 0; i < 4; i++) 993 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 994 995 /* Now program new ones. */ 996 IF_ADDR_LOCK(ifp); 997 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 998 if (ifma->ifma_addr->sa_family != AF_LINK) 999 continue; 1000 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1001 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1002 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1003 } 1004 IF_ADDR_UNLOCK(ifp); 1005 1006 for (i = 0; i < 4; i++) 1007 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1008 } 1009 1010 static void 1011 bge_sig_pre_reset(sc, type) 1012 struct bge_softc *sc; 1013 int type; 1014 { 1015 /* 1016 * Some chips don't like this so only do this if ASF is enabled 1017 */ 1018 if (sc->bge_asf_mode) 1019 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1020 1021 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1022 switch (type) { 1023 case BGE_RESET_START: 1024 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1025 break; 1026 case BGE_RESET_STOP: 1027 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1028 break; 1029 } 1030 } 1031 } 1032 1033 static void 1034 bge_sig_post_reset(sc, type) 1035 struct bge_softc *sc; 1036 int type; 1037 { 1038 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1039 switch (type) { 1040 case BGE_RESET_START: 1041 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1042 /* START DONE */ 1043 break; 1044 case BGE_RESET_STOP: 1045 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1046 break; 1047 } 1048 } 1049 } 1050 1051 static void 1052 bge_sig_legacy(sc, type) 1053 struct bge_softc *sc; 1054 int type; 1055 { 1056 if (sc->bge_asf_mode) { 1057 switch (type) { 1058 case BGE_RESET_START: 1059 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1060 break; 1061 case BGE_RESET_STOP: 1062 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1063 break; 1064 } 1065 } 1066 } 1067 1068 void bge_stop_fw(struct bge_softc *); 1069 void 1070 bge_stop_fw(sc) 1071 struct bge_softc *sc; 1072 { 1073 int i; 1074 1075 if (sc->bge_asf_mode) { 1076 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1077 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1078 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1079 1080 for (i = 0; i < 100; i++ ) { 1081 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1082 break; 1083 DELAY(10); 1084 } 1085 } 1086 } 1087 1088 /* 1089 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1090 * self-test results. 1091 */ 1092 static int 1093 bge_chipinit(struct bge_softc *sc) 1094 { 1095 uint32_t dma_rw_ctl; 1096 int i; 1097 1098 /* Set endianness before we access any non-PCI registers. */ 1099 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1100 1101 /* 1102 * Check the 'ROM failed' bit on the RX CPU to see if 1103 * self-tests passed. 1104 */ 1105 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1106 device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n"); 1107 return (ENODEV); 1108 } 1109 1110 /* Clear the MAC control register */ 1111 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1112 1113 /* 1114 * Clear the MAC statistics block in the NIC's 1115 * internal memory. 1116 */ 1117 for (i = BGE_STATS_BLOCK; 1118 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1119 BGE_MEMWIN_WRITE(sc, i, 0); 1120 1121 for (i = BGE_STATUS_BLOCK; 1122 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1123 BGE_MEMWIN_WRITE(sc, i, 0); 1124 1125 /* Set up the PCI DMA control register. */ 1126 if (sc->bge_flags & BGE_FLAG_PCIE) { 1127 /* PCI Express bus */ 1128 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1129 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0xF) | 1130 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x2); 1131 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1132 /* PCI-X bus */ 1133 if (BGE_IS_5714_FAMILY(sc)) { 1134 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD; 1135 dma_rw_ctl &= ~BGE_PCIDMARWCTL_ONEDMA_ATONCE; /* XXX */ 1136 /* XXX magic values, Broadcom-supplied Linux driver */ 1137 dma_rw_ctl |= (1 << 20) | (1 << 18); 1138 if (sc->bge_asicrev == BGE_ASICREV_BCM5780) 1139 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1140 else 1141 dma_rw_ctl |= 1 << 15; 1142 1143 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1144 /* 1145 * The 5704 uses a different encoding of read/write 1146 * watermarks. 1147 */ 1148 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1149 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1150 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3); 1151 else 1152 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1153 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x3) | 1154 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x3) | 1155 0x0F; 1156 1157 /* 1158 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1159 * for hardware bugs. 1160 */ 1161 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1162 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1163 uint32_t tmp; 1164 1165 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1166 if (tmp == 0x6 || tmp == 0x7) 1167 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1168 } 1169 } else 1170 /* Conventional PCI bus */ 1171 dma_rw_ctl = BGE_PCI_READ_CMD | BGE_PCI_WRITE_CMD | 1172 BGE_PCIDMARWCTL_RD_WAT_SHIFT(0x7) | 1173 BGE_PCIDMARWCTL_WR_WAT_SHIFT(0x7) | 1174 0x0F; 1175 1176 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1177 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1178 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1179 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1180 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1181 1182 /* 1183 * Set up general mode register. 1184 */ 1185 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1186 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1187 BGE_MODECTL_TX_NO_PHDR_CSUM); 1188 1189 /* 1190 * Tell the firmware the driver is running 1191 */ 1192 if (sc->bge_asf_mode & ASF_STACKUP) 1193 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1194 1195 /* 1196 * Disable memory write invalidate. Apparently it is not supported 1197 * properly by these devices. 1198 */ 1199 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1200 1201 #ifdef __brokenalpha__ 1202 /* 1203 * Must insure that we do not cross an 8K (bytes) boundary 1204 * for DMA reads. Our highest limit is 1K bytes. This is a 1205 * restriction on some ALPHA platforms with early revision 1206 * 21174 PCI chipsets, such as the AlphaPC 164lx 1207 */ 1208 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1209 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1210 #endif 1211 1212 /* Set the timer prescaler (always 66Mhz) */ 1213 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1214 1215 return (0); 1216 } 1217 1218 static int 1219 bge_blockinit(struct bge_softc *sc) 1220 { 1221 struct bge_rcb *rcb; 1222 bus_size_t vrcb; 1223 bge_hostaddr taddr; 1224 uint32_t val; 1225 int i; 1226 1227 /* 1228 * Initialize the memory window pointer register so that 1229 * we can access the first 32K of internal NIC RAM. This will 1230 * allow us to set up the TX send ring RCBs and the RX return 1231 * ring RCBs, plus other things which live in NIC memory. 1232 */ 1233 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1234 1235 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1236 1237 if (!(BGE_IS_5705_PLUS(sc))) { 1238 /* Configure mbuf memory pool */ 1239 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1240 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1241 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1242 else 1243 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1244 1245 /* Configure DMA resource pool */ 1246 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1247 BGE_DMA_DESCRIPTORS); 1248 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1249 } 1250 1251 /* Configure mbuf pool watermarks */ 1252 if (!(BGE_IS_5705_PLUS(sc))) { 1253 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1254 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1255 } else { 1256 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1257 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1258 } 1259 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1260 1261 /* Configure DMA resource watermarks */ 1262 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1263 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1264 1265 /* Enable buffer manager */ 1266 if (!(BGE_IS_5705_PLUS(sc))) { 1267 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1268 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1269 1270 /* Poll for buffer manager start indication */ 1271 for (i = 0; i < BGE_TIMEOUT; i++) { 1272 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1273 break; 1274 DELAY(10); 1275 } 1276 1277 if (i == BGE_TIMEOUT) { 1278 device_printf(sc->bge_dev, 1279 "buffer manager failed to start\n"); 1280 return (ENXIO); 1281 } 1282 } 1283 1284 /* Enable flow-through queues */ 1285 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1286 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1287 1288 /* Wait until queue initialization is complete */ 1289 for (i = 0; i < BGE_TIMEOUT; i++) { 1290 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1291 break; 1292 DELAY(10); 1293 } 1294 1295 if (i == BGE_TIMEOUT) { 1296 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1297 return (ENXIO); 1298 } 1299 1300 /* Initialize the standard RX ring control block */ 1301 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1302 rcb->bge_hostaddr.bge_addr_lo = 1303 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1304 rcb->bge_hostaddr.bge_addr_hi = 1305 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1306 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1307 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1308 if (BGE_IS_5705_PLUS(sc)) 1309 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1310 else 1311 rcb->bge_maxlen_flags = 1312 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1313 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1314 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1315 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1316 1317 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1318 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1319 1320 /* 1321 * Initialize the jumbo RX ring control block 1322 * We set the 'ring disabled' bit in the flags 1323 * field until we're actually ready to start 1324 * using this ring (i.e. once we set the MTU 1325 * high enough to require it). 1326 */ 1327 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1328 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1329 1330 rcb->bge_hostaddr.bge_addr_lo = 1331 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1332 rcb->bge_hostaddr.bge_addr_hi = 1333 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1334 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1335 sc->bge_cdata.bge_rx_jumbo_ring_map, 1336 BUS_DMASYNC_PREREAD); 1337 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1338 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1339 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1340 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1341 rcb->bge_hostaddr.bge_addr_hi); 1342 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1343 rcb->bge_hostaddr.bge_addr_lo); 1344 1345 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1346 rcb->bge_maxlen_flags); 1347 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1348 1349 /* Set up dummy disabled mini ring RCB */ 1350 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1351 rcb->bge_maxlen_flags = 1352 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1353 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1354 rcb->bge_maxlen_flags); 1355 } 1356 1357 /* 1358 * Set the BD ring replentish thresholds. The recommended 1359 * values are 1/8th the number of descriptors allocated to 1360 * each ring. 1361 * XXX The 5754 requires a lower threshold, so it might be a 1362 * requirement of all 575x family chips. The Linux driver sets 1363 * the lower threshold for all 5705 family chips as well, but there 1364 * are reports that it might not need to be so strict. 1365 */ 1366 if (BGE_IS_5705_PLUS(sc)) 1367 val = 8; 1368 else 1369 val = BGE_STD_RX_RING_CNT / 8; 1370 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1371 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1372 1373 /* 1374 * Disable all unused send rings by setting the 'ring disabled' 1375 * bit in the flags field of all the TX send ring control blocks. 1376 * These are located in NIC memory. 1377 */ 1378 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1379 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1380 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1381 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1382 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1383 vrcb += sizeof(struct bge_rcb); 1384 } 1385 1386 /* Configure TX RCB 0 (we use only the first ring) */ 1387 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1388 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1389 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1390 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1391 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1392 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1393 if (!(BGE_IS_5705_PLUS(sc))) 1394 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1395 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1396 1397 /* Disable all unused RX return rings */ 1398 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1399 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1400 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1401 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1402 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1403 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1404 BGE_RCB_FLAG_RING_DISABLED)); 1405 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1406 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1407 (i * (sizeof(uint64_t))), 0); 1408 vrcb += sizeof(struct bge_rcb); 1409 } 1410 1411 /* Initialize RX ring indexes */ 1412 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1413 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1414 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1415 1416 /* 1417 * Set up RX return ring 0 1418 * Note that the NIC address for RX return rings is 0x00000000. 1419 * The return rings live entirely within the host, so the 1420 * nicaddr field in the RCB isn't used. 1421 */ 1422 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1423 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1424 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1425 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1426 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1427 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1428 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1429 1430 /* Set random backoff seed for TX */ 1431 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1432 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1433 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1434 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1435 BGE_TX_BACKOFF_SEED_MASK); 1436 1437 /* Set inter-packet gap */ 1438 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1439 1440 /* 1441 * Specify which ring to use for packets that don't match 1442 * any RX rules. 1443 */ 1444 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1445 1446 /* 1447 * Configure number of RX lists. One interrupt distribution 1448 * list, sixteen active lists, one bad frames class. 1449 */ 1450 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1451 1452 /* Inialize RX list placement stats mask. */ 1453 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1454 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1455 1456 /* Disable host coalescing until we get it set up */ 1457 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1458 1459 /* Poll to make sure it's shut down. */ 1460 for (i = 0; i < BGE_TIMEOUT; i++) { 1461 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1462 break; 1463 DELAY(10); 1464 } 1465 1466 if (i == BGE_TIMEOUT) { 1467 device_printf(sc->bge_dev, 1468 "host coalescing engine failed to idle\n"); 1469 return (ENXIO); 1470 } 1471 1472 /* Set up host coalescing defaults */ 1473 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1474 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1475 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1476 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1477 if (!(BGE_IS_5705_PLUS(sc))) { 1478 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1479 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1480 } 1481 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1482 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1483 1484 /* Set up address of statistics block */ 1485 if (!(BGE_IS_5705_PLUS(sc))) { 1486 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1487 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1488 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1489 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1490 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1491 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1492 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1493 } 1494 1495 /* Set up address of status block */ 1496 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1497 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1498 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1499 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1500 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1501 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1502 1503 /* Turn on host coalescing state machine */ 1504 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1505 1506 /* Turn on RX BD completion state machine and enable attentions */ 1507 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1508 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1509 1510 /* Turn on RX list placement state machine */ 1511 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1512 1513 /* Turn on RX list selector state machine. */ 1514 if (!(BGE_IS_5705_PLUS(sc))) 1515 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1516 1517 /* Turn on DMA, clear stats */ 1518 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB | 1519 BGE_MACMODE_RXDMA_ENB | BGE_MACMODE_RX_STATS_CLEAR | 1520 BGE_MACMODE_TX_STATS_CLEAR | BGE_MACMODE_RX_STATS_ENB | 1521 BGE_MACMODE_TX_STATS_ENB | BGE_MACMODE_FRMHDR_DMA_ENB | 1522 ((sc->bge_flags & BGE_FLAG_TBI) ? 1523 BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1524 1525 /* Set misc. local control, enable interrupts on attentions */ 1526 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1527 1528 #ifdef notdef 1529 /* Assert GPIO pins for PHY reset */ 1530 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1531 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1532 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1533 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1534 #endif 1535 1536 /* Turn on DMA completion state machine */ 1537 if (!(BGE_IS_5705_PLUS(sc))) 1538 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1539 1540 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1541 1542 /* Enable host coalescing bug fix. */ 1543 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1544 sc->bge_asicrev == BGE_ASICREV_BCM5787) 1545 val |= 1 << 29; 1546 1547 /* Turn on write DMA state machine */ 1548 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1549 1550 /* Turn on read DMA state machine */ 1551 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1552 BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS); 1553 1554 /* Turn on RX data completion state machine */ 1555 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1556 1557 /* Turn on RX BD initiator state machine */ 1558 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1559 1560 /* Turn on RX data and RX BD initiator state machine */ 1561 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1562 1563 /* Turn on Mbuf cluster free state machine */ 1564 if (!(BGE_IS_5705_PLUS(sc))) 1565 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1566 1567 /* Turn on send BD completion state machine */ 1568 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1569 1570 /* Turn on send data completion state machine */ 1571 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1572 1573 /* Turn on send data initiator state machine */ 1574 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1575 1576 /* Turn on send BD initiator state machine */ 1577 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1578 1579 /* Turn on send BD selector state machine */ 1580 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1581 1582 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1583 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1584 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1585 1586 /* ack/clear link change events */ 1587 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1588 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1589 BGE_MACSTAT_LINK_CHANGED); 1590 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1591 1592 /* Enable PHY auto polling (for MII/GMII only) */ 1593 if (sc->bge_flags & BGE_FLAG_TBI) { 1594 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1595 } else { 1596 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1597 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1598 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1599 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1600 BGE_EVTENB_MI_INTERRUPT); 1601 } 1602 1603 /* 1604 * Clear any pending link state attention. 1605 * Otherwise some link state change events may be lost until attention 1606 * is cleared by bge_intr() -> bge_link_upd() sequence. 1607 * It's not necessary on newer BCM chips - perhaps enabling link 1608 * state change attentions implies clearing pending attention. 1609 */ 1610 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1611 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1612 BGE_MACSTAT_LINK_CHANGED); 1613 1614 /* Enable link state change attentions. */ 1615 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1616 1617 return (0); 1618 } 1619 1620 const struct bge_revision * 1621 bge_lookup_rev(uint32_t chipid) 1622 { 1623 const struct bge_revision *br; 1624 1625 for (br = bge_revisions; br->br_name != NULL; br++) { 1626 if (br->br_chipid == chipid) 1627 return (br); 1628 } 1629 1630 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1631 if (br->br_chipid == BGE_ASICREV(chipid)) 1632 return (br); 1633 } 1634 1635 return (NULL); 1636 } 1637 1638 const struct bge_vendor * 1639 bge_lookup_vendor(uint16_t vid) 1640 { 1641 const struct bge_vendor *v; 1642 1643 for (v = bge_vendors; v->v_name != NULL; v++) 1644 if (v->v_id == vid) 1645 return (v); 1646 1647 panic("%s: unknown vendor %d", __func__, vid); 1648 return (NULL); 1649 } 1650 1651 /* 1652 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1653 * against our list and return its name if we find a match. 1654 * 1655 * Note that since the Broadcom controller contains VPD support, we 1656 * try to get the device name string from the controller itself instead 1657 * of the compiled-in string. It guarantees we'll always announce the 1658 * right product name. We fall back to the compiled-in string when 1659 * VPD is unavailable or corrupt. 1660 */ 1661 static int 1662 bge_probe(device_t dev) 1663 { 1664 struct bge_type *t = bge_devs; 1665 struct bge_softc *sc = device_get_softc(dev); 1666 uint16_t vid, did; 1667 1668 sc->bge_dev = dev; 1669 vid = pci_get_vendor(dev); 1670 did = pci_get_device(dev); 1671 while(t->bge_vid != 0) { 1672 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1673 char model[64], buf[96]; 1674 const struct bge_revision *br; 1675 const struct bge_vendor *v; 1676 uint32_t id; 1677 1678 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1679 BGE_PCIMISCCTL_ASICREV; 1680 br = bge_lookup_rev(id); 1681 v = bge_lookup_vendor(vid); 1682 { 1683 #if __FreeBSD_version > 700024 1684 const char *pname; 1685 1686 if (pci_get_vpd_ident(dev, &pname) == 0) 1687 snprintf(model, 64, "%s", pname); 1688 else 1689 #endif 1690 snprintf(model, 64, "%s %s", 1691 v->v_name, 1692 br != NULL ? br->br_name : 1693 "NetXtreme Ethernet Controller"); 1694 } 1695 snprintf(buf, 96, "%s, %sASIC rev. %#04x", model, 1696 br != NULL ? "" : "unknown ", id >> 16); 1697 device_set_desc_copy(dev, buf); 1698 if (pci_get_subvendor(dev) == DELL_VENDORID) 1699 sc->bge_flags |= BGE_FLAG_NO_3LED; 1700 if (did == BCOM_DEVICEID_BCM5755M) 1701 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 1702 return (0); 1703 } 1704 t++; 1705 } 1706 1707 return (ENXIO); 1708 } 1709 1710 static void 1711 bge_dma_free(struct bge_softc *sc) 1712 { 1713 int i; 1714 1715 /* Destroy DMA maps for RX buffers. */ 1716 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1717 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1718 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1719 sc->bge_cdata.bge_rx_std_dmamap[i]); 1720 } 1721 1722 /* Destroy DMA maps for jumbo RX buffers. */ 1723 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1724 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1725 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1726 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1727 } 1728 1729 /* Destroy DMA maps for TX buffers. */ 1730 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1731 if (sc->bge_cdata.bge_tx_dmamap[i]) 1732 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1733 sc->bge_cdata.bge_tx_dmamap[i]); 1734 } 1735 1736 if (sc->bge_cdata.bge_mtag) 1737 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1738 1739 1740 /* Destroy standard RX ring. */ 1741 if (sc->bge_cdata.bge_rx_std_ring_map) 1742 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1743 sc->bge_cdata.bge_rx_std_ring_map); 1744 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 1745 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1746 sc->bge_ldata.bge_rx_std_ring, 1747 sc->bge_cdata.bge_rx_std_ring_map); 1748 1749 if (sc->bge_cdata.bge_rx_std_ring_tag) 1750 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1751 1752 /* Destroy jumbo RX ring. */ 1753 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 1754 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1755 sc->bge_cdata.bge_rx_jumbo_ring_map); 1756 1757 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 1758 sc->bge_ldata.bge_rx_jumbo_ring) 1759 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1760 sc->bge_ldata.bge_rx_jumbo_ring, 1761 sc->bge_cdata.bge_rx_jumbo_ring_map); 1762 1763 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1764 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1765 1766 /* Destroy RX return ring. */ 1767 if (sc->bge_cdata.bge_rx_return_ring_map) 1768 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1769 sc->bge_cdata.bge_rx_return_ring_map); 1770 1771 if (sc->bge_cdata.bge_rx_return_ring_map && 1772 sc->bge_ldata.bge_rx_return_ring) 1773 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1774 sc->bge_ldata.bge_rx_return_ring, 1775 sc->bge_cdata.bge_rx_return_ring_map); 1776 1777 if (sc->bge_cdata.bge_rx_return_ring_tag) 1778 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1779 1780 /* Destroy TX ring. */ 1781 if (sc->bge_cdata.bge_tx_ring_map) 1782 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1783 sc->bge_cdata.bge_tx_ring_map); 1784 1785 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 1786 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1787 sc->bge_ldata.bge_tx_ring, 1788 sc->bge_cdata.bge_tx_ring_map); 1789 1790 if (sc->bge_cdata.bge_tx_ring_tag) 1791 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1792 1793 /* Destroy status block. */ 1794 if (sc->bge_cdata.bge_status_map) 1795 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1796 sc->bge_cdata.bge_status_map); 1797 1798 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 1799 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1800 sc->bge_ldata.bge_status_block, 1801 sc->bge_cdata.bge_status_map); 1802 1803 if (sc->bge_cdata.bge_status_tag) 1804 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1805 1806 /* Destroy statistics block. */ 1807 if (sc->bge_cdata.bge_stats_map) 1808 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1809 sc->bge_cdata.bge_stats_map); 1810 1811 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 1812 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1813 sc->bge_ldata.bge_stats, 1814 sc->bge_cdata.bge_stats_map); 1815 1816 if (sc->bge_cdata.bge_stats_tag) 1817 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1818 1819 /* Destroy the parent tag. */ 1820 if (sc->bge_cdata.bge_parent_tag) 1821 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1822 } 1823 1824 static int 1825 bge_dma_alloc(device_t dev) 1826 { 1827 struct bge_dmamap_arg ctx; 1828 struct bge_softc *sc; 1829 int i, error; 1830 1831 sc = device_get_softc(dev); 1832 1833 /* 1834 * Allocate the parent bus DMA tag appropriate for PCI. 1835 */ 1836 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), /* parent */ 1837 1, 0, /* alignment, boundary */ 1838 BUS_SPACE_MAXADDR, /* lowaddr */ 1839 BUS_SPACE_MAXADDR, /* highaddr */ 1840 NULL, NULL, /* filter, filterarg */ 1841 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1842 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1843 0, /* flags */ 1844 NULL, NULL, /* lockfunc, lockarg */ 1845 &sc->bge_cdata.bge_parent_tag); 1846 1847 if (error != 0) { 1848 device_printf(sc->bge_dev, 1849 "could not allocate parent dma tag\n"); 1850 return (ENOMEM); 1851 } 1852 1853 /* 1854 * Create tag for RX mbufs. 1855 */ 1856 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 1857 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1858 NULL, MCLBYTES * BGE_NSEG_NEW, BGE_NSEG_NEW, MCLBYTES, 1859 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->bge_cdata.bge_mtag); 1860 1861 if (error) { 1862 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1863 return (ENOMEM); 1864 } 1865 1866 /* Create DMA maps for RX buffers. */ 1867 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1868 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1869 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1870 if (error) { 1871 device_printf(sc->bge_dev, 1872 "can't create DMA map for RX\n"); 1873 return (ENOMEM); 1874 } 1875 } 1876 1877 /* Create DMA maps for TX buffers. */ 1878 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1879 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1880 &sc->bge_cdata.bge_tx_dmamap[i]); 1881 if (error) { 1882 device_printf(sc->bge_dev, 1883 "can't create DMA map for RX\n"); 1884 return (ENOMEM); 1885 } 1886 } 1887 1888 /* Create tag for standard RX ring. */ 1889 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1890 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1891 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1892 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1893 1894 if (error) { 1895 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1896 return (ENOMEM); 1897 } 1898 1899 /* Allocate DMA'able memory for standard RX ring. */ 1900 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1901 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1902 &sc->bge_cdata.bge_rx_std_ring_map); 1903 if (error) 1904 return (ENOMEM); 1905 1906 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1907 1908 /* Load the address of the standard RX ring. */ 1909 ctx.bge_maxsegs = 1; 1910 ctx.sc = sc; 1911 1912 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1913 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1914 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1915 1916 if (error) 1917 return (ENOMEM); 1918 1919 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1920 1921 /* Create tags for jumbo mbufs. */ 1922 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1923 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1924 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1925 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 1926 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 1927 if (error) { 1928 device_printf(sc->bge_dev, 1929 "could not allocate jumbo dma tag\n"); 1930 return (ENOMEM); 1931 } 1932 1933 /* Create tag for jumbo RX ring. */ 1934 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1935 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1936 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 1937 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 1938 1939 if (error) { 1940 device_printf(sc->bge_dev, 1941 "could not allocate jumbo ring dma tag\n"); 1942 return (ENOMEM); 1943 } 1944 1945 /* Allocate DMA'able memory for jumbo RX ring. */ 1946 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1947 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 1948 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1949 &sc->bge_cdata.bge_rx_jumbo_ring_map); 1950 if (error) 1951 return (ENOMEM); 1952 1953 /* Load the address of the jumbo RX ring. */ 1954 ctx.bge_maxsegs = 1; 1955 ctx.sc = sc; 1956 1957 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1958 sc->bge_cdata.bge_rx_jumbo_ring_map, 1959 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 1960 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1961 1962 if (error) 1963 return (ENOMEM); 1964 1965 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 1966 1967 /* Create DMA maps for jumbo RX buffers. */ 1968 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1969 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 1970 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1971 if (error) { 1972 device_printf(sc->bge_dev, 1973 "can't create DMA map for jumbo RX\n"); 1974 return (ENOMEM); 1975 } 1976 } 1977 1978 } 1979 1980 /* Create tag for RX return ring. */ 1981 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1982 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1983 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 1984 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 1985 1986 if (error) { 1987 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 1988 return (ENOMEM); 1989 } 1990 1991 /* Allocate DMA'able memory for RX return ring. */ 1992 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 1993 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 1994 &sc->bge_cdata.bge_rx_return_ring_map); 1995 if (error) 1996 return (ENOMEM); 1997 1998 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 1999 BGE_RX_RTN_RING_SZ(sc)); 2000 2001 /* Load the address of the RX return ring. */ 2002 ctx.bge_maxsegs = 1; 2003 ctx.sc = sc; 2004 2005 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2006 sc->bge_cdata.bge_rx_return_ring_map, 2007 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2008 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2009 2010 if (error) 2011 return (ENOMEM); 2012 2013 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2014 2015 /* Create tag for TX ring. */ 2016 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2017 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2018 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2019 &sc->bge_cdata.bge_tx_ring_tag); 2020 2021 if (error) { 2022 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2023 return (ENOMEM); 2024 } 2025 2026 /* Allocate DMA'able memory for TX ring. */ 2027 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2028 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2029 &sc->bge_cdata.bge_tx_ring_map); 2030 if (error) 2031 return (ENOMEM); 2032 2033 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2034 2035 /* Load the address of the TX ring. */ 2036 ctx.bge_maxsegs = 1; 2037 ctx.sc = sc; 2038 2039 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2040 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2041 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2042 2043 if (error) 2044 return (ENOMEM); 2045 2046 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2047 2048 /* Create tag for status block. */ 2049 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2050 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2051 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2052 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2053 2054 if (error) { 2055 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2056 return (ENOMEM); 2057 } 2058 2059 /* Allocate DMA'able memory for status block. */ 2060 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2061 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2062 &sc->bge_cdata.bge_status_map); 2063 if (error) 2064 return (ENOMEM); 2065 2066 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2067 2068 /* Load the address of the status block. */ 2069 ctx.sc = sc; 2070 ctx.bge_maxsegs = 1; 2071 2072 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2073 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2074 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2075 2076 if (error) 2077 return (ENOMEM); 2078 2079 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2080 2081 /* Create tag for statistics block. */ 2082 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2083 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2084 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2085 &sc->bge_cdata.bge_stats_tag); 2086 2087 if (error) { 2088 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2089 return (ENOMEM); 2090 } 2091 2092 /* Allocate DMA'able memory for statistics block. */ 2093 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2094 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2095 &sc->bge_cdata.bge_stats_map); 2096 if (error) 2097 return (ENOMEM); 2098 2099 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2100 2101 /* Load the address of the statstics block. */ 2102 ctx.sc = sc; 2103 ctx.bge_maxsegs = 1; 2104 2105 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2106 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2107 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2108 2109 if (error) 2110 return (ENOMEM); 2111 2112 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2113 2114 return (0); 2115 } 2116 2117 #if __FreeBSD_version > 602105 2118 /* 2119 * Return true if this device has more than one port. 2120 */ 2121 static int 2122 bge_has_multiple_ports(struct bge_softc *sc) 2123 { 2124 device_t dev = sc->bge_dev; 2125 u_int b, s, f, fscan; 2126 2127 b = pci_get_bus(dev); 2128 s = pci_get_slot(dev); 2129 f = pci_get_function(dev); 2130 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2131 if (fscan != f && pci_find_bsf(b, s, fscan) != NULL) 2132 return (1); 2133 return (0); 2134 } 2135 2136 /* 2137 * Return true if MSI can be used with this device. 2138 */ 2139 static int 2140 bge_can_use_msi(struct bge_softc *sc) 2141 { 2142 int can_use_msi = 0; 2143 2144 switch (sc->bge_asicrev) { 2145 case BGE_ASICREV_BCM5714: 2146 /* 2147 * Apparently, MSI doesn't work when this chip is configured 2148 * in single-port mode. 2149 */ 2150 if (bge_has_multiple_ports(sc)) 2151 can_use_msi = 1; 2152 break; 2153 case BGE_ASICREV_BCM5750: 2154 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2155 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2156 can_use_msi = 1; 2157 break; 2158 case BGE_ASICREV_BCM5752: 2159 case BGE_ASICREV_BCM5780: 2160 can_use_msi = 1; 2161 break; 2162 } 2163 return (can_use_msi); 2164 } 2165 #endif 2166 2167 static int 2168 bge_attach(device_t dev) 2169 { 2170 struct ifnet *ifp; 2171 struct bge_softc *sc; 2172 uint32_t hwcfg = 0; 2173 uint32_t mac_tmp = 0; 2174 u_char eaddr[6]; 2175 int error = 0, rid, trys, reg; 2176 2177 sc = device_get_softc(dev); 2178 sc->bge_dev = dev; 2179 2180 /* 2181 * Map control/status registers. 2182 */ 2183 pci_enable_busmaster(dev); 2184 2185 rid = BGE_PCI_BAR0; 2186 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2187 RF_ACTIVE | PCI_RF_DENSE); 2188 2189 if (sc->bge_res == NULL) { 2190 device_printf (sc->bge_dev, "couldn't map memory\n"); 2191 error = ENXIO; 2192 goto fail; 2193 } 2194 2195 sc->bge_btag = rman_get_bustag(sc->bge_res); 2196 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2197 2198 /* Save ASIC rev. */ 2199 2200 sc->bge_chipid = 2201 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2202 BGE_PCIMISCCTL_ASICREV; 2203 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2204 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2205 2206 /* Save chipset family. */ 2207 switch (sc->bge_asicrev) { 2208 case BGE_ASICREV_BCM5700: 2209 case BGE_ASICREV_BCM5701: 2210 case BGE_ASICREV_BCM5703: 2211 case BGE_ASICREV_BCM5704: 2212 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2213 break; 2214 case BGE_ASICREV_BCM5714_A0: 2215 case BGE_ASICREV_BCM5780: 2216 case BGE_ASICREV_BCM5714: 2217 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2218 /* FALLTHRU */ 2219 case BGE_ASICREV_BCM5750: 2220 case BGE_ASICREV_BCM5752: 2221 case BGE_ASICREV_BCM5755: 2222 case BGE_ASICREV_BCM5787: 2223 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2224 /* FALLTHRU */ 2225 case BGE_ASICREV_BCM5705: 2226 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2227 break; 2228 } 2229 2230 /* Set various bug flags. */ 2231 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2232 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2233 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2234 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2235 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2236 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2237 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2238 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2239 if (BGE_IS_5705_PLUS(sc) && 2240 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2241 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2242 sc->bge_asicrev == BGE_ASICREV_BCM5787) 2243 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2244 else 2245 sc->bge_flags |= BGE_FLAG_BER_BUG; 2246 } 2247 2248 /* 2249 * Check if this is a PCI-X or PCI Express device. 2250 */ 2251 #if __FreeBSD_version > 700010 2252 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2253 /* 2254 * Found a PCI Express capabilities register, this 2255 * must be a PCI Express device. 2256 */ 2257 if (reg != 0) 2258 sc->bge_flags |= BGE_FLAG_PCIE; 2259 } else if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) { 2260 if (reg != 0) 2261 sc->bge_flags |= BGE_FLAG_PCIX; 2262 } 2263 2264 #else 2265 if (BGE_IS_5705_PLUS(sc)) { 2266 reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4); 2267 if ((reg & 0xFF) == BGE_PCIE_CAPID) 2268 sc->bge_flags |= BGE_FLAG_PCIE; 2269 } else { 2270 /* 2271 * Check if the device is in PCI-X Mode. 2272 * (This bit is not valid on PCI Express controllers.) 2273 */ 2274 if ((pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 2275 BGE_PCISTATE_PCI_BUSMODE) == 0) 2276 sc->bge_flags |= BGE_FLAG_PCIX; 2277 } 2278 #endif 2279 2280 #if __FreeBSD_version > 602105 2281 { 2282 int msicount; 2283 2284 /* 2285 * Allocate the interrupt, using MSI if possible. These devices 2286 * support 8 MSI messages, but only the first one is used in 2287 * normal operation. 2288 */ 2289 if (bge_can_use_msi(sc)) { 2290 msicount = pci_msi_count(dev); 2291 if (msicount > 1) 2292 msicount = 1; 2293 } else 2294 msicount = 0; 2295 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2296 rid = 1; 2297 sc->bge_flags |= BGE_FLAG_MSI; 2298 } else 2299 rid = 0; 2300 } 2301 #else 2302 rid = 0; 2303 #endif 2304 2305 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2306 RF_SHAREABLE | RF_ACTIVE); 2307 2308 if (sc->bge_irq == NULL) { 2309 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2310 error = ENXIO; 2311 goto fail; 2312 } 2313 2314 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2315 2316 /* Try to reset the chip. */ 2317 if (bge_reset(sc)) { 2318 device_printf(sc->bge_dev, "chip reset failed\n"); 2319 bge_release_resources(sc); 2320 error = ENXIO; 2321 goto fail; 2322 } 2323 2324 sc->bge_asf_mode = 0; 2325 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2326 == BGE_MAGIC_NUMBER)) { 2327 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2328 & BGE_HWCFG_ASF) { 2329 sc->bge_asf_mode |= ASF_ENABLE; 2330 sc->bge_asf_mode |= ASF_STACKUP; 2331 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) { 2332 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2333 } 2334 } 2335 } 2336 2337 /* Try to reset the chip again the nice way. */ 2338 bge_stop_fw(sc); 2339 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2340 if (bge_reset(sc)) { 2341 device_printf(sc->bge_dev, "chip reset failed\n"); 2342 bge_release_resources(sc); 2343 error = ENXIO; 2344 goto fail; 2345 } 2346 2347 bge_sig_legacy(sc, BGE_RESET_STOP); 2348 bge_sig_post_reset(sc, BGE_RESET_STOP); 2349 2350 if (bge_chipinit(sc)) { 2351 device_printf(sc->bge_dev, "chip initialization failed\n"); 2352 bge_release_resources(sc); 2353 error = ENXIO; 2354 goto fail; 2355 } 2356 2357 /* 2358 * Get station address from the EEPROM. 2359 */ 2360 mac_tmp = bge_readmem_ind(sc, 0x0C14); 2361 if ((mac_tmp >> 16) == 0x484B) { 2362 eaddr[0] = (u_char)(mac_tmp >> 8); 2363 eaddr[1] = (u_char)mac_tmp; 2364 mac_tmp = bge_readmem_ind(sc, 0x0C18); 2365 eaddr[2] = (u_char)(mac_tmp >> 24); 2366 eaddr[3] = (u_char)(mac_tmp >> 16); 2367 eaddr[4] = (u_char)(mac_tmp >> 8); 2368 eaddr[5] = (u_char)mac_tmp; 2369 } else if (bge_read_eeprom(sc, eaddr, 2370 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2371 device_printf(sc->bge_dev, "failed to read station address\n"); 2372 bge_release_resources(sc); 2373 error = ENXIO; 2374 goto fail; 2375 } 2376 2377 /* 5705 limits RX return ring to 512 entries. */ 2378 if (BGE_IS_5705_PLUS(sc)) 2379 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2380 else 2381 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2382 2383 if (bge_dma_alloc(dev)) { 2384 device_printf(sc->bge_dev, 2385 "failed to allocate DMA resources\n"); 2386 bge_release_resources(sc); 2387 error = ENXIO; 2388 goto fail; 2389 } 2390 2391 /* Set default tuneable values. */ 2392 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2393 sc->bge_rx_coal_ticks = 150; 2394 sc->bge_tx_coal_ticks = 150; 2395 sc->bge_rx_max_coal_bds = 10; 2396 sc->bge_tx_max_coal_bds = 10; 2397 2398 /* Set up ifnet structure */ 2399 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2400 if (ifp == NULL) { 2401 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2402 bge_release_resources(sc); 2403 error = ENXIO; 2404 goto fail; 2405 } 2406 ifp->if_softc = sc; 2407 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2408 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2409 ifp->if_ioctl = bge_ioctl; 2410 ifp->if_start = bge_start; 2411 ifp->if_init = bge_init; 2412 ifp->if_mtu = ETHERMTU; 2413 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2414 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2415 IFQ_SET_READY(&ifp->if_snd); 2416 ifp->if_hwassist = BGE_CSUM_FEATURES; 2417 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2418 IFCAP_VLAN_MTU; 2419 #ifdef IFCAP_VLAN_HWCSUM 2420 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2421 #endif 2422 ifp->if_capenable = ifp->if_capabilities; 2423 #ifdef DEVICE_POLLING 2424 ifp->if_capabilities |= IFCAP_POLLING; 2425 #endif 2426 2427 /* 2428 * 5700 B0 chips do not support checksumming correctly due 2429 * to hardware bugs. 2430 */ 2431 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2432 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2433 ifp->if_capenable &= IFCAP_HWCSUM; 2434 ifp->if_hwassist = 0; 2435 } 2436 2437 /* 2438 * Figure out what sort of media we have by checking the 2439 * hardware config word in the first 32k of NIC internal memory, 2440 * or fall back to examining the EEPROM if necessary. 2441 * Note: on some BCM5700 cards, this value appears to be unset. 2442 * If that's the case, we have to rely on identifying the NIC 2443 * by its PCI subsystem ID, as we do below for the SysKonnect 2444 * SK-9D41. 2445 */ 2446 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2447 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2448 else { 2449 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2450 sizeof(hwcfg))) { 2451 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2452 bge_release_resources(sc); 2453 error = ENXIO; 2454 goto fail; 2455 } 2456 hwcfg = ntohl(hwcfg); 2457 } 2458 2459 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2460 sc->bge_flags |= BGE_FLAG_TBI; 2461 2462 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2463 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2464 sc->bge_flags |= BGE_FLAG_TBI; 2465 2466 if (sc->bge_flags & BGE_FLAG_TBI) { 2467 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2468 bge_ifmedia_sts); 2469 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2470 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2471 0, NULL); 2472 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2473 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2474 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2475 } else { 2476 /* 2477 * Do transceiver setup and tell the firmware the 2478 * driver is down so we can try to get access the 2479 * probe if ASF is running. Retry a couple of times 2480 * if we get a conflict with the ASF firmware accessing 2481 * the PHY. 2482 */ 2483 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2484 again: 2485 bge_asf_driver_up(sc); 2486 2487 trys = 0; 2488 if (mii_phy_probe(dev, &sc->bge_miibus, 2489 bge_ifmedia_upd, bge_ifmedia_sts)) { 2490 if (trys++ < 4) { 2491 device_printf(sc->bge_dev, "Try again\n"); 2492 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2493 BMCR_RESET); 2494 goto again; 2495 } 2496 2497 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2498 bge_release_resources(sc); 2499 error = ENXIO; 2500 goto fail; 2501 } 2502 2503 /* 2504 * Now tell the firmware we are going up after probing the PHY 2505 */ 2506 if (sc->bge_asf_mode & ASF_STACKUP) 2507 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2508 } 2509 2510 /* 2511 * When using the BCM5701 in PCI-X mode, data corruption has 2512 * been observed in the first few bytes of some received packets. 2513 * Aligning the packet buffer in memory eliminates the corruption. 2514 * Unfortunately, this misaligns the packet payloads. On platforms 2515 * which do not support unaligned accesses, we will realign the 2516 * payloads by copying the received packets. 2517 */ 2518 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2519 sc->bge_flags & BGE_FLAG_PCIX) 2520 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2521 2522 /* 2523 * Call MI attach routine. 2524 */ 2525 ether_ifattach(ifp, eaddr); 2526 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2527 2528 /* 2529 * Hookup IRQ last. 2530 */ 2531 #if __FreeBSD_version > 700030 2532 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2533 NULL, bge_intr, sc, &sc->bge_intrhand); 2534 #else 2535 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2536 bge_intr, sc, &sc->bge_intrhand); 2537 #endif 2538 2539 if (error) { 2540 bge_detach(dev); 2541 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2542 } 2543 2544 bge_add_sysctls(sc); 2545 2546 fail: 2547 return (error); 2548 } 2549 2550 static int 2551 bge_detach(device_t dev) 2552 { 2553 struct bge_softc *sc; 2554 struct ifnet *ifp; 2555 2556 sc = device_get_softc(dev); 2557 ifp = sc->bge_ifp; 2558 2559 #ifdef DEVICE_POLLING 2560 if (ifp->if_capenable & IFCAP_POLLING) 2561 ether_poll_deregister(ifp); 2562 #endif 2563 2564 BGE_LOCK(sc); 2565 bge_stop(sc); 2566 bge_reset(sc); 2567 BGE_UNLOCK(sc); 2568 2569 callout_drain(&sc->bge_stat_ch); 2570 2571 ether_ifdetach(ifp); 2572 2573 if (sc->bge_flags & BGE_FLAG_TBI) { 2574 ifmedia_removeall(&sc->bge_ifmedia); 2575 } else { 2576 bus_generic_detach(dev); 2577 device_delete_child(dev, sc->bge_miibus); 2578 } 2579 2580 bge_release_resources(sc); 2581 2582 return (0); 2583 } 2584 2585 static void 2586 bge_release_resources(struct bge_softc *sc) 2587 { 2588 device_t dev; 2589 2590 dev = sc->bge_dev; 2591 2592 if (sc->bge_intrhand != NULL) 2593 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2594 2595 if (sc->bge_irq != NULL) 2596 bus_release_resource(dev, SYS_RES_IRQ, 2597 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 2598 2599 #if __FreeBSD_version > 602105 2600 if (sc->bge_flags & BGE_FLAG_MSI) 2601 pci_release_msi(dev); 2602 #endif 2603 2604 if (sc->bge_res != NULL) 2605 bus_release_resource(dev, SYS_RES_MEMORY, 2606 BGE_PCI_BAR0, sc->bge_res); 2607 2608 if (sc->bge_ifp != NULL) 2609 if_free(sc->bge_ifp); 2610 2611 bge_dma_free(sc); 2612 2613 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2614 BGE_LOCK_DESTROY(sc); 2615 } 2616 2617 static int 2618 bge_reset(struct bge_softc *sc) 2619 { 2620 device_t dev; 2621 uint32_t cachesize, command, pcistate, reset; 2622 void (*write_op)(struct bge_softc *, int, int); 2623 int i, val = 0; 2624 2625 dev = sc->bge_dev; 2626 2627 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc)) { 2628 if (sc->bge_flags & BGE_FLAG_PCIE) 2629 write_op = bge_writemem_direct; 2630 else 2631 write_op = bge_writemem_ind; 2632 } else 2633 write_op = bge_writereg_ind; 2634 2635 /* Save some important PCI state. */ 2636 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2637 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2638 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2639 2640 pci_write_config(dev, BGE_PCI_MISC_CTL, 2641 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2642 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2643 2644 /* Disable fastboot on controllers that support it. */ 2645 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 2646 sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2647 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2648 if (bootverbose) 2649 device_printf(sc->bge_dev, "Disabling fastboot\n"); 2650 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 2651 } 2652 2653 /* 2654 * Write the magic number to SRAM at offset 0xB50. 2655 * When firmware finishes its initialization it will 2656 * write ~BGE_MAGIC_NUMBER to the same location. 2657 */ 2658 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2659 2660 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 2661 2662 /* XXX: Broadcom Linux driver. */ 2663 if (sc->bge_flags & BGE_FLAG_PCIE) { 2664 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 2665 CSR_WRITE_4(sc, 0x7E2C, 0x20); 2666 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2667 /* Prevent PCIE link training during global reset */ 2668 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 2669 reset |= 1 << 29; 2670 } 2671 } 2672 2673 /* 2674 * Set GPHY Power Down Override to leave GPHY 2675 * powered up in D0 uninitialized. 2676 */ 2677 if (BGE_IS_5705_PLUS(sc)) 2678 reset |= 0x04000000; 2679 2680 /* Issue global reset */ 2681 write_op(sc, BGE_MISC_CFG, reset); 2682 2683 DELAY(1000); 2684 2685 /* XXX: Broadcom Linux driver. */ 2686 if (sc->bge_flags & BGE_FLAG_PCIE) { 2687 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 2688 uint32_t v; 2689 2690 DELAY(500000); /* wait for link training to complete */ 2691 v = pci_read_config(dev, 0xC4, 4); 2692 pci_write_config(dev, 0xC4, v | (1 << 15), 4); 2693 } 2694 /* 2695 * Set PCIE max payload size to 128 bytes and clear error 2696 * status. 2697 */ 2698 pci_write_config(dev, 0xD8, 0xF5000, 4); 2699 } 2700 2701 /* Reset some of the PCI state that got zapped by reset. */ 2702 pci_write_config(dev, BGE_PCI_MISC_CTL, 2703 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 2704 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 2705 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2706 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2707 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 2708 2709 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 2710 if (BGE_IS_5714_FAMILY(sc)) { 2711 uint32_t val; 2712 2713 /* This chip disables MSI on reset. */ 2714 if (sc->bge_flags & BGE_FLAG_MSI) { 2715 val = pci_read_config(dev, BGE_PCI_MSI_CTL, 2); 2716 pci_write_config(dev, BGE_PCI_MSI_CTL, 2717 val | PCIM_MSICTRL_MSI_ENABLE, 2); 2718 val = CSR_READ_4(sc, BGE_MSI_MODE); 2719 CSR_WRITE_4(sc, BGE_MSI_MODE, 2720 val | BGE_MSIMODE_ENABLE); 2721 } 2722 val = CSR_READ_4(sc, BGE_MARB_MODE); 2723 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 2724 } else 2725 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2726 2727 /* 2728 * Poll until we see the 1's complement of the magic number. 2729 * This indicates that the firmware initialization 2730 * is complete. 2731 */ 2732 for (i = 0; i < BGE_TIMEOUT; i++) { 2733 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2734 if (val == ~BGE_MAGIC_NUMBER) 2735 break; 2736 DELAY(10); 2737 } 2738 2739 if (i == BGE_TIMEOUT) { 2740 device_printf(sc->bge_dev, "firmware handshake timed out, " 2741 "found 0x%08x\n", val); 2742 } 2743 2744 /* 2745 * XXX Wait for the value of the PCISTATE register to 2746 * return to its original pre-reset state. This is a 2747 * fairly good indicator of reset completion. If we don't 2748 * wait for the reset to fully complete, trying to read 2749 * from the device's non-PCI registers may yield garbage 2750 * results. 2751 */ 2752 for (i = 0; i < BGE_TIMEOUT; i++) { 2753 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2754 break; 2755 DELAY(10); 2756 } 2757 2758 if (sc->bge_flags & BGE_FLAG_PCIE) { 2759 reset = bge_readmem_ind(sc, 0x7C00); 2760 bge_writemem_ind(sc, 0x7C00, reset | (1 << 25)); 2761 } 2762 2763 /* Fix up byte swapping. */ 2764 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 2765 BGE_MODECTL_BYTESWAP_DATA); 2766 2767 /* Tell the ASF firmware we are up */ 2768 if (sc->bge_asf_mode & ASF_STACKUP) 2769 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2770 2771 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2772 2773 /* 2774 * The 5704 in TBI mode apparently needs some special 2775 * adjustment to insure the SERDES drive level is set 2776 * to 1.2V. 2777 */ 2778 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 2779 sc->bge_flags & BGE_FLAG_TBI) { 2780 uint32_t serdescfg; 2781 2782 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG); 2783 serdescfg = (serdescfg & ~0xFFF) | 0x880; 2784 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg); 2785 } 2786 2787 /* XXX: Broadcom Linux driver. */ 2788 if (sc->bge_flags & BGE_FLAG_PCIE && 2789 sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 2790 uint32_t v; 2791 2792 v = CSR_READ_4(sc, 0x7C00); 2793 CSR_WRITE_4(sc, 0x7C00, v | (1 << 25)); 2794 } 2795 DELAY(10000); 2796 2797 return(0); 2798 } 2799 2800 /* 2801 * Frame reception handling. This is called if there's a frame 2802 * on the receive return list. 2803 * 2804 * Note: we have to be able to handle two possibilities here: 2805 * 1) the frame is from the jumbo receive ring 2806 * 2) the frame is from the standard receive ring 2807 */ 2808 2809 static void 2810 bge_rxeof(struct bge_softc *sc) 2811 { 2812 struct ifnet *ifp; 2813 int stdcnt = 0, jumbocnt = 0; 2814 2815 BGE_LOCK_ASSERT(sc); 2816 2817 /* Nothing to do. */ 2818 if (sc->bge_rx_saved_considx == 2819 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) 2820 return; 2821 2822 ifp = sc->bge_ifp; 2823 2824 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2825 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 2826 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2827 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2828 if (BGE_IS_JUMBO_CAPABLE(sc)) 2829 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2830 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTREAD); 2831 2832 while(sc->bge_rx_saved_considx != 2833 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2834 struct bge_rx_bd *cur_rx; 2835 uint32_t rxidx; 2836 struct mbuf *m = NULL; 2837 uint16_t vlan_tag = 0; 2838 int have_tag = 0; 2839 2840 #ifdef DEVICE_POLLING 2841 if (ifp->if_capenable & IFCAP_POLLING) { 2842 if (sc->rxcycles <= 0) 2843 break; 2844 sc->rxcycles--; 2845 } 2846 #endif 2847 2848 cur_rx = 2849 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2850 2851 rxidx = cur_rx->bge_idx; 2852 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2853 2854 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2855 have_tag = 1; 2856 vlan_tag = cur_rx->bge_vlan_tag; 2857 } 2858 2859 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2860 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2861 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2862 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2863 BUS_DMASYNC_POSTREAD); 2864 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2865 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2866 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2867 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2868 jumbocnt++; 2869 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2870 ifp->if_ierrors++; 2871 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2872 continue; 2873 } 2874 if (bge_newbuf_jumbo(sc, 2875 sc->bge_jumbo, NULL) == ENOBUFS) { 2876 ifp->if_ierrors++; 2877 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2878 continue; 2879 } 2880 } else { 2881 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2882 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2883 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2884 BUS_DMASYNC_POSTREAD); 2885 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2886 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2887 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2888 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2889 stdcnt++; 2890 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2891 ifp->if_ierrors++; 2892 bge_newbuf_std(sc, sc->bge_std, m); 2893 continue; 2894 } 2895 if (bge_newbuf_std(sc, sc->bge_std, 2896 NULL) == ENOBUFS) { 2897 ifp->if_ierrors++; 2898 bge_newbuf_std(sc, sc->bge_std, m); 2899 continue; 2900 } 2901 } 2902 2903 ifp->if_ipackets++; 2904 #ifndef __NO_STRICT_ALIGNMENT 2905 /* 2906 * For architectures with strict alignment we must make sure 2907 * the payload is aligned. 2908 */ 2909 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 2910 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2911 cur_rx->bge_len); 2912 m->m_data += ETHER_ALIGN; 2913 } 2914 #endif 2915 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2916 m->m_pkthdr.rcvif = ifp; 2917 2918 if (ifp->if_capenable & IFCAP_RXCSUM) { 2919 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 2920 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2921 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 2922 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2923 } 2924 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 2925 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 2926 m->m_pkthdr.csum_data = 2927 cur_rx->bge_tcp_udp_csum; 2928 m->m_pkthdr.csum_flags |= 2929 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2930 } 2931 } 2932 2933 /* 2934 * If we received a packet with a vlan tag, 2935 * attach that information to the packet. 2936 */ 2937 if (have_tag) { 2938 #if __FreeBSD_version > 700022 2939 m->m_pkthdr.ether_vtag = vlan_tag; 2940 m->m_flags |= M_VLANTAG; 2941 #else 2942 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 2943 if (m == NULL) 2944 continue; 2945 #endif 2946 } 2947 2948 BGE_UNLOCK(sc); 2949 (*ifp->if_input)(ifp, m); 2950 BGE_LOCK(sc); 2951 } 2952 2953 if (stdcnt > 0) 2954 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2955 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 2956 2957 if (BGE_IS_JUMBO_CAPABLE(sc) && jumbocnt > 0) 2958 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2959 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 2960 2961 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2962 if (stdcnt) 2963 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2964 if (jumbocnt) 2965 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2966 #ifdef notyet 2967 /* 2968 * This register wraps very quickly under heavy packet drops. 2969 * If you need correct statistics, you can enable this check. 2970 */ 2971 if (BGE_IS_5705_PLUS(sc)) 2972 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 2973 #endif 2974 } 2975 2976 static void 2977 bge_txeof(struct bge_softc *sc) 2978 { 2979 struct bge_tx_bd *cur_tx = NULL; 2980 struct ifnet *ifp; 2981 2982 BGE_LOCK_ASSERT(sc); 2983 2984 /* Nothing to do. */ 2985 if (sc->bge_tx_saved_considx == 2986 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) 2987 return; 2988 2989 ifp = sc->bge_ifp; 2990 2991 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 2992 sc->bge_cdata.bge_tx_ring_map, 2993 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2994 /* 2995 * Go through our tx ring and free mbufs for those 2996 * frames that have been sent. 2997 */ 2998 while (sc->bge_tx_saved_considx != 2999 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 3000 uint32_t idx = 0; 3001 3002 idx = sc->bge_tx_saved_considx; 3003 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3004 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3005 ifp->if_opackets++; 3006 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3007 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 3008 sc->bge_cdata.bge_tx_dmamap[idx], 3009 BUS_DMASYNC_POSTWRITE); 3010 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 3011 sc->bge_cdata.bge_tx_dmamap[idx]); 3012 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3013 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3014 } 3015 sc->bge_txcnt--; 3016 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3017 } 3018 3019 if (cur_tx != NULL) 3020 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3021 if (sc->bge_txcnt == 0) 3022 sc->bge_timer = 0; 3023 } 3024 3025 #ifdef DEVICE_POLLING 3026 static void 3027 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3028 { 3029 struct bge_softc *sc = ifp->if_softc; 3030 uint32_t statusword; 3031 3032 BGE_LOCK(sc); 3033 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3034 BGE_UNLOCK(sc); 3035 return; 3036 } 3037 3038 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3039 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3040 3041 statusword = atomic_readandclear_32( 3042 &sc->bge_ldata.bge_status_block->bge_status); 3043 3044 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3045 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3046 3047 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3048 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3049 sc->bge_link_evt++; 3050 3051 if (cmd == POLL_AND_CHECK_STATUS) 3052 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3053 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3054 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3055 bge_link_upd(sc); 3056 3057 sc->rxcycles = count; 3058 bge_rxeof(sc); 3059 bge_txeof(sc); 3060 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3061 bge_start_locked(ifp); 3062 3063 BGE_UNLOCK(sc); 3064 } 3065 #endif /* DEVICE_POLLING */ 3066 3067 static void 3068 bge_intr(void *xsc) 3069 { 3070 struct bge_softc *sc; 3071 struct ifnet *ifp; 3072 uint32_t statusword; 3073 3074 sc = xsc; 3075 3076 BGE_LOCK(sc); 3077 3078 ifp = sc->bge_ifp; 3079 3080 #ifdef DEVICE_POLLING 3081 if (ifp->if_capenable & IFCAP_POLLING) { 3082 BGE_UNLOCK(sc); 3083 return; 3084 } 3085 #endif 3086 3087 /* 3088 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3089 * disable interrupts by writing nonzero like we used to, since with 3090 * our current organization this just gives complications and 3091 * pessimizations for re-enabling interrupts. We used to have races 3092 * instead of the necessary complications. Disabling interrupts 3093 * would just reduce the chance of a status update while we are 3094 * running (by switching to the interrupt-mode coalescence 3095 * parameters), but this chance is already very low so it is more 3096 * efficient to get another interrupt than prevent it. 3097 * 3098 * We do the ack first to ensure another interrupt if there is a 3099 * status update after the ack. We don't check for the status 3100 * changing later because it is more efficient to get another 3101 * interrupt than prevent it, not quite as above (not checking is 3102 * a smaller optimization than not toggling the interrupt enable, 3103 * since checking doesn't involve PCI accesses and toggling require 3104 * the status check). So toggling would probably be a pessimization 3105 * even with MSI. It would only be needed for using a task queue. 3106 */ 3107 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3108 3109 /* 3110 * Do the mandatory PCI flush as well as get the link status. 3111 */ 3112 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3113 3114 /* Make sure the descriptor ring indexes are coherent. */ 3115 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3116 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTREAD); 3117 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3118 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREREAD); 3119 3120 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3121 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3122 statusword || sc->bge_link_evt) 3123 bge_link_upd(sc); 3124 3125 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3126 /* Check RX return ring producer/consumer. */ 3127 bge_rxeof(sc); 3128 3129 /* Check TX ring producer/consumer. */ 3130 bge_txeof(sc); 3131 } 3132 3133 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3134 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3135 bge_start_locked(ifp); 3136 3137 BGE_UNLOCK(sc); 3138 } 3139 3140 static void 3141 bge_asf_driver_up(struct bge_softc *sc) 3142 { 3143 if (sc->bge_asf_mode & ASF_STACKUP) { 3144 /* Send ASF heartbeat aprox. every 2s */ 3145 if (sc->bge_asf_count) 3146 sc->bge_asf_count --; 3147 else { 3148 sc->bge_asf_count = 5; 3149 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3150 BGE_FW_DRV_ALIVE); 3151 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3152 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3153 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3154 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3155 } 3156 } 3157 } 3158 3159 static void 3160 bge_tick(void *xsc) 3161 { 3162 struct bge_softc *sc = xsc; 3163 struct mii_data *mii = NULL; 3164 3165 BGE_LOCK_ASSERT(sc); 3166 3167 /* Synchronize with possible callout reset/stop. */ 3168 if (callout_pending(&sc->bge_stat_ch) || 3169 !callout_active(&sc->bge_stat_ch)) 3170 return; 3171 3172 if (BGE_IS_5705_PLUS(sc)) 3173 bge_stats_update_regs(sc); 3174 else 3175 bge_stats_update(sc); 3176 3177 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3178 mii = device_get_softc(sc->bge_miibus); 3179 /* Don't mess with the PHY in IPMI/ASF mode */ 3180 if (!((sc->bge_asf_mode & ASF_STACKUP) && (sc->bge_link))) 3181 mii_tick(mii); 3182 } else { 3183 /* 3184 * Since in TBI mode auto-polling can't be used we should poll 3185 * link status manually. Here we register pending link event 3186 * and trigger interrupt. 3187 */ 3188 #ifdef DEVICE_POLLING 3189 /* In polling mode we poll link state in bge_poll(). */ 3190 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3191 #endif 3192 { 3193 sc->bge_link_evt++; 3194 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3195 } 3196 } 3197 3198 bge_asf_driver_up(sc); 3199 bge_watchdog(sc); 3200 3201 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3202 } 3203 3204 static void 3205 bge_stats_update_regs(struct bge_softc *sc) 3206 { 3207 struct ifnet *ifp; 3208 3209 ifp = sc->bge_ifp; 3210 3211 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3212 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3213 3214 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3215 } 3216 3217 static void 3218 bge_stats_update(struct bge_softc *sc) 3219 { 3220 struct ifnet *ifp; 3221 bus_size_t stats; 3222 uint32_t cnt; /* current register value */ 3223 3224 ifp = sc->bge_ifp; 3225 3226 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3227 3228 #define READ_STAT(sc, stats, stat) \ 3229 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3230 3231 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3232 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3233 sc->bge_tx_collisions = cnt; 3234 3235 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3236 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3237 sc->bge_rx_discards = cnt; 3238 3239 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3240 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3241 sc->bge_tx_discards = cnt; 3242 3243 #undef READ_STAT 3244 } 3245 3246 /* 3247 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3248 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3249 * but when such padded frames employ the bge IP/TCP checksum offload, 3250 * the hardware checksum assist gives incorrect results (possibly 3251 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3252 * If we pad such runts with zeros, the onboard checksum comes out correct. 3253 */ 3254 static __inline int 3255 bge_cksum_pad(struct mbuf *m) 3256 { 3257 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3258 struct mbuf *last; 3259 3260 /* If there's only the packet-header and we can pad there, use it. */ 3261 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3262 M_TRAILINGSPACE(m) >= padlen) { 3263 last = m; 3264 } else { 3265 /* 3266 * Walk packet chain to find last mbuf. We will either 3267 * pad there, or append a new mbuf and pad it. 3268 */ 3269 for (last = m; last->m_next != NULL; last = last->m_next); 3270 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3271 /* Allocate new empty mbuf, pad it. Compact later. */ 3272 struct mbuf *n; 3273 3274 MGET(n, M_DONTWAIT, MT_DATA); 3275 if (n == NULL) 3276 return (ENOBUFS); 3277 n->m_len = 0; 3278 last->m_next = n; 3279 last = n; 3280 } 3281 } 3282 3283 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3284 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3285 last->m_len += padlen; 3286 m->m_pkthdr.len += padlen; 3287 3288 return (0); 3289 } 3290 3291 /* 3292 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3293 * pointers to descriptors. 3294 */ 3295 static int 3296 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3297 { 3298 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3299 bus_dmamap_t map; 3300 struct bge_tx_bd *d; 3301 struct mbuf *m = *m_head; 3302 uint32_t idx = *txidx; 3303 uint16_t csum_flags; 3304 int nsegs, i, error; 3305 3306 csum_flags = 0; 3307 if (m->m_pkthdr.csum_flags) { 3308 if (m->m_pkthdr.csum_flags & CSUM_IP) 3309 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3310 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3311 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3312 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3313 (error = bge_cksum_pad(m)) != 0) { 3314 m_freem(m); 3315 *m_head = NULL; 3316 return (error); 3317 } 3318 } 3319 if (m->m_flags & M_LASTFRAG) 3320 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3321 else if (m->m_flags & M_FRAG) 3322 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3323 } 3324 3325 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3326 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, segs, 3327 &nsegs, BUS_DMA_NOWAIT); 3328 if (error == EFBIG) { 3329 m = m_defrag(m, M_DONTWAIT); 3330 if (m == NULL) { 3331 m_freem(*m_head); 3332 *m_head = NULL; 3333 return (ENOBUFS); 3334 } 3335 *m_head = m; 3336 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag, map, m, 3337 segs, &nsegs, BUS_DMA_NOWAIT); 3338 if (error) { 3339 m_freem(m); 3340 *m_head = NULL; 3341 return (error); 3342 } 3343 } else if (error != 0) 3344 return (error); 3345 3346 /* 3347 * Sanity check: avoid coming within 16 descriptors 3348 * of the end of the ring. 3349 */ 3350 if (nsegs > (BGE_TX_RING_CNT - sc->bge_txcnt - 16)) { 3351 bus_dmamap_unload(sc->bge_cdata.bge_mtag, map); 3352 return (ENOBUFS); 3353 } 3354 3355 bus_dmamap_sync(sc->bge_cdata.bge_mtag, map, BUS_DMASYNC_PREWRITE); 3356 3357 for (i = 0; ; i++) { 3358 d = &sc->bge_ldata.bge_tx_ring[idx]; 3359 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 3360 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 3361 d->bge_len = segs[i].ds_len; 3362 d->bge_flags = csum_flags; 3363 if (i == nsegs - 1) 3364 break; 3365 BGE_INC(idx, BGE_TX_RING_CNT); 3366 } 3367 3368 /* Mark the last segment as end of packet... */ 3369 d->bge_flags |= BGE_TXBDFLAG_END; 3370 3371 /* ... and put VLAN tag into first segment. */ 3372 d = &sc->bge_ldata.bge_tx_ring[*txidx]; 3373 #if __FreeBSD_version > 700022 3374 if (m->m_flags & M_VLANTAG) { 3375 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3376 d->bge_vlan_tag = m->m_pkthdr.ether_vtag; 3377 } else 3378 d->bge_vlan_tag = 0; 3379 #else 3380 { 3381 struct m_tag *mtag; 3382 3383 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 3384 d->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 3385 d->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 3386 } else 3387 d->bge_vlan_tag = 0; 3388 } 3389 #endif 3390 3391 /* 3392 * Insure that the map for this transmission 3393 * is placed at the array index of the last descriptor 3394 * in this chain. 3395 */ 3396 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 3397 sc->bge_cdata.bge_tx_dmamap[idx] = map; 3398 sc->bge_cdata.bge_tx_chain[idx] = m; 3399 sc->bge_txcnt += nsegs; 3400 3401 BGE_INC(idx, BGE_TX_RING_CNT); 3402 *txidx = idx; 3403 3404 return (0); 3405 } 3406 3407 /* 3408 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3409 * to the mbuf data regions directly in the transmit descriptors. 3410 */ 3411 static void 3412 bge_start_locked(struct ifnet *ifp) 3413 { 3414 struct bge_softc *sc; 3415 struct mbuf *m_head = NULL; 3416 uint32_t prodidx; 3417 int count = 0; 3418 3419 sc = ifp->if_softc; 3420 3421 if (!sc->bge_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3422 return; 3423 3424 prodidx = sc->bge_tx_prodidx; 3425 3426 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3427 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 3428 if (m_head == NULL) 3429 break; 3430 3431 /* 3432 * XXX 3433 * The code inside the if() block is never reached since we 3434 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 3435 * requests to checksum TCP/UDP in a fragmented packet. 3436 * 3437 * XXX 3438 * safety overkill. If this is a fragmented packet chain 3439 * with delayed TCP/UDP checksums, then only encapsulate 3440 * it if we have enough descriptors to handle the entire 3441 * chain at once. 3442 * (paranoia -- may not actually be needed) 3443 */ 3444 if (m_head->m_flags & M_FIRSTFRAG && 3445 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3446 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3447 m_head->m_pkthdr.csum_data + 16) { 3448 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3449 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3450 break; 3451 } 3452 } 3453 3454 /* 3455 * Pack the data into the transmit ring. If we 3456 * don't have room, set the OACTIVE flag and wait 3457 * for the NIC to drain the ring. 3458 */ 3459 if (bge_encap(sc, &m_head, &prodidx)) { 3460 if (m_head == NULL) 3461 break; 3462 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 3463 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3464 break; 3465 } 3466 ++count; 3467 3468 /* 3469 * If there's a BPF listener, bounce a copy of this frame 3470 * to him. 3471 */ 3472 #ifdef ETHER_BPF_MTAP 3473 ETHER_BPF_MTAP(ifp, m_head); 3474 #else 3475 BPF_MTAP(ifp, m_head); 3476 #endif 3477 } 3478 3479 if (count == 0) 3480 /* No packets were dequeued. */ 3481 return; 3482 3483 /* Transmit. */ 3484 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3485 /* 5700 b2 errata */ 3486 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3487 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3488 3489 sc->bge_tx_prodidx = prodidx; 3490 3491 /* 3492 * Set a timeout in case the chip goes out to lunch. 3493 */ 3494 sc->bge_timer = 5; 3495 } 3496 3497 /* 3498 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3499 * to the mbuf data regions directly in the transmit descriptors. 3500 */ 3501 static void 3502 bge_start(struct ifnet *ifp) 3503 { 3504 struct bge_softc *sc; 3505 3506 sc = ifp->if_softc; 3507 BGE_LOCK(sc); 3508 bge_start_locked(ifp); 3509 BGE_UNLOCK(sc); 3510 } 3511 3512 static void 3513 bge_init_locked(struct bge_softc *sc) 3514 { 3515 struct ifnet *ifp; 3516 uint16_t *m; 3517 3518 BGE_LOCK_ASSERT(sc); 3519 3520 ifp = sc->bge_ifp; 3521 3522 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 3523 return; 3524 3525 /* Cancel pending I/O and flush buffers. */ 3526 bge_stop(sc); 3527 3528 bge_stop_fw(sc); 3529 bge_sig_pre_reset(sc, BGE_RESET_START); 3530 bge_reset(sc); 3531 bge_sig_legacy(sc, BGE_RESET_START); 3532 bge_sig_post_reset(sc, BGE_RESET_START); 3533 3534 bge_chipinit(sc); 3535 3536 /* 3537 * Init the various state machines, ring 3538 * control blocks and firmware. 3539 */ 3540 if (bge_blockinit(sc)) { 3541 device_printf(sc->bge_dev, "initialization failure\n"); 3542 return; 3543 } 3544 3545 ifp = sc->bge_ifp; 3546 3547 /* Specify MTU. */ 3548 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3549 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3550 3551 /* Load our MAC address. */ 3552 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 3553 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3554 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3555 3556 /* Program promiscuous mode. */ 3557 bge_setpromisc(sc); 3558 3559 /* Program multicast filter. */ 3560 bge_setmulti(sc); 3561 3562 /* Init RX ring. */ 3563 bge_init_rx_ring_std(sc); 3564 3565 /* 3566 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3567 * memory to insure that the chip has in fact read the first 3568 * entry of the ring. 3569 */ 3570 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3571 uint32_t v, i; 3572 for (i = 0; i < 10; i++) { 3573 DELAY(20); 3574 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3575 if (v == (MCLBYTES - ETHER_ALIGN)) 3576 break; 3577 } 3578 if (i == 10) 3579 device_printf (sc->bge_dev, 3580 "5705 A0 chip failed to load RX ring\n"); 3581 } 3582 3583 /* Init jumbo RX ring. */ 3584 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3585 bge_init_rx_ring_jumbo(sc); 3586 3587 /* Init our RX return ring index. */ 3588 sc->bge_rx_saved_considx = 0; 3589 3590 /* Init our RX/TX stat counters. */ 3591 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 3592 3593 /* Init TX ring. */ 3594 bge_init_tx_ring(sc); 3595 3596 /* Turn on transmitter. */ 3597 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3598 3599 /* Turn on receiver. */ 3600 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3601 3602 /* Tell firmware we're alive. */ 3603 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3604 3605 #ifdef DEVICE_POLLING 3606 /* Disable interrupts if we are polling. */ 3607 if (ifp->if_capenable & IFCAP_POLLING) { 3608 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3609 BGE_PCIMISCCTL_MASK_PCI_INTR); 3610 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3611 } else 3612 #endif 3613 3614 /* Enable host interrupts. */ 3615 { 3616 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3617 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3618 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3619 } 3620 3621 bge_ifmedia_upd_locked(ifp); 3622 3623 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3624 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3625 3626 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3627 } 3628 3629 static void 3630 bge_init(void *xsc) 3631 { 3632 struct bge_softc *sc = xsc; 3633 3634 BGE_LOCK(sc); 3635 bge_init_locked(sc); 3636 BGE_UNLOCK(sc); 3637 } 3638 3639 /* 3640 * Set media options. 3641 */ 3642 static int 3643 bge_ifmedia_upd(struct ifnet *ifp) 3644 { 3645 struct bge_softc *sc = ifp->if_softc; 3646 int res; 3647 3648 BGE_LOCK(sc); 3649 res = bge_ifmedia_upd_locked(ifp); 3650 BGE_UNLOCK(sc); 3651 3652 return (res); 3653 } 3654 3655 static int 3656 bge_ifmedia_upd_locked(struct ifnet *ifp) 3657 { 3658 struct bge_softc *sc = ifp->if_softc; 3659 struct mii_data *mii; 3660 struct ifmedia *ifm; 3661 3662 BGE_LOCK_ASSERT(sc); 3663 3664 ifm = &sc->bge_ifmedia; 3665 3666 /* If this is a 1000baseX NIC, enable the TBI port. */ 3667 if (sc->bge_flags & BGE_FLAG_TBI) { 3668 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3669 return (EINVAL); 3670 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3671 case IFM_AUTO: 3672 /* 3673 * The BCM5704 ASIC appears to have a special 3674 * mechanism for programming the autoneg 3675 * advertisement registers in TBI mode. 3676 */ 3677 if (bge_fake_autoneg == 0 && 3678 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3679 uint32_t sgdig; 3680 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 3681 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 3682 sgdig |= BGE_SGDIGCFG_AUTO | 3683 BGE_SGDIGCFG_PAUSE_CAP | 3684 BGE_SGDIGCFG_ASYM_PAUSE; 3685 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 3686 sgdig | BGE_SGDIGCFG_SEND); 3687 DELAY(5); 3688 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 3689 } 3690 break; 3691 case IFM_1000_SX: 3692 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3693 BGE_CLRBIT(sc, BGE_MAC_MODE, 3694 BGE_MACMODE_HALF_DUPLEX); 3695 } else { 3696 BGE_SETBIT(sc, BGE_MAC_MODE, 3697 BGE_MACMODE_HALF_DUPLEX); 3698 } 3699 break; 3700 default: 3701 return (EINVAL); 3702 } 3703 return (0); 3704 } 3705 3706 sc->bge_link_evt++; 3707 mii = device_get_softc(sc->bge_miibus); 3708 if (mii->mii_instance) { 3709 struct mii_softc *miisc; 3710 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3711 miisc = LIST_NEXT(miisc, mii_list)) 3712 mii_phy_reset(miisc); 3713 } 3714 mii_mediachg(mii); 3715 3716 return (0); 3717 } 3718 3719 /* 3720 * Report current media status. 3721 */ 3722 static void 3723 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3724 { 3725 struct bge_softc *sc = ifp->if_softc; 3726 struct mii_data *mii; 3727 3728 BGE_LOCK(sc); 3729 3730 if (sc->bge_flags & BGE_FLAG_TBI) { 3731 ifmr->ifm_status = IFM_AVALID; 3732 ifmr->ifm_active = IFM_ETHER; 3733 if (CSR_READ_4(sc, BGE_MAC_STS) & 3734 BGE_MACSTAT_TBI_PCS_SYNCHED) 3735 ifmr->ifm_status |= IFM_ACTIVE; 3736 else { 3737 ifmr->ifm_active |= IFM_NONE; 3738 BGE_UNLOCK(sc); 3739 return; 3740 } 3741 ifmr->ifm_active |= IFM_1000_SX; 3742 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3743 ifmr->ifm_active |= IFM_HDX; 3744 else 3745 ifmr->ifm_active |= IFM_FDX; 3746 BGE_UNLOCK(sc); 3747 return; 3748 } 3749 3750 mii = device_get_softc(sc->bge_miibus); 3751 mii_pollstat(mii); 3752 ifmr->ifm_active = mii->mii_media_active; 3753 ifmr->ifm_status = mii->mii_media_status; 3754 3755 BGE_UNLOCK(sc); 3756 } 3757 3758 static int 3759 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3760 { 3761 struct bge_softc *sc = ifp->if_softc; 3762 struct ifreq *ifr = (struct ifreq *) data; 3763 struct mii_data *mii; 3764 int flags, mask, error = 0; 3765 3766 switch (command) { 3767 case SIOCSIFMTU: 3768 if (ifr->ifr_mtu < ETHERMIN || 3769 ((BGE_IS_JUMBO_CAPABLE(sc)) && 3770 ifr->ifr_mtu > BGE_JUMBO_MTU) || 3771 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 3772 ifr->ifr_mtu > ETHERMTU)) 3773 error = EINVAL; 3774 else if (ifp->if_mtu != ifr->ifr_mtu) { 3775 ifp->if_mtu = ifr->ifr_mtu; 3776 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3777 bge_init(sc); 3778 } 3779 break; 3780 case SIOCSIFFLAGS: 3781 BGE_LOCK(sc); 3782 if (ifp->if_flags & IFF_UP) { 3783 /* 3784 * If only the state of the PROMISC flag changed, 3785 * then just use the 'set promisc mode' command 3786 * instead of reinitializing the entire NIC. Doing 3787 * a full re-init means reloading the firmware and 3788 * waiting for it to start up, which may take a 3789 * second or two. Similarly for ALLMULTI. 3790 */ 3791 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3792 flags = ifp->if_flags ^ sc->bge_if_flags; 3793 if (flags & IFF_PROMISC) 3794 bge_setpromisc(sc); 3795 if (flags & IFF_ALLMULTI) 3796 bge_setmulti(sc); 3797 } else 3798 bge_init_locked(sc); 3799 } else { 3800 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3801 bge_stop(sc); 3802 } 3803 } 3804 sc->bge_if_flags = ifp->if_flags; 3805 BGE_UNLOCK(sc); 3806 error = 0; 3807 break; 3808 case SIOCADDMULTI: 3809 case SIOCDELMULTI: 3810 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3811 BGE_LOCK(sc); 3812 bge_setmulti(sc); 3813 BGE_UNLOCK(sc); 3814 error = 0; 3815 } 3816 break; 3817 case SIOCSIFMEDIA: 3818 case SIOCGIFMEDIA: 3819 if (sc->bge_flags & BGE_FLAG_TBI) { 3820 error = ifmedia_ioctl(ifp, ifr, 3821 &sc->bge_ifmedia, command); 3822 } else { 3823 mii = device_get_softc(sc->bge_miibus); 3824 error = ifmedia_ioctl(ifp, ifr, 3825 &mii->mii_media, command); 3826 } 3827 break; 3828 case SIOCSIFCAP: 3829 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3830 #ifdef DEVICE_POLLING 3831 if (mask & IFCAP_POLLING) { 3832 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3833 error = ether_poll_register(bge_poll, ifp); 3834 if (error) 3835 return (error); 3836 BGE_LOCK(sc); 3837 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 3838 BGE_PCIMISCCTL_MASK_PCI_INTR); 3839 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3840 ifp->if_capenable |= IFCAP_POLLING; 3841 BGE_UNLOCK(sc); 3842 } else { 3843 error = ether_poll_deregister(ifp); 3844 /* Enable interrupt even in error case */ 3845 BGE_LOCK(sc); 3846 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 3847 BGE_PCIMISCCTL_MASK_PCI_INTR); 3848 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3849 ifp->if_capenable &= ~IFCAP_POLLING; 3850 BGE_UNLOCK(sc); 3851 } 3852 } 3853 #endif 3854 if (mask & IFCAP_HWCSUM) { 3855 ifp->if_capenable ^= IFCAP_HWCSUM; 3856 if (IFCAP_HWCSUM & ifp->if_capenable && 3857 IFCAP_HWCSUM & ifp->if_capabilities) 3858 ifp->if_hwassist = BGE_CSUM_FEATURES; 3859 else 3860 ifp->if_hwassist = 0; 3861 #ifdef VLAN_CAPABILITIES 3862 VLAN_CAPABILITIES(ifp); 3863 #endif 3864 } 3865 break; 3866 default: 3867 error = ether_ioctl(ifp, command, data); 3868 break; 3869 } 3870 3871 return (error); 3872 } 3873 3874 static void 3875 bge_watchdog(struct bge_softc *sc) 3876 { 3877 struct ifnet *ifp; 3878 3879 BGE_LOCK_ASSERT(sc); 3880 3881 if (sc->bge_timer == 0 || --sc->bge_timer) 3882 return; 3883 3884 ifp = sc->bge_ifp; 3885 3886 if_printf(ifp, "watchdog timeout -- resetting\n"); 3887 3888 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3889 bge_init_locked(sc); 3890 3891 ifp->if_oerrors++; 3892 } 3893 3894 /* 3895 * Stop the adapter and free any mbufs allocated to the 3896 * RX and TX lists. 3897 */ 3898 static void 3899 bge_stop(struct bge_softc *sc) 3900 { 3901 struct ifnet *ifp; 3902 struct ifmedia_entry *ifm; 3903 struct mii_data *mii = NULL; 3904 int mtmp, itmp; 3905 3906 BGE_LOCK_ASSERT(sc); 3907 3908 ifp = sc->bge_ifp; 3909 3910 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) 3911 mii = device_get_softc(sc->bge_miibus); 3912 3913 callout_stop(&sc->bge_stat_ch); 3914 3915 /* 3916 * Disable all of the receiver blocks. 3917 */ 3918 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3919 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3920 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3921 if (!(BGE_IS_5705_PLUS(sc))) 3922 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3923 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3924 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3925 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3926 3927 /* 3928 * Disable all of the transmit blocks. 3929 */ 3930 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3931 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3932 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3933 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3934 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3935 if (!(BGE_IS_5705_PLUS(sc))) 3936 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3937 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3938 3939 /* 3940 * Shut down all of the memory managers and related 3941 * state machines. 3942 */ 3943 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3944 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3945 if (!(BGE_IS_5705_PLUS(sc))) 3946 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3947 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3948 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3949 if (!(BGE_IS_5705_PLUS(sc))) { 3950 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3951 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3952 } 3953 3954 /* Disable host interrupts. */ 3955 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3956 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3957 3958 /* 3959 * Tell firmware we're shutting down. 3960 */ 3961 3962 bge_stop_fw(sc); 3963 bge_sig_pre_reset(sc, BGE_RESET_STOP); 3964 bge_reset(sc); 3965 bge_sig_legacy(sc, BGE_RESET_STOP); 3966 bge_sig_post_reset(sc, BGE_RESET_STOP); 3967 3968 /* 3969 * Keep the ASF firmware running if up. 3970 */ 3971 if (sc->bge_asf_mode & ASF_STACKUP) 3972 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3973 else 3974 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3975 3976 /* Free the RX lists. */ 3977 bge_free_rx_ring_std(sc); 3978 3979 /* Free jumbo RX list. */ 3980 if (BGE_IS_JUMBO_CAPABLE(sc)) 3981 bge_free_rx_ring_jumbo(sc); 3982 3983 /* Free TX buffers. */ 3984 bge_free_tx_ring(sc); 3985 3986 /* 3987 * Isolate/power down the PHY, but leave the media selection 3988 * unchanged so that things will be put back to normal when 3989 * we bring the interface back up. 3990 */ 3991 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3992 itmp = ifp->if_flags; 3993 ifp->if_flags |= IFF_UP; 3994 /* 3995 * If we are called from bge_detach(), mii is already NULL. 3996 */ 3997 if (mii != NULL) { 3998 ifm = mii->mii_media.ifm_cur; 3999 mtmp = ifm->ifm_media; 4000 ifm->ifm_media = IFM_ETHER | IFM_NONE; 4001 mii_mediachg(mii); 4002 ifm->ifm_media = mtmp; 4003 } 4004 ifp->if_flags = itmp; 4005 } 4006 4007 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4008 4009 /* Clear MAC's link state (PHY may still have link UP). */ 4010 if (bootverbose && sc->bge_link) 4011 if_printf(sc->bge_ifp, "link DOWN\n"); 4012 sc->bge_link = 0; 4013 4014 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4015 } 4016 4017 /* 4018 * Stop all chip I/O so that the kernel's probe routines don't 4019 * get confused by errant DMAs when rebooting. 4020 */ 4021 static void 4022 bge_shutdown(device_t dev) 4023 { 4024 struct bge_softc *sc; 4025 4026 sc = device_get_softc(dev); 4027 4028 BGE_LOCK(sc); 4029 bge_stop(sc); 4030 bge_reset(sc); 4031 BGE_UNLOCK(sc); 4032 } 4033 4034 static int 4035 bge_suspend(device_t dev) 4036 { 4037 struct bge_softc *sc; 4038 4039 sc = device_get_softc(dev); 4040 BGE_LOCK(sc); 4041 bge_stop(sc); 4042 BGE_UNLOCK(sc); 4043 4044 return (0); 4045 } 4046 4047 static int 4048 bge_resume(device_t dev) 4049 { 4050 struct bge_softc *sc; 4051 struct ifnet *ifp; 4052 4053 sc = device_get_softc(dev); 4054 BGE_LOCK(sc); 4055 ifp = sc->bge_ifp; 4056 if (ifp->if_flags & IFF_UP) { 4057 bge_init_locked(sc); 4058 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4059 bge_start_locked(ifp); 4060 } 4061 BGE_UNLOCK(sc); 4062 4063 return (0); 4064 } 4065 4066 static void 4067 bge_link_upd(struct bge_softc *sc) 4068 { 4069 struct mii_data *mii; 4070 uint32_t link, status; 4071 4072 BGE_LOCK_ASSERT(sc); 4073 4074 /* Clear 'pending link event' flag. */ 4075 sc->bge_link_evt = 0; 4076 4077 /* 4078 * Process link state changes. 4079 * Grrr. The link status word in the status block does 4080 * not work correctly on the BCM5700 rev AX and BX chips, 4081 * according to all available information. Hence, we have 4082 * to enable MII interrupts in order to properly obtain 4083 * async link changes. Unfortunately, this also means that 4084 * we have to read the MAC status register to detect link 4085 * changes, thereby adding an additional register access to 4086 * the interrupt handler. 4087 * 4088 * XXX: perhaps link state detection procedure used for 4089 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4090 */ 4091 4092 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4093 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4094 status = CSR_READ_4(sc, BGE_MAC_STS); 4095 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4096 mii = device_get_softc(sc->bge_miibus); 4097 mii_pollstat(mii); 4098 if (!sc->bge_link && 4099 mii->mii_media_status & IFM_ACTIVE && 4100 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4101 sc->bge_link++; 4102 if (bootverbose) 4103 if_printf(sc->bge_ifp, "link UP\n"); 4104 } else if (sc->bge_link && 4105 (!(mii->mii_media_status & IFM_ACTIVE) || 4106 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4107 sc->bge_link = 0; 4108 if (bootverbose) 4109 if_printf(sc->bge_ifp, "link DOWN\n"); 4110 } 4111 4112 /* Clear the interrupt. */ 4113 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4114 BGE_EVTENB_MI_INTERRUPT); 4115 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4116 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4117 BRGPHY_INTRS); 4118 } 4119 return; 4120 } 4121 4122 if (sc->bge_flags & BGE_FLAG_TBI) { 4123 status = CSR_READ_4(sc, BGE_MAC_STS); 4124 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4125 if (!sc->bge_link) { 4126 sc->bge_link++; 4127 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4128 BGE_CLRBIT(sc, BGE_MAC_MODE, 4129 BGE_MACMODE_TBI_SEND_CFGS); 4130 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4131 if (bootverbose) 4132 if_printf(sc->bge_ifp, "link UP\n"); 4133 if_link_state_change(sc->bge_ifp, 4134 LINK_STATE_UP); 4135 } 4136 } else if (sc->bge_link) { 4137 sc->bge_link = 0; 4138 if (bootverbose) 4139 if_printf(sc->bge_ifp, "link DOWN\n"); 4140 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4141 } 4142 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4143 /* 4144 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4145 * in status word always set. Workaround this bug by reading 4146 * PHY link status directly. 4147 */ 4148 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4149 4150 if (link != sc->bge_link || 4151 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4152 mii = device_get_softc(sc->bge_miibus); 4153 mii_pollstat(mii); 4154 if (!sc->bge_link && 4155 mii->mii_media_status & IFM_ACTIVE && 4156 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4157 sc->bge_link++; 4158 if (bootverbose) 4159 if_printf(sc->bge_ifp, "link UP\n"); 4160 } else if (sc->bge_link && 4161 (!(mii->mii_media_status & IFM_ACTIVE) || 4162 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4163 sc->bge_link = 0; 4164 if (bootverbose) 4165 if_printf(sc->bge_ifp, "link DOWN\n"); 4166 } 4167 } 4168 } else { 4169 /* 4170 * Discard link events for MII/GMII controllers 4171 * if MI auto-polling is disabled. 4172 */ 4173 } 4174 4175 /* Clear the attention. */ 4176 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4177 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4178 BGE_MACSTAT_LINK_CHANGED); 4179 } 4180 4181 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4182 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4183 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4184 desc) 4185 4186 static void 4187 bge_add_sysctls(struct bge_softc *sc) 4188 { 4189 struct sysctl_ctx_list *ctx; 4190 struct sysctl_oid_list *children, *schildren; 4191 struct sysctl_oid *tree; 4192 4193 ctx = device_get_sysctl_ctx(sc->bge_dev); 4194 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4195 4196 #ifdef BGE_REGISTER_DEBUG 4197 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4198 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4199 "Debug Information"); 4200 4201 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4202 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4203 "Register Read"); 4204 4205 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4206 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4207 "Memory Read"); 4208 4209 #endif 4210 4211 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4212 NULL, "BGE Statistics"); 4213 schildren = children = SYSCTL_CHILDREN(tree); 4214 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4215 children, COSFramesDroppedDueToFilters, 4216 "FramesDroppedDueToFilters"); 4217 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4218 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4219 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4220 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4221 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4222 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4223 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4224 children, ifInDiscards, "InputDiscards"); 4225 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4226 children, ifInErrors, "InputErrors"); 4227 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4228 children, nicRecvThresholdHit, "RecvThresholdHit"); 4229 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4230 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4231 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4232 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4233 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4234 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4235 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4236 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4237 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4238 children, nicRingStatusUpdate, "RingStatusUpdate"); 4239 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4240 children, nicInterrupts, "Interrupts"); 4241 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4242 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4243 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4244 children, nicSendThresholdHit, "SendThresholdHit"); 4245 4246 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4247 NULL, "BGE RX Statistics"); 4248 children = SYSCTL_CHILDREN(tree); 4249 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4250 children, rxstats.ifHCInOctets, "Octets"); 4251 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4252 children, rxstats.etherStatsFragments, "Fragments"); 4253 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4254 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4255 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4256 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4257 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4258 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4259 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4260 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4261 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4262 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4263 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4264 children, rxstats.xoffPauseFramesReceived, 4265 "xoffPauseFramesReceived"); 4266 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4267 children, rxstats.macControlFramesReceived, 4268 "ControlFramesReceived"); 4269 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 4270 children, rxstats.xoffStateEntered, "xoffStateEntered"); 4271 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 4272 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 4273 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 4274 children, rxstats.etherStatsJabbers, "Jabbers"); 4275 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 4276 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 4277 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 4278 children, rxstats.inRangeLengthError, "inRangeLengthError"); 4279 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 4280 children, rxstats.outRangeLengthError, "outRangeLengthError"); 4281 4282 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 4283 NULL, "BGE TX Statistics"); 4284 children = SYSCTL_CHILDREN(tree); 4285 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 4286 children, txstats.ifHCOutOctets, "Octets"); 4287 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 4288 children, txstats.etherStatsCollisions, "Collisions"); 4289 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 4290 children, txstats.outXonSent, "XonSent"); 4291 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 4292 children, txstats.outXoffSent, "XoffSent"); 4293 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 4294 children, txstats.flowControlDone, "flowControlDone"); 4295 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 4296 children, txstats.dot3StatsInternalMacTransmitErrors, 4297 "InternalMacTransmitErrors"); 4298 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 4299 children, txstats.dot3StatsSingleCollisionFrames, 4300 "SingleCollisionFrames"); 4301 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 4302 children, txstats.dot3StatsMultipleCollisionFrames, 4303 "MultipleCollisionFrames"); 4304 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 4305 children, txstats.dot3StatsDeferredTransmissions, 4306 "DeferredTransmissions"); 4307 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 4308 children, txstats.dot3StatsExcessiveCollisions, 4309 "ExcessiveCollisions"); 4310 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 4311 children, txstats.dot3StatsLateCollisions, 4312 "LateCollisions"); 4313 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 4314 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 4315 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 4316 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 4317 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 4318 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 4319 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 4320 children, txstats.dot3StatsCarrierSenseErrors, 4321 "CarrierSenseErrors"); 4322 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 4323 children, txstats.ifOutDiscards, "Discards"); 4324 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 4325 children, txstats.ifOutErrors, "Errors"); 4326 } 4327 4328 static int 4329 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 4330 { 4331 struct bge_softc *sc; 4332 uint32_t result; 4333 int base, offset; 4334 4335 sc = (struct bge_softc *)arg1; 4336 offset = arg2; 4337 if (BGE_IS_5705_PLUS(sc)) 4338 base = BGE_MAC_STATS; 4339 else 4340 base = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4341 result = CSR_READ_4(sc, base + offset + offsetof(bge_hostaddr, 4342 bge_addr_lo)); 4343 return (sysctl_handle_int(oidp, &result, sizeof(result), req)); 4344 } 4345 4346 #ifdef BGE_REGISTER_DEBUG 4347 static int 4348 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 4349 { 4350 struct bge_softc *sc; 4351 uint16_t *sbdata; 4352 int error; 4353 int result; 4354 int i, j; 4355 4356 result = -1; 4357 error = sysctl_handle_int(oidp, &result, 0, req); 4358 if (error || (req->newptr == NULL)) 4359 return (error); 4360 4361 if (result == 1) { 4362 sc = (struct bge_softc *)arg1; 4363 4364 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 4365 printf("Status Block:\n"); 4366 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 4367 printf("%06x:", i); 4368 for (j = 0; j < 8; j++) { 4369 printf(" %04x", sbdata[i]); 4370 i += 4; 4371 } 4372 printf("\n"); 4373 } 4374 4375 printf("Registers:\n"); 4376 for (i = 0x800; i < 0xA00; ) { 4377 printf("%06x:", i); 4378 for (j = 0; j < 8; j++) { 4379 printf(" %08x", CSR_READ_4(sc, i)); 4380 i += 4; 4381 } 4382 printf("\n"); 4383 } 4384 4385 printf("Hardware Flags:\n"); 4386 if (BGE_IS_575X_PLUS(sc)) 4387 printf(" - 575X Plus\n"); 4388 if (BGE_IS_5705_PLUS(sc)) 4389 printf(" - 5705 Plus\n"); 4390 if (BGE_IS_5714_FAMILY(sc)) 4391 printf(" - 5714 Family\n"); 4392 if (BGE_IS_5700_FAMILY(sc)) 4393 printf(" - 5700 Family\n"); 4394 if (sc->bge_flags & BGE_FLAG_JUMBO) 4395 printf(" - Supports Jumbo Frames\n"); 4396 if (sc->bge_flags & BGE_FLAG_PCIX) 4397 printf(" - PCI-X Bus\n"); 4398 if (sc->bge_flags & BGE_FLAG_PCIE) 4399 printf(" - PCI Express Bus\n"); 4400 if (sc->bge_flags & BGE_FLAG_NO_3LED) 4401 printf(" - No 3 LEDs\n"); 4402 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 4403 printf(" - RX Alignment Bug\n"); 4404 } 4405 4406 return (error); 4407 } 4408 4409 static int 4410 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 4411 { 4412 struct bge_softc *sc; 4413 int error; 4414 uint16_t result; 4415 uint32_t val; 4416 4417 result = -1; 4418 error = sysctl_handle_int(oidp, &result, 0, req); 4419 if (error || (req->newptr == NULL)) 4420 return (error); 4421 4422 if (result < 0x8000) { 4423 sc = (struct bge_softc *)arg1; 4424 val = CSR_READ_4(sc, result); 4425 printf("reg 0x%06X = 0x%08X\n", result, val); 4426 } 4427 4428 return (error); 4429 } 4430 4431 static int 4432 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 4433 { 4434 struct bge_softc *sc; 4435 int error; 4436 uint16_t result; 4437 uint32_t val; 4438 4439 result = -1; 4440 error = sysctl_handle_int(oidp, &result, 0, req); 4441 if (error || (req->newptr == NULL)) 4442 return (error); 4443 4444 if (result < 0x8000) { 4445 sc = (struct bge_softc *)arg1; 4446 val = bge_readmem_ind(sc, result); 4447 printf("mem 0x%06X = 0x%08X\n", result, val); 4448 } 4449 4450 return (error); 4451 } 4452 #endif 4453