1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 36 * 37 * The Broadcom BCM5700 is based on technology originally developed by 38 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 39 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 40 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 41 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 42 * frames, highly configurable RX filtering, and 16 RX and TX queues 43 * (which, along with RX filter rules, can be used for QOS applications). 44 * Other features, such as TCP segmentation, may be available as part 45 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 46 * firmware images can be stored in hardware and need not be compiled 47 * into the driver. 48 * 49 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 50 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 51 * 52 * The BCM5701 is a single-chip solution incorporating both the BCM5700 53 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 54 * does not support external SSRAM. 55 * 56 * Broadcom also produces a variation of the BCM5700 under the "Altima" 57 * brand name, which is functionally similar but lacks PCI-X support. 58 * 59 * Without external SSRAM, you can only have at most 4 TX rings, 60 * and the use of the mini RX ring is disabled. This seems to imply 61 * that these features are simply not available on the BCM5701. As a 62 * result, this driver does not implement any support for the mini RX 63 * ring. 64 */ 65 66 #include <sys/cdefs.h> 67 __FBSDID("$FreeBSD$"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/sockio.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/queue.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 84 #include <net/bpf.h> 85 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <netinet/in_systm.h> 90 #include <netinet/in.h> 91 #include <netinet/ip.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/clock.h> /* for DELAY */ 96 #include <machine/bus_memio.h> 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 #include "miidevs.h" 105 #include <dev/mii/brgphyreg.h> 106 107 #include <pci/pcireg.h> 108 #include <pci/pcivar.h> 109 110 #include <dev/bge/if_bgereg.h> 111 112 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 113 114 MODULE_DEPEND(bge, pci, 1, 1, 1); 115 MODULE_DEPEND(bge, ether, 1, 1, 1); 116 MODULE_DEPEND(bge, miibus, 1, 1, 1); 117 118 /* "controller miibus0" required. See GENERIC if you get errors here. */ 119 #include "miibus_if.h" 120 121 /* 122 * Various supported device vendors/types and their names. Note: the 123 * spec seems to indicate that the hardware still has Alteon's vendor 124 * ID burned into it, though it will always be overriden by the vendor 125 * ID in the EEPROM. Just to be safe, we cover all possibilities. 126 */ 127 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 128 129 static struct bge_type bge_devs[] = { 130 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 131 "Broadcom BCM5700 Gigabit Ethernet" }, 132 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 133 "Broadcom BCM5701 Gigabit Ethernet" }, 134 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 135 "Broadcom BCM5700 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 137 "Broadcom BCM5701 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 139 "Broadcom BCM5702X Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 141 "Broadcom BCM5703X Gigabit Ethernet" }, 142 { SK_VENDORID, SK_DEVICEID_ALTIMA, 143 "SysKonnect Gigabit Ethernet" }, 144 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 145 "Altima AC1000 Gigabit Ethernet" }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 147 "Altima AC9100 Gigabit Ethernet" }, 148 { 0, 0, NULL } 149 }; 150 151 static int bge_probe (device_t); 152 static int bge_attach (device_t); 153 static int bge_detach (device_t); 154 static void bge_release_resources 155 (struct bge_softc *); 156 static void bge_txeof (struct bge_softc *); 157 static void bge_rxeof (struct bge_softc *); 158 159 static void bge_tick (void *); 160 static void bge_stats_update (struct bge_softc *); 161 static int bge_encap (struct bge_softc *, struct mbuf *, 162 u_int32_t *); 163 164 static void bge_intr (void *); 165 static void bge_start (struct ifnet *); 166 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 167 static void bge_init (void *); 168 static void bge_stop (struct bge_softc *); 169 static void bge_watchdog (struct ifnet *); 170 static void bge_shutdown (device_t); 171 static int bge_ifmedia_upd (struct ifnet *); 172 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 173 174 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 175 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 176 177 static u_int32_t bge_crc (caddr_t); 178 static void bge_setmulti (struct bge_softc *); 179 180 static void bge_handle_events (struct bge_softc *); 181 static int bge_alloc_jumbo_mem (struct bge_softc *); 182 static void bge_free_jumbo_mem (struct bge_softc *); 183 static void *bge_jalloc (struct bge_softc *); 184 static void bge_jfree (void *, void *); 185 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 186 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 187 static int bge_init_rx_ring_std (struct bge_softc *); 188 static void bge_free_rx_ring_std (struct bge_softc *); 189 static int bge_init_rx_ring_jumbo (struct bge_softc *); 190 static void bge_free_rx_ring_jumbo (struct bge_softc *); 191 static void bge_free_tx_ring (struct bge_softc *); 192 static int bge_init_tx_ring (struct bge_softc *); 193 194 static int bge_chipinit (struct bge_softc *); 195 static int bge_blockinit (struct bge_softc *); 196 197 #ifdef notdef 198 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 199 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 200 static void bge_vpd_read (struct bge_softc *); 201 #endif 202 203 static u_int32_t bge_readmem_ind 204 (struct bge_softc *, int); 205 static void bge_writemem_ind (struct bge_softc *, int, int); 206 #ifdef notdef 207 static u_int32_t bge_readreg_ind 208 (struct bge_softc *, int); 209 #endif 210 static void bge_writereg_ind (struct bge_softc *, int, int); 211 212 static int bge_miibus_readreg (device_t, int, int); 213 static int bge_miibus_writereg (device_t, int, int, int); 214 static void bge_miibus_statchg (device_t); 215 216 static void bge_reset (struct bge_softc *); 217 static void bge_phy_hack (struct bge_softc *); 218 219 static device_method_t bge_methods[] = { 220 /* Device interface */ 221 DEVMETHOD(device_probe, bge_probe), 222 DEVMETHOD(device_attach, bge_attach), 223 DEVMETHOD(device_detach, bge_detach), 224 DEVMETHOD(device_shutdown, bge_shutdown), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 232 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 233 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 234 235 { 0, 0 } 236 }; 237 238 static driver_t bge_driver = { 239 "bge", 240 bge_methods, 241 sizeof(struct bge_softc) 242 }; 243 244 static devclass_t bge_devclass; 245 246 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 247 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 248 249 static u_int32_t 250 bge_readmem_ind(sc, off) 251 struct bge_softc *sc; 252 int off; 253 { 254 device_t dev; 255 256 dev = sc->bge_dev; 257 258 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 259 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 260 } 261 262 static void 263 bge_writemem_ind(sc, off, val) 264 struct bge_softc *sc; 265 int off, val; 266 { 267 device_t dev; 268 269 dev = sc->bge_dev; 270 271 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 272 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 273 274 return; 275 } 276 277 #ifdef notdef 278 static u_int32_t 279 bge_readreg_ind(sc, off) 280 struct bge_softc *sc; 281 int off; 282 { 283 device_t dev; 284 285 dev = sc->bge_dev; 286 287 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 288 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 289 } 290 #endif 291 292 static void 293 bge_writereg_ind(sc, off, val) 294 struct bge_softc *sc; 295 int off, val; 296 { 297 device_t dev; 298 299 dev = sc->bge_dev; 300 301 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 302 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 303 304 return; 305 } 306 307 #ifdef notdef 308 static u_int8_t 309 bge_vpd_readbyte(sc, addr) 310 struct bge_softc *sc; 311 int addr; 312 { 313 int i; 314 device_t dev; 315 u_int32_t val; 316 317 dev = sc->bge_dev; 318 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 319 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 320 DELAY(10); 321 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 322 break; 323 } 324 325 if (i == BGE_TIMEOUT) { 326 printf("bge%d: VPD read timed out\n", sc->bge_unit); 327 return(0); 328 } 329 330 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 331 332 return((val >> ((addr % 4) * 8)) & 0xFF); 333 } 334 335 static void 336 bge_vpd_read_res(sc, res, addr) 337 struct bge_softc *sc; 338 struct vpd_res *res; 339 int addr; 340 { 341 int i; 342 u_int8_t *ptr; 343 344 ptr = (u_int8_t *)res; 345 for (i = 0; i < sizeof(struct vpd_res); i++) 346 ptr[i] = bge_vpd_readbyte(sc, i + addr); 347 348 return; 349 } 350 351 static void 352 bge_vpd_read(sc) 353 struct bge_softc *sc; 354 { 355 int pos = 0, i; 356 struct vpd_res res; 357 358 if (sc->bge_vpd_prodname != NULL) 359 free(sc->bge_vpd_prodname, M_DEVBUF); 360 if (sc->bge_vpd_readonly != NULL) 361 free(sc->bge_vpd_readonly, M_DEVBUF); 362 sc->bge_vpd_prodname = NULL; 363 sc->bge_vpd_readonly = NULL; 364 365 bge_vpd_read_res(sc, &res, pos); 366 367 if (res.vr_id != VPD_RES_ID) { 368 printf("bge%d: bad VPD resource id: expected %x got %x\n", 369 sc->bge_unit, VPD_RES_ID, res.vr_id); 370 return; 371 } 372 373 pos += sizeof(res); 374 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 375 for (i = 0; i < res.vr_len; i++) 376 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 377 sc->bge_vpd_prodname[i] = '\0'; 378 pos += i; 379 380 bge_vpd_read_res(sc, &res, pos); 381 382 if (res.vr_id != VPD_RES_READ) { 383 printf("bge%d: bad VPD resource id: expected %x got %x\n", 384 sc->bge_unit, VPD_RES_READ, res.vr_id); 385 return; 386 } 387 388 pos += sizeof(res); 389 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 390 for (i = 0; i < res.vr_len + 1; i++) 391 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 392 393 return; 394 } 395 #endif 396 397 /* 398 * Read a byte of data stored in the EEPROM at address 'addr.' The 399 * BCM570x supports both the traditional bitbang interface and an 400 * auto access interface for reading the EEPROM. We use the auto 401 * access method. 402 */ 403 static u_int8_t 404 bge_eeprom_getbyte(sc, addr, dest) 405 struct bge_softc *sc; 406 int addr; 407 u_int8_t *dest; 408 { 409 int i; 410 u_int32_t byte = 0; 411 412 /* 413 * Enable use of auto EEPROM access so we can avoid 414 * having to use the bitbang method. 415 */ 416 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 417 418 /* Reset the EEPROM, load the clock period. */ 419 CSR_WRITE_4(sc, BGE_EE_ADDR, 420 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 421 DELAY(20); 422 423 /* Issue the read EEPROM command. */ 424 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 425 426 /* Wait for completion */ 427 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 428 DELAY(10); 429 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 430 break; 431 } 432 433 if (i == BGE_TIMEOUT) { 434 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 435 return(0); 436 } 437 438 /* Get result. */ 439 byte = CSR_READ_4(sc, BGE_EE_DATA); 440 441 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 442 443 return(0); 444 } 445 446 /* 447 * Read a sequence of bytes from the EEPROM. 448 */ 449 static int 450 bge_read_eeprom(sc, dest, off, cnt) 451 struct bge_softc *sc; 452 caddr_t dest; 453 int off; 454 int cnt; 455 { 456 int err = 0, i; 457 u_int8_t byte = 0; 458 459 for (i = 0; i < cnt; i++) { 460 err = bge_eeprom_getbyte(sc, off + i, &byte); 461 if (err) 462 break; 463 *(dest + i) = byte; 464 } 465 466 return(err ? 1 : 0); 467 } 468 469 static int 470 bge_miibus_readreg(dev, phy, reg) 471 device_t dev; 472 int phy, reg; 473 { 474 struct bge_softc *sc; 475 struct ifnet *ifp; 476 u_int32_t val; 477 int i; 478 479 sc = device_get_softc(dev); 480 ifp = &sc->arpcom.ac_if; 481 482 if (phy != 1) 483 switch(sc->bge_asicrev) { 484 case BGE_ASICREV_BCM5701_B5: 485 case BGE_ASICREV_BCM5703_A2: 486 return(0); 487 } 488 489 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 490 BGE_MIPHY(phy)|BGE_MIREG(reg)); 491 492 for (i = 0; i < BGE_TIMEOUT; i++) { 493 val = CSR_READ_4(sc, BGE_MI_COMM); 494 if (!(val & BGE_MICOMM_BUSY)) 495 break; 496 } 497 498 if (i == BGE_TIMEOUT) { 499 printf("bge%d: PHY read timed out\n", sc->bge_unit); 500 return(0); 501 } 502 503 val = CSR_READ_4(sc, BGE_MI_COMM); 504 505 if (val & BGE_MICOMM_READFAIL) 506 return(0); 507 508 return(val & 0xFFFF); 509 } 510 511 static int 512 bge_miibus_writereg(dev, phy, reg, val) 513 device_t dev; 514 int phy, reg, val; 515 { 516 struct bge_softc *sc; 517 int i; 518 519 sc = device_get_softc(dev); 520 521 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 522 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 523 524 for (i = 0; i < BGE_TIMEOUT; i++) { 525 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 526 break; 527 } 528 529 if (i == BGE_TIMEOUT) { 530 printf("bge%d: PHY read timed out\n", sc->bge_unit); 531 return(0); 532 } 533 534 return(0); 535 } 536 537 static void 538 bge_miibus_statchg(dev) 539 device_t dev; 540 { 541 struct bge_softc *sc; 542 struct mii_data *mii; 543 544 sc = device_get_softc(dev); 545 mii = device_get_softc(sc->bge_miibus); 546 547 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 548 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 549 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 550 } else { 551 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 552 } 553 554 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 555 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 556 } else { 557 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 558 } 559 560 bge_phy_hack(sc); 561 562 return; 563 } 564 565 /* 566 * Handle events that have triggered interrupts. 567 */ 568 static void 569 bge_handle_events(sc) 570 struct bge_softc *sc; 571 { 572 573 return; 574 } 575 576 /* 577 * Memory management for jumbo frames. 578 */ 579 580 static int 581 bge_alloc_jumbo_mem(sc) 582 struct bge_softc *sc; 583 { 584 caddr_t ptr; 585 register int i; 586 struct bge_jpool_entry *entry; 587 588 /* Grab a big chunk o' storage. */ 589 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 590 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 591 592 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 593 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 594 return(ENOBUFS); 595 } 596 597 SLIST_INIT(&sc->bge_jfree_listhead); 598 SLIST_INIT(&sc->bge_jinuse_listhead); 599 600 /* 601 * Now divide it up into 9K pieces and save the addresses 602 * in an array. 603 */ 604 ptr = sc->bge_cdata.bge_jumbo_buf; 605 for (i = 0; i < BGE_JSLOTS; i++) { 606 sc->bge_cdata.bge_jslots[i] = ptr; 607 ptr += BGE_JLEN; 608 entry = malloc(sizeof(struct bge_jpool_entry), 609 M_DEVBUF, M_NOWAIT); 610 if (entry == NULL) { 611 contigfree(sc->bge_cdata.bge_jumbo_buf, 612 BGE_JMEM, M_DEVBUF); 613 sc->bge_cdata.bge_jumbo_buf = NULL; 614 printf("bge%d: no memory for jumbo " 615 "buffer queue!\n", sc->bge_unit); 616 return(ENOBUFS); 617 } 618 entry->slot = i; 619 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 620 entry, jpool_entries); 621 } 622 623 return(0); 624 } 625 626 static void 627 bge_free_jumbo_mem(sc) 628 struct bge_softc *sc; 629 { 630 int i; 631 struct bge_jpool_entry *entry; 632 633 for (i = 0; i < BGE_JSLOTS; i++) { 634 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 635 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 636 free(entry, M_DEVBUF); 637 } 638 639 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 640 641 return; 642 } 643 644 /* 645 * Allocate a jumbo buffer. 646 */ 647 static void * 648 bge_jalloc(sc) 649 struct bge_softc *sc; 650 { 651 struct bge_jpool_entry *entry; 652 653 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 654 655 if (entry == NULL) { 656 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 657 return(NULL); 658 } 659 660 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 661 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 662 return(sc->bge_cdata.bge_jslots[entry->slot]); 663 } 664 665 /* 666 * Release a jumbo buffer. 667 */ 668 static void 669 bge_jfree(buf, args) 670 void *buf; 671 void *args; 672 { 673 struct bge_jpool_entry *entry; 674 struct bge_softc *sc; 675 int i; 676 677 /* Extract the softc struct pointer. */ 678 sc = (struct bge_softc *)args; 679 680 if (sc == NULL) 681 panic("bge_jfree: can't find softc pointer!"); 682 683 /* calculate the slot this buffer belongs to */ 684 685 i = ((vm_offset_t)buf 686 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 687 688 if ((i < 0) || (i >= BGE_JSLOTS)) 689 panic("bge_jfree: asked to free buffer that we don't manage!"); 690 691 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 692 if (entry == NULL) 693 panic("bge_jfree: buffer not in use!"); 694 entry->slot = i; 695 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 696 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 697 698 return; 699 } 700 701 702 /* 703 * Intialize a standard receive ring descriptor. 704 */ 705 static int 706 bge_newbuf_std(sc, i, m) 707 struct bge_softc *sc; 708 int i; 709 struct mbuf *m; 710 { 711 struct mbuf *m_new = NULL; 712 struct bge_rx_bd *r; 713 714 if (m == NULL) { 715 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 716 if (m_new == NULL) { 717 return(ENOBUFS); 718 } 719 720 MCLGET(m_new, M_DONTWAIT); 721 if (!(m_new->m_flags & M_EXT)) { 722 m_freem(m_new); 723 return(ENOBUFS); 724 } 725 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 726 } else { 727 m_new = m; 728 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 729 m_new->m_data = m_new->m_ext.ext_buf; 730 } 731 732 if (!sc->bge_rx_alignment_bug) 733 m_adj(m_new, ETHER_ALIGN); 734 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 735 r = &sc->bge_rdata->bge_rx_std_ring[i]; 736 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 737 r->bge_flags = BGE_RXBDFLAG_END; 738 r->bge_len = m_new->m_len; 739 r->bge_idx = i; 740 741 return(0); 742 } 743 744 /* 745 * Initialize a jumbo receive ring descriptor. This allocates 746 * a jumbo buffer from the pool managed internally by the driver. 747 */ 748 static int 749 bge_newbuf_jumbo(sc, i, m) 750 struct bge_softc *sc; 751 int i; 752 struct mbuf *m; 753 { 754 struct mbuf *m_new = NULL; 755 struct bge_rx_bd *r; 756 757 if (m == NULL) { 758 caddr_t *buf = NULL; 759 760 /* Allocate the mbuf. */ 761 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 762 if (m_new == NULL) { 763 return(ENOBUFS); 764 } 765 766 /* Allocate the jumbo buffer */ 767 buf = bge_jalloc(sc); 768 if (buf == NULL) { 769 m_freem(m_new); 770 printf("bge%d: jumbo allocation failed " 771 "-- packet dropped!\n", sc->bge_unit); 772 return(ENOBUFS); 773 } 774 775 /* Attach the buffer to the mbuf. */ 776 m_new->m_data = (void *) buf; 777 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 778 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 779 (struct bge_softc *)sc, 0, EXT_NET_DRV); 780 } else { 781 m_new = m; 782 m_new->m_data = m_new->m_ext.ext_buf; 783 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 784 } 785 786 if (!sc->bge_rx_alignment_bug) 787 m_adj(m_new, ETHER_ALIGN); 788 /* Set up the descriptor. */ 789 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 790 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 791 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 792 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 793 r->bge_len = m_new->m_len; 794 r->bge_idx = i; 795 796 return(0); 797 } 798 799 /* 800 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 801 * that's 1MB or memory, which is a lot. For now, we fill only the first 802 * 256 ring entries and hope that our CPU is fast enough to keep up with 803 * the NIC. 804 */ 805 static int 806 bge_init_rx_ring_std(sc) 807 struct bge_softc *sc; 808 { 809 int i; 810 811 for (i = 0; i < BGE_SSLOTS; i++) { 812 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 813 return(ENOBUFS); 814 }; 815 816 sc->bge_std = i - 1; 817 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 818 819 return(0); 820 } 821 822 static void 823 bge_free_rx_ring_std(sc) 824 struct bge_softc *sc; 825 { 826 int i; 827 828 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 829 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 830 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 831 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 832 } 833 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 834 sizeof(struct bge_rx_bd)); 835 } 836 837 return; 838 } 839 840 static int 841 bge_init_rx_ring_jumbo(sc) 842 struct bge_softc *sc; 843 { 844 int i; 845 struct bge_rcb *rcb; 846 847 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 848 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 849 return(ENOBUFS); 850 }; 851 852 sc->bge_jumbo = i - 1; 853 854 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 855 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 856 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 857 858 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 859 860 return(0); 861 } 862 863 static void 864 bge_free_rx_ring_jumbo(sc) 865 struct bge_softc *sc; 866 { 867 int i; 868 869 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 870 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 871 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 872 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 873 } 874 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 875 sizeof(struct bge_rx_bd)); 876 } 877 878 return; 879 } 880 881 static void 882 bge_free_tx_ring(sc) 883 struct bge_softc *sc; 884 { 885 int i; 886 887 if (sc->bge_rdata->bge_tx_ring == NULL) 888 return; 889 890 for (i = 0; i < BGE_TX_RING_CNT; i++) { 891 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 892 m_freem(sc->bge_cdata.bge_tx_chain[i]); 893 sc->bge_cdata.bge_tx_chain[i] = NULL; 894 } 895 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 896 sizeof(struct bge_tx_bd)); 897 } 898 899 return; 900 } 901 902 static int 903 bge_init_tx_ring(sc) 904 struct bge_softc *sc; 905 { 906 sc->bge_txcnt = 0; 907 sc->bge_tx_saved_considx = 0; 908 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 909 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 910 911 return(0); 912 } 913 914 #define BGE_POLY 0xEDB88320 915 916 static u_int32_t 917 bge_crc(addr) 918 caddr_t addr; 919 { 920 u_int32_t idx, bit, data, crc; 921 922 /* Compute CRC for the address value. */ 923 crc = 0xFFFFFFFF; /* initial value */ 924 925 for (idx = 0; idx < 6; idx++) { 926 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 927 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 928 } 929 930 return(crc & 0x7F); 931 } 932 933 static void 934 bge_setmulti(sc) 935 struct bge_softc *sc; 936 { 937 struct ifnet *ifp; 938 struct ifmultiaddr *ifma; 939 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 940 int h, i; 941 942 ifp = &sc->arpcom.ac_if; 943 944 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 945 for (i = 0; i < 4; i++) 946 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 947 return; 948 } 949 950 /* First, zot all the existing filters. */ 951 for (i = 0; i < 4; i++) 952 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 953 954 /* Now program new ones. */ 955 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 956 if (ifma->ifma_addr->sa_family != AF_LINK) 957 continue; 958 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 959 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 960 } 961 962 for (i = 0; i < 4; i++) 963 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 964 965 return; 966 } 967 968 /* 969 * Do endian, PCI and DMA initialization. Also check the on-board ROM 970 * self-test results. 971 */ 972 static int 973 bge_chipinit(sc) 974 struct bge_softc *sc; 975 { 976 int i; 977 978 /* Set endianness before we access any non-PCI registers. */ 979 #if BYTE_ORDER == BIG_ENDIAN 980 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 981 BGE_BIGENDIAN_INIT, 4); 982 #else 983 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 984 BGE_LITTLEENDIAN_INIT, 4); 985 #endif 986 987 /* 988 * Check the 'ROM failed' bit on the RX CPU to see if 989 * self-tests passed. 990 */ 991 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 992 printf("bge%d: RX CPU self-diagnostics failed!\n", 993 sc->bge_unit); 994 return(ENODEV); 995 } 996 997 /* Clear the MAC control register */ 998 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 999 1000 /* 1001 * Clear the MAC statistics block in the NIC's 1002 * internal memory. 1003 */ 1004 for (i = BGE_STATS_BLOCK; 1005 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1006 BGE_MEMWIN_WRITE(sc, i, 0); 1007 1008 for (i = BGE_STATUS_BLOCK; 1009 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1010 BGE_MEMWIN_WRITE(sc, i, 0); 1011 1012 /* Set up the PCI DMA control register. */ 1013 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1014 BGE_PCISTATE_PCI_BUSMODE) { 1015 /* Conventional PCI bus */ 1016 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1017 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4); 1018 } else { 1019 /* PCI-X bus */ 1020 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1021 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4); 1022 } 1023 1024 /* 1025 * Set up general mode register. 1026 */ 1027 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1028 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1029 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1030 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1031 BGE_MODECTL_RX_NO_PHDR_CSUM); 1032 1033 /* 1034 * Disable memory write invalidate. Apparently it is not supported 1035 * properly by these devices. 1036 */ 1037 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1038 1039 #ifdef __brokenalpha__ 1040 /* 1041 * Must insure that we do not cross an 8K (bytes) boundary 1042 * for DMA reads. Our highest limit is 1K bytes. This is a 1043 * restriction on some ALPHA platforms with early revision 1044 * 21174 PCI chipsets, such as the AlphaPC 164lx 1045 */ 1046 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1047 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1048 #endif 1049 1050 /* Set the timer prescaler (always 66Mhz) */ 1051 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1052 1053 return(0); 1054 } 1055 1056 static int 1057 bge_blockinit(sc) 1058 struct bge_softc *sc; 1059 { 1060 struct bge_rcb *rcb; 1061 volatile struct bge_rcb *vrcb; 1062 int i; 1063 1064 /* 1065 * Initialize the memory window pointer register so that 1066 * we can access the first 32K of internal NIC RAM. This will 1067 * allow us to set up the TX send ring RCBs and the RX return 1068 * ring RCBs, plus other things which live in NIC memory. 1069 */ 1070 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1071 1072 /* Configure mbuf memory pool */ 1073 if (sc->bge_extram) { 1074 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1075 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1076 } else { 1077 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1078 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1079 } 1080 1081 /* Configure DMA resource pool */ 1082 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1083 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1084 1085 /* Configure mbuf pool watermarks */ 1086 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1087 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1088 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1089 1090 /* Configure DMA resource watermarks */ 1091 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1092 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1093 1094 /* Enable buffer manager */ 1095 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1096 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1097 1098 /* Poll for buffer manager start indication */ 1099 for (i = 0; i < BGE_TIMEOUT; i++) { 1100 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1101 break; 1102 DELAY(10); 1103 } 1104 1105 if (i == BGE_TIMEOUT) { 1106 printf("bge%d: buffer manager failed to start\n", 1107 sc->bge_unit); 1108 return(ENXIO); 1109 } 1110 1111 /* Enable flow-through queues */ 1112 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1113 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1114 1115 /* Wait until queue initialization is complete */ 1116 for (i = 0; i < BGE_TIMEOUT; i++) { 1117 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1118 break; 1119 DELAY(10); 1120 } 1121 1122 if (i == BGE_TIMEOUT) { 1123 printf("bge%d: flow-through queue init failed\n", 1124 sc->bge_unit); 1125 return(ENXIO); 1126 } 1127 1128 /* Initialize the standard RX ring control block */ 1129 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1130 BGE_HOSTADDR(rcb->bge_hostaddr) = 1131 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1132 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1133 if (sc->bge_extram) 1134 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1135 else 1136 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1137 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1139 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1140 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1141 1142 /* 1143 * Initialize the jumbo RX ring control block 1144 * We set the 'ring disabled' bit in the flags 1145 * field until we're actually ready to start 1146 * using this ring (i.e. once we set the MTU 1147 * high enough to require it). 1148 */ 1149 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1150 BGE_HOSTADDR(rcb->bge_hostaddr) = 1151 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1152 rcb->bge_maxlen_flags = 1153 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1154 if (sc->bge_extram) 1155 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1156 else 1157 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1158 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1159 rcb->bge_hostaddr.bge_addr_hi); 1160 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1161 rcb->bge_hostaddr.bge_addr_lo); 1162 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1163 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1164 1165 /* Set up dummy disabled mini ring RCB */ 1166 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1167 rcb->bge_maxlen_flags = 1168 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1169 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1170 1171 /* 1172 * Set the BD ring replentish thresholds. The recommended 1173 * values are 1/8th the number of descriptors allocated to 1174 * each ring. 1175 */ 1176 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1177 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1178 1179 /* 1180 * Disable all unused send rings by setting the 'ring disabled' 1181 * bit in the flags field of all the TX send ring control blocks. 1182 * These are located in NIC memory. 1183 */ 1184 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1185 BGE_SEND_RING_RCB); 1186 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1187 vrcb->bge_maxlen_flags = 1188 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1189 vrcb->bge_nicaddr = 0; 1190 vrcb++; 1191 } 1192 1193 /* Configure TX RCB 0 (we use only the first ring) */ 1194 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1195 BGE_SEND_RING_RCB); 1196 vrcb->bge_hostaddr.bge_addr_hi = 0; 1197 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1198 vtophys(&sc->bge_rdata->bge_tx_ring); 1199 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1200 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1201 1202 /* Disable all unused RX return rings */ 1203 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1204 BGE_RX_RETURN_RING_RCB); 1205 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1206 vrcb->bge_hostaddr.bge_addr_hi = 0; 1207 vrcb->bge_hostaddr.bge_addr_lo = 0; 1208 vrcb->bge_maxlen_flags = 1209 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1210 BGE_RCB_FLAG_RING_DISABLED); 1211 vrcb->bge_nicaddr = 0; 1212 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1213 (i * (sizeof(u_int64_t))), 0); 1214 vrcb++; 1215 } 1216 1217 /* Initialize RX ring indexes */ 1218 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1219 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1220 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1221 1222 /* 1223 * Set up RX return ring 0 1224 * Note that the NIC address for RX return rings is 0x00000000. 1225 * The return rings live entirely within the host, so the 1226 * nicaddr field in the RCB isn't used. 1227 */ 1228 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1229 BGE_RX_RETURN_RING_RCB); 1230 vrcb->bge_hostaddr.bge_addr_hi = 0; 1231 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1232 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1233 vrcb->bge_nicaddr = 0x00000000; 1234 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1235 1236 /* Set random backoff seed for TX */ 1237 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1238 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1239 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1240 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1241 BGE_TX_BACKOFF_SEED_MASK); 1242 1243 /* Set inter-packet gap */ 1244 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1245 1246 /* 1247 * Specify which ring to use for packets that don't match 1248 * any RX rules. 1249 */ 1250 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1251 1252 /* 1253 * Configure number of RX lists. One interrupt distribution 1254 * list, sixteen active lists, one bad frames class. 1255 */ 1256 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1257 1258 /* Inialize RX list placement stats mask. */ 1259 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1260 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1261 1262 /* Disable host coalescing until we get it set up */ 1263 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1264 1265 /* Poll to make sure it's shut down. */ 1266 for (i = 0; i < BGE_TIMEOUT; i++) { 1267 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1268 break; 1269 DELAY(10); 1270 } 1271 1272 if (i == BGE_TIMEOUT) { 1273 printf("bge%d: host coalescing engine failed to idle\n", 1274 sc->bge_unit); 1275 return(ENXIO); 1276 } 1277 1278 /* Set up host coalescing defaults */ 1279 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1280 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1281 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1282 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1283 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1284 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1285 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1286 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1287 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1288 1289 /* Set up address of statistics block */ 1290 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1291 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1292 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1293 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1294 1295 /* Set up address of status block */ 1296 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1297 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1298 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1299 vtophys(&sc->bge_rdata->bge_status_block)); 1300 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1301 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1302 1303 /* Turn on host coalescing state machine */ 1304 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1305 1306 /* Turn on RX BD completion state machine and enable attentions */ 1307 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1308 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1309 1310 /* Turn on RX list placement state machine */ 1311 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1312 1313 /* Turn on RX list selector state machine. */ 1314 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1315 1316 /* Turn on DMA, clear stats */ 1317 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1318 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1319 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1320 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1321 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1322 1323 /* Set misc. local control, enable interrupts on attentions */ 1324 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1325 1326 #ifdef notdef 1327 /* Assert GPIO pins for PHY reset */ 1328 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1329 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1330 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1331 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1332 #endif 1333 1334 /* Turn on DMA completion state machine */ 1335 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1336 1337 /* Turn on write DMA state machine */ 1338 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1339 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1340 1341 /* Turn on read DMA state machine */ 1342 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1343 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1344 1345 /* Turn on RX data completion state machine */ 1346 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1347 1348 /* Turn on RX BD initiator state machine */ 1349 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1350 1351 /* Turn on RX data and RX BD initiator state machine */ 1352 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1353 1354 /* Turn on Mbuf cluster free state machine */ 1355 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1356 1357 /* Turn on send BD completion state machine */ 1358 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1359 1360 /* Turn on send data completion state machine */ 1361 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1362 1363 /* Turn on send data initiator state machine */ 1364 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1365 1366 /* Turn on send BD initiator state machine */ 1367 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1368 1369 /* Turn on send BD selector state machine */ 1370 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1371 1372 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1373 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1374 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1375 1376 /* init LED register */ 1377 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1378 1379 /* ack/clear link change events */ 1380 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1381 BGE_MACSTAT_CFG_CHANGED); 1382 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1383 1384 /* Enable PHY auto polling (for MII/GMII only) */ 1385 if (sc->bge_tbi) { 1386 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1387 } else { 1388 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1389 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1390 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1391 BGE_EVTENB_MI_INTERRUPT); 1392 } 1393 1394 /* Enable link state change attentions. */ 1395 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1396 1397 return(0); 1398 } 1399 1400 /* 1401 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1402 * against our list and return its name if we find a match. Note 1403 * that since the Broadcom controller contains VPD support, we 1404 * can get the device name string from the controller itself instead 1405 * of the compiled-in string. This is a little slow, but it guarantees 1406 * we'll always announce the right product name. 1407 */ 1408 static int 1409 bge_probe(dev) 1410 device_t dev; 1411 { 1412 struct bge_type *t; 1413 struct bge_softc *sc; 1414 char *descbuf; 1415 1416 t = bge_devs; 1417 1418 sc = device_get_softc(dev); 1419 bzero(sc, sizeof(struct bge_softc)); 1420 sc->bge_unit = device_get_unit(dev); 1421 sc->bge_dev = dev; 1422 1423 while(t->bge_name != NULL) { 1424 if ((pci_get_vendor(dev) == t->bge_vid) && 1425 (pci_get_device(dev) == t->bge_did)) { 1426 #ifdef notdef 1427 bge_vpd_read(sc); 1428 device_set_desc(dev, sc->bge_vpd_prodname); 1429 #endif 1430 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1431 if (descbuf == NULL) 1432 return(ENOMEM); 1433 snprintf(descbuf, BGE_DEVDESC_MAX, 1434 "%s, ASIC rev. %#04x", t->bge_name, 1435 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1436 device_set_desc_copy(dev, descbuf); 1437 free(descbuf, M_TEMP); 1438 return(0); 1439 } 1440 t++; 1441 } 1442 1443 return(ENXIO); 1444 } 1445 1446 static int 1447 bge_attach(dev) 1448 device_t dev; 1449 { 1450 int s; 1451 struct ifnet *ifp; 1452 struct bge_softc *sc; 1453 u_int32_t hwcfg = 0; 1454 u_int32_t mac_addr = 0; 1455 int unit, error = 0, rid; 1456 1457 s = splimp(); 1458 1459 sc = device_get_softc(dev); 1460 unit = device_get_unit(dev); 1461 sc->bge_dev = dev; 1462 sc->bge_unit = unit; 1463 1464 /* 1465 * Map control/status registers. 1466 */ 1467 pci_enable_busmaster(dev); 1468 1469 rid = BGE_PCI_BAR0; 1470 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1471 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1472 1473 if (sc->bge_res == NULL) { 1474 printf ("bge%d: couldn't map memory\n", unit); 1475 error = ENXIO; 1476 goto fail; 1477 } 1478 1479 sc->bge_btag = rman_get_bustag(sc->bge_res); 1480 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1481 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1482 1483 /* Allocate interrupt */ 1484 rid = 0; 1485 1486 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1487 RF_SHAREABLE | RF_ACTIVE); 1488 1489 if (sc->bge_irq == NULL) { 1490 printf("bge%d: couldn't map interrupt\n", unit); 1491 error = ENXIO; 1492 goto fail; 1493 } 1494 1495 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1496 bge_intr, sc, &sc->bge_intrhand); 1497 1498 if (error) { 1499 bge_release_resources(sc); 1500 printf("bge%d: couldn't set up irq\n", unit); 1501 goto fail; 1502 } 1503 1504 sc->bge_unit = unit; 1505 1506 /* Try to reset the chip. */ 1507 bge_reset(sc); 1508 1509 if (bge_chipinit(sc)) { 1510 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1511 bge_release_resources(sc); 1512 error = ENXIO; 1513 goto fail; 1514 } 1515 1516 /* 1517 * Get station address from the EEPROM. 1518 */ 1519 mac_addr = bge_readmem_ind(sc, 0x0c14); 1520 if ((mac_addr >> 16) == 0x484b) { 1521 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1522 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1523 mac_addr = bge_readmem_ind(sc, 0x0c18); 1524 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1525 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1526 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1527 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1528 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1529 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1530 printf("bge%d: failed to read station address\n", unit); 1531 bge_release_resources(sc); 1532 error = ENXIO; 1533 goto fail; 1534 } 1535 1536 /* 1537 * A Broadcom chip was detected. Inform the world. 1538 */ 1539 printf("bge%d: Ethernet address: %6D\n", unit, 1540 sc->arpcom.ac_enaddr, ":"); 1541 1542 /* Allocate the general information block and ring buffers. */ 1543 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1544 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1545 1546 if (sc->bge_rdata == NULL) { 1547 bge_release_resources(sc); 1548 error = ENXIO; 1549 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1550 goto fail; 1551 } 1552 1553 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1554 1555 /* Try to allocate memory for jumbo buffers. */ 1556 if (bge_alloc_jumbo_mem(sc)) { 1557 printf("bge%d: jumbo buffer allocation " 1558 "failed\n", sc->bge_unit); 1559 bge_release_resources(sc); 1560 error = ENXIO; 1561 goto fail; 1562 } 1563 1564 /* Set default tuneable values. */ 1565 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1566 sc->bge_rx_coal_ticks = 150; 1567 sc->bge_tx_coal_ticks = 150; 1568 sc->bge_rx_max_coal_bds = 64; 1569 sc->bge_tx_max_coal_bds = 128; 1570 1571 /* Set up ifnet structure */ 1572 ifp = &sc->arpcom.ac_if; 1573 ifp->if_softc = sc; 1574 ifp->if_unit = sc->bge_unit; 1575 ifp->if_name = "bge"; 1576 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1577 ifp->if_ioctl = bge_ioctl; 1578 ifp->if_output = ether_output; 1579 ifp->if_start = bge_start; 1580 ifp->if_watchdog = bge_watchdog; 1581 ifp->if_init = bge_init; 1582 ifp->if_mtu = ETHERMTU; 1583 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1584 ifp->if_hwassist = BGE_CSUM_FEATURES; 1585 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1586 ifp->if_capenable = ifp->if_capabilities; 1587 1588 /* Save ASIC rev. */ 1589 1590 sc->bge_asicrev = 1591 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1592 BGE_PCIMISCCTL_ASICREV; 1593 1594 /* Pretend all 5700s are the same */ 1595 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700) 1596 sc->bge_asicrev = BGE_ASICREV_BCM5700; 1597 1598 /* 1599 * Figure out what sort of media we have by checking the 1600 * hardware config word in the first 32k of NIC internal memory, 1601 * or fall back to examining the EEPROM if necessary. 1602 * Note: on some BCM5700 cards, this value appears to be unset. 1603 * If that's the case, we have to rely on identifying the NIC 1604 * by its PCI subsystem ID, as we do below for the SysKonnect 1605 * SK-9D41. 1606 */ 1607 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1608 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1609 else { 1610 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1611 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1612 hwcfg = ntohl(hwcfg); 1613 } 1614 1615 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1616 sc->bge_tbi = 1; 1617 1618 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1619 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1620 sc->bge_tbi = 1; 1621 1622 if (sc->bge_tbi) { 1623 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1624 bge_ifmedia_upd, bge_ifmedia_sts); 1625 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1626 ifmedia_add(&sc->bge_ifmedia, 1627 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1628 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1629 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1630 } else { 1631 /* 1632 * Do transceiver setup. 1633 */ 1634 if (mii_phy_probe(dev, &sc->bge_miibus, 1635 bge_ifmedia_upd, bge_ifmedia_sts)) { 1636 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1637 bge_release_resources(sc); 1638 bge_free_jumbo_mem(sc); 1639 error = ENXIO; 1640 goto fail; 1641 } 1642 } 1643 1644 /* 1645 * When using the BCM5701 in PCI-X mode, data corruption has 1646 * been observed in the first few bytes of some received packets. 1647 * Aligning the packet buffer in memory eliminates the corruption. 1648 * Unfortunately, this misaligns the packet payloads. On platforms 1649 * which do not support unaligned accesses, we will realign the 1650 * payloads by copying the received packets. 1651 */ 1652 switch (sc->bge_asicrev) { 1653 case BGE_ASICREV_BCM5701_A0: 1654 case BGE_ASICREV_BCM5701_B0: 1655 case BGE_ASICREV_BCM5701_B2: 1656 case BGE_ASICREV_BCM5701_B5: 1657 /* If in PCI-X mode, work around the alignment bug. */ 1658 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1659 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1660 BGE_PCISTATE_PCI_BUSSPEED) 1661 sc->bge_rx_alignment_bug = 1; 1662 break; 1663 } 1664 1665 /* 1666 * Call MI attach routine. 1667 */ 1668 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1669 callout_handle_init(&sc->bge_stat_ch); 1670 1671 fail: 1672 splx(s); 1673 1674 return(error); 1675 } 1676 1677 static int 1678 bge_detach(dev) 1679 device_t dev; 1680 { 1681 struct bge_softc *sc; 1682 struct ifnet *ifp; 1683 int s; 1684 1685 s = splimp(); 1686 1687 sc = device_get_softc(dev); 1688 ifp = &sc->arpcom.ac_if; 1689 1690 ether_ifdetach(ifp); 1691 bge_stop(sc); 1692 bge_reset(sc); 1693 1694 if (sc->bge_tbi) { 1695 ifmedia_removeall(&sc->bge_ifmedia); 1696 } else { 1697 bus_generic_detach(dev); 1698 device_delete_child(dev, sc->bge_miibus); 1699 } 1700 1701 bge_release_resources(sc); 1702 bge_free_jumbo_mem(sc); 1703 1704 splx(s); 1705 1706 return(0); 1707 } 1708 1709 static void 1710 bge_release_resources(sc) 1711 struct bge_softc *sc; 1712 { 1713 device_t dev; 1714 1715 dev = sc->bge_dev; 1716 1717 if (sc->bge_vpd_prodname != NULL) 1718 free(sc->bge_vpd_prodname, M_DEVBUF); 1719 1720 if (sc->bge_vpd_readonly != NULL) 1721 free(sc->bge_vpd_readonly, M_DEVBUF); 1722 1723 if (sc->bge_intrhand != NULL) 1724 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1725 1726 if (sc->bge_irq != NULL) 1727 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1728 1729 if (sc->bge_res != NULL) 1730 bus_release_resource(dev, SYS_RES_MEMORY, 1731 BGE_PCI_BAR0, sc->bge_res); 1732 1733 if (sc->bge_rdata != NULL) 1734 contigfree(sc->bge_rdata, 1735 sizeof(struct bge_ring_data), M_DEVBUF); 1736 1737 return; 1738 } 1739 1740 static void 1741 bge_reset(sc) 1742 struct bge_softc *sc; 1743 { 1744 device_t dev; 1745 u_int32_t cachesize, command, pcistate; 1746 int i, val = 0; 1747 1748 dev = sc->bge_dev; 1749 1750 /* Save some important PCI state. */ 1751 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1752 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1753 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1754 1755 pci_write_config(dev, BGE_PCI_MISC_CTL, 1756 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1757 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1758 1759 /* Issue global reset */ 1760 bge_writereg_ind(sc, BGE_MISC_CFG, 1761 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1762 1763 DELAY(1000); 1764 1765 /* Reset some of the PCI state that got zapped by reset */ 1766 pci_write_config(dev, BGE_PCI_MISC_CTL, 1767 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1768 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1769 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1770 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1771 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1772 1773 /* 1774 * Prevent PXE restart: write a magic number to the 1775 * general communications memory at 0xB50. 1776 */ 1777 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1778 /* 1779 * Poll the value location we just wrote until 1780 * we see the 1's complement of the magic number. 1781 * This indicates that the firmware initialization 1782 * is complete. 1783 */ 1784 for (i = 0; i < BGE_TIMEOUT; i++) { 1785 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1786 if (val == ~BGE_MAGIC_NUMBER) 1787 break; 1788 DELAY(10); 1789 } 1790 1791 if (i == BGE_TIMEOUT) { 1792 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1793 return; 1794 } 1795 1796 /* 1797 * XXX Wait for the value of the PCISTATE register to 1798 * return to its original pre-reset state. This is a 1799 * fairly good indicator of reset completion. If we don't 1800 * wait for the reset to fully complete, trying to read 1801 * from the device's non-PCI registers may yield garbage 1802 * results. 1803 */ 1804 for (i = 0; i < BGE_TIMEOUT; i++) { 1805 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1806 break; 1807 DELAY(10); 1808 } 1809 1810 /* Enable memory arbiter. */ 1811 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1812 1813 /* Fix up byte swapping */ 1814 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1815 BGE_MODECTL_BYTESWAP_DATA); 1816 1817 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1818 1819 DELAY(10000); 1820 1821 return; 1822 } 1823 1824 /* 1825 * Frame reception handling. This is called if there's a frame 1826 * on the receive return list. 1827 * 1828 * Note: we have to be able to handle two possibilities here: 1829 * 1) the frame is from the jumbo recieve ring 1830 * 2) the frame is from the standard receive ring 1831 */ 1832 1833 static void 1834 bge_rxeof(sc) 1835 struct bge_softc *sc; 1836 { 1837 struct ifnet *ifp; 1838 int stdcnt = 0, jumbocnt = 0; 1839 1840 ifp = &sc->arpcom.ac_if; 1841 1842 while(sc->bge_rx_saved_considx != 1843 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1844 struct bge_rx_bd *cur_rx; 1845 u_int32_t rxidx; 1846 struct ether_header *eh; 1847 struct mbuf *m = NULL; 1848 u_int16_t vlan_tag = 0; 1849 int have_tag = 0; 1850 1851 cur_rx = 1852 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1853 1854 rxidx = cur_rx->bge_idx; 1855 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1856 1857 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1858 have_tag = 1; 1859 vlan_tag = cur_rx->bge_vlan_tag; 1860 } 1861 1862 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1863 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1864 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1865 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1866 jumbocnt++; 1867 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1868 ifp->if_ierrors++; 1869 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1870 continue; 1871 } 1872 if (bge_newbuf_jumbo(sc, 1873 sc->bge_jumbo, NULL) == ENOBUFS) { 1874 ifp->if_ierrors++; 1875 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1876 continue; 1877 } 1878 } else { 1879 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1880 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1881 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1882 stdcnt++; 1883 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1884 ifp->if_ierrors++; 1885 bge_newbuf_std(sc, sc->bge_std, m); 1886 continue; 1887 } 1888 if (bge_newbuf_std(sc, sc->bge_std, 1889 NULL) == ENOBUFS) { 1890 ifp->if_ierrors++; 1891 bge_newbuf_std(sc, sc->bge_std, m); 1892 continue; 1893 } 1894 } 1895 1896 ifp->if_ipackets++; 1897 #ifndef __i386__ 1898 /* 1899 * The i386 allows unaligned accesses, but for other 1900 * platforms we must make sure the payload is aligned. 1901 */ 1902 if (sc->bge_rx_alignment_bug) { 1903 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1904 cur_rx->bge_len); 1905 m->m_data += ETHER_ALIGN; 1906 } 1907 #endif 1908 eh = mtod(m, struct ether_header *); 1909 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1910 m->m_pkthdr.rcvif = ifp; 1911 1912 #if 0 /* currently broken for some packets, possibly related to TCP options */ 1913 if (ifp->if_hwassist) { 1914 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1915 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1916 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1917 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1918 m->m_pkthdr.csum_data = 1919 cur_rx->bge_tcp_udp_csum; 1920 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1921 } 1922 } 1923 #endif 1924 1925 /* 1926 * If we received a packet with a vlan tag, 1927 * attach that information to the packet. 1928 */ 1929 if (have_tag) 1930 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1931 1932 (*ifp->if_input)(ifp, m); 1933 } 1934 1935 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1936 if (stdcnt) 1937 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1938 if (jumbocnt) 1939 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1940 1941 return; 1942 } 1943 1944 static void 1945 bge_txeof(sc) 1946 struct bge_softc *sc; 1947 { 1948 struct bge_tx_bd *cur_tx = NULL; 1949 struct ifnet *ifp; 1950 1951 ifp = &sc->arpcom.ac_if; 1952 1953 /* 1954 * Go through our tx ring and free mbufs for those 1955 * frames that have been sent. 1956 */ 1957 while (sc->bge_tx_saved_considx != 1958 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1959 u_int32_t idx = 0; 1960 1961 idx = sc->bge_tx_saved_considx; 1962 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1963 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1964 ifp->if_opackets++; 1965 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1966 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1967 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1968 } 1969 sc->bge_txcnt--; 1970 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1971 ifp->if_timer = 0; 1972 } 1973 1974 if (cur_tx != NULL) 1975 ifp->if_flags &= ~IFF_OACTIVE; 1976 1977 return; 1978 } 1979 1980 static void 1981 bge_intr(xsc) 1982 void *xsc; 1983 { 1984 struct bge_softc *sc; 1985 struct ifnet *ifp; 1986 1987 sc = xsc; 1988 ifp = &sc->arpcom.ac_if; 1989 1990 #ifdef notdef 1991 /* Avoid this for now -- checking this register is expensive. */ 1992 /* Make sure this is really our interrupt. */ 1993 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1994 return; 1995 #endif 1996 /* Ack interrupt and stop others from occuring. */ 1997 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 1998 1999 /* 2000 * Process link state changes. 2001 * Grrr. The link status word in the status block does 2002 * not work correctly on the BCM5700 rev AX and BX chips, 2003 * according to all avaibable information. Hence, we have 2004 * to enable MII interrupts in order to properly obtain 2005 * async link changes. Unfortunately, this also means that 2006 * we have to read the MAC status register to detect link 2007 * changes, thereby adding an additional register access to 2008 * the interrupt handler. 2009 */ 2010 2011 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2012 u_int32_t status; 2013 2014 status = CSR_READ_4(sc, BGE_MAC_STS); 2015 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2016 sc->bge_link = 0; 2017 untimeout(bge_tick, sc, sc->bge_stat_ch); 2018 bge_tick(sc); 2019 /* Clear the interrupt */ 2020 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2021 BGE_EVTENB_MI_INTERRUPT); 2022 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2023 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2024 BRGPHY_INTRS); 2025 } 2026 } else { 2027 if (sc->bge_rdata->bge_status_block.bge_status & 2028 BGE_STATFLAG_LINKSTATE_CHANGED) { 2029 sc->bge_link = 0; 2030 untimeout(bge_tick, sc, sc->bge_stat_ch); 2031 bge_tick(sc); 2032 /* Clear the interrupt */ 2033 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2034 BGE_MACSTAT_CFG_CHANGED); 2035 } 2036 } 2037 2038 if (ifp->if_flags & IFF_RUNNING) { 2039 /* Check RX return ring producer/consumer */ 2040 bge_rxeof(sc); 2041 2042 /* Check TX ring producer/consumer */ 2043 bge_txeof(sc); 2044 } 2045 2046 bge_handle_events(sc); 2047 2048 /* Re-enable interrupts. */ 2049 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2050 2051 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2052 bge_start(ifp); 2053 2054 return; 2055 } 2056 2057 static void 2058 bge_tick(xsc) 2059 void *xsc; 2060 { 2061 struct bge_softc *sc; 2062 struct mii_data *mii = NULL; 2063 struct ifmedia *ifm = NULL; 2064 struct ifnet *ifp; 2065 int s; 2066 2067 sc = xsc; 2068 ifp = &sc->arpcom.ac_if; 2069 2070 s = splimp(); 2071 2072 bge_stats_update(sc); 2073 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2074 if (sc->bge_link) { 2075 splx(s); 2076 return; 2077 } 2078 2079 if (sc->bge_tbi) { 2080 ifm = &sc->bge_ifmedia; 2081 if (CSR_READ_4(sc, BGE_MAC_STS) & 2082 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2083 sc->bge_link++; 2084 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2085 printf("bge%d: gigabit link up\n", sc->bge_unit); 2086 if (ifp->if_snd.ifq_head != NULL) 2087 bge_start(ifp); 2088 } 2089 splx(s); 2090 return; 2091 } 2092 2093 mii = device_get_softc(sc->bge_miibus); 2094 mii_tick(mii); 2095 2096 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2097 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2098 sc->bge_link++; 2099 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2100 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2101 printf("bge%d: gigabit link up\n", 2102 sc->bge_unit); 2103 if (ifp->if_snd.ifq_head != NULL) 2104 bge_start(ifp); 2105 } 2106 2107 splx(s); 2108 2109 return; 2110 } 2111 2112 static void 2113 bge_stats_update(sc) 2114 struct bge_softc *sc; 2115 { 2116 struct ifnet *ifp; 2117 struct bge_stats *stats; 2118 2119 ifp = &sc->arpcom.ac_if; 2120 2121 stats = (struct bge_stats *)(sc->bge_vhandle + 2122 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2123 2124 ifp->if_collisions += 2125 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2126 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2127 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2128 stats->dot3StatsLateCollisions.bge_addr_lo) - 2129 ifp->if_collisions; 2130 2131 #ifdef notdef 2132 ifp->if_collisions += 2133 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2134 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2135 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2136 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2137 ifp->if_collisions; 2138 #endif 2139 2140 return; 2141 } 2142 2143 /* 2144 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2145 * pointers to descriptors. 2146 */ 2147 static int 2148 bge_encap(sc, m_head, txidx) 2149 struct bge_softc *sc; 2150 struct mbuf *m_head; 2151 u_int32_t *txidx; 2152 { 2153 struct bge_tx_bd *f = NULL; 2154 struct mbuf *m; 2155 u_int32_t frag, cur, cnt = 0; 2156 u_int16_t csum_flags = 0; 2157 struct m_tag *mtag; 2158 2159 m = m_head; 2160 cur = frag = *txidx; 2161 2162 if (m_head->m_pkthdr.csum_flags) { 2163 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2164 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2165 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2166 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2167 if (m_head->m_flags & M_LASTFRAG) 2168 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2169 else if (m_head->m_flags & M_FRAG) 2170 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2171 } 2172 2173 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2174 2175 /* 2176 * Start packing the mbufs in this chain into 2177 * the fragment pointers. Stop when we run out 2178 * of fragments or hit the end of the mbuf chain. 2179 */ 2180 for (m = m_head; m != NULL; m = m->m_next) { 2181 if (m->m_len != 0) { 2182 f = &sc->bge_rdata->bge_tx_ring[frag]; 2183 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2184 break; 2185 BGE_HOSTADDR(f->bge_addr) = 2186 vtophys(mtod(m, vm_offset_t)); 2187 f->bge_len = m->m_len; 2188 f->bge_flags = csum_flags; 2189 if (mtag != NULL) { 2190 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2191 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2192 } else { 2193 f->bge_vlan_tag = 0; 2194 } 2195 /* 2196 * Sanity check: avoid coming within 16 descriptors 2197 * of the end of the ring. 2198 */ 2199 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2200 return(ENOBUFS); 2201 cur = frag; 2202 BGE_INC(frag, BGE_TX_RING_CNT); 2203 cnt++; 2204 } 2205 } 2206 2207 if (m != NULL) 2208 return(ENOBUFS); 2209 2210 if (frag == sc->bge_tx_saved_considx) 2211 return(ENOBUFS); 2212 2213 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2214 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2215 sc->bge_txcnt += cnt; 2216 2217 *txidx = frag; 2218 2219 return(0); 2220 } 2221 2222 /* 2223 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2224 * to the mbuf data regions directly in the transmit descriptors. 2225 */ 2226 static void 2227 bge_start(ifp) 2228 struct ifnet *ifp; 2229 { 2230 struct bge_softc *sc; 2231 struct mbuf *m_head = NULL; 2232 u_int32_t prodidx = 0; 2233 2234 sc = ifp->if_softc; 2235 2236 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2237 return; 2238 2239 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2240 2241 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2242 IF_DEQUEUE(&ifp->if_snd, m_head); 2243 if (m_head == NULL) 2244 break; 2245 2246 /* 2247 * XXX 2248 * safety overkill. If this is a fragmented packet chain 2249 * with delayed TCP/UDP checksums, then only encapsulate 2250 * it if we have enough descriptors to handle the entire 2251 * chain at once. 2252 * (paranoia -- may not actually be needed) 2253 */ 2254 if (m_head->m_flags & M_FIRSTFRAG && 2255 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2256 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2257 m_head->m_pkthdr.csum_data + 16) { 2258 IF_PREPEND(&ifp->if_snd, m_head); 2259 ifp->if_flags |= IFF_OACTIVE; 2260 break; 2261 } 2262 } 2263 2264 /* 2265 * Pack the data into the transmit ring. If we 2266 * don't have room, set the OACTIVE flag and wait 2267 * for the NIC to drain the ring. 2268 */ 2269 if (bge_encap(sc, m_head, &prodidx)) { 2270 IF_PREPEND(&ifp->if_snd, m_head); 2271 ifp->if_flags |= IFF_OACTIVE; 2272 break; 2273 } 2274 2275 /* 2276 * If there's a BPF listener, bounce a copy of this frame 2277 * to him. 2278 */ 2279 BPF_MTAP(ifp, m_head); 2280 } 2281 2282 /* Transmit */ 2283 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2284 2285 /* 2286 * Set a timeout in case the chip goes out to lunch. 2287 */ 2288 ifp->if_timer = 5; 2289 2290 return; 2291 } 2292 2293 /* 2294 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2295 * program its internal DSP. Failing to do this can result in 2296 * massive packet loss at 1Gb speeds. 2297 */ 2298 static void 2299 bge_phy_hack(sc) 2300 struct bge_softc *sc; 2301 { 2302 struct bge_bcom_hack bhack[] = { 2303 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2304 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2305 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2306 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2307 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2308 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2309 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2310 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2311 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2312 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2313 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2314 { 0, 0 } }; 2315 u_int16_t vid, did; 2316 int i; 2317 2318 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2319 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2320 2321 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2322 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2323 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2324 i = 0; 2325 while(bhack[i].reg) { 2326 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2327 bhack[i].val); 2328 i++; 2329 } 2330 } 2331 2332 return; 2333 } 2334 2335 static void 2336 bge_init(xsc) 2337 void *xsc; 2338 { 2339 struct bge_softc *sc = xsc; 2340 struct ifnet *ifp; 2341 u_int16_t *m; 2342 int s; 2343 2344 s = splimp(); 2345 2346 ifp = &sc->arpcom.ac_if; 2347 2348 if (ifp->if_flags & IFF_RUNNING) { 2349 splx(s); 2350 return; 2351 } 2352 2353 /* Cancel pending I/O and flush buffers. */ 2354 bge_stop(sc); 2355 bge_reset(sc); 2356 bge_chipinit(sc); 2357 2358 /* 2359 * Init the various state machines, ring 2360 * control blocks and firmware. 2361 */ 2362 if (bge_blockinit(sc)) { 2363 printf("bge%d: initialization failure\n", sc->bge_unit); 2364 splx(s); 2365 return; 2366 } 2367 2368 ifp = &sc->arpcom.ac_if; 2369 2370 /* Specify MTU. */ 2371 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2372 ETHER_HDR_LEN + ETHER_CRC_LEN); 2373 2374 /* Load our MAC address. */ 2375 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2376 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2377 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2378 2379 /* Enable or disable promiscuous mode as needed. */ 2380 if (ifp->if_flags & IFF_PROMISC) { 2381 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2382 } else { 2383 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2384 } 2385 2386 /* Program multicast filter. */ 2387 bge_setmulti(sc); 2388 2389 /* Init RX ring. */ 2390 bge_init_rx_ring_std(sc); 2391 2392 /* Init jumbo RX ring. */ 2393 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2394 bge_init_rx_ring_jumbo(sc); 2395 2396 /* Init our RX return ring index */ 2397 sc->bge_rx_saved_considx = 0; 2398 2399 /* Init TX ring. */ 2400 bge_init_tx_ring(sc); 2401 2402 /* Turn on transmitter */ 2403 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2404 2405 /* Turn on receiver */ 2406 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2407 2408 /* Tell firmware we're alive. */ 2409 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2410 2411 /* Enable host interrupts. */ 2412 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2413 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2414 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2415 2416 bge_ifmedia_upd(ifp); 2417 2418 ifp->if_flags |= IFF_RUNNING; 2419 ifp->if_flags &= ~IFF_OACTIVE; 2420 2421 splx(s); 2422 2423 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2424 2425 return; 2426 } 2427 2428 /* 2429 * Set media options. 2430 */ 2431 static int 2432 bge_ifmedia_upd(ifp) 2433 struct ifnet *ifp; 2434 { 2435 struct bge_softc *sc; 2436 struct mii_data *mii; 2437 struct ifmedia *ifm; 2438 2439 sc = ifp->if_softc; 2440 ifm = &sc->bge_ifmedia; 2441 2442 /* If this is a 1000baseX NIC, enable the TBI port. */ 2443 if (sc->bge_tbi) { 2444 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2445 return(EINVAL); 2446 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2447 case IFM_AUTO: 2448 break; 2449 case IFM_1000_SX: 2450 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2451 BGE_CLRBIT(sc, BGE_MAC_MODE, 2452 BGE_MACMODE_HALF_DUPLEX); 2453 } else { 2454 BGE_SETBIT(sc, BGE_MAC_MODE, 2455 BGE_MACMODE_HALF_DUPLEX); 2456 } 2457 break; 2458 default: 2459 return(EINVAL); 2460 } 2461 return(0); 2462 } 2463 2464 mii = device_get_softc(sc->bge_miibus); 2465 sc->bge_link = 0; 2466 if (mii->mii_instance) { 2467 struct mii_softc *miisc; 2468 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2469 miisc = LIST_NEXT(miisc, mii_list)) 2470 mii_phy_reset(miisc); 2471 } 2472 bge_phy_hack(sc); 2473 mii_mediachg(mii); 2474 2475 return(0); 2476 } 2477 2478 /* 2479 * Report current media status. 2480 */ 2481 static void 2482 bge_ifmedia_sts(ifp, ifmr) 2483 struct ifnet *ifp; 2484 struct ifmediareq *ifmr; 2485 { 2486 struct bge_softc *sc; 2487 struct mii_data *mii; 2488 2489 sc = ifp->if_softc; 2490 2491 if (sc->bge_tbi) { 2492 ifmr->ifm_status = IFM_AVALID; 2493 ifmr->ifm_active = IFM_ETHER; 2494 if (CSR_READ_4(sc, BGE_MAC_STS) & 2495 BGE_MACSTAT_TBI_PCS_SYNCHED) 2496 ifmr->ifm_status |= IFM_ACTIVE; 2497 ifmr->ifm_active |= IFM_1000_SX; 2498 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2499 ifmr->ifm_active |= IFM_HDX; 2500 else 2501 ifmr->ifm_active |= IFM_FDX; 2502 return; 2503 } 2504 2505 mii = device_get_softc(sc->bge_miibus); 2506 mii_pollstat(mii); 2507 ifmr->ifm_active = mii->mii_media_active; 2508 ifmr->ifm_status = mii->mii_media_status; 2509 2510 return; 2511 } 2512 2513 static int 2514 bge_ioctl(ifp, command, data) 2515 struct ifnet *ifp; 2516 u_long command; 2517 caddr_t data; 2518 { 2519 struct bge_softc *sc = ifp->if_softc; 2520 struct ifreq *ifr = (struct ifreq *) data; 2521 int s, mask, error = 0; 2522 struct mii_data *mii; 2523 2524 s = splimp(); 2525 2526 switch(command) { 2527 case SIOCSIFMTU: 2528 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2529 error = EINVAL; 2530 else { 2531 ifp->if_mtu = ifr->ifr_mtu; 2532 ifp->if_flags &= ~IFF_RUNNING; 2533 bge_init(sc); 2534 } 2535 break; 2536 case SIOCSIFFLAGS: 2537 if (ifp->if_flags & IFF_UP) { 2538 /* 2539 * If only the state of the PROMISC flag changed, 2540 * then just use the 'set promisc mode' command 2541 * instead of reinitializing the entire NIC. Doing 2542 * a full re-init means reloading the firmware and 2543 * waiting for it to start up, which may take a 2544 * second or two. 2545 */ 2546 if (ifp->if_flags & IFF_RUNNING && 2547 ifp->if_flags & IFF_PROMISC && 2548 !(sc->bge_if_flags & IFF_PROMISC)) { 2549 BGE_SETBIT(sc, BGE_RX_MODE, 2550 BGE_RXMODE_RX_PROMISC); 2551 } else if (ifp->if_flags & IFF_RUNNING && 2552 !(ifp->if_flags & IFF_PROMISC) && 2553 sc->bge_if_flags & IFF_PROMISC) { 2554 BGE_CLRBIT(sc, BGE_RX_MODE, 2555 BGE_RXMODE_RX_PROMISC); 2556 } else 2557 bge_init(sc); 2558 } else { 2559 if (ifp->if_flags & IFF_RUNNING) { 2560 bge_stop(sc); 2561 } 2562 } 2563 sc->bge_if_flags = ifp->if_flags; 2564 error = 0; 2565 break; 2566 case SIOCADDMULTI: 2567 case SIOCDELMULTI: 2568 if (ifp->if_flags & IFF_RUNNING) { 2569 bge_setmulti(sc); 2570 error = 0; 2571 } 2572 break; 2573 case SIOCSIFMEDIA: 2574 case SIOCGIFMEDIA: 2575 if (sc->bge_tbi) { 2576 error = ifmedia_ioctl(ifp, ifr, 2577 &sc->bge_ifmedia, command); 2578 } else { 2579 mii = device_get_softc(sc->bge_miibus); 2580 error = ifmedia_ioctl(ifp, ifr, 2581 &mii->mii_media, command); 2582 } 2583 break; 2584 case SIOCSIFCAP: 2585 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2586 if (mask & IFCAP_HWCSUM) { 2587 if (IFCAP_HWCSUM & ifp->if_capenable) 2588 ifp->if_capenable &= ~IFCAP_HWCSUM; 2589 else 2590 ifp->if_capenable |= IFCAP_HWCSUM; 2591 } 2592 error = 0; 2593 break; 2594 default: 2595 error = ether_ioctl(ifp, command, data); 2596 break; 2597 } 2598 2599 (void)splx(s); 2600 2601 return(error); 2602 } 2603 2604 static void 2605 bge_watchdog(ifp) 2606 struct ifnet *ifp; 2607 { 2608 struct bge_softc *sc; 2609 2610 sc = ifp->if_softc; 2611 2612 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2613 2614 ifp->if_flags &= ~IFF_RUNNING; 2615 bge_init(sc); 2616 2617 ifp->if_oerrors++; 2618 2619 return; 2620 } 2621 2622 /* 2623 * Stop the adapter and free any mbufs allocated to the 2624 * RX and TX lists. 2625 */ 2626 static void 2627 bge_stop(sc) 2628 struct bge_softc *sc; 2629 { 2630 struct ifnet *ifp; 2631 struct ifmedia_entry *ifm; 2632 struct mii_data *mii = NULL; 2633 int mtmp, itmp; 2634 2635 ifp = &sc->arpcom.ac_if; 2636 2637 if (!sc->bge_tbi) 2638 mii = device_get_softc(sc->bge_miibus); 2639 2640 untimeout(bge_tick, sc, sc->bge_stat_ch); 2641 2642 /* 2643 * Disable all of the receiver blocks 2644 */ 2645 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2646 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2647 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2648 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2649 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2650 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2651 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2652 2653 /* 2654 * Disable all of the transmit blocks 2655 */ 2656 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2657 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2658 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2659 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2660 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2661 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2662 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2663 2664 /* 2665 * Shut down all of the memory managers and related 2666 * state machines. 2667 */ 2668 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2669 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2670 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2671 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2672 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2673 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2674 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2675 2676 /* Disable host interrupts. */ 2677 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2678 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2679 2680 /* 2681 * Tell firmware we're shutting down. 2682 */ 2683 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2684 2685 /* Free the RX lists. */ 2686 bge_free_rx_ring_std(sc); 2687 2688 /* Free jumbo RX list. */ 2689 bge_free_rx_ring_jumbo(sc); 2690 2691 /* Free TX buffers. */ 2692 bge_free_tx_ring(sc); 2693 2694 /* 2695 * Isolate/power down the PHY, but leave the media selection 2696 * unchanged so that things will be put back to normal when 2697 * we bring the interface back up. 2698 */ 2699 if (!sc->bge_tbi) { 2700 itmp = ifp->if_flags; 2701 ifp->if_flags |= IFF_UP; 2702 ifm = mii->mii_media.ifm_cur; 2703 mtmp = ifm->ifm_media; 2704 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2705 mii_mediachg(mii); 2706 ifm->ifm_media = mtmp; 2707 ifp->if_flags = itmp; 2708 } 2709 2710 sc->bge_link = 0; 2711 2712 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2713 2714 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2715 2716 return; 2717 } 2718 2719 /* 2720 * Stop all chip I/O so that the kernel's probe routines don't 2721 * get confused by errant DMAs when rebooting. 2722 */ 2723 static void 2724 bge_shutdown(dev) 2725 device_t dev; 2726 { 2727 struct bge_softc *sc; 2728 2729 sc = device_get_softc(dev); 2730 2731 bge_stop(sc); 2732 bge_reset(sc); 2733 2734 return; 2735 } 2736