1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 36 * 37 * The Broadcom BCM5700 is based on technology originally developed by 38 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 39 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 40 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 41 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 42 * frames, highly configurable RX filtering, and 16 RX and TX queues 43 * (which, along with RX filter rules, can be used for QOS applications). 44 * Other features, such as TCP segmentation, may be available as part 45 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 46 * firmware images can be stored in hardware and need not be compiled 47 * into the driver. 48 * 49 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 50 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 51 * 52 * The BCM5701 is a single-chip solution incorporating both the BCM5700 53 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 54 * does not support external SSRAM. 55 * 56 * Broadcom also produces a variation of the BCM5700 under the "Altima" 57 * brand name, which is functionally similar but lacks PCI-X support. 58 * 59 * Without external SSRAM, you can only have at most 4 TX rings, 60 * and the use of the mini RX ring is disabled. This seems to imply 61 * that these features are simply not available on the BCM5701. As a 62 * result, this driver does not implement any support for the mini RX 63 * ring. 64 */ 65 66 #include <sys/cdefs.h> 67 __FBSDID("$FreeBSD$"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/sockio.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/queue.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 84 #include <net/bpf.h> 85 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <netinet/in_systm.h> 90 #include <netinet/in.h> 91 #include <netinet/ip.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/clock.h> /* for DELAY */ 96 #include <machine/bus_memio.h> 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 #include "miidevs.h" 105 #include <dev/mii/brgphyreg.h> 106 107 #include <pci/pcireg.h> 108 #include <pci/pcivar.h> 109 110 #include <dev/bge/if_bgereg.h> 111 112 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 113 114 MODULE_DEPEND(bge, pci, 1, 1, 1); 115 MODULE_DEPEND(bge, ether, 1, 1, 1); 116 MODULE_DEPEND(bge, miibus, 1, 1, 1); 117 118 /* "controller miibus0" required. See GENERIC if you get errors here. */ 119 #include "miibus_if.h" 120 121 /* 122 * Various supported device vendors/types and their names. Note: the 123 * spec seems to indicate that the hardware still has Alteon's vendor 124 * ID burned into it, though it will always be overriden by the vendor 125 * ID in the EEPROM. Just to be safe, we cover all possibilities. 126 */ 127 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 128 129 static struct bge_type bge_devs[] = { 130 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 131 "Broadcom BCM5700 Gigabit Ethernet" }, 132 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 133 "Broadcom BCM5701 Gigabit Ethernet" }, 134 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 135 "Broadcom BCM5700 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 137 "Broadcom BCM5701 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 139 "Broadcom BCM5702 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 141 "Broadcom BCM5702X Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 143 "Broadcom BCM5703 Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 145 "Broadcom BCM5703X Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 147 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 149 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 151 "Broadcom BCM5705 Gigabit Ethernet" }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 153 "Broadcom BCM5705M Gigabit Ethernet" }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 155 "Broadcom BCM5705M Gigabit Ethernet" }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 157 "Broadcom BCM5782 Gigabit Ethernet" }, 158 { SK_VENDORID, SK_DEVICEID_ALTIMA, 159 "SysKonnect Gigabit Ethernet" }, 160 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 161 "Altima AC1000 Gigabit Ethernet" }, 162 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 163 "Altima AC9100 Gigabit Ethernet" }, 164 { 0, 0, NULL } 165 }; 166 167 static int bge_probe (device_t); 168 static int bge_attach (device_t); 169 static int bge_detach (device_t); 170 static void bge_release_resources 171 (struct bge_softc *); 172 static void bge_txeof (struct bge_softc *); 173 static void bge_rxeof (struct bge_softc *); 174 175 static void bge_tick (void *); 176 static void bge_stats_update (struct bge_softc *); 177 static void bge_stats_update_regs 178 (struct bge_softc *); 179 static int bge_encap (struct bge_softc *, struct mbuf *, 180 u_int32_t *); 181 182 static void bge_intr (void *); 183 static void bge_start (struct ifnet *); 184 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 185 static void bge_init (void *); 186 static void bge_stop (struct bge_softc *); 187 static void bge_watchdog (struct ifnet *); 188 static void bge_shutdown (device_t); 189 static int bge_ifmedia_upd (struct ifnet *); 190 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 191 192 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 193 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 194 195 static u_int32_t bge_crc (caddr_t); 196 static void bge_setmulti (struct bge_softc *); 197 198 static void bge_handle_events (struct bge_softc *); 199 static int bge_alloc_jumbo_mem (struct bge_softc *); 200 static void bge_free_jumbo_mem (struct bge_softc *); 201 static void *bge_jalloc (struct bge_softc *); 202 static void bge_jfree (void *, void *); 203 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 204 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 205 static int bge_init_rx_ring_std (struct bge_softc *); 206 static void bge_free_rx_ring_std (struct bge_softc *); 207 static int bge_init_rx_ring_jumbo (struct bge_softc *); 208 static void bge_free_rx_ring_jumbo (struct bge_softc *); 209 static void bge_free_tx_ring (struct bge_softc *); 210 static int bge_init_tx_ring (struct bge_softc *); 211 212 static int bge_chipinit (struct bge_softc *); 213 static int bge_blockinit (struct bge_softc *); 214 215 #ifdef notdef 216 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 217 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 218 static void bge_vpd_read (struct bge_softc *); 219 #endif 220 221 static u_int32_t bge_readmem_ind 222 (struct bge_softc *, int); 223 static void bge_writemem_ind (struct bge_softc *, int, int); 224 #ifdef notdef 225 static u_int32_t bge_readreg_ind 226 (struct bge_softc *, int); 227 #endif 228 static void bge_writereg_ind (struct bge_softc *, int, int); 229 230 static int bge_miibus_readreg (device_t, int, int); 231 static int bge_miibus_writereg (device_t, int, int, int); 232 static void bge_miibus_statchg (device_t); 233 234 static void bge_reset (struct bge_softc *); 235 236 static device_method_t bge_methods[] = { 237 /* Device interface */ 238 DEVMETHOD(device_probe, bge_probe), 239 DEVMETHOD(device_attach, bge_attach), 240 DEVMETHOD(device_detach, bge_detach), 241 DEVMETHOD(device_shutdown, bge_shutdown), 242 243 /* bus interface */ 244 DEVMETHOD(bus_print_child, bus_generic_print_child), 245 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 246 247 /* MII interface */ 248 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 249 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 250 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 251 252 { 0, 0 } 253 }; 254 255 static driver_t bge_driver = { 256 "bge", 257 bge_methods, 258 sizeof(struct bge_softc) 259 }; 260 261 static devclass_t bge_devclass; 262 263 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 264 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 265 266 static u_int32_t 267 bge_readmem_ind(sc, off) 268 struct bge_softc *sc; 269 int off; 270 { 271 device_t dev; 272 273 dev = sc->bge_dev; 274 275 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 276 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 277 } 278 279 static void 280 bge_writemem_ind(sc, off, val) 281 struct bge_softc *sc; 282 int off, val; 283 { 284 device_t dev; 285 286 dev = sc->bge_dev; 287 288 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 289 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 290 291 return; 292 } 293 294 #ifdef notdef 295 static u_int32_t 296 bge_readreg_ind(sc, off) 297 struct bge_softc *sc; 298 int off; 299 { 300 device_t dev; 301 302 dev = sc->bge_dev; 303 304 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 305 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 306 } 307 #endif 308 309 static void 310 bge_writereg_ind(sc, off, val) 311 struct bge_softc *sc; 312 int off, val; 313 { 314 device_t dev; 315 316 dev = sc->bge_dev; 317 318 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 319 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 320 321 return; 322 } 323 324 #ifdef notdef 325 static u_int8_t 326 bge_vpd_readbyte(sc, addr) 327 struct bge_softc *sc; 328 int addr; 329 { 330 int i; 331 device_t dev; 332 u_int32_t val; 333 334 dev = sc->bge_dev; 335 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 336 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 337 DELAY(10); 338 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 339 break; 340 } 341 342 if (i == BGE_TIMEOUT) { 343 printf("bge%d: VPD read timed out\n", sc->bge_unit); 344 return(0); 345 } 346 347 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 348 349 return((val >> ((addr % 4) * 8)) & 0xFF); 350 } 351 352 static void 353 bge_vpd_read_res(sc, res, addr) 354 struct bge_softc *sc; 355 struct vpd_res *res; 356 int addr; 357 { 358 int i; 359 u_int8_t *ptr; 360 361 ptr = (u_int8_t *)res; 362 for (i = 0; i < sizeof(struct vpd_res); i++) 363 ptr[i] = bge_vpd_readbyte(sc, i + addr); 364 365 return; 366 } 367 368 static void 369 bge_vpd_read(sc) 370 struct bge_softc *sc; 371 { 372 int pos = 0, i; 373 struct vpd_res res; 374 375 if (sc->bge_vpd_prodname != NULL) 376 free(sc->bge_vpd_prodname, M_DEVBUF); 377 if (sc->bge_vpd_readonly != NULL) 378 free(sc->bge_vpd_readonly, M_DEVBUF); 379 sc->bge_vpd_prodname = NULL; 380 sc->bge_vpd_readonly = NULL; 381 382 bge_vpd_read_res(sc, &res, pos); 383 384 if (res.vr_id != VPD_RES_ID) { 385 printf("bge%d: bad VPD resource id: expected %x got %x\n", 386 sc->bge_unit, VPD_RES_ID, res.vr_id); 387 return; 388 } 389 390 pos += sizeof(res); 391 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 392 for (i = 0; i < res.vr_len; i++) 393 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 394 sc->bge_vpd_prodname[i] = '\0'; 395 pos += i; 396 397 bge_vpd_read_res(sc, &res, pos); 398 399 if (res.vr_id != VPD_RES_READ) { 400 printf("bge%d: bad VPD resource id: expected %x got %x\n", 401 sc->bge_unit, VPD_RES_READ, res.vr_id); 402 return; 403 } 404 405 pos += sizeof(res); 406 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 407 for (i = 0; i < res.vr_len + 1; i++) 408 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 409 410 return; 411 } 412 #endif 413 414 /* 415 * Read a byte of data stored in the EEPROM at address 'addr.' The 416 * BCM570x supports both the traditional bitbang interface and an 417 * auto access interface for reading the EEPROM. We use the auto 418 * access method. 419 */ 420 static u_int8_t 421 bge_eeprom_getbyte(sc, addr, dest) 422 struct bge_softc *sc; 423 int addr; 424 u_int8_t *dest; 425 { 426 int i; 427 u_int32_t byte = 0; 428 429 /* 430 * Enable use of auto EEPROM access so we can avoid 431 * having to use the bitbang method. 432 */ 433 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 434 435 /* Reset the EEPROM, load the clock period. */ 436 CSR_WRITE_4(sc, BGE_EE_ADDR, 437 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 438 DELAY(20); 439 440 /* Issue the read EEPROM command. */ 441 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 442 443 /* Wait for completion */ 444 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 445 DELAY(10); 446 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 447 break; 448 } 449 450 if (i == BGE_TIMEOUT) { 451 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 452 return(0); 453 } 454 455 /* Get result. */ 456 byte = CSR_READ_4(sc, BGE_EE_DATA); 457 458 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 459 460 return(0); 461 } 462 463 /* 464 * Read a sequence of bytes from the EEPROM. 465 */ 466 static int 467 bge_read_eeprom(sc, dest, off, cnt) 468 struct bge_softc *sc; 469 caddr_t dest; 470 int off; 471 int cnt; 472 { 473 int err = 0, i; 474 u_int8_t byte = 0; 475 476 for (i = 0; i < cnt; i++) { 477 err = bge_eeprom_getbyte(sc, off + i, &byte); 478 if (err) 479 break; 480 *(dest + i) = byte; 481 } 482 483 return(err ? 1 : 0); 484 } 485 486 static int 487 bge_miibus_readreg(dev, phy, reg) 488 device_t dev; 489 int phy, reg; 490 { 491 struct bge_softc *sc; 492 u_int32_t val, autopoll; 493 int i; 494 495 sc = device_get_softc(dev); 496 497 /* 498 * Broadcom's own driver always assumes the internal 499 * PHY is at GMII address 1. On some chips, the PHY responds 500 * to accesses at all addresses, which could cause us to 501 * bogusly attach the PHY 32 times at probe type. Always 502 * restricting the lookup to address 1 is simpler than 503 * trying to figure out which chips revisions should be 504 * special-cased. 505 */ 506 if (phy != 1) 507 return(0); 508 509 /* Reading with autopolling on may trigger PCI errors */ 510 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 511 if (autopoll & BGE_MIMODE_AUTOPOLL) { 512 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 513 DELAY(40); 514 } 515 516 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 517 BGE_MIPHY(phy)|BGE_MIREG(reg)); 518 519 for (i = 0; i < BGE_TIMEOUT; i++) { 520 val = CSR_READ_4(sc, BGE_MI_COMM); 521 if (!(val & BGE_MICOMM_BUSY)) 522 break; 523 } 524 525 if (i == BGE_TIMEOUT) { 526 printf("bge%d: PHY read timed out\n", sc->bge_unit); 527 val = 0; 528 goto done; 529 } 530 531 val = CSR_READ_4(sc, BGE_MI_COMM); 532 533 done: 534 if (autopoll & BGE_MIMODE_AUTOPOLL) { 535 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 536 DELAY(40); 537 } 538 539 if (val & BGE_MICOMM_READFAIL) 540 return(0); 541 542 return(val & 0xFFFF); 543 } 544 545 static int 546 bge_miibus_writereg(dev, phy, reg, val) 547 device_t dev; 548 int phy, reg, val; 549 { 550 struct bge_softc *sc; 551 u_int32_t autopoll; 552 int i; 553 554 sc = device_get_softc(dev); 555 556 /* Reading with autopolling on may trigger PCI errors */ 557 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 558 if (autopoll & BGE_MIMODE_AUTOPOLL) { 559 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 560 DELAY(40); 561 } 562 563 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 564 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 565 566 for (i = 0; i < BGE_TIMEOUT; i++) { 567 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 568 break; 569 } 570 571 if (autopoll & BGE_MIMODE_AUTOPOLL) { 572 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 573 DELAY(40); 574 } 575 576 if (i == BGE_TIMEOUT) { 577 printf("bge%d: PHY read timed out\n", sc->bge_unit); 578 return(0); 579 } 580 581 return(0); 582 } 583 584 static void 585 bge_miibus_statchg(dev) 586 device_t dev; 587 { 588 struct bge_softc *sc; 589 struct mii_data *mii; 590 591 sc = device_get_softc(dev); 592 mii = device_get_softc(sc->bge_miibus); 593 594 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 595 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 596 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 597 } else { 598 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 599 } 600 601 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 602 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 603 } else { 604 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 605 } 606 607 return; 608 } 609 610 /* 611 * Handle events that have triggered interrupts. 612 */ 613 static void 614 bge_handle_events(sc) 615 struct bge_softc *sc; 616 { 617 618 return; 619 } 620 621 /* 622 * Memory management for jumbo frames. 623 */ 624 625 static int 626 bge_alloc_jumbo_mem(sc) 627 struct bge_softc *sc; 628 { 629 caddr_t ptr; 630 register int i; 631 struct bge_jpool_entry *entry; 632 633 /* Grab a big chunk o' storage. */ 634 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 635 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 636 637 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 638 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 639 return(ENOBUFS); 640 } 641 642 SLIST_INIT(&sc->bge_jfree_listhead); 643 SLIST_INIT(&sc->bge_jinuse_listhead); 644 645 /* 646 * Now divide it up into 9K pieces and save the addresses 647 * in an array. 648 */ 649 ptr = sc->bge_cdata.bge_jumbo_buf; 650 for (i = 0; i < BGE_JSLOTS; i++) { 651 sc->bge_cdata.bge_jslots[i] = ptr; 652 ptr += BGE_JLEN; 653 entry = malloc(sizeof(struct bge_jpool_entry), 654 M_DEVBUF, M_NOWAIT); 655 if (entry == NULL) { 656 contigfree(sc->bge_cdata.bge_jumbo_buf, 657 BGE_JMEM, M_DEVBUF); 658 sc->bge_cdata.bge_jumbo_buf = NULL; 659 printf("bge%d: no memory for jumbo " 660 "buffer queue!\n", sc->bge_unit); 661 return(ENOBUFS); 662 } 663 entry->slot = i; 664 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 665 entry, jpool_entries); 666 } 667 668 return(0); 669 } 670 671 static void 672 bge_free_jumbo_mem(sc) 673 struct bge_softc *sc; 674 { 675 int i; 676 struct bge_jpool_entry *entry; 677 678 for (i = 0; i < BGE_JSLOTS; i++) { 679 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 680 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 681 free(entry, M_DEVBUF); 682 } 683 684 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 685 686 return; 687 } 688 689 /* 690 * Allocate a jumbo buffer. 691 */ 692 static void * 693 bge_jalloc(sc) 694 struct bge_softc *sc; 695 { 696 struct bge_jpool_entry *entry; 697 698 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 699 700 if (entry == NULL) { 701 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 702 return(NULL); 703 } 704 705 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 706 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 707 return(sc->bge_cdata.bge_jslots[entry->slot]); 708 } 709 710 /* 711 * Release a jumbo buffer. 712 */ 713 static void 714 bge_jfree(buf, args) 715 void *buf; 716 void *args; 717 { 718 struct bge_jpool_entry *entry; 719 struct bge_softc *sc; 720 int i; 721 722 /* Extract the softc struct pointer. */ 723 sc = (struct bge_softc *)args; 724 725 if (sc == NULL) 726 panic("bge_jfree: can't find softc pointer!"); 727 728 /* calculate the slot this buffer belongs to */ 729 730 i = ((vm_offset_t)buf 731 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 732 733 if ((i < 0) || (i >= BGE_JSLOTS)) 734 panic("bge_jfree: asked to free buffer that we don't manage!"); 735 736 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 737 if (entry == NULL) 738 panic("bge_jfree: buffer not in use!"); 739 entry->slot = i; 740 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 741 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 742 743 return; 744 } 745 746 747 /* 748 * Intialize a standard receive ring descriptor. 749 */ 750 static int 751 bge_newbuf_std(sc, i, m) 752 struct bge_softc *sc; 753 int i; 754 struct mbuf *m; 755 { 756 struct mbuf *m_new = NULL; 757 struct bge_rx_bd *r; 758 759 if (m == NULL) { 760 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 761 if (m_new == NULL) { 762 return(ENOBUFS); 763 } 764 765 MCLGET(m_new, M_DONTWAIT); 766 if (!(m_new->m_flags & M_EXT)) { 767 m_freem(m_new); 768 return(ENOBUFS); 769 } 770 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 771 } else { 772 m_new = m; 773 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 774 m_new->m_data = m_new->m_ext.ext_buf; 775 } 776 777 if (!sc->bge_rx_alignment_bug) 778 m_adj(m_new, ETHER_ALIGN); 779 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 780 r = &sc->bge_rdata->bge_rx_std_ring[i]; 781 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 782 r->bge_flags = BGE_RXBDFLAG_END; 783 r->bge_len = m_new->m_len; 784 r->bge_idx = i; 785 786 return(0); 787 } 788 789 /* 790 * Initialize a jumbo receive ring descriptor. This allocates 791 * a jumbo buffer from the pool managed internally by the driver. 792 */ 793 static int 794 bge_newbuf_jumbo(sc, i, m) 795 struct bge_softc *sc; 796 int i; 797 struct mbuf *m; 798 { 799 struct mbuf *m_new = NULL; 800 struct bge_rx_bd *r; 801 802 if (m == NULL) { 803 caddr_t *buf = NULL; 804 805 /* Allocate the mbuf. */ 806 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 807 if (m_new == NULL) { 808 return(ENOBUFS); 809 } 810 811 /* Allocate the jumbo buffer */ 812 buf = bge_jalloc(sc); 813 if (buf == NULL) { 814 m_freem(m_new); 815 printf("bge%d: jumbo allocation failed " 816 "-- packet dropped!\n", sc->bge_unit); 817 return(ENOBUFS); 818 } 819 820 /* Attach the buffer to the mbuf. */ 821 m_new->m_data = (void *) buf; 822 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 823 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 824 (struct bge_softc *)sc, 0, EXT_NET_DRV); 825 } else { 826 m_new = m; 827 m_new->m_data = m_new->m_ext.ext_buf; 828 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 829 } 830 831 if (!sc->bge_rx_alignment_bug) 832 m_adj(m_new, ETHER_ALIGN); 833 /* Set up the descriptor. */ 834 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 835 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 836 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 837 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 838 r->bge_len = m_new->m_len; 839 r->bge_idx = i; 840 841 return(0); 842 } 843 844 /* 845 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 846 * that's 1MB or memory, which is a lot. For now, we fill only the first 847 * 256 ring entries and hope that our CPU is fast enough to keep up with 848 * the NIC. 849 */ 850 static int 851 bge_init_rx_ring_std(sc) 852 struct bge_softc *sc; 853 { 854 int i; 855 856 for (i = 0; i < BGE_SSLOTS; i++) { 857 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 858 return(ENOBUFS); 859 }; 860 861 sc->bge_std = i - 1; 862 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 863 864 return(0); 865 } 866 867 static void 868 bge_free_rx_ring_std(sc) 869 struct bge_softc *sc; 870 { 871 int i; 872 873 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 874 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 875 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 876 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 877 } 878 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 879 sizeof(struct bge_rx_bd)); 880 } 881 882 return; 883 } 884 885 static int 886 bge_init_rx_ring_jumbo(sc) 887 struct bge_softc *sc; 888 { 889 int i; 890 struct bge_rcb *rcb; 891 892 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 893 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 894 return(ENOBUFS); 895 }; 896 897 sc->bge_jumbo = i - 1; 898 899 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 900 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 901 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 902 903 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 904 905 return(0); 906 } 907 908 static void 909 bge_free_rx_ring_jumbo(sc) 910 struct bge_softc *sc; 911 { 912 int i; 913 914 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 915 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 916 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 917 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 918 } 919 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 920 sizeof(struct bge_rx_bd)); 921 } 922 923 return; 924 } 925 926 static void 927 bge_free_tx_ring(sc) 928 struct bge_softc *sc; 929 { 930 int i; 931 932 if (sc->bge_rdata->bge_tx_ring == NULL) 933 return; 934 935 for (i = 0; i < BGE_TX_RING_CNT; i++) { 936 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 937 m_freem(sc->bge_cdata.bge_tx_chain[i]); 938 sc->bge_cdata.bge_tx_chain[i] = NULL; 939 } 940 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 941 sizeof(struct bge_tx_bd)); 942 } 943 944 return; 945 } 946 947 static int 948 bge_init_tx_ring(sc) 949 struct bge_softc *sc; 950 { 951 sc->bge_txcnt = 0; 952 sc->bge_tx_saved_considx = 0; 953 954 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 955 /* 5700 b2 errata */ 956 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 957 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 958 959 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 960 /* 5700 b2 errata */ 961 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 962 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 963 964 return(0); 965 } 966 967 #define BGE_POLY 0xEDB88320 968 969 static u_int32_t 970 bge_crc(addr) 971 caddr_t addr; 972 { 973 u_int32_t idx, bit, data, crc; 974 975 /* Compute CRC for the address value. */ 976 crc = 0xFFFFFFFF; /* initial value */ 977 978 for (idx = 0; idx < 6; idx++) { 979 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 980 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 981 } 982 983 return(crc & 0x7F); 984 } 985 986 static void 987 bge_setmulti(sc) 988 struct bge_softc *sc; 989 { 990 struct ifnet *ifp; 991 struct ifmultiaddr *ifma; 992 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 993 int h, i; 994 995 ifp = &sc->arpcom.ac_if; 996 997 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 998 for (i = 0; i < 4; i++) 999 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1000 return; 1001 } 1002 1003 /* First, zot all the existing filters. */ 1004 for (i = 0; i < 4; i++) 1005 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1006 1007 /* Now program new ones. */ 1008 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1009 if (ifma->ifma_addr->sa_family != AF_LINK) 1010 continue; 1011 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1012 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1013 } 1014 1015 for (i = 0; i < 4; i++) 1016 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1017 1018 return; 1019 } 1020 1021 /* 1022 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1023 * self-test results. 1024 */ 1025 static int 1026 bge_chipinit(sc) 1027 struct bge_softc *sc; 1028 { 1029 int i; 1030 u_int32_t dma_rw_ctl; 1031 1032 /* Set endianness before we access any non-PCI registers. */ 1033 #if BYTE_ORDER == BIG_ENDIAN 1034 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1035 BGE_BIGENDIAN_INIT, 4); 1036 #else 1037 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1038 BGE_LITTLEENDIAN_INIT, 4); 1039 #endif 1040 1041 /* 1042 * Check the 'ROM failed' bit on the RX CPU to see if 1043 * self-tests passed. 1044 */ 1045 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1046 printf("bge%d: RX CPU self-diagnostics failed!\n", 1047 sc->bge_unit); 1048 return(ENODEV); 1049 } 1050 1051 /* Clear the MAC control register */ 1052 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1053 1054 /* 1055 * Clear the MAC statistics block in the NIC's 1056 * internal memory. 1057 */ 1058 for (i = BGE_STATS_BLOCK; 1059 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1060 BGE_MEMWIN_WRITE(sc, i, 0); 1061 1062 for (i = BGE_STATUS_BLOCK; 1063 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1064 BGE_MEMWIN_WRITE(sc, i, 0); 1065 1066 /* Set up the PCI DMA control register. */ 1067 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1068 BGE_PCISTATE_PCI_BUSMODE) { 1069 /* Conventional PCI bus */ 1070 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1071 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1072 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1073 (0x0F); 1074 } else { 1075 /* PCI-X bus */ 1076 /* 1077 * The 5704 uses a different encoding of read/write 1078 * watermarks. 1079 */ 1080 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1081 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1082 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1083 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1084 else 1085 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1086 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1087 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1088 (0x0F); 1089 1090 /* 1091 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1092 * for hardware bugs. 1093 */ 1094 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1095 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1096 u_int32_t tmp; 1097 1098 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1099 if (tmp == 0x6 || tmp == 0x7) 1100 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1101 } 1102 } 1103 1104 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1105 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1106 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1107 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1108 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1109 1110 /* 1111 * Set up general mode register. 1112 */ 1113 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1114 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1115 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1116 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1117 BGE_MODECTL_RX_NO_PHDR_CSUM); 1118 1119 /* 1120 * Disable memory write invalidate. Apparently it is not supported 1121 * properly by these devices. 1122 */ 1123 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1124 1125 #ifdef __brokenalpha__ 1126 /* 1127 * Must insure that we do not cross an 8K (bytes) boundary 1128 * for DMA reads. Our highest limit is 1K bytes. This is a 1129 * restriction on some ALPHA platforms with early revision 1130 * 21174 PCI chipsets, such as the AlphaPC 164lx 1131 */ 1132 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1133 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1134 #endif 1135 1136 /* Set the timer prescaler (always 66Mhz) */ 1137 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1138 1139 return(0); 1140 } 1141 1142 static int 1143 bge_blockinit(sc) 1144 struct bge_softc *sc; 1145 { 1146 struct bge_rcb *rcb; 1147 volatile struct bge_rcb *vrcb; 1148 int i; 1149 1150 /* 1151 * Initialize the memory window pointer register so that 1152 * we can access the first 32K of internal NIC RAM. This will 1153 * allow us to set up the TX send ring RCBs and the RX return 1154 * ring RCBs, plus other things which live in NIC memory. 1155 */ 1156 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1157 1158 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1159 /* Configure mbuf memory pool */ 1160 if (sc->bge_extram) { 1161 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1162 BGE_EXT_SSRAM); 1163 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1164 } else { 1165 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1166 BGE_BUFFPOOL_1); 1167 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1168 } 1169 1170 /* Configure DMA resource pool */ 1171 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1172 BGE_DMA_DESCRIPTORS); 1173 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1174 } 1175 1176 /* Configure mbuf pool watermarks */ 1177 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1178 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1179 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1180 } else { 1181 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1182 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1183 } 1184 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1185 1186 /* Configure DMA resource watermarks */ 1187 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1188 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1189 1190 /* Enable buffer manager */ 1191 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1192 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1193 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1194 1195 /* Poll for buffer manager start indication */ 1196 for (i = 0; i < BGE_TIMEOUT; i++) { 1197 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1198 break; 1199 DELAY(10); 1200 } 1201 1202 if (i == BGE_TIMEOUT) { 1203 printf("bge%d: buffer manager failed to start\n", 1204 sc->bge_unit); 1205 return(ENXIO); 1206 } 1207 } 1208 1209 /* Enable flow-through queues */ 1210 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1211 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1212 1213 /* Wait until queue initialization is complete */ 1214 for (i = 0; i < BGE_TIMEOUT; i++) { 1215 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1216 break; 1217 DELAY(10); 1218 } 1219 1220 if (i == BGE_TIMEOUT) { 1221 printf("bge%d: flow-through queue init failed\n", 1222 sc->bge_unit); 1223 return(ENXIO); 1224 } 1225 1226 /* Initialize the standard RX ring control block */ 1227 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1228 BGE_HOSTADDR(rcb->bge_hostaddr, 1229 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1230 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1231 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1232 else 1233 rcb->bge_maxlen_flags = 1234 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1235 if (sc->bge_extram) 1236 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1237 else 1238 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1239 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1240 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1241 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1242 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1243 1244 /* 1245 * Initialize the jumbo RX ring control block 1246 * We set the 'ring disabled' bit in the flags 1247 * field until we're actually ready to start 1248 * using this ring (i.e. once we set the MTU 1249 * high enough to require it). 1250 */ 1251 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1252 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1253 BGE_HOSTADDR(rcb->bge_hostaddr, 1254 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1255 rcb->bge_maxlen_flags = 1256 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1257 BGE_RCB_FLAG_RING_DISABLED); 1258 if (sc->bge_extram) 1259 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1260 else 1261 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1262 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1263 rcb->bge_hostaddr.bge_addr_hi); 1264 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1265 rcb->bge_hostaddr.bge_addr_lo); 1266 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1267 rcb->bge_maxlen_flags); 1268 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1269 1270 /* Set up dummy disabled mini ring RCB */ 1271 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1272 rcb->bge_maxlen_flags = 1273 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1274 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1275 rcb->bge_maxlen_flags); 1276 } 1277 1278 /* 1279 * Set the BD ring replentish thresholds. The recommended 1280 * values are 1/8th the number of descriptors allocated to 1281 * each ring. 1282 */ 1283 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1284 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1285 1286 /* 1287 * Disable all unused send rings by setting the 'ring disabled' 1288 * bit in the flags field of all the TX send ring control blocks. 1289 * These are located in NIC memory. 1290 */ 1291 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1292 BGE_SEND_RING_RCB); 1293 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1294 vrcb->bge_maxlen_flags = 1295 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1296 vrcb->bge_nicaddr = 0; 1297 vrcb++; 1298 } 1299 1300 /* Configure TX RCB 0 (we use only the first ring) */ 1301 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1302 BGE_SEND_RING_RCB); 1303 vrcb->bge_hostaddr.bge_addr_hi = 0; 1304 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1305 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1306 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1307 vrcb->bge_maxlen_flags = 1308 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1309 1310 /* Disable all unused RX return rings */ 1311 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1312 BGE_RX_RETURN_RING_RCB); 1313 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1314 vrcb->bge_hostaddr.bge_addr_hi = 0; 1315 vrcb->bge_hostaddr.bge_addr_lo = 0; 1316 vrcb->bge_maxlen_flags = 1317 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1318 BGE_RCB_FLAG_RING_DISABLED); 1319 vrcb->bge_nicaddr = 0; 1320 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1321 (i * (sizeof(u_int64_t))), 0); 1322 vrcb++; 1323 } 1324 1325 /* Initialize RX ring indexes */ 1326 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1327 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1328 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1329 1330 /* 1331 * Set up RX return ring 0 1332 * Note that the NIC address for RX return rings is 0x00000000. 1333 * The return rings live entirely within the host, so the 1334 * nicaddr field in the RCB isn't used. 1335 */ 1336 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1337 BGE_RX_RETURN_RING_RCB); 1338 vrcb->bge_hostaddr.bge_addr_hi = 0; 1339 BGE_HOSTADDR(vrcb->bge_hostaddr, 1340 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1341 vrcb->bge_nicaddr = 0x00000000; 1342 vrcb->bge_maxlen_flags = 1343 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1344 1345 /* Set random backoff seed for TX */ 1346 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1347 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1348 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1349 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1350 BGE_TX_BACKOFF_SEED_MASK); 1351 1352 /* Set inter-packet gap */ 1353 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1354 1355 /* 1356 * Specify which ring to use for packets that don't match 1357 * any RX rules. 1358 */ 1359 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1360 1361 /* 1362 * Configure number of RX lists. One interrupt distribution 1363 * list, sixteen active lists, one bad frames class. 1364 */ 1365 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1366 1367 /* Inialize RX list placement stats mask. */ 1368 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1369 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1370 1371 /* Disable host coalescing until we get it set up */ 1372 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1373 1374 /* Poll to make sure it's shut down. */ 1375 for (i = 0; i < BGE_TIMEOUT; i++) { 1376 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1377 break; 1378 DELAY(10); 1379 } 1380 1381 if (i == BGE_TIMEOUT) { 1382 printf("bge%d: host coalescing engine failed to idle\n", 1383 sc->bge_unit); 1384 return(ENXIO); 1385 } 1386 1387 /* Set up host coalescing defaults */ 1388 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1389 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1390 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1391 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1392 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1393 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1394 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1395 } 1396 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1397 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1398 1399 /* Set up address of statistics block */ 1400 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1401 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1402 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1403 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1404 1405 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1406 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1407 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1408 } 1409 1410 /* Set up address of status block */ 1411 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1412 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1413 vtophys(&sc->bge_rdata->bge_status_block)); 1414 1415 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1416 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1417 1418 /* Turn on host coalescing state machine */ 1419 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1420 1421 /* Turn on RX BD completion state machine and enable attentions */ 1422 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1423 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1424 1425 /* Turn on RX list placement state machine */ 1426 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1427 1428 /* Turn on RX list selector state machine. */ 1429 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1430 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1431 1432 /* Turn on DMA, clear stats */ 1433 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1434 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1435 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1436 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1437 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1438 1439 /* Set misc. local control, enable interrupts on attentions */ 1440 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1441 1442 #ifdef notdef 1443 /* Assert GPIO pins for PHY reset */ 1444 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1445 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1446 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1447 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1448 #endif 1449 1450 /* Turn on DMA completion state machine */ 1451 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1452 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1453 1454 /* Turn on write DMA state machine */ 1455 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1456 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1457 1458 /* Turn on read DMA state machine */ 1459 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1460 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1461 1462 /* Turn on RX data completion state machine */ 1463 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1464 1465 /* Turn on RX BD initiator state machine */ 1466 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1467 1468 /* Turn on RX data and RX BD initiator state machine */ 1469 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1470 1471 /* Turn on Mbuf cluster free state machine */ 1472 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1473 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1474 1475 /* Turn on send BD completion state machine */ 1476 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1477 1478 /* Turn on send data completion state machine */ 1479 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1480 1481 /* Turn on send data initiator state machine */ 1482 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1483 1484 /* Turn on send BD initiator state machine */ 1485 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1486 1487 /* Turn on send BD selector state machine */ 1488 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1489 1490 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1491 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1492 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1493 1494 /* ack/clear link change events */ 1495 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1496 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1497 BGE_MACSTAT_LINK_CHANGED); 1498 1499 /* Enable PHY auto polling (for MII/GMII only) */ 1500 if (sc->bge_tbi) { 1501 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1502 } else { 1503 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1504 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1505 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1506 BGE_EVTENB_MI_INTERRUPT); 1507 } 1508 1509 /* Enable link state change attentions. */ 1510 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1511 1512 return(0); 1513 } 1514 1515 /* 1516 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1517 * against our list and return its name if we find a match. Note 1518 * that since the Broadcom controller contains VPD support, we 1519 * can get the device name string from the controller itself instead 1520 * of the compiled-in string. This is a little slow, but it guarantees 1521 * we'll always announce the right product name. 1522 */ 1523 static int 1524 bge_probe(dev) 1525 device_t dev; 1526 { 1527 struct bge_type *t; 1528 struct bge_softc *sc; 1529 char *descbuf; 1530 1531 t = bge_devs; 1532 1533 sc = device_get_softc(dev); 1534 bzero(sc, sizeof(struct bge_softc)); 1535 sc->bge_unit = device_get_unit(dev); 1536 sc->bge_dev = dev; 1537 1538 while(t->bge_name != NULL) { 1539 if ((pci_get_vendor(dev) == t->bge_vid) && 1540 (pci_get_device(dev) == t->bge_did)) { 1541 #ifdef notdef 1542 bge_vpd_read(sc); 1543 device_set_desc(dev, sc->bge_vpd_prodname); 1544 #endif 1545 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1546 if (descbuf == NULL) 1547 return(ENOMEM); 1548 snprintf(descbuf, BGE_DEVDESC_MAX, 1549 "%s, ASIC rev. %#04x", t->bge_name, 1550 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1551 device_set_desc_copy(dev, descbuf); 1552 free(descbuf, M_TEMP); 1553 return(0); 1554 } 1555 t++; 1556 } 1557 1558 return(ENXIO); 1559 } 1560 1561 static int 1562 bge_attach(dev) 1563 device_t dev; 1564 { 1565 int s; 1566 struct ifnet *ifp; 1567 struct bge_softc *sc; 1568 u_int32_t hwcfg = 0; 1569 u_int32_t mac_addr = 0; 1570 int unit, error = 0, rid; 1571 1572 s = splimp(); 1573 1574 sc = device_get_softc(dev); 1575 unit = device_get_unit(dev); 1576 sc->bge_dev = dev; 1577 sc->bge_unit = unit; 1578 1579 /* 1580 * Map control/status registers. 1581 */ 1582 pci_enable_busmaster(dev); 1583 1584 rid = BGE_PCI_BAR0; 1585 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1586 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1587 1588 if (sc->bge_res == NULL) { 1589 printf ("bge%d: couldn't map memory\n", unit); 1590 error = ENXIO; 1591 goto fail; 1592 } 1593 1594 sc->bge_btag = rman_get_bustag(sc->bge_res); 1595 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1596 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1597 1598 /* Allocate interrupt */ 1599 rid = 0; 1600 1601 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1602 RF_SHAREABLE | RF_ACTIVE); 1603 1604 if (sc->bge_irq == NULL) { 1605 printf("bge%d: couldn't map interrupt\n", unit); 1606 error = ENXIO; 1607 goto fail; 1608 } 1609 1610 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1611 bge_intr, sc, &sc->bge_intrhand); 1612 1613 if (error) { 1614 bge_release_resources(sc); 1615 printf("bge%d: couldn't set up irq\n", unit); 1616 goto fail; 1617 } 1618 1619 sc->bge_unit = unit; 1620 1621 /* Try to reset the chip. */ 1622 bge_reset(sc); 1623 1624 if (bge_chipinit(sc)) { 1625 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1626 bge_release_resources(sc); 1627 error = ENXIO; 1628 goto fail; 1629 } 1630 1631 /* 1632 * Get station address from the EEPROM. 1633 */ 1634 mac_addr = bge_readmem_ind(sc, 0x0c14); 1635 if ((mac_addr >> 16) == 0x484b) { 1636 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1637 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1638 mac_addr = bge_readmem_ind(sc, 0x0c18); 1639 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1640 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1641 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1642 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1643 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1644 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1645 printf("bge%d: failed to read station address\n", unit); 1646 bge_release_resources(sc); 1647 error = ENXIO; 1648 goto fail; 1649 } 1650 1651 /* 1652 * A Broadcom chip was detected. Inform the world. 1653 */ 1654 printf("bge%d: Ethernet address: %6D\n", unit, 1655 sc->arpcom.ac_enaddr, ":"); 1656 1657 /* Allocate the general information block and ring buffers. */ 1658 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1659 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1660 1661 if (sc->bge_rdata == NULL) { 1662 bge_release_resources(sc); 1663 error = ENXIO; 1664 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1665 goto fail; 1666 } 1667 1668 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1669 1670 /* Save ASIC rev. */ 1671 1672 sc->bge_chipid = 1673 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1674 BGE_PCIMISCCTL_ASICREV; 1675 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1676 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1677 1678 /* 1679 * Try to allocate memory for jumbo buffers. 1680 * The 5705 does not appear to support jumbo frames. 1681 */ 1682 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1683 if (bge_alloc_jumbo_mem(sc)) { 1684 printf("bge%d: jumbo buffer allocation " 1685 "failed\n", sc->bge_unit); 1686 bge_release_resources(sc); 1687 error = ENXIO; 1688 goto fail; 1689 } 1690 } 1691 1692 /* Set default tuneable values. */ 1693 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1694 sc->bge_rx_coal_ticks = 150; 1695 sc->bge_tx_coal_ticks = 150; 1696 sc->bge_rx_max_coal_bds = 64; 1697 sc->bge_tx_max_coal_bds = 128; 1698 1699 /* 5705 limits RX return ring to 512 entries. */ 1700 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1701 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 1702 else 1703 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 1704 1705 /* Set up ifnet structure */ 1706 ifp = &sc->arpcom.ac_if; 1707 ifp->if_softc = sc; 1708 ifp->if_unit = sc->bge_unit; 1709 ifp->if_name = "bge"; 1710 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1711 ifp->if_ioctl = bge_ioctl; 1712 ifp->if_output = ether_output; 1713 ifp->if_start = bge_start; 1714 ifp->if_watchdog = bge_watchdog; 1715 ifp->if_init = bge_init; 1716 ifp->if_mtu = ETHERMTU; 1717 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1718 ifp->if_hwassist = BGE_CSUM_FEATURES; 1719 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 1720 IFCAP_VLAN_MTU; 1721 ifp->if_capenable = ifp->if_capabilities; 1722 1723 /* 1724 * Figure out what sort of media we have by checking the 1725 * hardware config word in the first 32k of NIC internal memory, 1726 * or fall back to examining the EEPROM if necessary. 1727 * Note: on some BCM5700 cards, this value appears to be unset. 1728 * If that's the case, we have to rely on identifying the NIC 1729 * by its PCI subsystem ID, as we do below for the SysKonnect 1730 * SK-9D41. 1731 */ 1732 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1733 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1734 else { 1735 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1736 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1737 hwcfg = ntohl(hwcfg); 1738 } 1739 1740 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1741 sc->bge_tbi = 1; 1742 1743 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1744 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1745 sc->bge_tbi = 1; 1746 1747 if (sc->bge_tbi) { 1748 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1749 bge_ifmedia_upd, bge_ifmedia_sts); 1750 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1751 ifmedia_add(&sc->bge_ifmedia, 1752 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1753 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1754 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1755 } else { 1756 /* 1757 * Do transceiver setup. 1758 */ 1759 if (mii_phy_probe(dev, &sc->bge_miibus, 1760 bge_ifmedia_upd, bge_ifmedia_sts)) { 1761 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1762 bge_release_resources(sc); 1763 bge_free_jumbo_mem(sc); 1764 error = ENXIO; 1765 goto fail; 1766 } 1767 } 1768 1769 /* 1770 * When using the BCM5701 in PCI-X mode, data corruption has 1771 * been observed in the first few bytes of some received packets. 1772 * Aligning the packet buffer in memory eliminates the corruption. 1773 * Unfortunately, this misaligns the packet payloads. On platforms 1774 * which do not support unaligned accesses, we will realign the 1775 * payloads by copying the received packets. 1776 */ 1777 switch (sc->bge_chipid) { 1778 case BGE_CHIPID_BCM5701_A0: 1779 case BGE_CHIPID_BCM5701_B0: 1780 case BGE_CHIPID_BCM5701_B2: 1781 case BGE_CHIPID_BCM5701_B5: 1782 /* If in PCI-X mode, work around the alignment bug. */ 1783 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1784 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1785 BGE_PCISTATE_PCI_BUSSPEED) 1786 sc->bge_rx_alignment_bug = 1; 1787 break; 1788 } 1789 1790 /* 1791 * Call MI attach routine. 1792 */ 1793 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1794 callout_handle_init(&sc->bge_stat_ch); 1795 1796 fail: 1797 splx(s); 1798 1799 return(error); 1800 } 1801 1802 static int 1803 bge_detach(dev) 1804 device_t dev; 1805 { 1806 struct bge_softc *sc; 1807 struct ifnet *ifp; 1808 int s; 1809 1810 s = splimp(); 1811 1812 sc = device_get_softc(dev); 1813 ifp = &sc->arpcom.ac_if; 1814 1815 ether_ifdetach(ifp); 1816 bge_stop(sc); 1817 bge_reset(sc); 1818 1819 if (sc->bge_tbi) { 1820 ifmedia_removeall(&sc->bge_ifmedia); 1821 } else { 1822 bus_generic_detach(dev); 1823 device_delete_child(dev, sc->bge_miibus); 1824 } 1825 1826 bge_release_resources(sc); 1827 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1828 bge_free_jumbo_mem(sc); 1829 1830 splx(s); 1831 1832 return(0); 1833 } 1834 1835 static void 1836 bge_release_resources(sc) 1837 struct bge_softc *sc; 1838 { 1839 device_t dev; 1840 1841 dev = sc->bge_dev; 1842 1843 if (sc->bge_vpd_prodname != NULL) 1844 free(sc->bge_vpd_prodname, M_DEVBUF); 1845 1846 if (sc->bge_vpd_readonly != NULL) 1847 free(sc->bge_vpd_readonly, M_DEVBUF); 1848 1849 if (sc->bge_intrhand != NULL) 1850 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1851 1852 if (sc->bge_irq != NULL) 1853 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1854 1855 if (sc->bge_res != NULL) 1856 bus_release_resource(dev, SYS_RES_MEMORY, 1857 BGE_PCI_BAR0, sc->bge_res); 1858 1859 if (sc->bge_rdata != NULL) 1860 contigfree(sc->bge_rdata, 1861 sizeof(struct bge_ring_data), M_DEVBUF); 1862 1863 return; 1864 } 1865 1866 static void 1867 bge_reset(sc) 1868 struct bge_softc *sc; 1869 { 1870 device_t dev; 1871 u_int32_t cachesize, command, pcistate; 1872 int i, val = 0; 1873 1874 dev = sc->bge_dev; 1875 1876 /* Save some important PCI state. */ 1877 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1878 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1879 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1880 1881 pci_write_config(dev, BGE_PCI_MISC_CTL, 1882 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1883 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1884 1885 /* Issue global reset */ 1886 bge_writereg_ind(sc, BGE_MISC_CFG, 1887 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1888 1889 DELAY(1000); 1890 1891 /* Reset some of the PCI state that got zapped by reset */ 1892 pci_write_config(dev, BGE_PCI_MISC_CTL, 1893 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1894 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1895 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1896 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1897 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1898 1899 /* 1900 * Prevent PXE restart: write a magic number to the 1901 * general communications memory at 0xB50. 1902 */ 1903 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1904 /* 1905 * Poll the value location we just wrote until 1906 * we see the 1's complement of the magic number. 1907 * This indicates that the firmware initialization 1908 * is complete. 1909 */ 1910 for (i = 0; i < BGE_TIMEOUT; i++) { 1911 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1912 if (val == ~BGE_MAGIC_NUMBER) 1913 break; 1914 DELAY(10); 1915 } 1916 1917 if (i == BGE_TIMEOUT) { 1918 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1919 return; 1920 } 1921 1922 /* 1923 * XXX Wait for the value of the PCISTATE register to 1924 * return to its original pre-reset state. This is a 1925 * fairly good indicator of reset completion. If we don't 1926 * wait for the reset to fully complete, trying to read 1927 * from the device's non-PCI registers may yield garbage 1928 * results. 1929 */ 1930 for (i = 0; i < BGE_TIMEOUT; i++) { 1931 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1932 break; 1933 DELAY(10); 1934 } 1935 1936 /* Enable memory arbiter. */ 1937 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1938 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1939 1940 /* Fix up byte swapping */ 1941 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1942 BGE_MODECTL_BYTESWAP_DATA); 1943 1944 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1945 1946 DELAY(10000); 1947 1948 return; 1949 } 1950 1951 /* 1952 * Frame reception handling. This is called if there's a frame 1953 * on the receive return list. 1954 * 1955 * Note: we have to be able to handle two possibilities here: 1956 * 1) the frame is from the jumbo recieve ring 1957 * 2) the frame is from the standard receive ring 1958 */ 1959 1960 static void 1961 bge_rxeof(sc) 1962 struct bge_softc *sc; 1963 { 1964 struct ifnet *ifp; 1965 int stdcnt = 0, jumbocnt = 0; 1966 1967 ifp = &sc->arpcom.ac_if; 1968 1969 while(sc->bge_rx_saved_considx != 1970 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1971 struct bge_rx_bd *cur_rx; 1972 u_int32_t rxidx; 1973 struct ether_header *eh; 1974 struct mbuf *m = NULL; 1975 u_int16_t vlan_tag = 0; 1976 int have_tag = 0; 1977 1978 cur_rx = 1979 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1980 1981 rxidx = cur_rx->bge_idx; 1982 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 1983 1984 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1985 have_tag = 1; 1986 vlan_tag = cur_rx->bge_vlan_tag; 1987 } 1988 1989 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1990 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1991 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1992 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1993 jumbocnt++; 1994 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1995 ifp->if_ierrors++; 1996 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1997 continue; 1998 } 1999 if (bge_newbuf_jumbo(sc, 2000 sc->bge_jumbo, NULL) == ENOBUFS) { 2001 ifp->if_ierrors++; 2002 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2003 continue; 2004 } 2005 } else { 2006 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2007 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2008 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2009 stdcnt++; 2010 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2011 ifp->if_ierrors++; 2012 bge_newbuf_std(sc, sc->bge_std, m); 2013 continue; 2014 } 2015 if (bge_newbuf_std(sc, sc->bge_std, 2016 NULL) == ENOBUFS) { 2017 ifp->if_ierrors++; 2018 bge_newbuf_std(sc, sc->bge_std, m); 2019 continue; 2020 } 2021 } 2022 2023 ifp->if_ipackets++; 2024 #ifndef __i386__ 2025 /* 2026 * The i386 allows unaligned accesses, but for other 2027 * platforms we must make sure the payload is aligned. 2028 */ 2029 if (sc->bge_rx_alignment_bug) { 2030 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2031 cur_rx->bge_len); 2032 m->m_data += ETHER_ALIGN; 2033 } 2034 #endif 2035 eh = mtod(m, struct ether_header *); 2036 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 2037 m->m_pkthdr.rcvif = ifp; 2038 2039 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2040 if (ifp->if_hwassist) { 2041 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2042 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2043 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2044 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2045 m->m_pkthdr.csum_data = 2046 cur_rx->bge_tcp_udp_csum; 2047 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2048 } 2049 } 2050 #endif 2051 2052 /* 2053 * If we received a packet with a vlan tag, 2054 * attach that information to the packet. 2055 */ 2056 if (have_tag) 2057 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2058 2059 (*ifp->if_input)(ifp, m); 2060 } 2061 2062 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2063 if (stdcnt) 2064 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2065 if (jumbocnt) 2066 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2067 2068 return; 2069 } 2070 2071 static void 2072 bge_txeof(sc) 2073 struct bge_softc *sc; 2074 { 2075 struct bge_tx_bd *cur_tx = NULL; 2076 struct ifnet *ifp; 2077 2078 ifp = &sc->arpcom.ac_if; 2079 2080 /* 2081 * Go through our tx ring and free mbufs for those 2082 * frames that have been sent. 2083 */ 2084 while (sc->bge_tx_saved_considx != 2085 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2086 u_int32_t idx = 0; 2087 2088 idx = sc->bge_tx_saved_considx; 2089 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2090 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2091 ifp->if_opackets++; 2092 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2093 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2094 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2095 } 2096 sc->bge_txcnt--; 2097 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2098 ifp->if_timer = 0; 2099 } 2100 2101 if (cur_tx != NULL) 2102 ifp->if_flags &= ~IFF_OACTIVE; 2103 2104 return; 2105 } 2106 2107 static void 2108 bge_intr(xsc) 2109 void *xsc; 2110 { 2111 struct bge_softc *sc; 2112 struct ifnet *ifp; 2113 u_int32_t statusword; 2114 u_int32_t status; 2115 2116 sc = xsc; 2117 ifp = &sc->arpcom.ac_if; 2118 statusword = 2119 atomic_readandclear_32(&sc->bge_rdata->bge_status_block.bge_status); 2120 2121 #ifdef notdef 2122 /* Avoid this for now -- checking this register is expensive. */ 2123 /* Make sure this is really our interrupt. */ 2124 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2125 return; 2126 #endif 2127 /* Ack interrupt and stop others from occuring. */ 2128 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2129 2130 /* 2131 * Process link state changes. 2132 * Grrr. The link status word in the status block does 2133 * not work correctly on the BCM5700 rev AX and BX chips, 2134 * according to all avaibable information. Hence, we have 2135 * to enable MII interrupts in order to properly obtain 2136 * async link changes. Unfortunately, this also means that 2137 * we have to read the MAC status register to detect link 2138 * changes, thereby adding an additional register access to 2139 * the interrupt handler. 2140 */ 2141 2142 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2143 2144 status = CSR_READ_4(sc, BGE_MAC_STS); 2145 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2146 sc->bge_link = 0; 2147 untimeout(bge_tick, sc, sc->bge_stat_ch); 2148 bge_tick(sc); 2149 /* Clear the interrupt */ 2150 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2151 BGE_EVTENB_MI_INTERRUPT); 2152 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2153 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2154 BRGPHY_INTRS); 2155 } 2156 } else { 2157 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2158 /* 2159 * Sometimes PCS encoding errors are detected in 2160 * TBI mode (on fiber NICs), and for some reason 2161 * the chip will signal them as link changes. 2162 * If we get a link change event, but the 'PCS 2163 * encoding error' bit in the MAC status register 2164 * is set, don't bother doing a link check. 2165 * This avoids spurious "gigabit link up" messages 2166 * that sometimes appear on fiber NICs during 2167 * periods of heavy traffic. (There should be no 2168 * effect on copper NICs.) 2169 */ 2170 status = CSR_READ_4(sc, BGE_MAC_STS); 2171 if (!(status & BGE_MACSTAT_PORT_DECODE_ERROR)) { 2172 sc->bge_link = 0; 2173 untimeout(bge_tick, sc, sc->bge_stat_ch); 2174 bge_tick(sc); 2175 } 2176 /* Clear the interrupt */ 2177 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2178 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2179 BGE_MACSTAT_LINK_CHANGED); 2180 2181 /* Force flush the status block cached by PCI bridge */ 2182 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2183 } 2184 } 2185 2186 if (ifp->if_flags & IFF_RUNNING) { 2187 /* Check RX return ring producer/consumer */ 2188 bge_rxeof(sc); 2189 2190 /* Check TX ring producer/consumer */ 2191 bge_txeof(sc); 2192 } 2193 2194 bge_handle_events(sc); 2195 2196 /* Re-enable interrupts. */ 2197 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2198 2199 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2200 bge_start(ifp); 2201 2202 return; 2203 } 2204 2205 static void 2206 bge_tick(xsc) 2207 void *xsc; 2208 { 2209 struct bge_softc *sc; 2210 struct mii_data *mii = NULL; 2211 struct ifmedia *ifm = NULL; 2212 struct ifnet *ifp; 2213 int s; 2214 2215 sc = xsc; 2216 ifp = &sc->arpcom.ac_if; 2217 2218 s = splimp(); 2219 2220 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2221 bge_stats_update_regs(sc); 2222 else 2223 bge_stats_update(sc); 2224 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2225 if (sc->bge_link) { 2226 splx(s); 2227 return; 2228 } 2229 2230 if (sc->bge_tbi) { 2231 ifm = &sc->bge_ifmedia; 2232 if (CSR_READ_4(sc, BGE_MAC_STS) & 2233 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2234 sc->bge_link++; 2235 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2236 printf("bge%d: gigabit link up\n", sc->bge_unit); 2237 if (ifp->if_snd.ifq_head != NULL) 2238 bge_start(ifp); 2239 } 2240 splx(s); 2241 return; 2242 } 2243 2244 mii = device_get_softc(sc->bge_miibus); 2245 mii_tick(mii); 2246 2247 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2248 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2249 sc->bge_link++; 2250 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2251 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2252 printf("bge%d: gigabit link up\n", 2253 sc->bge_unit); 2254 if (ifp->if_snd.ifq_head != NULL) 2255 bge_start(ifp); 2256 } 2257 2258 splx(s); 2259 2260 return; 2261 } 2262 2263 static void 2264 bge_stats_update_regs(sc) 2265 struct bge_softc *sc; 2266 { 2267 struct ifnet *ifp; 2268 struct bge_mac_stats_regs stats; 2269 u_int32_t *s; 2270 int i; 2271 2272 ifp = &sc->arpcom.ac_if; 2273 2274 s = (u_int32_t *)&stats; 2275 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2276 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2277 s++; 2278 } 2279 2280 ifp->if_collisions += 2281 (stats.dot3StatsSingleCollisionFrames + 2282 stats.dot3StatsMultipleCollisionFrames + 2283 stats.dot3StatsExcessiveCollisions + 2284 stats.dot3StatsLateCollisions) - 2285 ifp->if_collisions; 2286 2287 return; 2288 } 2289 2290 static void 2291 bge_stats_update(sc) 2292 struct bge_softc *sc; 2293 { 2294 struct ifnet *ifp; 2295 struct bge_stats *stats; 2296 2297 ifp = &sc->arpcom.ac_if; 2298 2299 stats = (struct bge_stats *)(sc->bge_vhandle + 2300 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2301 2302 ifp->if_collisions += 2303 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 2304 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 2305 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 2306 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 2307 ifp->if_collisions; 2308 2309 #ifdef notdef 2310 ifp->if_collisions += 2311 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2312 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2313 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2314 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2315 ifp->if_collisions; 2316 #endif 2317 2318 return; 2319 } 2320 2321 /* 2322 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2323 * pointers to descriptors. 2324 */ 2325 static int 2326 bge_encap(sc, m_head, txidx) 2327 struct bge_softc *sc; 2328 struct mbuf *m_head; 2329 u_int32_t *txidx; 2330 { 2331 struct bge_tx_bd *f = NULL; 2332 struct mbuf *m; 2333 u_int32_t frag, cur, cnt = 0; 2334 u_int16_t csum_flags = 0; 2335 struct m_tag *mtag; 2336 2337 m = m_head; 2338 cur = frag = *txidx; 2339 2340 if (m_head->m_pkthdr.csum_flags) { 2341 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2342 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2343 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2344 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2345 if (m_head->m_flags & M_LASTFRAG) 2346 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2347 else if (m_head->m_flags & M_FRAG) 2348 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2349 } 2350 2351 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2352 2353 /* 2354 * Start packing the mbufs in this chain into 2355 * the fragment pointers. Stop when we run out 2356 * of fragments or hit the end of the mbuf chain. 2357 */ 2358 for (m = m_head; m != NULL; m = m->m_next) { 2359 if (m->m_len != 0) { 2360 f = &sc->bge_rdata->bge_tx_ring[frag]; 2361 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2362 break; 2363 BGE_HOSTADDR(f->bge_addr, 2364 vtophys(mtod(m, vm_offset_t))); 2365 f->bge_len = m->m_len; 2366 f->bge_flags = csum_flags; 2367 if (mtag != NULL) { 2368 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2369 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2370 } else { 2371 f->bge_vlan_tag = 0; 2372 } 2373 /* 2374 * Sanity check: avoid coming within 16 descriptors 2375 * of the end of the ring. 2376 */ 2377 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2378 return(ENOBUFS); 2379 cur = frag; 2380 BGE_INC(frag, BGE_TX_RING_CNT); 2381 cnt++; 2382 } 2383 } 2384 2385 if (m != NULL) 2386 return(ENOBUFS); 2387 2388 if (frag == sc->bge_tx_saved_considx) 2389 return(ENOBUFS); 2390 2391 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2392 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2393 sc->bge_txcnt += cnt; 2394 2395 *txidx = frag; 2396 2397 return(0); 2398 } 2399 2400 /* 2401 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2402 * to the mbuf data regions directly in the transmit descriptors. 2403 */ 2404 static void 2405 bge_start(ifp) 2406 struct ifnet *ifp; 2407 { 2408 struct bge_softc *sc; 2409 struct mbuf *m_head = NULL; 2410 u_int32_t prodidx = 0; 2411 2412 sc = ifp->if_softc; 2413 2414 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2415 return; 2416 2417 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2418 2419 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2420 IF_DEQUEUE(&ifp->if_snd, m_head); 2421 if (m_head == NULL) 2422 break; 2423 2424 /* 2425 * XXX 2426 * safety overkill. If this is a fragmented packet chain 2427 * with delayed TCP/UDP checksums, then only encapsulate 2428 * it if we have enough descriptors to handle the entire 2429 * chain at once. 2430 * (paranoia -- may not actually be needed) 2431 */ 2432 if (m_head->m_flags & M_FIRSTFRAG && 2433 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2434 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2435 m_head->m_pkthdr.csum_data + 16) { 2436 IF_PREPEND(&ifp->if_snd, m_head); 2437 ifp->if_flags |= IFF_OACTIVE; 2438 break; 2439 } 2440 } 2441 2442 /* 2443 * Pack the data into the transmit ring. If we 2444 * don't have room, set the OACTIVE flag and wait 2445 * for the NIC to drain the ring. 2446 */ 2447 if (bge_encap(sc, m_head, &prodidx)) { 2448 IF_PREPEND(&ifp->if_snd, m_head); 2449 ifp->if_flags |= IFF_OACTIVE; 2450 break; 2451 } 2452 2453 /* 2454 * If there's a BPF listener, bounce a copy of this frame 2455 * to him. 2456 */ 2457 BPF_MTAP(ifp, m_head); 2458 } 2459 2460 /* Transmit */ 2461 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2462 /* 5700 b2 errata */ 2463 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2464 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2465 2466 /* 2467 * Set a timeout in case the chip goes out to lunch. 2468 */ 2469 ifp->if_timer = 5; 2470 2471 return; 2472 } 2473 2474 static void 2475 bge_init(xsc) 2476 void *xsc; 2477 { 2478 struct bge_softc *sc = xsc; 2479 struct ifnet *ifp; 2480 u_int16_t *m; 2481 int s; 2482 2483 s = splimp(); 2484 2485 ifp = &sc->arpcom.ac_if; 2486 2487 if (ifp->if_flags & IFF_RUNNING) { 2488 splx(s); 2489 return; 2490 } 2491 2492 /* Cancel pending I/O and flush buffers. */ 2493 bge_stop(sc); 2494 bge_reset(sc); 2495 bge_chipinit(sc); 2496 2497 /* 2498 * Init the various state machines, ring 2499 * control blocks and firmware. 2500 */ 2501 if (bge_blockinit(sc)) { 2502 printf("bge%d: initialization failure\n", sc->bge_unit); 2503 splx(s); 2504 return; 2505 } 2506 2507 ifp = &sc->arpcom.ac_if; 2508 2509 /* Specify MTU. */ 2510 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2511 ETHER_HDR_LEN + ETHER_CRC_LEN); 2512 2513 /* Load our MAC address. */ 2514 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2515 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2516 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2517 2518 /* Enable or disable promiscuous mode as needed. */ 2519 if (ifp->if_flags & IFF_PROMISC) { 2520 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2521 } else { 2522 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2523 } 2524 2525 /* Program multicast filter. */ 2526 bge_setmulti(sc); 2527 2528 /* Init RX ring. */ 2529 bge_init_rx_ring_std(sc); 2530 2531 /* 2532 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 2533 * memory to insure that the chip has in fact read the first 2534 * entry of the ring. 2535 */ 2536 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 2537 u_int32_t v, i; 2538 for (i = 0; i < 10; i++) { 2539 DELAY(20); 2540 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 2541 if (v == (MCLBYTES - ETHER_ALIGN)) 2542 break; 2543 } 2544 if (i == 10) 2545 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 2546 sc->bge_unit); 2547 } 2548 2549 /* Init jumbo RX ring. */ 2550 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2551 bge_init_rx_ring_jumbo(sc); 2552 2553 /* Init our RX return ring index */ 2554 sc->bge_rx_saved_considx = 0; 2555 2556 /* Init TX ring. */ 2557 bge_init_tx_ring(sc); 2558 2559 /* Turn on transmitter */ 2560 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2561 2562 /* Turn on receiver */ 2563 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2564 2565 /* Tell firmware we're alive. */ 2566 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2567 2568 /* Enable host interrupts. */ 2569 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2570 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2571 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2572 2573 bge_ifmedia_upd(ifp); 2574 2575 ifp->if_flags |= IFF_RUNNING; 2576 ifp->if_flags &= ~IFF_OACTIVE; 2577 2578 splx(s); 2579 2580 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2581 2582 return; 2583 } 2584 2585 /* 2586 * Set media options. 2587 */ 2588 static int 2589 bge_ifmedia_upd(ifp) 2590 struct ifnet *ifp; 2591 { 2592 struct bge_softc *sc; 2593 struct mii_data *mii; 2594 struct ifmedia *ifm; 2595 2596 sc = ifp->if_softc; 2597 ifm = &sc->bge_ifmedia; 2598 2599 /* If this is a 1000baseX NIC, enable the TBI port. */ 2600 if (sc->bge_tbi) { 2601 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2602 return(EINVAL); 2603 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2604 case IFM_AUTO: 2605 break; 2606 case IFM_1000_SX: 2607 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2608 BGE_CLRBIT(sc, BGE_MAC_MODE, 2609 BGE_MACMODE_HALF_DUPLEX); 2610 } else { 2611 BGE_SETBIT(sc, BGE_MAC_MODE, 2612 BGE_MACMODE_HALF_DUPLEX); 2613 } 2614 break; 2615 default: 2616 return(EINVAL); 2617 } 2618 return(0); 2619 } 2620 2621 mii = device_get_softc(sc->bge_miibus); 2622 sc->bge_link = 0; 2623 if (mii->mii_instance) { 2624 struct mii_softc *miisc; 2625 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2626 miisc = LIST_NEXT(miisc, mii_list)) 2627 mii_phy_reset(miisc); 2628 } 2629 mii_mediachg(mii); 2630 2631 return(0); 2632 } 2633 2634 /* 2635 * Report current media status. 2636 */ 2637 static void 2638 bge_ifmedia_sts(ifp, ifmr) 2639 struct ifnet *ifp; 2640 struct ifmediareq *ifmr; 2641 { 2642 struct bge_softc *sc; 2643 struct mii_data *mii; 2644 2645 sc = ifp->if_softc; 2646 2647 if (sc->bge_tbi) { 2648 ifmr->ifm_status = IFM_AVALID; 2649 ifmr->ifm_active = IFM_ETHER; 2650 if (CSR_READ_4(sc, BGE_MAC_STS) & 2651 BGE_MACSTAT_TBI_PCS_SYNCHED) 2652 ifmr->ifm_status |= IFM_ACTIVE; 2653 ifmr->ifm_active |= IFM_1000_SX; 2654 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2655 ifmr->ifm_active |= IFM_HDX; 2656 else 2657 ifmr->ifm_active |= IFM_FDX; 2658 return; 2659 } 2660 2661 mii = device_get_softc(sc->bge_miibus); 2662 mii_pollstat(mii); 2663 ifmr->ifm_active = mii->mii_media_active; 2664 ifmr->ifm_status = mii->mii_media_status; 2665 2666 return; 2667 } 2668 2669 static int 2670 bge_ioctl(ifp, command, data) 2671 struct ifnet *ifp; 2672 u_long command; 2673 caddr_t data; 2674 { 2675 struct bge_softc *sc = ifp->if_softc; 2676 struct ifreq *ifr = (struct ifreq *) data; 2677 int s, mask, error = 0; 2678 struct mii_data *mii; 2679 2680 s = splimp(); 2681 2682 switch(command) { 2683 case SIOCSIFMTU: 2684 /* Disallow jumbo frames on 5705. */ 2685 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2686 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 2687 error = EINVAL; 2688 else { 2689 ifp->if_mtu = ifr->ifr_mtu; 2690 ifp->if_flags &= ~IFF_RUNNING; 2691 bge_init(sc); 2692 } 2693 break; 2694 case SIOCSIFFLAGS: 2695 if (ifp->if_flags & IFF_UP) { 2696 /* 2697 * If only the state of the PROMISC flag changed, 2698 * then just use the 'set promisc mode' command 2699 * instead of reinitializing the entire NIC. Doing 2700 * a full re-init means reloading the firmware and 2701 * waiting for it to start up, which may take a 2702 * second or two. 2703 */ 2704 if (ifp->if_flags & IFF_RUNNING && 2705 ifp->if_flags & IFF_PROMISC && 2706 !(sc->bge_if_flags & IFF_PROMISC)) { 2707 BGE_SETBIT(sc, BGE_RX_MODE, 2708 BGE_RXMODE_RX_PROMISC); 2709 } else if (ifp->if_flags & IFF_RUNNING && 2710 !(ifp->if_flags & IFF_PROMISC) && 2711 sc->bge_if_flags & IFF_PROMISC) { 2712 BGE_CLRBIT(sc, BGE_RX_MODE, 2713 BGE_RXMODE_RX_PROMISC); 2714 } else 2715 bge_init(sc); 2716 } else { 2717 if (ifp->if_flags & IFF_RUNNING) { 2718 bge_stop(sc); 2719 } 2720 } 2721 sc->bge_if_flags = ifp->if_flags; 2722 error = 0; 2723 break; 2724 case SIOCADDMULTI: 2725 case SIOCDELMULTI: 2726 if (ifp->if_flags & IFF_RUNNING) { 2727 bge_setmulti(sc); 2728 error = 0; 2729 } 2730 break; 2731 case SIOCSIFMEDIA: 2732 case SIOCGIFMEDIA: 2733 if (sc->bge_tbi) { 2734 error = ifmedia_ioctl(ifp, ifr, 2735 &sc->bge_ifmedia, command); 2736 } else { 2737 mii = device_get_softc(sc->bge_miibus); 2738 error = ifmedia_ioctl(ifp, ifr, 2739 &mii->mii_media, command); 2740 } 2741 break; 2742 case SIOCSIFCAP: 2743 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2744 if (mask & IFCAP_HWCSUM) { 2745 if (IFCAP_HWCSUM & ifp->if_capenable) 2746 ifp->if_capenable &= ~IFCAP_HWCSUM; 2747 else 2748 ifp->if_capenable |= IFCAP_HWCSUM; 2749 } 2750 error = 0; 2751 break; 2752 default: 2753 error = ether_ioctl(ifp, command, data); 2754 break; 2755 } 2756 2757 (void)splx(s); 2758 2759 return(error); 2760 } 2761 2762 static void 2763 bge_watchdog(ifp) 2764 struct ifnet *ifp; 2765 { 2766 struct bge_softc *sc; 2767 2768 sc = ifp->if_softc; 2769 2770 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2771 2772 ifp->if_flags &= ~IFF_RUNNING; 2773 bge_init(sc); 2774 2775 ifp->if_oerrors++; 2776 2777 return; 2778 } 2779 2780 /* 2781 * Stop the adapter and free any mbufs allocated to the 2782 * RX and TX lists. 2783 */ 2784 static void 2785 bge_stop(sc) 2786 struct bge_softc *sc; 2787 { 2788 struct ifnet *ifp; 2789 struct ifmedia_entry *ifm; 2790 struct mii_data *mii = NULL; 2791 int mtmp, itmp; 2792 2793 ifp = &sc->arpcom.ac_if; 2794 2795 if (!sc->bge_tbi) 2796 mii = device_get_softc(sc->bge_miibus); 2797 2798 untimeout(bge_tick, sc, sc->bge_stat_ch); 2799 2800 /* 2801 * Disable all of the receiver blocks 2802 */ 2803 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2804 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2805 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2806 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2807 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2808 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2809 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2810 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2811 2812 /* 2813 * Disable all of the transmit blocks 2814 */ 2815 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2816 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2817 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2818 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2819 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2820 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2821 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2822 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2823 2824 /* 2825 * Shut down all of the memory managers and related 2826 * state machines. 2827 */ 2828 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2829 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2830 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2831 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2832 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2833 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2834 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2835 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2836 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2837 } 2838 2839 /* Disable host interrupts. */ 2840 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2841 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2842 2843 /* 2844 * Tell firmware we're shutting down. 2845 */ 2846 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2847 2848 /* Free the RX lists. */ 2849 bge_free_rx_ring_std(sc); 2850 2851 /* Free jumbo RX list. */ 2852 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2853 bge_free_rx_ring_jumbo(sc); 2854 2855 /* Free TX buffers. */ 2856 bge_free_tx_ring(sc); 2857 2858 /* 2859 * Isolate/power down the PHY, but leave the media selection 2860 * unchanged so that things will be put back to normal when 2861 * we bring the interface back up. 2862 */ 2863 if (!sc->bge_tbi) { 2864 itmp = ifp->if_flags; 2865 ifp->if_flags |= IFF_UP; 2866 ifm = mii->mii_media.ifm_cur; 2867 mtmp = ifm->ifm_media; 2868 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2869 mii_mediachg(mii); 2870 ifm->ifm_media = mtmp; 2871 ifp->if_flags = itmp; 2872 } 2873 2874 sc->bge_link = 0; 2875 2876 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2877 2878 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2879 2880 return; 2881 } 2882 2883 /* 2884 * Stop all chip I/O so that the kernel's probe routines don't 2885 * get confused by errant DMAs when rebooting. 2886 */ 2887 static void 2888 bge_shutdown(dev) 2889 device_t dev; 2890 { 2891 struct bge_softc *sc; 2892 2893 sc = device_get_softc(dev); 2894 2895 bge_stop(sc); 2896 bge_reset(sc); 2897 2898 return; 2899 } 2900