1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #include <sys/param.h> 70 #include <sys/endian.h> 71 #include <sys/systm.h> 72 #include <sys/sockio.h> 73 #include <sys/mbuf.h> 74 #include <sys/malloc.h> 75 #include <sys/kernel.h> 76 #include <sys/socket.h> 77 #include <sys/queue.h> 78 79 #include <net/if.h> 80 #include <net/if_arp.h> 81 #include <net/ethernet.h> 82 #include <net/if_dl.h> 83 #include <net/if_media.h> 84 85 #include <net/bpf.h> 86 87 #include <net/if_types.h> 88 #include <net/if_vlan_var.h> 89 90 #include <netinet/in_systm.h> 91 #include <netinet/in.h> 92 #include <netinet/ip.h> 93 94 #include <machine/clock.h> /* for DELAY */ 95 #include <machine/bus_memio.h> 96 #include <machine/bus.h> 97 #include <machine/resource.h> 98 #include <sys/bus.h> 99 #include <sys/rman.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 #include "miidevs.h" 104 #include <dev/mii/brgphyreg.h> 105 106 #include <dev/pci/pcireg.h> 107 #include <dev/pci/pcivar.h> 108 109 #include <dev/bge/if_bgereg.h> 110 111 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 112 113 MODULE_DEPEND(bge, pci, 1, 1, 1); 114 MODULE_DEPEND(bge, ether, 1, 1, 1); 115 MODULE_DEPEND(bge, miibus, 1, 1, 1); 116 117 /* "controller miibus0" required. See GENERIC if you get errors here. */ 118 #include "miibus_if.h" 119 120 /* 121 * Various supported device vendors/types and their names. Note: the 122 * spec seems to indicate that the hardware still has Alteon's vendor 123 * ID burned into it, though it will always be overriden by the vendor 124 * ID in the EEPROM. Just to be safe, we cover all possibilities. 125 */ 126 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 127 128 static struct bge_type bge_devs[] = { 129 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 130 "Broadcom BCM5700 Gigabit Ethernet" }, 131 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 132 "Broadcom BCM5701 Gigabit Ethernet" }, 133 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 134 "Broadcom BCM5700 Gigabit Ethernet" }, 135 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 136 "Broadcom BCM5701 Gigabit Ethernet" }, 137 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 138 "Broadcom BCM5702 Gigabit Ethernet" }, 139 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 140 "Broadcom BCM5702X Gigabit Ethernet" }, 141 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 142 "Broadcom BCM5703 Gigabit Ethernet" }, 143 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 144 "Broadcom BCM5703X Gigabit Ethernet" }, 145 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 146 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 147 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 148 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 149 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 150 "Broadcom BCM5705 Gigabit Ethernet" }, 151 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K, 152 "Broadcom BCM5705K Gigabit Ethernet" }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 154 "Broadcom BCM5705M Gigabit Ethernet" }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 156 "Broadcom BCM5705M Gigabit Ethernet" }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 158 "Broadcom BCM5782 Gigabit Ethernet" }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788, 160 "Broadcom BCM5788 Gigabit Ethernet" }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901, 162 "Broadcom BCM5901 Fast Ethernet" }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2, 164 "Broadcom BCM5901A2 Fast Ethernet" }, 165 { SK_VENDORID, SK_DEVICEID_ALTIMA, 166 "SysKonnect Gigabit Ethernet" }, 167 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 168 "Altima AC1000 Gigabit Ethernet" }, 169 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002, 170 "Altima AC1002 Gigabit Ethernet" }, 171 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 172 "Altima AC9100 Gigabit Ethernet" }, 173 { 0, 0, NULL } 174 }; 175 176 static int bge_probe (device_t); 177 static int bge_attach (device_t); 178 static int bge_detach (device_t); 179 static void bge_release_resources 180 (struct bge_softc *); 181 static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 182 static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 183 bus_size_t, int); 184 static int bge_dma_alloc (device_t); 185 static void bge_dma_free (struct bge_softc *); 186 187 static void bge_txeof (struct bge_softc *); 188 static void bge_rxeof (struct bge_softc *); 189 190 static void bge_tick_locked (struct bge_softc *); 191 static void bge_tick (void *); 192 static void bge_stats_update (struct bge_softc *); 193 static void bge_stats_update_regs 194 (struct bge_softc *); 195 static int bge_encap (struct bge_softc *, struct mbuf *, 196 u_int32_t *); 197 198 static void bge_intr (void *); 199 static void bge_start_locked (struct ifnet *); 200 static void bge_start (struct ifnet *); 201 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 202 static void bge_init_locked (struct bge_softc *); 203 static void bge_init (void *); 204 static void bge_stop (struct bge_softc *); 205 static void bge_watchdog (struct ifnet *); 206 static void bge_shutdown (device_t); 207 static int bge_ifmedia_upd (struct ifnet *); 208 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 209 210 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 211 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 212 213 static uint32_t bge_mchash (const uint8_t *); 214 static void bge_setmulti (struct bge_softc *); 215 216 static void bge_handle_events (struct bge_softc *); 217 static int bge_alloc_jumbo_mem (struct bge_softc *); 218 static void bge_free_jumbo_mem (struct bge_softc *); 219 static void *bge_jalloc (struct bge_softc *); 220 static void bge_jfree (void *, void *); 221 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 222 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 223 static int bge_init_rx_ring_std (struct bge_softc *); 224 static void bge_free_rx_ring_std (struct bge_softc *); 225 static int bge_init_rx_ring_jumbo (struct bge_softc *); 226 static void bge_free_rx_ring_jumbo (struct bge_softc *); 227 static void bge_free_tx_ring (struct bge_softc *); 228 static int bge_init_tx_ring (struct bge_softc *); 229 230 static int bge_chipinit (struct bge_softc *); 231 static int bge_blockinit (struct bge_softc *); 232 233 #ifdef notdef 234 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 235 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 236 static void bge_vpd_read (struct bge_softc *); 237 #endif 238 239 static u_int32_t bge_readmem_ind 240 (struct bge_softc *, int); 241 static void bge_writemem_ind (struct bge_softc *, int, int); 242 #ifdef notdef 243 static u_int32_t bge_readreg_ind 244 (struct bge_softc *, int); 245 #endif 246 static void bge_writereg_ind (struct bge_softc *, int, int); 247 248 static int bge_miibus_readreg (device_t, int, int); 249 static int bge_miibus_writereg (device_t, int, int, int); 250 static void bge_miibus_statchg (device_t); 251 252 static void bge_reset (struct bge_softc *); 253 254 static device_method_t bge_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, bge_probe), 257 DEVMETHOD(device_attach, bge_attach), 258 DEVMETHOD(device_detach, bge_detach), 259 DEVMETHOD(device_shutdown, bge_shutdown), 260 261 /* bus interface */ 262 DEVMETHOD(bus_print_child, bus_generic_print_child), 263 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 264 265 /* MII interface */ 266 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 267 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 268 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 269 270 { 0, 0 } 271 }; 272 273 static driver_t bge_driver = { 274 "bge", 275 bge_methods, 276 sizeof(struct bge_softc) 277 }; 278 279 static devclass_t bge_devclass; 280 281 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 282 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 283 284 static u_int32_t 285 bge_readmem_ind(sc, off) 286 struct bge_softc *sc; 287 int off; 288 { 289 device_t dev; 290 291 dev = sc->bge_dev; 292 293 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 294 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 295 } 296 297 static void 298 bge_writemem_ind(sc, off, val) 299 struct bge_softc *sc; 300 int off, val; 301 { 302 device_t dev; 303 304 dev = sc->bge_dev; 305 306 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 307 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 308 309 return; 310 } 311 312 #ifdef notdef 313 static u_int32_t 314 bge_readreg_ind(sc, off) 315 struct bge_softc *sc; 316 int off; 317 { 318 device_t dev; 319 320 dev = sc->bge_dev; 321 322 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 323 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 324 } 325 #endif 326 327 static void 328 bge_writereg_ind(sc, off, val) 329 struct bge_softc *sc; 330 int off, val; 331 { 332 device_t dev; 333 334 dev = sc->bge_dev; 335 336 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 337 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 338 339 return; 340 } 341 342 /* 343 * Map a single buffer address. 344 */ 345 346 static void 347 bge_dma_map_addr(arg, segs, nseg, error) 348 void *arg; 349 bus_dma_segment_t *segs; 350 int nseg; 351 int error; 352 { 353 struct bge_dmamap_arg *ctx; 354 355 if (error) 356 return; 357 358 ctx = arg; 359 360 if (nseg > ctx->bge_maxsegs) { 361 ctx->bge_maxsegs = 0; 362 return; 363 } 364 365 ctx->bge_busaddr = segs->ds_addr; 366 367 return; 368 } 369 370 /* 371 * Map an mbuf chain into an TX ring. 372 */ 373 374 static void 375 bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 376 void *arg; 377 bus_dma_segment_t *segs; 378 int nseg; 379 bus_size_t mapsize; 380 int error; 381 { 382 struct bge_dmamap_arg *ctx; 383 struct bge_tx_bd *d = NULL; 384 int i = 0, idx; 385 386 if (error) 387 return; 388 389 ctx = arg; 390 391 /* Signal error to caller if there's too many segments */ 392 if (nseg > ctx->bge_maxsegs) { 393 ctx->bge_maxsegs = 0; 394 return; 395 } 396 397 idx = ctx->bge_idx; 398 while(1) { 399 d = &ctx->bge_ring[idx]; 400 d->bge_addr.bge_addr_lo = 401 htole32(BGE_ADDR_LO(segs[i].ds_addr)); 402 d->bge_addr.bge_addr_hi = 403 htole32(BGE_ADDR_HI(segs[i].ds_addr)); 404 d->bge_len = htole16(segs[i].ds_len); 405 d->bge_flags = htole16(ctx->bge_flags); 406 i++; 407 if (i == nseg) 408 break; 409 BGE_INC(idx, BGE_TX_RING_CNT); 410 } 411 412 d->bge_flags |= htole16(BGE_TXBDFLAG_END); 413 ctx->bge_maxsegs = nseg; 414 ctx->bge_idx = idx; 415 416 return; 417 } 418 419 420 #ifdef notdef 421 static u_int8_t 422 bge_vpd_readbyte(sc, addr) 423 struct bge_softc *sc; 424 int addr; 425 { 426 int i; 427 device_t dev; 428 u_int32_t val; 429 430 dev = sc->bge_dev; 431 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 432 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 433 DELAY(10); 434 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 435 break; 436 } 437 438 if (i == BGE_TIMEOUT) { 439 printf("bge%d: VPD read timed out\n", sc->bge_unit); 440 return(0); 441 } 442 443 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 444 445 return((val >> ((addr % 4) * 8)) & 0xFF); 446 } 447 448 static void 449 bge_vpd_read_res(sc, res, addr) 450 struct bge_softc *sc; 451 struct vpd_res *res; 452 int addr; 453 { 454 int i; 455 u_int8_t *ptr; 456 457 ptr = (u_int8_t *)res; 458 for (i = 0; i < sizeof(struct vpd_res); i++) 459 ptr[i] = bge_vpd_readbyte(sc, i + addr); 460 461 return; 462 } 463 464 static void 465 bge_vpd_read(sc) 466 struct bge_softc *sc; 467 { 468 int pos = 0, i; 469 struct vpd_res res; 470 471 if (sc->bge_vpd_prodname != NULL) 472 free(sc->bge_vpd_prodname, M_DEVBUF); 473 if (sc->bge_vpd_readonly != NULL) 474 free(sc->bge_vpd_readonly, M_DEVBUF); 475 sc->bge_vpd_prodname = NULL; 476 sc->bge_vpd_readonly = NULL; 477 478 bge_vpd_read_res(sc, &res, pos); 479 480 if (res.vr_id != VPD_RES_ID) { 481 printf("bge%d: bad VPD resource id: expected %x got %x\n", 482 sc->bge_unit, VPD_RES_ID, res.vr_id); 483 return; 484 } 485 486 pos += sizeof(res); 487 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 488 for (i = 0; i < res.vr_len; i++) 489 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 490 sc->bge_vpd_prodname[i] = '\0'; 491 pos += i; 492 493 bge_vpd_read_res(sc, &res, pos); 494 495 if (res.vr_id != VPD_RES_READ) { 496 printf("bge%d: bad VPD resource id: expected %x got %x\n", 497 sc->bge_unit, VPD_RES_READ, res.vr_id); 498 return; 499 } 500 501 pos += sizeof(res); 502 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 503 for (i = 0; i < res.vr_len + 1; i++) 504 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 505 506 return; 507 } 508 #endif 509 510 /* 511 * Read a byte of data stored in the EEPROM at address 'addr.' The 512 * BCM570x supports both the traditional bitbang interface and an 513 * auto access interface for reading the EEPROM. We use the auto 514 * access method. 515 */ 516 static u_int8_t 517 bge_eeprom_getbyte(sc, addr, dest) 518 struct bge_softc *sc; 519 int addr; 520 u_int8_t *dest; 521 { 522 int i; 523 u_int32_t byte = 0; 524 525 /* 526 * Enable use of auto EEPROM access so we can avoid 527 * having to use the bitbang method. 528 */ 529 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 530 531 /* Reset the EEPROM, load the clock period. */ 532 CSR_WRITE_4(sc, BGE_EE_ADDR, 533 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 534 DELAY(20); 535 536 /* Issue the read EEPROM command. */ 537 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 538 539 /* Wait for completion */ 540 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 541 DELAY(10); 542 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 543 break; 544 } 545 546 if (i == BGE_TIMEOUT) { 547 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 548 return(0); 549 } 550 551 /* Get result. */ 552 byte = CSR_READ_4(sc, BGE_EE_DATA); 553 554 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 555 556 return(0); 557 } 558 559 /* 560 * Read a sequence of bytes from the EEPROM. 561 */ 562 static int 563 bge_read_eeprom(sc, dest, off, cnt) 564 struct bge_softc *sc; 565 caddr_t dest; 566 int off; 567 int cnt; 568 { 569 int err = 0, i; 570 u_int8_t byte = 0; 571 572 for (i = 0; i < cnt; i++) { 573 err = bge_eeprom_getbyte(sc, off + i, &byte); 574 if (err) 575 break; 576 *(dest + i) = byte; 577 } 578 579 return(err ? 1 : 0); 580 } 581 582 static int 583 bge_miibus_readreg(dev, phy, reg) 584 device_t dev; 585 int phy, reg; 586 { 587 struct bge_softc *sc; 588 u_int32_t val, autopoll; 589 int i; 590 591 sc = device_get_softc(dev); 592 593 /* 594 * Broadcom's own driver always assumes the internal 595 * PHY is at GMII address 1. On some chips, the PHY responds 596 * to accesses at all addresses, which could cause us to 597 * bogusly attach the PHY 32 times at probe type. Always 598 * restricting the lookup to address 1 is simpler than 599 * trying to figure out which chips revisions should be 600 * special-cased. 601 */ 602 if (phy != 1) 603 return(0); 604 605 /* Reading with autopolling on may trigger PCI errors */ 606 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 607 if (autopoll & BGE_MIMODE_AUTOPOLL) { 608 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 609 DELAY(40); 610 } 611 612 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 613 BGE_MIPHY(phy)|BGE_MIREG(reg)); 614 615 for (i = 0; i < BGE_TIMEOUT; i++) { 616 val = CSR_READ_4(sc, BGE_MI_COMM); 617 if (!(val & BGE_MICOMM_BUSY)) 618 break; 619 } 620 621 if (i == BGE_TIMEOUT) { 622 printf("bge%d: PHY read timed out\n", sc->bge_unit); 623 val = 0; 624 goto done; 625 } 626 627 val = CSR_READ_4(sc, BGE_MI_COMM); 628 629 done: 630 if (autopoll & BGE_MIMODE_AUTOPOLL) { 631 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 632 DELAY(40); 633 } 634 635 if (val & BGE_MICOMM_READFAIL) 636 return(0); 637 638 return(val & 0xFFFF); 639 } 640 641 static int 642 bge_miibus_writereg(dev, phy, reg, val) 643 device_t dev; 644 int phy, reg, val; 645 { 646 struct bge_softc *sc; 647 u_int32_t autopoll; 648 int i; 649 650 sc = device_get_softc(dev); 651 652 /* Reading with autopolling on may trigger PCI errors */ 653 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 654 if (autopoll & BGE_MIMODE_AUTOPOLL) { 655 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 656 DELAY(40); 657 } 658 659 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 660 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 661 662 for (i = 0; i < BGE_TIMEOUT; i++) { 663 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 664 break; 665 } 666 667 if (autopoll & BGE_MIMODE_AUTOPOLL) { 668 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 669 DELAY(40); 670 } 671 672 if (i == BGE_TIMEOUT) { 673 printf("bge%d: PHY read timed out\n", sc->bge_unit); 674 return(0); 675 } 676 677 return(0); 678 } 679 680 static void 681 bge_miibus_statchg(dev) 682 device_t dev; 683 { 684 struct bge_softc *sc; 685 struct mii_data *mii; 686 687 sc = device_get_softc(dev); 688 mii = device_get_softc(sc->bge_miibus); 689 690 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 691 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 692 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 693 } else { 694 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 695 } 696 697 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 698 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 699 } else { 700 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 701 } 702 703 return; 704 } 705 706 /* 707 * Handle events that have triggered interrupts. 708 */ 709 static void 710 bge_handle_events(sc) 711 struct bge_softc *sc; 712 { 713 714 return; 715 } 716 717 /* 718 * Memory management for jumbo frames. 719 */ 720 721 static int 722 bge_alloc_jumbo_mem(sc) 723 struct bge_softc *sc; 724 { 725 caddr_t ptr; 726 register int i, error; 727 struct bge_jpool_entry *entry; 728 729 /* Create tag for jumbo buffer block */ 730 731 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 732 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 733 NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL, 734 &sc->bge_cdata.bge_jumbo_tag); 735 736 if (error) { 737 printf("bge%d: could not allocate jumbo dma tag\n", 738 sc->bge_unit); 739 return (ENOMEM); 740 } 741 742 /* Allocate DMA'able memory for jumbo buffer block */ 743 744 error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag, 745 (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT, 746 &sc->bge_cdata.bge_jumbo_map); 747 748 if (error) 749 return (ENOMEM); 750 751 SLIST_INIT(&sc->bge_jfree_listhead); 752 SLIST_INIT(&sc->bge_jinuse_listhead); 753 754 /* 755 * Now divide it up into 9K pieces and save the addresses 756 * in an array. 757 */ 758 ptr = sc->bge_ldata.bge_jumbo_buf; 759 for (i = 0; i < BGE_JSLOTS; i++) { 760 sc->bge_cdata.bge_jslots[i] = ptr; 761 ptr += BGE_JLEN; 762 entry = malloc(sizeof(struct bge_jpool_entry), 763 M_DEVBUF, M_NOWAIT); 764 if (entry == NULL) { 765 bge_free_jumbo_mem(sc); 766 sc->bge_ldata.bge_jumbo_buf = NULL; 767 printf("bge%d: no memory for jumbo " 768 "buffer queue!\n", sc->bge_unit); 769 return(ENOBUFS); 770 } 771 entry->slot = i; 772 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 773 entry, jpool_entries); 774 } 775 776 return(0); 777 } 778 779 static void 780 bge_free_jumbo_mem(sc) 781 struct bge_softc *sc; 782 { 783 int i; 784 struct bge_jpool_entry *entry; 785 786 for (i = 0; i < BGE_JSLOTS; i++) { 787 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 788 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 789 free(entry, M_DEVBUF); 790 } 791 792 /* Destroy jumbo buffer block */ 793 794 if (sc->bge_ldata.bge_rx_jumbo_ring) 795 bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag, 796 sc->bge_ldata.bge_jumbo_buf, 797 sc->bge_cdata.bge_jumbo_map); 798 799 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 800 bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag, 801 sc->bge_cdata.bge_jumbo_map); 802 803 if (sc->bge_cdata.bge_jumbo_tag) 804 bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag); 805 806 return; 807 } 808 809 /* 810 * Allocate a jumbo buffer. 811 */ 812 static void * 813 bge_jalloc(sc) 814 struct bge_softc *sc; 815 { 816 struct bge_jpool_entry *entry; 817 818 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 819 820 if (entry == NULL) { 821 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 822 return(NULL); 823 } 824 825 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 826 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 827 return(sc->bge_cdata.bge_jslots[entry->slot]); 828 } 829 830 /* 831 * Release a jumbo buffer. 832 */ 833 static void 834 bge_jfree(buf, args) 835 void *buf; 836 void *args; 837 { 838 struct bge_jpool_entry *entry; 839 struct bge_softc *sc; 840 int i; 841 842 /* Extract the softc struct pointer. */ 843 sc = (struct bge_softc *)args; 844 845 if (sc == NULL) 846 panic("bge_jfree: can't find softc pointer!"); 847 848 /* calculate the slot this buffer belongs to */ 849 850 i = ((vm_offset_t)buf 851 - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN; 852 853 if ((i < 0) || (i >= BGE_JSLOTS)) 854 panic("bge_jfree: asked to free buffer that we don't manage!"); 855 856 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 857 if (entry == NULL) 858 panic("bge_jfree: buffer not in use!"); 859 entry->slot = i; 860 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 861 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 862 863 return; 864 } 865 866 867 /* 868 * Intialize a standard receive ring descriptor. 869 */ 870 static int 871 bge_newbuf_std(sc, i, m) 872 struct bge_softc *sc; 873 int i; 874 struct mbuf *m; 875 { 876 struct mbuf *m_new = NULL; 877 struct bge_rx_bd *r; 878 struct bge_dmamap_arg ctx; 879 int error; 880 881 if (m == NULL) { 882 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 883 if (m_new == NULL) { 884 return(ENOBUFS); 885 } 886 887 MCLGET(m_new, M_DONTWAIT); 888 if (!(m_new->m_flags & M_EXT)) { 889 m_freem(m_new); 890 return(ENOBUFS); 891 } 892 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 893 } else { 894 m_new = m; 895 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 896 m_new->m_data = m_new->m_ext.ext_buf; 897 } 898 899 if (!sc->bge_rx_alignment_bug) 900 m_adj(m_new, ETHER_ALIGN); 901 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 902 r = &sc->bge_ldata.bge_rx_std_ring[i]; 903 ctx.bge_maxsegs = 1; 904 ctx.sc = sc; 905 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 906 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 907 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 908 if (error || ctx.bge_maxsegs == 0) { 909 if (m == NULL) 910 m_freem(m_new); 911 return(ENOMEM); 912 } 913 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 914 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 915 r->bge_flags = htole16(BGE_RXBDFLAG_END); 916 r->bge_len = htole16(m_new->m_len); 917 r->bge_idx = htole16(i); 918 919 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 920 sc->bge_cdata.bge_rx_std_dmamap[i], 921 BUS_DMASYNC_PREREAD); 922 923 return(0); 924 } 925 926 /* 927 * Initialize a jumbo receive ring descriptor. This allocates 928 * a jumbo buffer from the pool managed internally by the driver. 929 */ 930 static int 931 bge_newbuf_jumbo(sc, i, m) 932 struct bge_softc *sc; 933 int i; 934 struct mbuf *m; 935 { 936 struct mbuf *m_new = NULL; 937 struct bge_rx_bd *r; 938 struct bge_dmamap_arg ctx; 939 int error; 940 941 if (m == NULL) { 942 caddr_t *buf = NULL; 943 944 /* Allocate the mbuf. */ 945 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 946 if (m_new == NULL) { 947 return(ENOBUFS); 948 } 949 950 /* Allocate the jumbo buffer */ 951 buf = bge_jalloc(sc); 952 if (buf == NULL) { 953 m_freem(m_new); 954 printf("bge%d: jumbo allocation failed " 955 "-- packet dropped!\n", sc->bge_unit); 956 return(ENOBUFS); 957 } 958 959 /* Attach the buffer to the mbuf. */ 960 m_new->m_data = (void *) buf; 961 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 962 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 963 (struct bge_softc *)sc, 0, EXT_NET_DRV); 964 } else { 965 m_new = m; 966 m_new->m_data = m_new->m_ext.ext_buf; 967 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 968 } 969 970 if (!sc->bge_rx_alignment_bug) 971 m_adj(m_new, ETHER_ALIGN); 972 /* Set up the descriptor. */ 973 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 974 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 975 ctx.bge_maxsegs = 1; 976 ctx.sc = sc; 977 error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo, 978 sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *), 979 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 980 if (error || ctx.bge_maxsegs == 0) { 981 if (m == NULL) 982 m_freem(m_new); 983 return(ENOMEM); 984 } 985 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 986 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 987 r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING); 988 r->bge_len = htole16(m_new->m_len); 989 r->bge_idx = htole16(i); 990 991 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 992 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 993 BUS_DMASYNC_PREREAD); 994 995 return(0); 996 } 997 998 /* 999 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 1000 * that's 1MB or memory, which is a lot. For now, we fill only the first 1001 * 256 ring entries and hope that our CPU is fast enough to keep up with 1002 * the NIC. 1003 */ 1004 static int 1005 bge_init_rx_ring_std(sc) 1006 struct bge_softc *sc; 1007 { 1008 int i; 1009 1010 for (i = 0; i < BGE_SSLOTS; i++) { 1011 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1012 return(ENOBUFS); 1013 }; 1014 1015 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1016 sc->bge_cdata.bge_rx_std_ring_map, 1017 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1018 1019 sc->bge_std = i - 1; 1020 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1021 1022 return(0); 1023 } 1024 1025 static void 1026 bge_free_rx_ring_std(sc) 1027 struct bge_softc *sc; 1028 { 1029 int i; 1030 1031 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1032 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1033 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1034 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1035 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1036 sc->bge_cdata.bge_rx_std_dmamap[i]); 1037 } 1038 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1039 sizeof(struct bge_rx_bd)); 1040 } 1041 1042 return; 1043 } 1044 1045 static int 1046 bge_init_rx_ring_jumbo(sc) 1047 struct bge_softc *sc; 1048 { 1049 int i; 1050 struct bge_rcb *rcb; 1051 1052 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1053 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1054 return(ENOBUFS); 1055 }; 1056 1057 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1058 sc->bge_cdata.bge_rx_jumbo_ring_map, 1059 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1060 1061 sc->bge_jumbo = i - 1; 1062 1063 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1064 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1065 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1066 1067 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1068 1069 return(0); 1070 } 1071 1072 static void 1073 bge_free_rx_ring_jumbo(sc) 1074 struct bge_softc *sc; 1075 { 1076 int i; 1077 1078 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1079 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1080 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1081 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1082 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1083 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1084 } 1085 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1086 sizeof(struct bge_rx_bd)); 1087 } 1088 1089 return; 1090 } 1091 1092 static void 1093 bge_free_tx_ring(sc) 1094 struct bge_softc *sc; 1095 { 1096 int i; 1097 1098 if (sc->bge_ldata.bge_tx_ring == NULL) 1099 return; 1100 1101 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1102 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1103 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1104 sc->bge_cdata.bge_tx_chain[i] = NULL; 1105 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1106 sc->bge_cdata.bge_tx_dmamap[i]); 1107 } 1108 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1109 sizeof(struct bge_tx_bd)); 1110 } 1111 1112 return; 1113 } 1114 1115 static int 1116 bge_init_tx_ring(sc) 1117 struct bge_softc *sc; 1118 { 1119 sc->bge_txcnt = 0; 1120 sc->bge_tx_saved_considx = 0; 1121 1122 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1123 /* 5700 b2 errata */ 1124 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1125 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1126 1127 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1128 /* 5700 b2 errata */ 1129 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1130 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1131 1132 return(0); 1133 } 1134 1135 #define BGE_POLY 0xEDB88320 1136 1137 static uint32_t 1138 bge_mchash(addr) 1139 const uint8_t *addr; 1140 { 1141 uint32_t crc; 1142 int idx, bit; 1143 uint8_t data; 1144 1145 /* Compute CRC for the address value. */ 1146 crc = 0xFFFFFFFF; /* initial value */ 1147 1148 for (idx = 0; idx < 6; idx++) { 1149 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1150 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1151 } 1152 1153 return(crc & 0x7F); 1154 } 1155 1156 static void 1157 bge_setmulti(sc) 1158 struct bge_softc *sc; 1159 { 1160 struct ifnet *ifp; 1161 struct ifmultiaddr *ifma; 1162 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1163 int h, i; 1164 1165 BGE_LOCK_ASSERT(sc); 1166 1167 ifp = &sc->arpcom.ac_if; 1168 1169 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1170 for (i = 0; i < 4; i++) 1171 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1172 return; 1173 } 1174 1175 /* First, zot all the existing filters. */ 1176 for (i = 0; i < 4; i++) 1177 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1178 1179 /* Now program new ones. */ 1180 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1181 if (ifma->ifma_addr->sa_family != AF_LINK) 1182 continue; 1183 h = bge_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1184 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1185 } 1186 1187 for (i = 0; i < 4; i++) 1188 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1189 1190 return; 1191 } 1192 1193 /* 1194 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1195 * self-test results. 1196 */ 1197 static int 1198 bge_chipinit(sc) 1199 struct bge_softc *sc; 1200 { 1201 int i; 1202 u_int32_t dma_rw_ctl; 1203 1204 /* Set endianness before we access any non-PCI registers. */ 1205 #if BYTE_ORDER == BIG_ENDIAN 1206 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1207 BGE_BIGENDIAN_INIT, 4); 1208 #else 1209 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1210 BGE_LITTLEENDIAN_INIT, 4); 1211 #endif 1212 1213 /* 1214 * Check the 'ROM failed' bit on the RX CPU to see if 1215 * self-tests passed. 1216 */ 1217 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1218 printf("bge%d: RX CPU self-diagnostics failed!\n", 1219 sc->bge_unit); 1220 return(ENODEV); 1221 } 1222 1223 /* Clear the MAC control register */ 1224 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1225 1226 /* 1227 * Clear the MAC statistics block in the NIC's 1228 * internal memory. 1229 */ 1230 for (i = BGE_STATS_BLOCK; 1231 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1232 BGE_MEMWIN_WRITE(sc, i, 0); 1233 1234 for (i = BGE_STATUS_BLOCK; 1235 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1236 BGE_MEMWIN_WRITE(sc, i, 0); 1237 1238 /* Set up the PCI DMA control register. */ 1239 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1240 BGE_PCISTATE_PCI_BUSMODE) { 1241 /* Conventional PCI bus */ 1242 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1243 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1244 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1245 (0x0F); 1246 } else { 1247 /* PCI-X bus */ 1248 /* 1249 * The 5704 uses a different encoding of read/write 1250 * watermarks. 1251 */ 1252 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1253 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1254 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1255 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1256 else 1257 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1258 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1259 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1260 (0x0F); 1261 1262 /* 1263 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1264 * for hardware bugs. 1265 */ 1266 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1267 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1268 u_int32_t tmp; 1269 1270 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1271 if (tmp == 0x6 || tmp == 0x7) 1272 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1273 } 1274 } 1275 1276 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1277 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1278 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1279 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1280 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1281 1282 /* 1283 * Set up general mode register. 1284 */ 1285 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1286 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1287 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1288 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1289 1290 /* 1291 * Disable memory write invalidate. Apparently it is not supported 1292 * properly by these devices. 1293 */ 1294 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1295 1296 #ifdef __brokenalpha__ 1297 /* 1298 * Must insure that we do not cross an 8K (bytes) boundary 1299 * for DMA reads. Our highest limit is 1K bytes. This is a 1300 * restriction on some ALPHA platforms with early revision 1301 * 21174 PCI chipsets, such as the AlphaPC 164lx 1302 */ 1303 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1304 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1305 #endif 1306 1307 /* Set the timer prescaler (always 66Mhz) */ 1308 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1309 1310 return(0); 1311 } 1312 1313 static int 1314 bge_blockinit(sc) 1315 struct bge_softc *sc; 1316 { 1317 struct bge_rcb *rcb; 1318 volatile struct bge_rcb *vrcb; 1319 int i; 1320 1321 /* 1322 * Initialize the memory window pointer register so that 1323 * we can access the first 32K of internal NIC RAM. This will 1324 * allow us to set up the TX send ring RCBs and the RX return 1325 * ring RCBs, plus other things which live in NIC memory. 1326 */ 1327 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1328 1329 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1330 1331 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1332 /* Configure mbuf memory pool */ 1333 if (sc->bge_extram) { 1334 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1335 BGE_EXT_SSRAM); 1336 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1337 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1338 else 1339 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1340 } else { 1341 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1342 BGE_BUFFPOOL_1); 1343 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1344 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1345 else 1346 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1347 } 1348 1349 /* Configure DMA resource pool */ 1350 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1351 BGE_DMA_DESCRIPTORS); 1352 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1353 } 1354 1355 /* Configure mbuf pool watermarks */ 1356 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1357 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1358 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1359 } else { 1360 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1361 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1362 } 1363 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1364 1365 /* Configure DMA resource watermarks */ 1366 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1367 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1368 1369 /* Enable buffer manager */ 1370 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1371 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1372 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1373 1374 /* Poll for buffer manager start indication */ 1375 for (i = 0; i < BGE_TIMEOUT; i++) { 1376 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1377 break; 1378 DELAY(10); 1379 } 1380 1381 if (i == BGE_TIMEOUT) { 1382 printf("bge%d: buffer manager failed to start\n", 1383 sc->bge_unit); 1384 return(ENXIO); 1385 } 1386 } 1387 1388 /* Enable flow-through queues */ 1389 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1390 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1391 1392 /* Wait until queue initialization is complete */ 1393 for (i = 0; i < BGE_TIMEOUT; i++) { 1394 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1395 break; 1396 DELAY(10); 1397 } 1398 1399 if (i == BGE_TIMEOUT) { 1400 printf("bge%d: flow-through queue init failed\n", 1401 sc->bge_unit); 1402 return(ENXIO); 1403 } 1404 1405 /* Initialize the standard RX ring control block */ 1406 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1407 rcb->bge_hostaddr.bge_addr_lo = 1408 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1409 rcb->bge_hostaddr.bge_addr_hi = 1410 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1411 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1412 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1413 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1414 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1415 else 1416 rcb->bge_maxlen_flags = 1417 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1418 if (sc->bge_extram) 1419 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1420 else 1421 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1422 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1423 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1424 1425 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1426 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1427 1428 /* 1429 * Initialize the jumbo RX ring control block 1430 * We set the 'ring disabled' bit in the flags 1431 * field until we're actually ready to start 1432 * using this ring (i.e. once we set the MTU 1433 * high enough to require it). 1434 */ 1435 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1436 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1437 1438 rcb->bge_hostaddr.bge_addr_lo = 1439 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1440 rcb->bge_hostaddr.bge_addr_hi = 1441 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1442 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1443 sc->bge_cdata.bge_rx_jumbo_ring_map, 1444 BUS_DMASYNC_PREREAD); 1445 rcb->bge_maxlen_flags = 1446 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1447 BGE_RCB_FLAG_RING_DISABLED); 1448 if (sc->bge_extram) 1449 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1450 else 1451 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1452 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1453 rcb->bge_hostaddr.bge_addr_hi); 1454 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1455 rcb->bge_hostaddr.bge_addr_lo); 1456 1457 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1458 rcb->bge_maxlen_flags); 1459 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1460 1461 /* Set up dummy disabled mini ring RCB */ 1462 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1463 rcb->bge_maxlen_flags = 1464 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1465 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1466 rcb->bge_maxlen_flags); 1467 } 1468 1469 /* 1470 * Set the BD ring replentish thresholds. The recommended 1471 * values are 1/8th the number of descriptors allocated to 1472 * each ring. 1473 */ 1474 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1475 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1476 1477 /* 1478 * Disable all unused send rings by setting the 'ring disabled' 1479 * bit in the flags field of all the TX send ring control blocks. 1480 * These are located in NIC memory. 1481 */ 1482 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1483 BGE_SEND_RING_RCB); 1484 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1485 vrcb->bge_maxlen_flags = 1486 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1487 vrcb->bge_nicaddr = 0; 1488 vrcb++; 1489 } 1490 1491 /* Configure TX RCB 0 (we use only the first ring) */ 1492 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1493 BGE_SEND_RING_RCB); 1494 vrcb->bge_hostaddr.bge_addr_lo = 1495 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr)); 1496 vrcb->bge_hostaddr.bge_addr_hi = 1497 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr)); 1498 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1499 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1500 vrcb->bge_maxlen_flags = 1501 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1502 1503 /* Disable all unused RX return rings */ 1504 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1505 BGE_RX_RETURN_RING_RCB); 1506 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1507 vrcb->bge_hostaddr.bge_addr_hi = 0; 1508 vrcb->bge_hostaddr.bge_addr_lo = 0; 1509 vrcb->bge_maxlen_flags = 1510 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1511 BGE_RCB_FLAG_RING_DISABLED); 1512 vrcb->bge_nicaddr = 0; 1513 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1514 (i * (sizeof(u_int64_t))), 0); 1515 vrcb++; 1516 } 1517 1518 /* Initialize RX ring indexes */ 1519 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1520 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1521 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1522 1523 /* 1524 * Set up RX return ring 0 1525 * Note that the NIC address for RX return rings is 0x00000000. 1526 * The return rings live entirely within the host, so the 1527 * nicaddr field in the RCB isn't used. 1528 */ 1529 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1530 BGE_RX_RETURN_RING_RCB); 1531 vrcb->bge_hostaddr.bge_addr_lo = 1532 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr); 1533 vrcb->bge_hostaddr.bge_addr_hi = 1534 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr); 1535 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 1536 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 1537 vrcb->bge_nicaddr = 0x00000000; 1538 vrcb->bge_maxlen_flags = 1539 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1540 1541 /* Set random backoff seed for TX */ 1542 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1543 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1544 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1545 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1546 BGE_TX_BACKOFF_SEED_MASK); 1547 1548 /* Set inter-packet gap */ 1549 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1550 1551 /* 1552 * Specify which ring to use for packets that don't match 1553 * any RX rules. 1554 */ 1555 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1556 1557 /* 1558 * Configure number of RX lists. One interrupt distribution 1559 * list, sixteen active lists, one bad frames class. 1560 */ 1561 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1562 1563 /* Inialize RX list placement stats mask. */ 1564 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1565 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1566 1567 /* Disable host coalescing until we get it set up */ 1568 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1569 1570 /* Poll to make sure it's shut down. */ 1571 for (i = 0; i < BGE_TIMEOUT; i++) { 1572 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1573 break; 1574 DELAY(10); 1575 } 1576 1577 if (i == BGE_TIMEOUT) { 1578 printf("bge%d: host coalescing engine failed to idle\n", 1579 sc->bge_unit); 1580 return(ENXIO); 1581 } 1582 1583 /* Set up host coalescing defaults */ 1584 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1585 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1586 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1587 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1588 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1589 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1590 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1591 } 1592 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1593 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1594 1595 /* Set up address of statistics block */ 1596 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1597 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1598 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1599 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1600 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1601 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1602 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1603 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1604 } 1605 1606 /* Set up address of status block */ 1607 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1608 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1609 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1610 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1611 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1612 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 1613 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1614 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1615 1616 /* Turn on host coalescing state machine */ 1617 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1618 1619 /* Turn on RX BD completion state machine and enable attentions */ 1620 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1621 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1622 1623 /* Turn on RX list placement state machine */ 1624 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1625 1626 /* Turn on RX list selector state machine. */ 1627 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1628 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1629 1630 /* Turn on DMA, clear stats */ 1631 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1632 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1633 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1634 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1635 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1636 1637 /* Set misc. local control, enable interrupts on attentions */ 1638 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1639 1640 #ifdef notdef 1641 /* Assert GPIO pins for PHY reset */ 1642 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1643 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1644 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1645 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1646 #endif 1647 1648 /* Turn on DMA completion state machine */ 1649 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1650 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1651 1652 /* Turn on write DMA state machine */ 1653 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1654 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1655 1656 /* Turn on read DMA state machine */ 1657 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1658 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1659 1660 /* Turn on RX data completion state machine */ 1661 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1662 1663 /* Turn on RX BD initiator state machine */ 1664 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1665 1666 /* Turn on RX data and RX BD initiator state machine */ 1667 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1668 1669 /* Turn on Mbuf cluster free state machine */ 1670 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1671 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1672 1673 /* Turn on send BD completion state machine */ 1674 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1675 1676 /* Turn on send data completion state machine */ 1677 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1678 1679 /* Turn on send data initiator state machine */ 1680 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1681 1682 /* Turn on send BD initiator state machine */ 1683 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1684 1685 /* Turn on send BD selector state machine */ 1686 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1687 1688 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1689 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1690 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1691 1692 /* ack/clear link change events */ 1693 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1694 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1695 BGE_MACSTAT_LINK_CHANGED); 1696 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1697 1698 /* Enable PHY auto polling (for MII/GMII only) */ 1699 if (sc->bge_tbi) { 1700 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1701 } else { 1702 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1703 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1704 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1705 BGE_EVTENB_MI_INTERRUPT); 1706 } 1707 1708 /* Enable link state change attentions. */ 1709 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1710 1711 return(0); 1712 } 1713 1714 /* 1715 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1716 * against our list and return its name if we find a match. Note 1717 * that since the Broadcom controller contains VPD support, we 1718 * can get the device name string from the controller itself instead 1719 * of the compiled-in string. This is a little slow, but it guarantees 1720 * we'll always announce the right product name. 1721 */ 1722 static int 1723 bge_probe(dev) 1724 device_t dev; 1725 { 1726 struct bge_type *t; 1727 struct bge_softc *sc; 1728 char *descbuf; 1729 1730 t = bge_devs; 1731 1732 sc = device_get_softc(dev); 1733 bzero(sc, sizeof(struct bge_softc)); 1734 sc->bge_unit = device_get_unit(dev); 1735 sc->bge_dev = dev; 1736 1737 while(t->bge_name != NULL) { 1738 if ((pci_get_vendor(dev) == t->bge_vid) && 1739 (pci_get_device(dev) == t->bge_did)) { 1740 #ifdef notdef 1741 bge_vpd_read(sc); 1742 device_set_desc(dev, sc->bge_vpd_prodname); 1743 #endif 1744 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1745 if (descbuf == NULL) 1746 return(ENOMEM); 1747 snprintf(descbuf, BGE_DEVDESC_MAX, 1748 "%s, ASIC rev. %#04x", t->bge_name, 1749 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1750 device_set_desc_copy(dev, descbuf); 1751 if (pci_get_subvendor(dev) == DELL_VENDORID) 1752 sc->bge_no_3_led = 1; 1753 free(descbuf, M_TEMP); 1754 return(0); 1755 } 1756 t++; 1757 } 1758 1759 return(ENXIO); 1760 } 1761 1762 static void 1763 bge_dma_free(sc) 1764 struct bge_softc *sc; 1765 { 1766 int i; 1767 1768 1769 /* Destroy DMA maps for RX buffers */ 1770 1771 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1772 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1773 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1774 sc->bge_cdata.bge_rx_std_dmamap[i]); 1775 } 1776 1777 /* Destroy DMA maps for jumbo RX buffers */ 1778 1779 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1780 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1781 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1782 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1783 } 1784 1785 /* Destroy DMA maps for TX buffers */ 1786 1787 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1788 if (sc->bge_cdata.bge_tx_dmamap[i]) 1789 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1790 sc->bge_cdata.bge_tx_dmamap[i]); 1791 } 1792 1793 if (sc->bge_cdata.bge_mtag) 1794 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1795 1796 1797 /* Destroy standard RX ring */ 1798 1799 if (sc->bge_ldata.bge_rx_std_ring) 1800 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1801 sc->bge_ldata.bge_rx_std_ring, 1802 sc->bge_cdata.bge_rx_std_ring_map); 1803 1804 if (sc->bge_cdata.bge_rx_std_ring_map) { 1805 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1806 sc->bge_cdata.bge_rx_std_ring_map); 1807 bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag, 1808 sc->bge_cdata.bge_rx_std_ring_map); 1809 } 1810 1811 if (sc->bge_cdata.bge_rx_std_ring_tag) 1812 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1813 1814 /* Destroy jumbo RX ring */ 1815 1816 if (sc->bge_ldata.bge_rx_jumbo_ring) 1817 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1818 sc->bge_ldata.bge_rx_jumbo_ring, 1819 sc->bge_cdata.bge_rx_jumbo_ring_map); 1820 1821 if (sc->bge_cdata.bge_rx_jumbo_ring_map) { 1822 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1823 sc->bge_cdata.bge_rx_jumbo_ring_map); 1824 bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1825 sc->bge_cdata.bge_rx_jumbo_ring_map); 1826 } 1827 1828 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1829 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1830 1831 /* Destroy RX return ring */ 1832 1833 if (sc->bge_ldata.bge_rx_return_ring) 1834 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1835 sc->bge_ldata.bge_rx_return_ring, 1836 sc->bge_cdata.bge_rx_return_ring_map); 1837 1838 if (sc->bge_cdata.bge_rx_return_ring_map) { 1839 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1840 sc->bge_cdata.bge_rx_return_ring_map); 1841 bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag, 1842 sc->bge_cdata.bge_rx_return_ring_map); 1843 } 1844 1845 if (sc->bge_cdata.bge_rx_return_ring_tag) 1846 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1847 1848 /* Destroy TX ring */ 1849 1850 if (sc->bge_ldata.bge_tx_ring) 1851 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1852 sc->bge_ldata.bge_tx_ring, 1853 sc->bge_cdata.bge_tx_ring_map); 1854 1855 if (sc->bge_cdata.bge_tx_ring_map) { 1856 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1857 sc->bge_cdata.bge_tx_ring_map); 1858 bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag, 1859 sc->bge_cdata.bge_tx_ring_map); 1860 } 1861 1862 if (sc->bge_cdata.bge_tx_ring_tag) 1863 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1864 1865 /* Destroy status block */ 1866 1867 if (sc->bge_ldata.bge_status_block) 1868 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1869 sc->bge_ldata.bge_status_block, 1870 sc->bge_cdata.bge_status_map); 1871 1872 if (sc->bge_cdata.bge_status_map) { 1873 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1874 sc->bge_cdata.bge_status_map); 1875 bus_dmamap_destroy(sc->bge_cdata.bge_status_tag, 1876 sc->bge_cdata.bge_status_map); 1877 } 1878 1879 if (sc->bge_cdata.bge_status_tag) 1880 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1881 1882 /* Destroy statistics block */ 1883 1884 if (sc->bge_ldata.bge_stats) 1885 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1886 sc->bge_ldata.bge_stats, 1887 sc->bge_cdata.bge_stats_map); 1888 1889 if (sc->bge_cdata.bge_stats_map) { 1890 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1891 sc->bge_cdata.bge_stats_map); 1892 bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag, 1893 sc->bge_cdata.bge_stats_map); 1894 } 1895 1896 if (sc->bge_cdata.bge_stats_tag) 1897 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1898 1899 /* Destroy the parent tag */ 1900 1901 if (sc->bge_cdata.bge_parent_tag) 1902 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1903 1904 return; 1905 } 1906 1907 static int 1908 bge_dma_alloc(dev) 1909 device_t dev; 1910 { 1911 struct bge_softc *sc; 1912 int nseg, i, error; 1913 struct bge_dmamap_arg ctx; 1914 1915 sc = device_get_softc(dev); 1916 1917 /* 1918 * Allocate the parent bus DMA tag appropriate for PCI. 1919 */ 1920 #define BGE_NSEG_NEW 32 1921 error = bus_dma_tag_create(NULL, /* parent */ 1922 PAGE_SIZE, 0, /* alignment, boundary */ 1923 BUS_SPACE_MAXADDR, /* lowaddr */ 1924 BUS_SPACE_MAXADDR_32BIT,/* highaddr */ 1925 NULL, NULL, /* filter, filterarg */ 1926 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1927 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1928 BUS_DMA_ALLOCNOW, /* flags */ 1929 NULL, NULL, /* lockfunc, lockarg */ 1930 &sc->bge_cdata.bge_parent_tag); 1931 1932 /* 1933 * Create tag for RX mbufs. 1934 */ 1935 nseg = 32; 1936 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, ETHER_ALIGN, 1937 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1938 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, 1939 &sc->bge_cdata.bge_mtag); 1940 1941 if (error) { 1942 device_printf(dev, "could not allocate dma tag\n"); 1943 return (ENOMEM); 1944 } 1945 1946 /* Create DMA maps for RX buffers */ 1947 1948 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1949 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1950 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1951 if (error) { 1952 device_printf(dev, "can't create DMA map for RX\n"); 1953 return(ENOMEM); 1954 } 1955 } 1956 1957 /* Create DMA maps for TX buffers */ 1958 1959 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1960 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1961 &sc->bge_cdata.bge_tx_dmamap[i]); 1962 if (error) { 1963 device_printf(dev, "can't create DMA map for RX\n"); 1964 return(ENOMEM); 1965 } 1966 } 1967 1968 /* Create tag for standard RX ring */ 1969 1970 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1971 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1972 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1973 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1974 1975 if (error) { 1976 device_printf(dev, "could not allocate dma tag\n"); 1977 return (ENOMEM); 1978 } 1979 1980 /* Allocate DMA'able memory for standard RX ring */ 1981 1982 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1983 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1984 &sc->bge_cdata.bge_rx_std_ring_map); 1985 if (error) 1986 return (ENOMEM); 1987 1988 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1989 1990 /* Load the address of the standard RX ring */ 1991 1992 ctx.bge_maxsegs = 1; 1993 ctx.sc = sc; 1994 1995 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1996 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1997 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1998 1999 if (error) 2000 return (ENOMEM); 2001 2002 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2003 2004 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2005 2006 /* 2007 * Create tag for jumbo mbufs. 2008 * This is really a bit of a kludge. We allocate a special 2009 * jumbo buffer pool which (thanks to the way our DMA 2010 * memory allocation works) will consist of contiguous 2011 * pages. This means that even though a jumbo buffer might 2012 * be larger than a page size, we don't really need to 2013 * map it into more than one DMA segment. However, the 2014 * default mbuf tag will result in multi-segment mappings, 2015 * so we have to create a special jumbo mbuf tag that 2016 * lets us get away with mapping the jumbo buffers as 2017 * a single segment. I think eventually the driver should 2018 * be changed so that it uses ordinary mbufs and cluster 2019 * buffers, i.e. jumbo frames can span multiple DMA 2020 * descriptors. But that's a project for another day. 2021 */ 2022 2023 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2024 ETHER_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2025 NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL, 2026 &sc->bge_cdata.bge_mtag_jumbo); 2027 2028 if (error) { 2029 device_printf(dev, "could not allocate dma tag\n"); 2030 return (ENOMEM); 2031 } 2032 2033 /* Create tag for jumbo RX ring */ 2034 2035 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2036 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2037 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2038 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2039 2040 if (error) { 2041 device_printf(dev, "could not allocate dma tag\n"); 2042 return (ENOMEM); 2043 } 2044 2045 /* Allocate DMA'able memory for jumbo RX ring */ 2046 2047 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2048 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT, 2049 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2050 if (error) 2051 return (ENOMEM); 2052 2053 bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring, 2054 BGE_JUMBO_RX_RING_SZ); 2055 2056 /* Load the address of the jumbo RX ring */ 2057 2058 ctx.bge_maxsegs = 1; 2059 ctx.sc = sc; 2060 2061 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2062 sc->bge_cdata.bge_rx_jumbo_ring_map, 2063 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2064 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2065 2066 if (error) 2067 return (ENOMEM); 2068 2069 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2070 2071 /* Create DMA maps for jumbo RX buffers */ 2072 2073 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2074 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2075 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2076 if (error) { 2077 device_printf(dev, 2078 "can't create DMA map for RX\n"); 2079 return(ENOMEM); 2080 } 2081 } 2082 2083 } 2084 2085 /* Create tag for RX return ring */ 2086 2087 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2088 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2089 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2090 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2091 2092 if (error) { 2093 device_printf(dev, "could not allocate dma tag\n"); 2094 return (ENOMEM); 2095 } 2096 2097 /* Allocate DMA'able memory for RX return ring */ 2098 2099 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2100 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2101 &sc->bge_cdata.bge_rx_return_ring_map); 2102 if (error) 2103 return (ENOMEM); 2104 2105 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2106 BGE_RX_RTN_RING_SZ(sc)); 2107 2108 /* Load the address of the RX return ring */ 2109 2110 ctx.bge_maxsegs = 1; 2111 ctx.sc = sc; 2112 2113 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2114 sc->bge_cdata.bge_rx_return_ring_map, 2115 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2116 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2117 2118 if (error) 2119 return (ENOMEM); 2120 2121 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2122 2123 /* Create tag for TX ring */ 2124 2125 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2126 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2127 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2128 &sc->bge_cdata.bge_tx_ring_tag); 2129 2130 if (error) { 2131 device_printf(dev, "could not allocate dma tag\n"); 2132 return (ENOMEM); 2133 } 2134 2135 /* Allocate DMA'able memory for TX ring */ 2136 2137 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2138 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2139 &sc->bge_cdata.bge_tx_ring_map); 2140 if (error) 2141 return (ENOMEM); 2142 2143 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2144 2145 /* Load the address of the TX ring */ 2146 2147 ctx.bge_maxsegs = 1; 2148 ctx.sc = sc; 2149 2150 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2151 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2152 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2153 2154 if (error) 2155 return (ENOMEM); 2156 2157 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2158 2159 /* Create tag for status block */ 2160 2161 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2162 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2163 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2164 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2165 2166 if (error) { 2167 device_printf(dev, "could not allocate dma tag\n"); 2168 return (ENOMEM); 2169 } 2170 2171 /* Allocate DMA'able memory for status block */ 2172 2173 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2174 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2175 &sc->bge_cdata.bge_status_map); 2176 if (error) 2177 return (ENOMEM); 2178 2179 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2180 2181 /* Load the address of the status block */ 2182 2183 ctx.sc = sc; 2184 ctx.bge_maxsegs = 1; 2185 2186 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2187 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2188 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2189 2190 if (error) 2191 return (ENOMEM); 2192 2193 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2194 2195 /* Create tag for statistics block */ 2196 2197 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2198 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2199 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2200 &sc->bge_cdata.bge_stats_tag); 2201 2202 if (error) { 2203 device_printf(dev, "could not allocate dma tag\n"); 2204 return (ENOMEM); 2205 } 2206 2207 /* Allocate DMA'able memory for statistics block */ 2208 2209 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2210 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2211 &sc->bge_cdata.bge_stats_map); 2212 if (error) 2213 return (ENOMEM); 2214 2215 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2216 2217 /* Load the address of the statstics block */ 2218 2219 ctx.sc = sc; 2220 ctx.bge_maxsegs = 1; 2221 2222 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2223 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2224 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2225 2226 if (error) 2227 return (ENOMEM); 2228 2229 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2230 2231 return(0); 2232 } 2233 2234 static int 2235 bge_attach(dev) 2236 device_t dev; 2237 { 2238 struct ifnet *ifp; 2239 struct bge_softc *sc; 2240 u_int32_t hwcfg = 0; 2241 u_int32_t mac_addr = 0; 2242 int unit, error = 0, rid; 2243 2244 sc = device_get_softc(dev); 2245 unit = device_get_unit(dev); 2246 sc->bge_dev = dev; 2247 sc->bge_unit = unit; 2248 2249 /* 2250 * Map control/status registers. 2251 */ 2252 pci_enable_busmaster(dev); 2253 2254 rid = BGE_PCI_BAR0; 2255 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2256 RF_ACTIVE|PCI_RF_DENSE); 2257 2258 if (sc->bge_res == NULL) { 2259 printf ("bge%d: couldn't map memory\n", unit); 2260 error = ENXIO; 2261 goto fail; 2262 } 2263 2264 sc->bge_btag = rman_get_bustag(sc->bge_res); 2265 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2266 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 2267 2268 /* Allocate interrupt */ 2269 rid = 0; 2270 2271 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2272 RF_SHAREABLE | RF_ACTIVE); 2273 2274 if (sc->bge_irq == NULL) { 2275 printf("bge%d: couldn't map interrupt\n", unit); 2276 error = ENXIO; 2277 goto fail; 2278 } 2279 2280 sc->bge_unit = unit; 2281 2282 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2283 2284 /* Try to reset the chip. */ 2285 bge_reset(sc); 2286 2287 if (bge_chipinit(sc)) { 2288 printf("bge%d: chip initialization failed\n", sc->bge_unit); 2289 bge_release_resources(sc); 2290 error = ENXIO; 2291 goto fail; 2292 } 2293 2294 /* 2295 * Get station address from the EEPROM. 2296 */ 2297 mac_addr = bge_readmem_ind(sc, 0x0c14); 2298 if ((mac_addr >> 16) == 0x484b) { 2299 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2300 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2301 mac_addr = bge_readmem_ind(sc, 0x0c18); 2302 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2303 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2304 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2305 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2306 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2307 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2308 printf("bge%d: failed to read station address\n", unit); 2309 bge_release_resources(sc); 2310 error = ENXIO; 2311 goto fail; 2312 } 2313 2314 /* Save ASIC rev. */ 2315 2316 sc->bge_chipid = 2317 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2318 BGE_PCIMISCCTL_ASICREV; 2319 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2320 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2321 2322 /* 5705 limits RX return ring to 512 entries. */ 2323 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2324 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2325 else 2326 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2327 2328 if (bge_dma_alloc(dev)) { 2329 printf ("bge%d: failed to allocate DMA resources\n", 2330 sc->bge_unit); 2331 bge_release_resources(sc); 2332 error = ENXIO; 2333 goto fail; 2334 } 2335 2336 /* 2337 * Try to allocate memory for jumbo buffers. 2338 * The 5705 does not appear to support jumbo frames. 2339 */ 2340 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2341 if (bge_alloc_jumbo_mem(sc)) { 2342 printf("bge%d: jumbo buffer allocation " 2343 "failed\n", sc->bge_unit); 2344 bge_release_resources(sc); 2345 error = ENXIO; 2346 goto fail; 2347 } 2348 } 2349 2350 /* Set default tuneable values. */ 2351 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2352 sc->bge_rx_coal_ticks = 150; 2353 sc->bge_tx_coal_ticks = 150; 2354 sc->bge_rx_max_coal_bds = 64; 2355 sc->bge_tx_max_coal_bds = 128; 2356 2357 /* Set up ifnet structure */ 2358 ifp = &sc->arpcom.ac_if; 2359 ifp->if_softc = sc; 2360 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2361 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2362 ifp->if_ioctl = bge_ioctl; 2363 ifp->if_start = bge_start; 2364 ifp->if_watchdog = bge_watchdog; 2365 ifp->if_init = bge_init; 2366 ifp->if_mtu = ETHERMTU; 2367 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 2368 ifp->if_hwassist = BGE_CSUM_FEATURES; 2369 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2370 IFCAP_VLAN_MTU; 2371 ifp->if_capenable = ifp->if_capabilities; 2372 2373 /* 2374 * Figure out what sort of media we have by checking the 2375 * hardware config word in the first 32k of NIC internal memory, 2376 * or fall back to examining the EEPROM if necessary. 2377 * Note: on some BCM5700 cards, this value appears to be unset. 2378 * If that's the case, we have to rely on identifying the NIC 2379 * by its PCI subsystem ID, as we do below for the SysKonnect 2380 * SK-9D41. 2381 */ 2382 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2383 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2384 else { 2385 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2386 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2387 hwcfg = ntohl(hwcfg); 2388 } 2389 2390 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2391 sc->bge_tbi = 1; 2392 2393 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2394 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2395 sc->bge_tbi = 1; 2396 2397 if (sc->bge_tbi) { 2398 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2399 bge_ifmedia_upd, bge_ifmedia_sts); 2400 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2401 ifmedia_add(&sc->bge_ifmedia, 2402 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2403 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2404 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2405 } else { 2406 /* 2407 * Do transceiver setup. 2408 */ 2409 if (mii_phy_probe(dev, &sc->bge_miibus, 2410 bge_ifmedia_upd, bge_ifmedia_sts)) { 2411 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 2412 bge_release_resources(sc); 2413 bge_free_jumbo_mem(sc); 2414 error = ENXIO; 2415 goto fail; 2416 } 2417 } 2418 2419 /* 2420 * When using the BCM5701 in PCI-X mode, data corruption has 2421 * been observed in the first few bytes of some received packets. 2422 * Aligning the packet buffer in memory eliminates the corruption. 2423 * Unfortunately, this misaligns the packet payloads. On platforms 2424 * which do not support unaligned accesses, we will realign the 2425 * payloads by copying the received packets. 2426 */ 2427 switch (sc->bge_chipid) { 2428 case BGE_CHIPID_BCM5701_A0: 2429 case BGE_CHIPID_BCM5701_B0: 2430 case BGE_CHIPID_BCM5701_B2: 2431 case BGE_CHIPID_BCM5701_B5: 2432 /* If in PCI-X mode, work around the alignment bug. */ 2433 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2434 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2435 BGE_PCISTATE_PCI_BUSSPEED) 2436 sc->bge_rx_alignment_bug = 1; 2437 break; 2438 } 2439 2440 /* 2441 * Call MI attach routine. 2442 */ 2443 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2444 callout_init(&sc->bge_stat_ch, CALLOUT_MPSAFE); 2445 2446 /* 2447 * Hookup IRQ last. 2448 */ 2449 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2450 bge_intr, sc, &sc->bge_intrhand); 2451 2452 if (error) { 2453 bge_release_resources(sc); 2454 printf("bge%d: couldn't set up irq\n", unit); 2455 } 2456 2457 fail: 2458 return(error); 2459 } 2460 2461 static int 2462 bge_detach(dev) 2463 device_t dev; 2464 { 2465 struct bge_softc *sc; 2466 struct ifnet *ifp; 2467 2468 sc = device_get_softc(dev); 2469 ifp = &sc->arpcom.ac_if; 2470 2471 BGE_LOCK(sc); 2472 bge_stop(sc); 2473 bge_reset(sc); 2474 BGE_UNLOCK(sc); 2475 2476 ether_ifdetach(ifp); 2477 2478 if (sc->bge_tbi) { 2479 ifmedia_removeall(&sc->bge_ifmedia); 2480 } else { 2481 bus_generic_detach(dev); 2482 device_delete_child(dev, sc->bge_miibus); 2483 } 2484 2485 bge_release_resources(sc); 2486 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2487 bge_free_jumbo_mem(sc); 2488 2489 return(0); 2490 } 2491 2492 static void 2493 bge_release_resources(sc) 2494 struct bge_softc *sc; 2495 { 2496 device_t dev; 2497 2498 dev = sc->bge_dev; 2499 2500 if (sc->bge_vpd_prodname != NULL) 2501 free(sc->bge_vpd_prodname, M_DEVBUF); 2502 2503 if (sc->bge_vpd_readonly != NULL) 2504 free(sc->bge_vpd_readonly, M_DEVBUF); 2505 2506 if (sc->bge_intrhand != NULL) 2507 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2508 2509 if (sc->bge_irq != NULL) 2510 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 2511 2512 if (sc->bge_res != NULL) 2513 bus_release_resource(dev, SYS_RES_MEMORY, 2514 BGE_PCI_BAR0, sc->bge_res); 2515 2516 bge_dma_free(sc); 2517 2518 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 2519 BGE_LOCK_DESTROY(sc); 2520 2521 return; 2522 } 2523 2524 static void 2525 bge_reset(sc) 2526 struct bge_softc *sc; 2527 { 2528 device_t dev; 2529 u_int32_t cachesize, command, pcistate; 2530 int i, val = 0; 2531 2532 dev = sc->bge_dev; 2533 2534 /* Save some important PCI state. */ 2535 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2536 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2537 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2538 2539 pci_write_config(dev, BGE_PCI_MISC_CTL, 2540 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2541 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2542 2543 /* Issue global reset */ 2544 bge_writereg_ind(sc, BGE_MISC_CFG, 2545 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2546 2547 DELAY(1000); 2548 2549 /* Reset some of the PCI state that got zapped by reset */ 2550 pci_write_config(dev, BGE_PCI_MISC_CTL, 2551 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2552 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2553 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2554 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2555 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2556 2557 /* Enable memory arbiter. */ 2558 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2559 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2560 2561 /* 2562 * Prevent PXE restart: write a magic number to the 2563 * general communications memory at 0xB50. 2564 */ 2565 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2566 /* 2567 * Poll the value location we just wrote until 2568 * we see the 1's complement of the magic number. 2569 * This indicates that the firmware initialization 2570 * is complete. 2571 */ 2572 for (i = 0; i < BGE_TIMEOUT; i++) { 2573 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2574 if (val == ~BGE_MAGIC_NUMBER) 2575 break; 2576 DELAY(10); 2577 } 2578 2579 if (i == BGE_TIMEOUT) { 2580 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2581 return; 2582 } 2583 2584 /* 2585 * XXX Wait for the value of the PCISTATE register to 2586 * return to its original pre-reset state. This is a 2587 * fairly good indicator of reset completion. If we don't 2588 * wait for the reset to fully complete, trying to read 2589 * from the device's non-PCI registers may yield garbage 2590 * results. 2591 */ 2592 for (i = 0; i < BGE_TIMEOUT; i++) { 2593 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2594 break; 2595 DELAY(10); 2596 } 2597 2598 /* Fix up byte swapping */ 2599 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2600 BGE_MODECTL_BYTESWAP_DATA); 2601 2602 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2603 2604 DELAY(10000); 2605 2606 return; 2607 } 2608 2609 /* 2610 * Frame reception handling. This is called if there's a frame 2611 * on the receive return list. 2612 * 2613 * Note: we have to be able to handle two possibilities here: 2614 * 1) the frame is from the jumbo recieve ring 2615 * 2) the frame is from the standard receive ring 2616 */ 2617 2618 static void 2619 bge_rxeof(sc) 2620 struct bge_softc *sc; 2621 { 2622 struct ifnet *ifp; 2623 int stdcnt = 0, jumbocnt = 0; 2624 2625 BGE_LOCK_ASSERT(sc); 2626 2627 ifp = &sc->arpcom.ac_if; 2628 2629 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2630 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE); 2631 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2632 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2633 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2634 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2635 sc->bge_cdata.bge_rx_jumbo_ring_map, 2636 BUS_DMASYNC_POSTREAD); 2637 } 2638 2639 while(sc->bge_rx_saved_considx != 2640 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2641 struct bge_rx_bd *cur_rx; 2642 u_int32_t rxidx; 2643 struct ether_header *eh; 2644 struct mbuf *m = NULL; 2645 u_int16_t vlan_tag = 0; 2646 int have_tag = 0; 2647 2648 cur_rx = 2649 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2650 2651 rxidx = cur_rx->bge_idx; 2652 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2653 2654 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2655 have_tag = 1; 2656 vlan_tag = cur_rx->bge_vlan_tag; 2657 } 2658 2659 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2660 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2661 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2662 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2663 BUS_DMASYNC_POSTREAD); 2664 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2665 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2666 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2667 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2668 jumbocnt++; 2669 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2670 ifp->if_ierrors++; 2671 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2672 continue; 2673 } 2674 if (bge_newbuf_jumbo(sc, 2675 sc->bge_jumbo, NULL) == ENOBUFS) { 2676 ifp->if_ierrors++; 2677 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2678 continue; 2679 } 2680 } else { 2681 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2682 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2683 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2684 BUS_DMASYNC_POSTREAD); 2685 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2686 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2687 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2688 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2689 stdcnt++; 2690 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2691 ifp->if_ierrors++; 2692 bge_newbuf_std(sc, sc->bge_std, m); 2693 continue; 2694 } 2695 if (bge_newbuf_std(sc, sc->bge_std, 2696 NULL) == ENOBUFS) { 2697 ifp->if_ierrors++; 2698 bge_newbuf_std(sc, sc->bge_std, m); 2699 continue; 2700 } 2701 } 2702 2703 ifp->if_ipackets++; 2704 #ifndef __i386__ 2705 /* 2706 * The i386 allows unaligned accesses, but for other 2707 * platforms we must make sure the payload is aligned. 2708 */ 2709 if (sc->bge_rx_alignment_bug) { 2710 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2711 cur_rx->bge_len); 2712 m->m_data += ETHER_ALIGN; 2713 } 2714 #endif 2715 eh = mtod(m, struct ether_header *); 2716 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2717 m->m_pkthdr.rcvif = ifp; 2718 2719 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2720 if (ifp->if_hwassist) { 2721 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2722 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2723 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2724 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2725 m->m_pkthdr.csum_data = 2726 cur_rx->bge_tcp_udp_csum; 2727 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2728 } 2729 } 2730 #endif 2731 2732 /* 2733 * If we received a packet with a vlan tag, 2734 * attach that information to the packet. 2735 */ 2736 if (have_tag) 2737 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2738 2739 BGE_UNLOCK(sc); 2740 (*ifp->if_input)(ifp, m); 2741 BGE_LOCK(sc); 2742 } 2743 2744 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2745 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 2746 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2747 sc->bge_cdata.bge_rx_std_ring_map, 2748 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE); 2749 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2750 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2751 sc->bge_cdata.bge_rx_jumbo_ring_map, 2752 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2753 } 2754 2755 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2756 if (stdcnt) 2757 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2758 if (jumbocnt) 2759 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2760 2761 return; 2762 } 2763 2764 static void 2765 bge_txeof(sc) 2766 struct bge_softc *sc; 2767 { 2768 struct bge_tx_bd *cur_tx = NULL; 2769 struct ifnet *ifp; 2770 2771 BGE_LOCK_ASSERT(sc); 2772 2773 ifp = &sc->arpcom.ac_if; 2774 2775 /* 2776 * Go through our tx ring and free mbufs for those 2777 * frames that have been sent. 2778 */ 2779 while (sc->bge_tx_saved_considx != 2780 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 2781 u_int32_t idx = 0; 2782 2783 idx = sc->bge_tx_saved_considx; 2784 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 2785 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2786 ifp->if_opackets++; 2787 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2788 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2789 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2790 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2791 sc->bge_cdata.bge_tx_dmamap[idx]); 2792 } 2793 sc->bge_txcnt--; 2794 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2795 ifp->if_timer = 0; 2796 } 2797 2798 if (cur_tx != NULL) 2799 ifp->if_flags &= ~IFF_OACTIVE; 2800 2801 return; 2802 } 2803 2804 static void 2805 bge_intr(xsc) 2806 void *xsc; 2807 { 2808 struct bge_softc *sc; 2809 struct ifnet *ifp; 2810 u_int32_t statusword; 2811 u_int32_t status; 2812 2813 sc = xsc; 2814 ifp = &sc->arpcom.ac_if; 2815 2816 BGE_LOCK(sc); 2817 2818 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2819 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE); 2820 2821 statusword = 2822 atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status); 2823 2824 #ifdef notdef 2825 /* Avoid this for now -- checking this register is expensive. */ 2826 /* Make sure this is really our interrupt. */ 2827 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2828 return; 2829 #endif 2830 /* Ack interrupt and stop others from occuring. */ 2831 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2832 2833 /* 2834 * Process link state changes. 2835 * Grrr. The link status word in the status block does 2836 * not work correctly on the BCM5700 rev AX and BX chips, 2837 * according to all available information. Hence, we have 2838 * to enable MII interrupts in order to properly obtain 2839 * async link changes. Unfortunately, this also means that 2840 * we have to read the MAC status register to detect link 2841 * changes, thereby adding an additional register access to 2842 * the interrupt handler. 2843 */ 2844 2845 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2846 2847 status = CSR_READ_4(sc, BGE_MAC_STS); 2848 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2849 sc->bge_link = 0; 2850 callout_stop(&sc->bge_stat_ch); 2851 bge_tick_locked(sc); 2852 /* Clear the interrupt */ 2853 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2854 BGE_EVTENB_MI_INTERRUPT); 2855 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2856 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2857 BRGPHY_INTRS); 2858 } 2859 } else { 2860 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2861 /* 2862 * Sometimes PCS encoding errors are detected in 2863 * TBI mode (on fiber NICs), and for some reason 2864 * the chip will signal them as link changes. 2865 * If we get a link change event, but the 'PCS 2866 * encoding error' bit in the MAC status register 2867 * is set, don't bother doing a link check. 2868 * This avoids spurious "gigabit link up" messages 2869 * that sometimes appear on fiber NICs during 2870 * periods of heavy traffic. (There should be no 2871 * effect on copper NICs.) 2872 */ 2873 status = CSR_READ_4(sc, BGE_MAC_STS); 2874 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2875 BGE_MACSTAT_MI_COMPLETE))) { 2876 sc->bge_link = 0; 2877 callout_stop(&sc->bge_stat_ch); 2878 bge_tick_locked(sc); 2879 } 2880 /* Clear the interrupt */ 2881 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2882 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2883 BGE_MACSTAT_LINK_CHANGED); 2884 2885 /* Force flush the status block cached by PCI bridge */ 2886 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2887 } 2888 } 2889 2890 if (ifp->if_flags & IFF_RUNNING) { 2891 /* Check RX return ring producer/consumer */ 2892 bge_rxeof(sc); 2893 2894 /* Check TX ring producer/consumer */ 2895 bge_txeof(sc); 2896 } 2897 2898 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2899 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 2900 2901 bge_handle_events(sc); 2902 2903 /* Re-enable interrupts. */ 2904 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2905 2906 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2907 bge_start_locked(ifp); 2908 2909 BGE_UNLOCK(sc); 2910 2911 return; 2912 } 2913 2914 static void 2915 bge_tick_locked(sc) 2916 struct bge_softc *sc; 2917 { 2918 struct mii_data *mii = NULL; 2919 struct ifmedia *ifm = NULL; 2920 struct ifnet *ifp; 2921 2922 ifp = &sc->arpcom.ac_if; 2923 2924 BGE_LOCK_ASSERT(sc); 2925 2926 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2927 bge_stats_update_regs(sc); 2928 else 2929 bge_stats_update(sc); 2930 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 2931 if (sc->bge_link) 2932 return; 2933 2934 if (sc->bge_tbi) { 2935 ifm = &sc->bge_ifmedia; 2936 if (CSR_READ_4(sc, BGE_MAC_STS) & 2937 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2938 sc->bge_link++; 2939 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2940 printf("bge%d: gigabit link up\n", sc->bge_unit); 2941 if (ifp->if_snd.ifq_head != NULL) 2942 bge_start_locked(ifp); 2943 } 2944 return; 2945 } 2946 2947 mii = device_get_softc(sc->bge_miibus); 2948 mii_tick(mii); 2949 2950 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2951 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2952 sc->bge_link++; 2953 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2954 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2955 printf("bge%d: gigabit link up\n", 2956 sc->bge_unit); 2957 if (ifp->if_snd.ifq_head != NULL) 2958 bge_start_locked(ifp); 2959 } 2960 2961 return; 2962 } 2963 2964 static void 2965 bge_tick(xsc) 2966 void *xsc; 2967 { 2968 struct bge_softc *sc; 2969 2970 sc = xsc; 2971 2972 BGE_LOCK(sc); 2973 bge_tick_locked(sc); 2974 BGE_UNLOCK(sc); 2975 } 2976 2977 static void 2978 bge_stats_update_regs(sc) 2979 struct bge_softc *sc; 2980 { 2981 struct ifnet *ifp; 2982 struct bge_mac_stats_regs stats; 2983 u_int32_t *s; 2984 int i; 2985 2986 ifp = &sc->arpcom.ac_if; 2987 2988 s = (u_int32_t *)&stats; 2989 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2990 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2991 s++; 2992 } 2993 2994 ifp->if_collisions += 2995 (stats.dot3StatsSingleCollisionFrames + 2996 stats.dot3StatsMultipleCollisionFrames + 2997 stats.dot3StatsExcessiveCollisions + 2998 stats.dot3StatsLateCollisions) - 2999 ifp->if_collisions; 3000 3001 return; 3002 } 3003 3004 static void 3005 bge_stats_update(sc) 3006 struct bge_softc *sc; 3007 { 3008 struct ifnet *ifp; 3009 struct bge_stats *stats; 3010 3011 ifp = &sc->arpcom.ac_if; 3012 3013 stats = (struct bge_stats *)(sc->bge_vhandle + 3014 BGE_MEMWIN_START + BGE_STATS_BLOCK); 3015 3016 ifp->if_collisions += 3017 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 3018 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 3019 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 3020 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 3021 ifp->if_collisions; 3022 3023 #ifdef notdef 3024 ifp->if_collisions += 3025 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3026 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3027 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3028 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3029 ifp->if_collisions; 3030 #endif 3031 3032 return; 3033 } 3034 3035 /* 3036 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3037 * pointers to descriptors. 3038 */ 3039 static int 3040 bge_encap(sc, m_head, txidx) 3041 struct bge_softc *sc; 3042 struct mbuf *m_head; 3043 u_int32_t *txidx; 3044 { 3045 struct bge_tx_bd *f = NULL; 3046 u_int16_t csum_flags = 0; 3047 struct m_tag *mtag; 3048 struct bge_dmamap_arg ctx; 3049 bus_dmamap_t map; 3050 int error; 3051 3052 3053 if (m_head->m_pkthdr.csum_flags) { 3054 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3055 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3056 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3057 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3058 if (m_head->m_flags & M_LASTFRAG) 3059 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3060 else if (m_head->m_flags & M_FRAG) 3061 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3062 } 3063 3064 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 3065 3066 ctx.sc = sc; 3067 ctx.bge_idx = *txidx; 3068 ctx.bge_ring = sc->bge_ldata.bge_tx_ring; 3069 ctx.bge_flags = csum_flags; 3070 /* 3071 * Sanity check: avoid coming within 16 descriptors 3072 * of the end of the ring. 3073 */ 3074 ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16; 3075 3076 map = sc->bge_cdata.bge_tx_dmamap[*txidx]; 3077 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, 3078 m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT); 3079 3080 if (error || ctx.bge_maxsegs == 0 /*|| 3081 ctx.bge_idx == sc->bge_tx_saved_considx*/) 3082 return (ENOBUFS); 3083 3084 /* 3085 * Insure that the map for this transmission 3086 * is placed at the array index of the last descriptor 3087 * in this chain. 3088 */ 3089 sc->bge_cdata.bge_tx_dmamap[*txidx] = 3090 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx]; 3091 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map; 3092 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head; 3093 sc->bge_txcnt += ctx.bge_maxsegs; 3094 f = &sc->bge_ldata.bge_tx_ring[*txidx]; 3095 if (mtag != NULL) { 3096 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG); 3097 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag)); 3098 } else { 3099 f->bge_vlan_tag = 0; 3100 } 3101 3102 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT); 3103 *txidx = ctx.bge_idx; 3104 3105 return(0); 3106 } 3107 3108 /* 3109 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3110 * to the mbuf data regions directly in the transmit descriptors. 3111 */ 3112 static void 3113 bge_start_locked(ifp) 3114 struct ifnet *ifp; 3115 { 3116 struct bge_softc *sc; 3117 struct mbuf *m_head = NULL; 3118 u_int32_t prodidx = 0; 3119 3120 sc = ifp->if_softc; 3121 3122 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3123 return; 3124 3125 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3126 3127 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3128 IF_DEQUEUE(&ifp->if_snd, m_head); 3129 if (m_head == NULL) 3130 break; 3131 3132 /* 3133 * XXX 3134 * safety overkill. If this is a fragmented packet chain 3135 * with delayed TCP/UDP checksums, then only encapsulate 3136 * it if we have enough descriptors to handle the entire 3137 * chain at once. 3138 * (paranoia -- may not actually be needed) 3139 */ 3140 if (m_head->m_flags & M_FIRSTFRAG && 3141 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3142 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3143 m_head->m_pkthdr.csum_data + 16) { 3144 IF_PREPEND(&ifp->if_snd, m_head); 3145 ifp->if_flags |= IFF_OACTIVE; 3146 break; 3147 } 3148 } 3149 3150 /* 3151 * Pack the data into the transmit ring. If we 3152 * don't have room, set the OACTIVE flag and wait 3153 * for the NIC to drain the ring. 3154 */ 3155 if (bge_encap(sc, m_head, &prodidx)) { 3156 IF_PREPEND(&ifp->if_snd, m_head); 3157 ifp->if_flags |= IFF_OACTIVE; 3158 break; 3159 } 3160 3161 /* 3162 * If there's a BPF listener, bounce a copy of this frame 3163 * to him. 3164 */ 3165 BPF_MTAP(ifp, m_head); 3166 } 3167 3168 /* Transmit */ 3169 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3170 /* 5700 b2 errata */ 3171 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3172 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3173 3174 /* 3175 * Set a timeout in case the chip goes out to lunch. 3176 */ 3177 ifp->if_timer = 5; 3178 3179 return; 3180 } 3181 3182 /* 3183 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3184 * to the mbuf data regions directly in the transmit descriptors. 3185 */ 3186 static void 3187 bge_start(ifp) 3188 struct ifnet *ifp; 3189 { 3190 struct bge_softc *sc; 3191 3192 sc = ifp->if_softc; 3193 BGE_LOCK(sc); 3194 bge_start_locked(ifp); 3195 BGE_UNLOCK(sc); 3196 } 3197 3198 static void 3199 bge_init_locked(sc) 3200 struct bge_softc *sc; 3201 { 3202 struct ifnet *ifp; 3203 u_int16_t *m; 3204 3205 BGE_LOCK_ASSERT(sc); 3206 3207 ifp = &sc->arpcom.ac_if; 3208 3209 if (ifp->if_flags & IFF_RUNNING) 3210 return; 3211 3212 /* Cancel pending I/O and flush buffers. */ 3213 bge_stop(sc); 3214 bge_reset(sc); 3215 bge_chipinit(sc); 3216 3217 /* 3218 * Init the various state machines, ring 3219 * control blocks and firmware. 3220 */ 3221 if (bge_blockinit(sc)) { 3222 printf("bge%d: initialization failure\n", sc->bge_unit); 3223 return; 3224 } 3225 3226 ifp = &sc->arpcom.ac_if; 3227 3228 /* Specify MTU. */ 3229 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3230 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3231 3232 /* Load our MAC address. */ 3233 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3234 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3235 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3236 3237 /* Enable or disable promiscuous mode as needed. */ 3238 if (ifp->if_flags & IFF_PROMISC) { 3239 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3240 } else { 3241 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3242 } 3243 3244 /* Program multicast filter. */ 3245 bge_setmulti(sc); 3246 3247 /* Init RX ring. */ 3248 bge_init_rx_ring_std(sc); 3249 3250 /* 3251 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3252 * memory to insure that the chip has in fact read the first 3253 * entry of the ring. 3254 */ 3255 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3256 u_int32_t v, i; 3257 for (i = 0; i < 10; i++) { 3258 DELAY(20); 3259 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3260 if (v == (MCLBYTES - ETHER_ALIGN)) 3261 break; 3262 } 3263 if (i == 10) 3264 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 3265 sc->bge_unit); 3266 } 3267 3268 /* Init jumbo RX ring. */ 3269 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3270 bge_init_rx_ring_jumbo(sc); 3271 3272 /* Init our RX return ring index */ 3273 sc->bge_rx_saved_considx = 0; 3274 3275 /* Init TX ring. */ 3276 bge_init_tx_ring(sc); 3277 3278 /* Turn on transmitter */ 3279 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3280 3281 /* Turn on receiver */ 3282 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3283 3284 /* Tell firmware we're alive. */ 3285 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3286 3287 /* Enable host interrupts. */ 3288 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3289 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3290 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3291 3292 bge_ifmedia_upd(ifp); 3293 3294 ifp->if_flags |= IFF_RUNNING; 3295 ifp->if_flags &= ~IFF_OACTIVE; 3296 3297 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3298 3299 return; 3300 } 3301 3302 static void 3303 bge_init(xsc) 3304 void *xsc; 3305 { 3306 struct bge_softc *sc = xsc; 3307 3308 BGE_LOCK(sc); 3309 bge_init_locked(sc); 3310 BGE_UNLOCK(sc); 3311 3312 return; 3313 } 3314 3315 /* 3316 * Set media options. 3317 */ 3318 static int 3319 bge_ifmedia_upd(ifp) 3320 struct ifnet *ifp; 3321 { 3322 struct bge_softc *sc; 3323 struct mii_data *mii; 3324 struct ifmedia *ifm; 3325 3326 sc = ifp->if_softc; 3327 ifm = &sc->bge_ifmedia; 3328 3329 /* If this is a 1000baseX NIC, enable the TBI port. */ 3330 if (sc->bge_tbi) { 3331 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3332 return(EINVAL); 3333 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3334 case IFM_AUTO: 3335 break; 3336 case IFM_1000_SX: 3337 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3338 BGE_CLRBIT(sc, BGE_MAC_MODE, 3339 BGE_MACMODE_HALF_DUPLEX); 3340 } else { 3341 BGE_SETBIT(sc, BGE_MAC_MODE, 3342 BGE_MACMODE_HALF_DUPLEX); 3343 } 3344 break; 3345 default: 3346 return(EINVAL); 3347 } 3348 return(0); 3349 } 3350 3351 mii = device_get_softc(sc->bge_miibus); 3352 sc->bge_link = 0; 3353 if (mii->mii_instance) { 3354 struct mii_softc *miisc; 3355 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3356 miisc = LIST_NEXT(miisc, mii_list)) 3357 mii_phy_reset(miisc); 3358 } 3359 mii_mediachg(mii); 3360 3361 return(0); 3362 } 3363 3364 /* 3365 * Report current media status. 3366 */ 3367 static void 3368 bge_ifmedia_sts(ifp, ifmr) 3369 struct ifnet *ifp; 3370 struct ifmediareq *ifmr; 3371 { 3372 struct bge_softc *sc; 3373 struct mii_data *mii; 3374 3375 sc = ifp->if_softc; 3376 3377 if (sc->bge_tbi) { 3378 ifmr->ifm_status = IFM_AVALID; 3379 ifmr->ifm_active = IFM_ETHER; 3380 if (CSR_READ_4(sc, BGE_MAC_STS) & 3381 BGE_MACSTAT_TBI_PCS_SYNCHED) 3382 ifmr->ifm_status |= IFM_ACTIVE; 3383 ifmr->ifm_active |= IFM_1000_SX; 3384 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3385 ifmr->ifm_active |= IFM_HDX; 3386 else 3387 ifmr->ifm_active |= IFM_FDX; 3388 return; 3389 } 3390 3391 mii = device_get_softc(sc->bge_miibus); 3392 mii_pollstat(mii); 3393 ifmr->ifm_active = mii->mii_media_active; 3394 ifmr->ifm_status = mii->mii_media_status; 3395 3396 return; 3397 } 3398 3399 static int 3400 bge_ioctl(ifp, command, data) 3401 struct ifnet *ifp; 3402 u_long command; 3403 caddr_t data; 3404 { 3405 struct bge_softc *sc = ifp->if_softc; 3406 struct ifreq *ifr = (struct ifreq *) data; 3407 int mask, error = 0; 3408 struct mii_data *mii; 3409 3410 switch(command) { 3411 case SIOCSIFMTU: 3412 /* Disallow jumbo frames on 5705. */ 3413 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3414 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 3415 error = EINVAL; 3416 else { 3417 ifp->if_mtu = ifr->ifr_mtu; 3418 ifp->if_flags &= ~IFF_RUNNING; 3419 bge_init(sc); 3420 } 3421 break; 3422 case SIOCSIFFLAGS: 3423 BGE_LOCK(sc); 3424 if (ifp->if_flags & IFF_UP) { 3425 /* 3426 * If only the state of the PROMISC flag changed, 3427 * then just use the 'set promisc mode' command 3428 * instead of reinitializing the entire NIC. Doing 3429 * a full re-init means reloading the firmware and 3430 * waiting for it to start up, which may take a 3431 * second or two. 3432 */ 3433 if (ifp->if_flags & IFF_RUNNING && 3434 ifp->if_flags & IFF_PROMISC && 3435 !(sc->bge_if_flags & IFF_PROMISC)) { 3436 BGE_SETBIT(sc, BGE_RX_MODE, 3437 BGE_RXMODE_RX_PROMISC); 3438 } else if (ifp->if_flags & IFF_RUNNING && 3439 !(ifp->if_flags & IFF_PROMISC) && 3440 sc->bge_if_flags & IFF_PROMISC) { 3441 BGE_CLRBIT(sc, BGE_RX_MODE, 3442 BGE_RXMODE_RX_PROMISC); 3443 } else 3444 bge_init_locked(sc); 3445 } else { 3446 if (ifp->if_flags & IFF_RUNNING) { 3447 bge_stop(sc); 3448 } 3449 } 3450 sc->bge_if_flags = ifp->if_flags; 3451 BGE_UNLOCK(sc); 3452 error = 0; 3453 break; 3454 case SIOCADDMULTI: 3455 case SIOCDELMULTI: 3456 if (ifp->if_flags & IFF_RUNNING) { 3457 BGE_LOCK(sc); 3458 bge_setmulti(sc); 3459 BGE_UNLOCK(sc); 3460 error = 0; 3461 } 3462 break; 3463 case SIOCSIFMEDIA: 3464 case SIOCGIFMEDIA: 3465 if (sc->bge_tbi) { 3466 error = ifmedia_ioctl(ifp, ifr, 3467 &sc->bge_ifmedia, command); 3468 } else { 3469 mii = device_get_softc(sc->bge_miibus); 3470 error = ifmedia_ioctl(ifp, ifr, 3471 &mii->mii_media, command); 3472 } 3473 break; 3474 case SIOCSIFCAP: 3475 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3476 if (mask & IFCAP_HWCSUM) { 3477 if (IFCAP_HWCSUM & ifp->if_capenable) 3478 ifp->if_capenable &= ~IFCAP_HWCSUM; 3479 else 3480 ifp->if_capenable |= IFCAP_HWCSUM; 3481 } 3482 error = 0; 3483 break; 3484 default: 3485 error = ether_ioctl(ifp, command, data); 3486 break; 3487 } 3488 3489 return(error); 3490 } 3491 3492 static void 3493 bge_watchdog(ifp) 3494 struct ifnet *ifp; 3495 { 3496 struct bge_softc *sc; 3497 3498 sc = ifp->if_softc; 3499 3500 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 3501 3502 ifp->if_flags &= ~IFF_RUNNING; 3503 bge_init(sc); 3504 3505 ifp->if_oerrors++; 3506 3507 return; 3508 } 3509 3510 /* 3511 * Stop the adapter and free any mbufs allocated to the 3512 * RX and TX lists. 3513 */ 3514 static void 3515 bge_stop(sc) 3516 struct bge_softc *sc; 3517 { 3518 struct ifnet *ifp; 3519 struct ifmedia_entry *ifm; 3520 struct mii_data *mii = NULL; 3521 int mtmp, itmp; 3522 3523 BGE_LOCK_ASSERT(sc); 3524 3525 ifp = &sc->arpcom.ac_if; 3526 3527 if (!sc->bge_tbi) 3528 mii = device_get_softc(sc->bge_miibus); 3529 3530 callout_stop(&sc->bge_stat_ch); 3531 3532 /* 3533 * Disable all of the receiver blocks 3534 */ 3535 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3536 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3537 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3538 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3539 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3540 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3541 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3542 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3543 3544 /* 3545 * Disable all of the transmit blocks 3546 */ 3547 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3548 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3549 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3550 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3551 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3552 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3553 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3554 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3555 3556 /* 3557 * Shut down all of the memory managers and related 3558 * state machines. 3559 */ 3560 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3561 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3562 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3563 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3564 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3565 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3566 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 3567 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3568 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3569 } 3570 3571 /* Disable host interrupts. */ 3572 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3573 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3574 3575 /* 3576 * Tell firmware we're shutting down. 3577 */ 3578 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3579 3580 /* Free the RX lists. */ 3581 bge_free_rx_ring_std(sc); 3582 3583 /* Free jumbo RX list. */ 3584 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3585 bge_free_rx_ring_jumbo(sc); 3586 3587 /* Free TX buffers. */ 3588 bge_free_tx_ring(sc); 3589 3590 /* 3591 * Isolate/power down the PHY, but leave the media selection 3592 * unchanged so that things will be put back to normal when 3593 * we bring the interface back up. 3594 */ 3595 if (!sc->bge_tbi) { 3596 itmp = ifp->if_flags; 3597 ifp->if_flags |= IFF_UP; 3598 ifm = mii->mii_media.ifm_cur; 3599 mtmp = ifm->ifm_media; 3600 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3601 mii_mediachg(mii); 3602 ifm->ifm_media = mtmp; 3603 ifp->if_flags = itmp; 3604 } 3605 3606 sc->bge_link = 0; 3607 3608 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3609 3610 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3611 3612 return; 3613 } 3614 3615 /* 3616 * Stop all chip I/O so that the kernel's probe routines don't 3617 * get confused by errant DMAs when rebooting. 3618 */ 3619 static void 3620 bge_shutdown(dev) 3621 device_t dev; 3622 { 3623 struct bge_softc *sc; 3624 3625 sc = device_get_softc(dev); 3626 3627 BGE_LOCK(sc); 3628 bge_stop(sc); 3629 bge_reset(sc); 3630 BGE_UNLOCK(sc); 3631 3632 return; 3633 } 3634