1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 218 219 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 220 221 { TC_VENDORID, TC_DEVICEID_3C996 }, 222 223 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 224 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 225 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 226 227 { 0, 0 } 228 }; 229 230 static const struct bge_vendor { 231 uint16_t v_id; 232 const char *v_name; 233 } bge_vendors[] = { 234 { ALTEON_VENDORID, "Alteon" }, 235 { ALTIMA_VENDORID, "Altima" }, 236 { APPLE_VENDORID, "Apple" }, 237 { BCOM_VENDORID, "Broadcom" }, 238 { SK_VENDORID, "SysKonnect" }, 239 { TC_VENDORID, "3Com" }, 240 { FJTSU_VENDORID, "Fujitsu" }, 241 242 { 0, NULL } 243 }; 244 245 static const struct bge_revision { 246 uint32_t br_chipid; 247 const char *br_name; 248 } bge_revisions[] = { 249 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 250 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 251 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 252 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 253 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 254 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 255 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 256 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 257 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 258 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 259 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 260 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 261 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 262 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 263 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 264 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 265 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 266 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 267 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 268 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 269 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 270 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 271 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 272 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 273 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 274 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 275 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 276 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 277 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 278 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 279 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 280 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 281 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 282 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 283 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 284 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 285 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 286 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 287 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 288 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 289 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 290 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 291 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 292 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 293 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 294 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 295 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 296 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 297 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 298 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 299 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 302 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 303 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 304 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 305 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 306 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 307 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 308 309 { 0, NULL } 310 }; 311 312 /* 313 * Some defaults for major revisions, so that newer steppings 314 * that we don't know about have a shot at working. 315 */ 316 static const struct bge_revision bge_majorrevs[] = { 317 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 318 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 319 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 320 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 321 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 322 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 323 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 324 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 325 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 326 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 327 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 328 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 329 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 330 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 331 /* 5754 and 5787 share the same ASIC ID */ 332 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 333 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 334 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 335 336 { 0, NULL } 337 }; 338 339 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 340 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 341 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 342 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 343 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 344 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 345 346 const struct bge_revision * bge_lookup_rev(uint32_t); 347 const struct bge_vendor * bge_lookup_vendor(uint16_t); 348 349 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 350 351 static int bge_probe(device_t); 352 static int bge_attach(device_t); 353 static int bge_detach(device_t); 354 static int bge_suspend(device_t); 355 static int bge_resume(device_t); 356 static void bge_release_resources(struct bge_softc *); 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 358 static int bge_dma_alloc(struct bge_softc *); 359 static void bge_dma_free(struct bge_softc *); 360 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 361 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 362 363 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 364 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 365 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 366 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 367 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 368 369 static void bge_txeof(struct bge_softc *, uint16_t); 370 static int bge_rxeof(struct bge_softc *, uint16_t, int); 371 372 static void bge_asf_driver_up (struct bge_softc *); 373 static void bge_tick(void *); 374 static void bge_stats_clear_regs(struct bge_softc *); 375 static void bge_stats_update(struct bge_softc *); 376 static void bge_stats_update_regs(struct bge_softc *); 377 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 378 uint16_t *); 379 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 380 381 static void bge_intr(void *); 382 static int bge_msi_intr(void *); 383 static void bge_intr_task(void *, int); 384 static void bge_start_locked(struct ifnet *); 385 static void bge_start(struct ifnet *); 386 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 387 static void bge_init_locked(struct bge_softc *); 388 static void bge_init(void *); 389 static void bge_stop(struct bge_softc *); 390 static void bge_watchdog(struct bge_softc *); 391 static int bge_shutdown(device_t); 392 static int bge_ifmedia_upd_locked(struct ifnet *); 393 static int bge_ifmedia_upd(struct ifnet *); 394 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 395 396 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 397 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 398 399 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 400 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 401 402 static void bge_setpromisc(struct bge_softc *); 403 static void bge_setmulti(struct bge_softc *); 404 static void bge_setvlan(struct bge_softc *); 405 406 static __inline void bge_rxreuse_std(struct bge_softc *, int); 407 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 408 static int bge_newbuf_std(struct bge_softc *, int); 409 static int bge_newbuf_jumbo(struct bge_softc *, int); 410 static int bge_init_rx_ring_std(struct bge_softc *); 411 static void bge_free_rx_ring_std(struct bge_softc *); 412 static int bge_init_rx_ring_jumbo(struct bge_softc *); 413 static void bge_free_rx_ring_jumbo(struct bge_softc *); 414 static void bge_free_tx_ring(struct bge_softc *); 415 static int bge_init_tx_ring(struct bge_softc *); 416 417 static int bge_chipinit(struct bge_softc *); 418 static int bge_blockinit(struct bge_softc *); 419 420 static int bge_has_eaddr(struct bge_softc *); 421 static uint32_t bge_readmem_ind(struct bge_softc *, int); 422 static void bge_writemem_ind(struct bge_softc *, int, int); 423 static void bge_writembx(struct bge_softc *, int, int); 424 #ifdef notdef 425 static uint32_t bge_readreg_ind(struct bge_softc *, int); 426 #endif 427 static void bge_writemem_direct(struct bge_softc *, int, int); 428 static void bge_writereg_ind(struct bge_softc *, int, int); 429 430 static int bge_miibus_readreg(device_t, int, int); 431 static int bge_miibus_writereg(device_t, int, int, int); 432 static void bge_miibus_statchg(device_t); 433 #ifdef DEVICE_POLLING 434 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 435 #endif 436 437 #define BGE_RESET_START 1 438 #define BGE_RESET_STOP 2 439 static void bge_sig_post_reset(struct bge_softc *, int); 440 static void bge_sig_legacy(struct bge_softc *, int); 441 static void bge_sig_pre_reset(struct bge_softc *, int); 442 static void bge_stop_fw(struct bge_softc *); 443 static int bge_reset(struct bge_softc *); 444 static void bge_link_upd(struct bge_softc *); 445 446 /* 447 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 448 * leak information to untrusted users. It is also known to cause alignment 449 * traps on certain architectures. 450 */ 451 #ifdef BGE_REGISTER_DEBUG 452 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 453 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 454 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 455 #endif 456 static void bge_add_sysctls(struct bge_softc *); 457 static void bge_add_sysctl_stats_regs(struct bge_softc *, 458 struct sysctl_ctx_list *, struct sysctl_oid_list *); 459 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 460 struct sysctl_oid_list *); 461 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 462 463 static device_method_t bge_methods[] = { 464 /* Device interface */ 465 DEVMETHOD(device_probe, bge_probe), 466 DEVMETHOD(device_attach, bge_attach), 467 DEVMETHOD(device_detach, bge_detach), 468 DEVMETHOD(device_shutdown, bge_shutdown), 469 DEVMETHOD(device_suspend, bge_suspend), 470 DEVMETHOD(device_resume, bge_resume), 471 472 /* bus interface */ 473 DEVMETHOD(bus_print_child, bus_generic_print_child), 474 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 475 476 /* MII interface */ 477 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 478 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 479 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 480 481 { 0, 0 } 482 }; 483 484 static driver_t bge_driver = { 485 "bge", 486 bge_methods, 487 sizeof(struct bge_softc) 488 }; 489 490 static devclass_t bge_devclass; 491 492 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 493 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 494 495 static int bge_allow_asf = 1; 496 497 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 498 499 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 500 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 501 "Allow ASF mode if available"); 502 503 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 504 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 505 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 506 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 507 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 508 509 static int 510 bge_has_eaddr(struct bge_softc *sc) 511 { 512 #ifdef __sparc64__ 513 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 514 device_t dev; 515 uint32_t subvendor; 516 517 dev = sc->bge_dev; 518 519 /* 520 * The on-board BGEs found in sun4u machines aren't fitted with 521 * an EEPROM which means that we have to obtain the MAC address 522 * via OFW and that some tests will always fail. We distinguish 523 * such BGEs by the subvendor ID, which also has to be obtained 524 * from OFW instead of the PCI configuration space as the latter 525 * indicates Broadcom as the subvendor of the netboot interface. 526 * For early Blade 1500 and 2500 we even have to check the OFW 527 * device path as the subvendor ID always defaults to Broadcom 528 * there. 529 */ 530 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 531 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 532 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 533 return (0); 534 memset(buf, 0, sizeof(buf)); 535 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 536 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 537 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 538 return (0); 539 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 540 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 541 return (0); 542 } 543 #endif 544 return (1); 545 } 546 547 static uint32_t 548 bge_readmem_ind(struct bge_softc *sc, int off) 549 { 550 device_t dev; 551 uint32_t val; 552 553 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 554 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 555 return (0); 556 557 dev = sc->bge_dev; 558 559 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 560 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 561 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 562 return (val); 563 } 564 565 static void 566 bge_writemem_ind(struct bge_softc *sc, int off, int val) 567 { 568 device_t dev; 569 570 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 571 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 572 return; 573 574 dev = sc->bge_dev; 575 576 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 577 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 578 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 579 } 580 581 #ifdef notdef 582 static uint32_t 583 bge_readreg_ind(struct bge_softc *sc, int off) 584 { 585 device_t dev; 586 587 dev = sc->bge_dev; 588 589 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 590 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 591 } 592 #endif 593 594 static void 595 bge_writereg_ind(struct bge_softc *sc, int off, int val) 596 { 597 device_t dev; 598 599 dev = sc->bge_dev; 600 601 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 602 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 603 } 604 605 static void 606 bge_writemem_direct(struct bge_softc *sc, int off, int val) 607 { 608 CSR_WRITE_4(sc, off, val); 609 } 610 611 static void 612 bge_writembx(struct bge_softc *sc, int off, int val) 613 { 614 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 615 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 616 617 CSR_WRITE_4(sc, off, val); 618 } 619 620 /* 621 * Map a single buffer address. 622 */ 623 624 static void 625 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 626 { 627 struct bge_dmamap_arg *ctx; 628 629 if (error) 630 return; 631 632 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 633 634 ctx = arg; 635 ctx->bge_busaddr = segs->ds_addr; 636 } 637 638 static uint8_t 639 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 640 { 641 uint32_t access, byte = 0; 642 int i; 643 644 /* Lock. */ 645 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 646 for (i = 0; i < 8000; i++) { 647 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 648 break; 649 DELAY(20); 650 } 651 if (i == 8000) 652 return (1); 653 654 /* Enable access. */ 655 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 656 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 657 658 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 659 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 660 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 661 DELAY(10); 662 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 663 DELAY(10); 664 break; 665 } 666 } 667 668 if (i == BGE_TIMEOUT * 10) { 669 if_printf(sc->bge_ifp, "nvram read timed out\n"); 670 return (1); 671 } 672 673 /* Get result. */ 674 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 675 676 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 677 678 /* Disable access. */ 679 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 680 681 /* Unlock. */ 682 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 683 CSR_READ_4(sc, BGE_NVRAM_SWARB); 684 685 return (0); 686 } 687 688 /* 689 * Read a sequence of bytes from NVRAM. 690 */ 691 static int 692 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 693 { 694 int err = 0, i; 695 uint8_t byte = 0; 696 697 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 698 return (1); 699 700 for (i = 0; i < cnt; i++) { 701 err = bge_nvram_getbyte(sc, off + i, &byte); 702 if (err) 703 break; 704 *(dest + i) = byte; 705 } 706 707 return (err ? 1 : 0); 708 } 709 710 /* 711 * Read a byte of data stored in the EEPROM at address 'addr.' The 712 * BCM570x supports both the traditional bitbang interface and an 713 * auto access interface for reading the EEPROM. We use the auto 714 * access method. 715 */ 716 static uint8_t 717 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 718 { 719 int i; 720 uint32_t byte = 0; 721 722 /* 723 * Enable use of auto EEPROM access so we can avoid 724 * having to use the bitbang method. 725 */ 726 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 727 728 /* Reset the EEPROM, load the clock period. */ 729 CSR_WRITE_4(sc, BGE_EE_ADDR, 730 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 731 DELAY(20); 732 733 /* Issue the read EEPROM command. */ 734 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 735 736 /* Wait for completion */ 737 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 738 DELAY(10); 739 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 740 break; 741 } 742 743 if (i == BGE_TIMEOUT * 10) { 744 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 745 return (1); 746 } 747 748 /* Get result. */ 749 byte = CSR_READ_4(sc, BGE_EE_DATA); 750 751 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 752 753 return (0); 754 } 755 756 /* 757 * Read a sequence of bytes from the EEPROM. 758 */ 759 static int 760 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 761 { 762 int i, error = 0; 763 uint8_t byte = 0; 764 765 for (i = 0; i < cnt; i++) { 766 error = bge_eeprom_getbyte(sc, off + i, &byte); 767 if (error) 768 break; 769 *(dest + i) = byte; 770 } 771 772 return (error ? 1 : 0); 773 } 774 775 static int 776 bge_miibus_readreg(device_t dev, int phy, int reg) 777 { 778 struct bge_softc *sc; 779 uint32_t val; 780 int i; 781 782 sc = device_get_softc(dev); 783 784 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 785 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 786 CSR_WRITE_4(sc, BGE_MI_MODE, 787 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 788 DELAY(80); 789 } 790 791 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 792 BGE_MIPHY(phy) | BGE_MIREG(reg)); 793 794 /* Poll for the PHY register access to complete. */ 795 for (i = 0; i < BGE_TIMEOUT; i++) { 796 DELAY(10); 797 val = CSR_READ_4(sc, BGE_MI_COMM); 798 if ((val & BGE_MICOMM_BUSY) == 0) { 799 DELAY(5); 800 val = CSR_READ_4(sc, BGE_MI_COMM); 801 break; 802 } 803 } 804 805 if (i == BGE_TIMEOUT) { 806 device_printf(sc->bge_dev, 807 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 808 phy, reg, val); 809 val = 0; 810 } 811 812 /* Restore the autopoll bit if necessary. */ 813 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 814 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 815 DELAY(80); 816 } 817 818 if (val & BGE_MICOMM_READFAIL) 819 return (0); 820 821 return (val & 0xFFFF); 822 } 823 824 static int 825 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 826 { 827 struct bge_softc *sc; 828 int i; 829 830 sc = device_get_softc(dev); 831 832 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 833 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 834 return (0); 835 836 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 837 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 838 CSR_WRITE_4(sc, BGE_MI_MODE, 839 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 840 DELAY(80); 841 } 842 843 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 844 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 845 846 for (i = 0; i < BGE_TIMEOUT; i++) { 847 DELAY(10); 848 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 849 DELAY(5); 850 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 851 break; 852 } 853 } 854 855 /* Restore the autopoll bit if necessary. */ 856 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 857 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 858 DELAY(80); 859 } 860 861 if (i == BGE_TIMEOUT) 862 device_printf(sc->bge_dev, 863 "PHY write timed out (phy %d, reg %d, val %d)\n", 864 phy, reg, val); 865 866 return (0); 867 } 868 869 static void 870 bge_miibus_statchg(device_t dev) 871 { 872 struct bge_softc *sc; 873 struct mii_data *mii; 874 sc = device_get_softc(dev); 875 mii = device_get_softc(sc->bge_miibus); 876 877 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 878 (IFM_ACTIVE | IFM_AVALID)) { 879 switch (IFM_SUBTYPE(mii->mii_media_active)) { 880 case IFM_10_T: 881 case IFM_100_TX: 882 sc->bge_link = 1; 883 break; 884 case IFM_1000_T: 885 case IFM_1000_SX: 886 case IFM_2500_SX: 887 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 888 sc->bge_link = 1; 889 else 890 sc->bge_link = 0; 891 break; 892 default: 893 sc->bge_link = 0; 894 break; 895 } 896 } else 897 sc->bge_link = 0; 898 if (sc->bge_link == 0) 899 return; 900 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 901 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 902 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 903 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 904 else 905 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 906 907 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 908 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 909 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG1) 910 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 911 else 912 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 913 if (IFM_OPTIONS(mii->mii_media_active) & IFM_FLAG0) 914 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 915 else 916 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 917 } else { 918 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 919 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 920 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 921 } 922 } 923 924 /* 925 * Intialize a standard receive ring descriptor. 926 */ 927 static int 928 bge_newbuf_std(struct bge_softc *sc, int i) 929 { 930 struct mbuf *m; 931 struct bge_rx_bd *r; 932 bus_dma_segment_t segs[1]; 933 bus_dmamap_t map; 934 int error, nsegs; 935 936 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 937 if (m == NULL) 938 return (ENOBUFS); 939 m->m_len = m->m_pkthdr.len = MCLBYTES; 940 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 941 m_adj(m, ETHER_ALIGN); 942 943 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 944 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 945 if (error != 0) { 946 m_freem(m); 947 return (error); 948 } 949 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 950 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 951 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 952 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 953 sc->bge_cdata.bge_rx_std_dmamap[i]); 954 } 955 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 956 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 957 sc->bge_cdata.bge_rx_std_sparemap = map; 958 sc->bge_cdata.bge_rx_std_chain[i] = m; 959 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 960 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 961 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 962 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 963 r->bge_flags = BGE_RXBDFLAG_END; 964 r->bge_len = segs[0].ds_len; 965 r->bge_idx = i; 966 967 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 968 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 969 970 return (0); 971 } 972 973 /* 974 * Initialize a jumbo receive ring descriptor. This allocates 975 * a jumbo buffer from the pool managed internally by the driver. 976 */ 977 static int 978 bge_newbuf_jumbo(struct bge_softc *sc, int i) 979 { 980 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 981 bus_dmamap_t map; 982 struct bge_extrx_bd *r; 983 struct mbuf *m; 984 int error, nsegs; 985 986 MGETHDR(m, M_DONTWAIT, MT_DATA); 987 if (m == NULL) 988 return (ENOBUFS); 989 990 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 991 if (!(m->m_flags & M_EXT)) { 992 m_freem(m); 993 return (ENOBUFS); 994 } 995 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 996 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 997 m_adj(m, ETHER_ALIGN); 998 999 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1000 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1001 if (error != 0) { 1002 m_freem(m); 1003 return (error); 1004 } 1005 1006 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { 1007 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1008 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1009 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1010 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1011 } 1012 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1013 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1014 sc->bge_cdata.bge_rx_jumbo_sparemap; 1015 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1016 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1017 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1018 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1019 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1020 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1021 1022 /* 1023 * Fill in the extended RX buffer descriptor. 1024 */ 1025 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1026 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1027 r->bge_idx = i; 1028 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1029 switch (nsegs) { 1030 case 4: 1031 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1032 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1033 r->bge_len3 = segs[3].ds_len; 1034 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1035 case 3: 1036 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1037 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1038 r->bge_len2 = segs[2].ds_len; 1039 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1040 case 2: 1041 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1042 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1043 r->bge_len1 = segs[1].ds_len; 1044 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1045 case 1: 1046 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1047 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1048 r->bge_len0 = segs[0].ds_len; 1049 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1050 break; 1051 default: 1052 panic("%s: %d segments\n", __func__, nsegs); 1053 } 1054 1055 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1056 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1057 1058 return (0); 1059 } 1060 1061 static int 1062 bge_init_rx_ring_std(struct bge_softc *sc) 1063 { 1064 int error, i; 1065 1066 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1067 sc->bge_std = 0; 1068 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1069 if ((error = bge_newbuf_std(sc, i)) != 0) 1070 return (error); 1071 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1072 } 1073 1074 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1075 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1076 1077 sc->bge_std = 0; 1078 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1079 1080 return (0); 1081 } 1082 1083 static void 1084 bge_free_rx_ring_std(struct bge_softc *sc) 1085 { 1086 int i; 1087 1088 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1089 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1090 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1091 sc->bge_cdata.bge_rx_std_dmamap[i], 1092 BUS_DMASYNC_POSTREAD); 1093 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1094 sc->bge_cdata.bge_rx_std_dmamap[i]); 1095 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1096 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1097 } 1098 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1099 sizeof(struct bge_rx_bd)); 1100 } 1101 } 1102 1103 static int 1104 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1105 { 1106 struct bge_rcb *rcb; 1107 int error, i; 1108 1109 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1110 sc->bge_jumbo = 0; 1111 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1112 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1113 return (error); 1114 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1115 } 1116 1117 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1118 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1119 1120 sc->bge_jumbo = 0; 1121 1122 /* Enable the jumbo receive producer ring. */ 1123 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1124 rcb->bge_maxlen_flags = 1125 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1126 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1127 1128 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1129 1130 return (0); 1131 } 1132 1133 static void 1134 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1135 { 1136 int i; 1137 1138 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1139 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1140 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1141 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1142 BUS_DMASYNC_POSTREAD); 1143 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1144 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1145 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1146 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1147 } 1148 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1149 sizeof(struct bge_extrx_bd)); 1150 } 1151 } 1152 1153 static void 1154 bge_free_tx_ring(struct bge_softc *sc) 1155 { 1156 int i; 1157 1158 if (sc->bge_ldata.bge_tx_ring == NULL) 1159 return; 1160 1161 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1162 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1163 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1164 sc->bge_cdata.bge_tx_dmamap[i], 1165 BUS_DMASYNC_POSTWRITE); 1166 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1167 sc->bge_cdata.bge_tx_dmamap[i]); 1168 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1169 sc->bge_cdata.bge_tx_chain[i] = NULL; 1170 } 1171 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1172 sizeof(struct bge_tx_bd)); 1173 } 1174 } 1175 1176 static int 1177 bge_init_tx_ring(struct bge_softc *sc) 1178 { 1179 sc->bge_txcnt = 0; 1180 sc->bge_tx_saved_considx = 0; 1181 1182 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1183 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1184 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1185 1186 /* Initialize transmit producer index for host-memory send ring. */ 1187 sc->bge_tx_prodidx = 0; 1188 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1189 1190 /* 5700 b2 errata */ 1191 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1192 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1193 1194 /* NIC-memory send ring not used; initialize to zero. */ 1195 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1196 /* 5700 b2 errata */ 1197 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1198 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1199 1200 return (0); 1201 } 1202 1203 static void 1204 bge_setpromisc(struct bge_softc *sc) 1205 { 1206 struct ifnet *ifp; 1207 1208 BGE_LOCK_ASSERT(sc); 1209 1210 ifp = sc->bge_ifp; 1211 1212 /* Enable or disable promiscuous mode as needed. */ 1213 if (ifp->if_flags & IFF_PROMISC) 1214 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1215 else 1216 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1217 } 1218 1219 static void 1220 bge_setmulti(struct bge_softc *sc) 1221 { 1222 struct ifnet *ifp; 1223 struct ifmultiaddr *ifma; 1224 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1225 int h, i; 1226 1227 BGE_LOCK_ASSERT(sc); 1228 1229 ifp = sc->bge_ifp; 1230 1231 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1232 for (i = 0; i < 4; i++) 1233 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1234 return; 1235 } 1236 1237 /* First, zot all the existing filters. */ 1238 for (i = 0; i < 4; i++) 1239 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1240 1241 /* Now program new ones. */ 1242 if_maddr_rlock(ifp); 1243 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1244 if (ifma->ifma_addr->sa_family != AF_LINK) 1245 continue; 1246 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1247 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1248 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1249 } 1250 if_maddr_runlock(ifp); 1251 1252 for (i = 0; i < 4; i++) 1253 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1254 } 1255 1256 static void 1257 bge_setvlan(struct bge_softc *sc) 1258 { 1259 struct ifnet *ifp; 1260 1261 BGE_LOCK_ASSERT(sc); 1262 1263 ifp = sc->bge_ifp; 1264 1265 /* Enable or disable VLAN tag stripping as needed. */ 1266 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1267 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1268 else 1269 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1270 } 1271 1272 static void 1273 bge_sig_pre_reset(struct bge_softc *sc, int type) 1274 { 1275 1276 /* 1277 * Some chips don't like this so only do this if ASF is enabled 1278 */ 1279 if (sc->bge_asf_mode) 1280 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1281 1282 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1283 switch (type) { 1284 case BGE_RESET_START: 1285 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1286 break; 1287 case BGE_RESET_STOP: 1288 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1289 break; 1290 } 1291 } 1292 } 1293 1294 static void 1295 bge_sig_post_reset(struct bge_softc *sc, int type) 1296 { 1297 1298 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1299 switch (type) { 1300 case BGE_RESET_START: 1301 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1302 /* START DONE */ 1303 break; 1304 case BGE_RESET_STOP: 1305 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1306 break; 1307 } 1308 } 1309 } 1310 1311 static void 1312 bge_sig_legacy(struct bge_softc *sc, int type) 1313 { 1314 1315 if (sc->bge_asf_mode) { 1316 switch (type) { 1317 case BGE_RESET_START: 1318 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1319 break; 1320 case BGE_RESET_STOP: 1321 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1322 break; 1323 } 1324 } 1325 } 1326 1327 static void 1328 bge_stop_fw(struct bge_softc *sc) 1329 { 1330 int i; 1331 1332 if (sc->bge_asf_mode) { 1333 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1334 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1335 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1336 1337 for (i = 0; i < 100; i++ ) { 1338 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1339 break; 1340 DELAY(10); 1341 } 1342 } 1343 } 1344 1345 /* 1346 * Do endian, PCI and DMA initialization. 1347 */ 1348 static int 1349 bge_chipinit(struct bge_softc *sc) 1350 { 1351 uint32_t dma_rw_ctl; 1352 uint16_t val; 1353 int i; 1354 1355 /* Set endianness before we access any non-PCI registers. */ 1356 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1357 1358 /* Clear the MAC control register */ 1359 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1360 1361 /* 1362 * Clear the MAC statistics block in the NIC's 1363 * internal memory. 1364 */ 1365 for (i = BGE_STATS_BLOCK; 1366 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1367 BGE_MEMWIN_WRITE(sc, i, 0); 1368 1369 for (i = BGE_STATUS_BLOCK; 1370 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1371 BGE_MEMWIN_WRITE(sc, i, 0); 1372 1373 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1374 /* 1375 * Fix data corruption caused by non-qword write with WB. 1376 * Fix master abort in PCI mode. 1377 * Fix PCI latency timer. 1378 */ 1379 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1380 val |= (1 << 10) | (1 << 12) | (1 << 13); 1381 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1382 } 1383 1384 /* 1385 * Set up the PCI DMA control register. 1386 */ 1387 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1388 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1389 if (sc->bge_flags & BGE_FLAG_PCIE) { 1390 /* Read watermark not used, 128 bytes for write. */ 1391 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1392 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1393 if (BGE_IS_5714_FAMILY(sc)) { 1394 /* 256 bytes for read and write. */ 1395 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1396 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1397 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1398 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1399 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1400 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1401 /* 1402 * In the BCM5703, the DMA read watermark should 1403 * be set to less than or equal to the maximum 1404 * memory read byte count of the PCI-X command 1405 * register. 1406 */ 1407 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1408 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1409 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1410 /* 1536 bytes for read, 384 bytes for write. */ 1411 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1412 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1413 } else { 1414 /* 384 bytes for read and write. */ 1415 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1416 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1417 0x0F; 1418 } 1419 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1420 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1421 uint32_t tmp; 1422 1423 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1424 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1425 if (tmp == 6 || tmp == 7) 1426 dma_rw_ctl |= 1427 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1428 1429 /* Set PCI-X DMA write workaround. */ 1430 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1431 } 1432 } else { 1433 /* Conventional PCI bus: 256 bytes for read and write. */ 1434 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1435 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1436 1437 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1438 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1439 dma_rw_ctl |= 0x0F; 1440 } 1441 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1442 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1443 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1444 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1445 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1446 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1447 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1448 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1449 1450 /* 1451 * Set up general mode register. 1452 */ 1453 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1454 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1455 BGE_MODECTL_TX_NO_PHDR_CSUM); 1456 1457 /* 1458 * BCM5701 B5 have a bug causing data corruption when using 1459 * 64-bit DMA reads, which can be terminated early and then 1460 * completed later as 32-bit accesses, in combination with 1461 * certain bridges. 1462 */ 1463 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1464 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1465 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1466 1467 /* 1468 * Tell the firmware the driver is running 1469 */ 1470 if (sc->bge_asf_mode & ASF_STACKUP) 1471 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1472 1473 /* 1474 * Disable memory write invalidate. Apparently it is not supported 1475 * properly by these devices. Also ensure that INTx isn't disabled, 1476 * as these chips need it even when using MSI. 1477 */ 1478 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1479 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1480 1481 /* Set the timer prescaler (always 66Mhz) */ 1482 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1483 1484 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1485 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1486 DELAY(40); /* XXX */ 1487 1488 /* Put PHY into ready state */ 1489 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1490 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1491 DELAY(40); 1492 } 1493 1494 return (0); 1495 } 1496 1497 static int 1498 bge_blockinit(struct bge_softc *sc) 1499 { 1500 struct bge_rcb *rcb; 1501 bus_size_t vrcb; 1502 bge_hostaddr taddr; 1503 uint32_t val; 1504 int i, limit; 1505 1506 /* 1507 * Initialize the memory window pointer register so that 1508 * we can access the first 32K of internal NIC RAM. This will 1509 * allow us to set up the TX send ring RCBs and the RX return 1510 * ring RCBs, plus other things which live in NIC memory. 1511 */ 1512 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1513 1514 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1515 1516 if (!(BGE_IS_5705_PLUS(sc))) { 1517 /* Configure mbuf memory pool */ 1518 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1519 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1520 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1521 else 1522 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1523 1524 /* Configure DMA resource pool */ 1525 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1526 BGE_DMA_DESCRIPTORS); 1527 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1528 } 1529 1530 /* Configure mbuf pool watermarks */ 1531 if (!BGE_IS_5705_PLUS(sc)) { 1532 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1533 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1534 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1535 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1536 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1537 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1538 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1539 } else { 1540 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1541 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1542 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1543 } 1544 1545 /* Configure DMA resource watermarks */ 1546 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1547 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1548 1549 /* Enable buffer manager */ 1550 if (!(BGE_IS_5705_PLUS(sc))) { 1551 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1552 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1553 1554 /* Poll for buffer manager start indication */ 1555 for (i = 0; i < BGE_TIMEOUT; i++) { 1556 DELAY(10); 1557 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1558 break; 1559 } 1560 1561 if (i == BGE_TIMEOUT) { 1562 device_printf(sc->bge_dev, 1563 "buffer manager failed to start\n"); 1564 return (ENXIO); 1565 } 1566 } 1567 1568 /* Enable flow-through queues */ 1569 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1570 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1571 1572 /* Wait until queue initialization is complete */ 1573 for (i = 0; i < BGE_TIMEOUT; i++) { 1574 DELAY(10); 1575 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1576 break; 1577 } 1578 1579 if (i == BGE_TIMEOUT) { 1580 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1581 return (ENXIO); 1582 } 1583 1584 /* 1585 * Summary of rings supported by the controller: 1586 * 1587 * Standard Receive Producer Ring 1588 * - This ring is used to feed receive buffers for "standard" 1589 * sized frames (typically 1536 bytes) to the controller. 1590 * 1591 * Jumbo Receive Producer Ring 1592 * - This ring is used to feed receive buffers for jumbo sized 1593 * frames (i.e. anything bigger than the "standard" frames) 1594 * to the controller. 1595 * 1596 * Mini Receive Producer Ring 1597 * - This ring is used to feed receive buffers for "mini" 1598 * sized frames to the controller. 1599 * - This feature required external memory for the controller 1600 * but was never used in a production system. Should always 1601 * be disabled. 1602 * 1603 * Receive Return Ring 1604 * - After the controller has placed an incoming frame into a 1605 * receive buffer that buffer is moved into a receive return 1606 * ring. The driver is then responsible to passing the 1607 * buffer up to the stack. Many versions of the controller 1608 * support multiple RR rings. 1609 * 1610 * Send Ring 1611 * - This ring is used for outgoing frames. Many versions of 1612 * the controller support multiple send rings. 1613 */ 1614 1615 /* Initialize the standard receive producer ring control block. */ 1616 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1617 rcb->bge_hostaddr.bge_addr_lo = 1618 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1619 rcb->bge_hostaddr.bge_addr_hi = 1620 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1621 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1622 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1623 if (BGE_IS_5705_PLUS(sc)) { 1624 /* 1625 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1626 * Bits 15-2 : Reserved (should be 0) 1627 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1628 * Bit 0 : Reserved 1629 */ 1630 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1631 } else { 1632 /* 1633 * Ring size is always XXX entries 1634 * Bits 31-16: Maximum RX frame size 1635 * Bits 15-2 : Reserved (should be 0) 1636 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1637 * Bit 0 : Reserved 1638 */ 1639 rcb->bge_maxlen_flags = 1640 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1641 } 1642 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1643 /* Write the standard receive producer ring control block. */ 1644 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1645 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1646 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1647 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1648 1649 /* Reset the standard receive producer ring producer index. */ 1650 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1651 1652 /* 1653 * Initialize the jumbo RX producer ring control 1654 * block. We set the 'ring disabled' bit in the 1655 * flags field until we're actually ready to start 1656 * using this ring (i.e. once we set the MTU 1657 * high enough to require it). 1658 */ 1659 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1660 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1661 /* Get the jumbo receive producer ring RCB parameters. */ 1662 rcb->bge_hostaddr.bge_addr_lo = 1663 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1664 rcb->bge_hostaddr.bge_addr_hi = 1665 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1666 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1667 sc->bge_cdata.bge_rx_jumbo_ring_map, 1668 BUS_DMASYNC_PREREAD); 1669 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1670 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1671 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1672 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1673 rcb->bge_hostaddr.bge_addr_hi); 1674 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1675 rcb->bge_hostaddr.bge_addr_lo); 1676 /* Program the jumbo receive producer ring RCB parameters. */ 1677 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1678 rcb->bge_maxlen_flags); 1679 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1680 /* Reset the jumbo receive producer ring producer index. */ 1681 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1682 } 1683 1684 /* Disable the mini receive producer ring RCB. */ 1685 if (BGE_IS_5700_FAMILY(sc)) { 1686 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1687 rcb->bge_maxlen_flags = 1688 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1689 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1690 rcb->bge_maxlen_flags); 1691 /* Reset the mini receive producer ring producer index. */ 1692 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1693 } 1694 1695 /* 1696 * The BD ring replenish thresholds control how often the 1697 * hardware fetches new BD's from the producer rings in host 1698 * memory. Setting the value too low on a busy system can 1699 * starve the hardware and recue the throughpout. 1700 * 1701 * Set the BD ring replentish thresholds. The recommended 1702 * values are 1/8th the number of descriptors allocated to 1703 * each ring. 1704 * XXX The 5754 requires a lower threshold, so it might be a 1705 * requirement of all 575x family chips. The Linux driver sets 1706 * the lower threshold for all 5705 family chips as well, but there 1707 * are reports that it might not need to be so strict. 1708 * 1709 * XXX Linux does some extra fiddling here for the 5906 parts as 1710 * well. 1711 */ 1712 if (BGE_IS_5705_PLUS(sc)) 1713 val = 8; 1714 else 1715 val = BGE_STD_RX_RING_CNT / 8; 1716 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1717 if (BGE_IS_JUMBO_CAPABLE(sc)) 1718 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1719 BGE_JUMBO_RX_RING_CNT/8); 1720 1721 /* 1722 * Disable all send rings by setting the 'ring disabled' bit 1723 * in the flags field of all the TX send ring control blocks, 1724 * located in NIC memory. 1725 */ 1726 if (!BGE_IS_5705_PLUS(sc)) 1727 /* 5700 to 5704 had 16 send rings. */ 1728 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1729 else 1730 limit = 1; 1731 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1732 for (i = 0; i < limit; i++) { 1733 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1734 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1735 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1736 vrcb += sizeof(struct bge_rcb); 1737 } 1738 1739 /* Configure send ring RCB 0 (we use only the first ring) */ 1740 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1741 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1742 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1743 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1744 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1745 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1746 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1747 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1748 1749 /* 1750 * Disable all receive return rings by setting the 1751 * 'ring diabled' bit in the flags field of all the receive 1752 * return ring control blocks, located in NIC memory. 1753 */ 1754 if (!BGE_IS_5705_PLUS(sc)) 1755 limit = BGE_RX_RINGS_MAX; 1756 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755) 1757 limit = 4; 1758 else 1759 limit = 1; 1760 /* Disable all receive return rings. */ 1761 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1762 for (i = 0; i < limit; i++) { 1763 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1764 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1765 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1766 BGE_RCB_FLAG_RING_DISABLED); 1767 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1768 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1769 (i * (sizeof(uint64_t))), 0); 1770 vrcb += sizeof(struct bge_rcb); 1771 } 1772 1773 /* 1774 * Set up receive return ring 0. Note that the NIC address 1775 * for RX return rings is 0x0. The return rings live entirely 1776 * within the host, so the nicaddr field in the RCB isn't used. 1777 */ 1778 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1779 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1780 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1781 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1782 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1783 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1784 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1785 1786 /* Set random backoff seed for TX */ 1787 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1788 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1789 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1790 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1791 BGE_TX_BACKOFF_SEED_MASK); 1792 1793 /* Set inter-packet gap */ 1794 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1795 1796 /* 1797 * Specify which ring to use for packets that don't match 1798 * any RX rules. 1799 */ 1800 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1801 1802 /* 1803 * Configure number of RX lists. One interrupt distribution 1804 * list, sixteen active lists, one bad frames class. 1805 */ 1806 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1807 1808 /* Inialize RX list placement stats mask. */ 1809 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1810 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1811 1812 /* Disable host coalescing until we get it set up */ 1813 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1814 1815 /* Poll to make sure it's shut down. */ 1816 for (i = 0; i < BGE_TIMEOUT; i++) { 1817 DELAY(10); 1818 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1819 break; 1820 } 1821 1822 if (i == BGE_TIMEOUT) { 1823 device_printf(sc->bge_dev, 1824 "host coalescing engine failed to idle\n"); 1825 return (ENXIO); 1826 } 1827 1828 /* Set up host coalescing defaults */ 1829 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1830 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1831 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1832 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1833 if (!(BGE_IS_5705_PLUS(sc))) { 1834 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1835 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1836 } 1837 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1838 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1839 1840 /* Set up address of statistics block */ 1841 if (!(BGE_IS_5705_PLUS(sc))) { 1842 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1843 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1844 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1845 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1846 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1847 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1848 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1849 } 1850 1851 /* Set up address of status block */ 1852 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1853 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1854 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1855 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1856 1857 /* Set up status block size. */ 1858 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1859 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1860 val = BGE_STATBLKSZ_FULL; 1861 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1862 } else { 1863 val = BGE_STATBLKSZ_32BYTE; 1864 bzero(sc->bge_ldata.bge_status_block, 32); 1865 } 1866 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1867 sc->bge_cdata.bge_status_map, 1868 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1869 1870 /* Turn on host coalescing state machine */ 1871 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1872 1873 /* Turn on RX BD completion state machine and enable attentions */ 1874 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1875 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1876 1877 /* Turn on RX list placement state machine */ 1878 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1879 1880 /* Turn on RX list selector state machine. */ 1881 if (!(BGE_IS_5705_PLUS(sc))) 1882 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1883 1884 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1885 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1886 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1887 BGE_MACMODE_FRMHDR_DMA_ENB; 1888 1889 if (sc->bge_flags & BGE_FLAG_TBI) 1890 val |= BGE_PORTMODE_TBI; 1891 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1892 val |= BGE_PORTMODE_GMII; 1893 else 1894 val |= BGE_PORTMODE_MII; 1895 1896 /* Turn on DMA, clear stats */ 1897 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1898 1899 /* Set misc. local control, enable interrupts on attentions */ 1900 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1901 1902 #ifdef notdef 1903 /* Assert GPIO pins for PHY reset */ 1904 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1905 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1906 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1907 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1908 #endif 1909 1910 /* Turn on DMA completion state machine */ 1911 if (!(BGE_IS_5705_PLUS(sc))) 1912 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1913 1914 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1915 1916 /* Enable host coalescing bug fix. */ 1917 if (BGE_IS_5755_PLUS(sc)) 1918 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1919 1920 /* Request larger DMA burst size to get better performance. */ 1921 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 1922 val |= BGE_WDMAMODE_BURST_ALL_DATA; 1923 1924 /* Turn on write DMA state machine */ 1925 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1926 DELAY(40); 1927 1928 /* Turn on read DMA state machine */ 1929 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1930 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1931 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1932 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1933 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1934 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1935 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1936 if (sc->bge_flags & BGE_FLAG_PCIE) 1937 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1938 if (sc->bge_flags & BGE_FLAG_TSO) { 1939 val |= BGE_RDMAMODE_TSO4_ENABLE; 1940 if (sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1941 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1942 val |= BGE_RDMAMODE_TSO6_ENABLE; 1943 } 1944 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 1945 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1946 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1947 sc->bge_asicrev == BGE_ASICREV_BCM57780) { 1948 /* 1949 * Enable fix for read DMA FIFO overruns. 1950 * The fix is to limit the number of RX BDs 1951 * the hardware would fetch at a fime. 1952 */ 1953 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, 1954 CSR_READ_4(sc, BGE_RDMA_RSRVCTRL) | 1955 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 1956 } 1957 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1958 DELAY(40); 1959 1960 /* Turn on RX data completion state machine */ 1961 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1962 1963 /* Turn on RX BD initiator state machine */ 1964 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1965 1966 /* Turn on RX data and RX BD initiator state machine */ 1967 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1968 1969 /* Turn on Mbuf cluster free state machine */ 1970 if (!(BGE_IS_5705_PLUS(sc))) 1971 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1972 1973 /* Turn on send BD completion state machine */ 1974 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1975 1976 /* Turn on send data completion state machine */ 1977 val = BGE_SDCMODE_ENABLE; 1978 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1979 val |= BGE_SDCMODE_CDELAY; 1980 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1981 1982 /* Turn on send data initiator state machine */ 1983 if (sc->bge_flags & BGE_FLAG_TSO) 1984 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1985 else 1986 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1987 1988 /* Turn on send BD initiator state machine */ 1989 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1990 1991 /* Turn on send BD selector state machine */ 1992 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1993 1994 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1995 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1996 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1997 1998 /* ack/clear link change events */ 1999 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2000 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2001 BGE_MACSTAT_LINK_CHANGED); 2002 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2003 2004 /* 2005 * Enable attention when the link has changed state for 2006 * devices that use auto polling. 2007 */ 2008 if (sc->bge_flags & BGE_FLAG_TBI) { 2009 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2010 } else { 2011 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2012 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2013 DELAY(80); 2014 } 2015 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2016 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2017 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2018 BGE_EVTENB_MI_INTERRUPT); 2019 } 2020 2021 /* 2022 * Clear any pending link state attention. 2023 * Otherwise some link state change events may be lost until attention 2024 * is cleared by bge_intr() -> bge_link_upd() sequence. 2025 * It's not necessary on newer BCM chips - perhaps enabling link 2026 * state change attentions implies clearing pending attention. 2027 */ 2028 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2029 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2030 BGE_MACSTAT_LINK_CHANGED); 2031 2032 /* Enable link state change attentions. */ 2033 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2034 2035 return (0); 2036 } 2037 2038 const struct bge_revision * 2039 bge_lookup_rev(uint32_t chipid) 2040 { 2041 const struct bge_revision *br; 2042 2043 for (br = bge_revisions; br->br_name != NULL; br++) { 2044 if (br->br_chipid == chipid) 2045 return (br); 2046 } 2047 2048 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2049 if (br->br_chipid == BGE_ASICREV(chipid)) 2050 return (br); 2051 } 2052 2053 return (NULL); 2054 } 2055 2056 const struct bge_vendor * 2057 bge_lookup_vendor(uint16_t vid) 2058 { 2059 const struct bge_vendor *v; 2060 2061 for (v = bge_vendors; v->v_name != NULL; v++) 2062 if (v->v_id == vid) 2063 return (v); 2064 2065 panic("%s: unknown vendor %d", __func__, vid); 2066 return (NULL); 2067 } 2068 2069 /* 2070 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2071 * against our list and return its name if we find a match. 2072 * 2073 * Note that since the Broadcom controller contains VPD support, we 2074 * try to get the device name string from the controller itself instead 2075 * of the compiled-in string. It guarantees we'll always announce the 2076 * right product name. We fall back to the compiled-in string when 2077 * VPD is unavailable or corrupt. 2078 */ 2079 static int 2080 bge_probe(device_t dev) 2081 { 2082 const struct bge_type *t = bge_devs; 2083 struct bge_softc *sc = device_get_softc(dev); 2084 uint16_t vid, did; 2085 2086 sc->bge_dev = dev; 2087 vid = pci_get_vendor(dev); 2088 did = pci_get_device(dev); 2089 while(t->bge_vid != 0) { 2090 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2091 char model[64], buf[96]; 2092 const struct bge_revision *br; 2093 const struct bge_vendor *v; 2094 uint32_t id; 2095 2096 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2097 BGE_PCIMISCCTL_ASICREV_SHIFT; 2098 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) 2099 id = pci_read_config(dev, 2100 BGE_PCI_PRODID_ASICREV, 4); 2101 br = bge_lookup_rev(id); 2102 v = bge_lookup_vendor(vid); 2103 { 2104 #if __FreeBSD_version > 700024 2105 const char *pname; 2106 2107 if (bge_has_eaddr(sc) && 2108 pci_get_vpd_ident(dev, &pname) == 0) 2109 snprintf(model, 64, "%s", pname); 2110 else 2111 #endif 2112 snprintf(model, 64, "%s %s", 2113 v->v_name, 2114 br != NULL ? br->br_name : 2115 "NetXtreme Ethernet Controller"); 2116 } 2117 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 2118 br != NULL ? "" : "unknown ", id); 2119 device_set_desc_copy(dev, buf); 2120 return (0); 2121 } 2122 t++; 2123 } 2124 2125 return (ENXIO); 2126 } 2127 2128 static void 2129 bge_dma_free(struct bge_softc *sc) 2130 { 2131 int i; 2132 2133 /* Destroy DMA maps for RX buffers. */ 2134 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2135 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2136 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2137 sc->bge_cdata.bge_rx_std_dmamap[i]); 2138 } 2139 if (sc->bge_cdata.bge_rx_std_sparemap) 2140 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2141 sc->bge_cdata.bge_rx_std_sparemap); 2142 2143 /* Destroy DMA maps for jumbo RX buffers. */ 2144 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2145 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2146 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2147 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2148 } 2149 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2150 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2151 sc->bge_cdata.bge_rx_jumbo_sparemap); 2152 2153 /* Destroy DMA maps for TX buffers. */ 2154 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2155 if (sc->bge_cdata.bge_tx_dmamap[i]) 2156 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2157 sc->bge_cdata.bge_tx_dmamap[i]); 2158 } 2159 2160 if (sc->bge_cdata.bge_rx_mtag) 2161 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2162 if (sc->bge_cdata.bge_tx_mtag) 2163 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2164 2165 2166 /* Destroy standard RX ring. */ 2167 if (sc->bge_cdata.bge_rx_std_ring_map) 2168 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2169 sc->bge_cdata.bge_rx_std_ring_map); 2170 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2171 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2172 sc->bge_ldata.bge_rx_std_ring, 2173 sc->bge_cdata.bge_rx_std_ring_map); 2174 2175 if (sc->bge_cdata.bge_rx_std_ring_tag) 2176 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2177 2178 /* Destroy jumbo RX ring. */ 2179 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2180 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2181 sc->bge_cdata.bge_rx_jumbo_ring_map); 2182 2183 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2184 sc->bge_ldata.bge_rx_jumbo_ring) 2185 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2186 sc->bge_ldata.bge_rx_jumbo_ring, 2187 sc->bge_cdata.bge_rx_jumbo_ring_map); 2188 2189 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2190 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2191 2192 /* Destroy RX return ring. */ 2193 if (sc->bge_cdata.bge_rx_return_ring_map) 2194 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2195 sc->bge_cdata.bge_rx_return_ring_map); 2196 2197 if (sc->bge_cdata.bge_rx_return_ring_map && 2198 sc->bge_ldata.bge_rx_return_ring) 2199 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2200 sc->bge_ldata.bge_rx_return_ring, 2201 sc->bge_cdata.bge_rx_return_ring_map); 2202 2203 if (sc->bge_cdata.bge_rx_return_ring_tag) 2204 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2205 2206 /* Destroy TX ring. */ 2207 if (sc->bge_cdata.bge_tx_ring_map) 2208 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2209 sc->bge_cdata.bge_tx_ring_map); 2210 2211 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2212 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2213 sc->bge_ldata.bge_tx_ring, 2214 sc->bge_cdata.bge_tx_ring_map); 2215 2216 if (sc->bge_cdata.bge_tx_ring_tag) 2217 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2218 2219 /* Destroy status block. */ 2220 if (sc->bge_cdata.bge_status_map) 2221 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2222 sc->bge_cdata.bge_status_map); 2223 2224 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2225 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2226 sc->bge_ldata.bge_status_block, 2227 sc->bge_cdata.bge_status_map); 2228 2229 if (sc->bge_cdata.bge_status_tag) 2230 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2231 2232 /* Destroy statistics block. */ 2233 if (sc->bge_cdata.bge_stats_map) 2234 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2235 sc->bge_cdata.bge_stats_map); 2236 2237 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2238 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2239 sc->bge_ldata.bge_stats, 2240 sc->bge_cdata.bge_stats_map); 2241 2242 if (sc->bge_cdata.bge_stats_tag) 2243 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2244 2245 if (sc->bge_cdata.bge_buffer_tag) 2246 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2247 2248 /* Destroy the parent tag. */ 2249 if (sc->bge_cdata.bge_parent_tag) 2250 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2251 } 2252 2253 static int 2254 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2255 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2256 bus_addr_t *paddr, const char *msg) 2257 { 2258 struct bge_dmamap_arg ctx; 2259 bus_addr_t lowaddr; 2260 bus_size_t ring_end; 2261 int error; 2262 2263 lowaddr = BUS_SPACE_MAXADDR; 2264 again: 2265 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2266 alignment, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2267 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2268 if (error != 0) { 2269 device_printf(sc->bge_dev, 2270 "could not create %s dma tag\n", msg); 2271 return (ENOMEM); 2272 } 2273 /* Allocate DMA'able memory for ring. */ 2274 error = bus_dmamem_alloc(*tag, (void **)ring, 2275 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2276 if (error != 0) { 2277 device_printf(sc->bge_dev, 2278 "could not allocate DMA'able memory for %s\n", msg); 2279 return (ENOMEM); 2280 } 2281 /* Load the address of the ring. */ 2282 ctx.bge_busaddr = 0; 2283 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2284 &ctx, BUS_DMA_NOWAIT); 2285 if (error != 0) { 2286 device_printf(sc->bge_dev, 2287 "could not load DMA'able memory for %s\n", msg); 2288 return (ENOMEM); 2289 } 2290 *paddr = ctx.bge_busaddr; 2291 ring_end = *paddr + maxsize; 2292 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0 && 2293 BGE_ADDR_HI(*paddr) != BGE_ADDR_HI(ring_end)) { 2294 /* 2295 * 4GB boundary crossed. Limit maximum allowable DMA 2296 * address space to 32bit and try again. 2297 */ 2298 bus_dmamap_unload(*tag, *map); 2299 bus_dmamem_free(*tag, *ring, *map); 2300 bus_dma_tag_destroy(*tag); 2301 if (bootverbose) 2302 device_printf(sc->bge_dev, "4GB boundary crossed, " 2303 "limit DMA address space to 32bit for %s\n", msg); 2304 *ring = NULL; 2305 *tag = NULL; 2306 *map = NULL; 2307 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2308 goto again; 2309 } 2310 return (0); 2311 } 2312 2313 static int 2314 bge_dma_alloc(struct bge_softc *sc) 2315 { 2316 bus_addr_t lowaddr; 2317 bus_size_t boundary, sbsz, txsegsz, txmaxsegsz; 2318 int i, error; 2319 2320 lowaddr = BUS_SPACE_MAXADDR; 2321 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2322 lowaddr = BGE_DMA_MAXADDR; 2323 /* 2324 * Allocate the parent bus DMA tag appropriate for PCI. 2325 */ 2326 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2327 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2328 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2329 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2330 if (error != 0) { 2331 device_printf(sc->bge_dev, 2332 "could not allocate parent dma tag\n"); 2333 return (ENOMEM); 2334 } 2335 2336 /* Create tag for standard RX ring. */ 2337 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2338 &sc->bge_cdata.bge_rx_std_ring_tag, 2339 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2340 &sc->bge_cdata.bge_rx_std_ring_map, 2341 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2342 if (error) 2343 return (error); 2344 2345 /* Create tag for RX return ring. */ 2346 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2347 &sc->bge_cdata.bge_rx_return_ring_tag, 2348 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2349 &sc->bge_cdata.bge_rx_return_ring_map, 2350 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2351 if (error) 2352 return (error); 2353 2354 /* Create tag for TX ring. */ 2355 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2356 &sc->bge_cdata.bge_tx_ring_tag, 2357 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2358 &sc->bge_cdata.bge_tx_ring_map, 2359 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2360 if (error) 2361 return (error); 2362 2363 /* 2364 * Create tag for status block. 2365 * Because we only use single Tx/Rx/Rx return ring, use 2366 * minimum status block size except BCM5700 AX/BX which 2367 * seems to want to see full status block size regardless 2368 * of configured number of ring. 2369 */ 2370 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2371 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2372 sbsz = BGE_STATUS_BLK_SZ; 2373 else 2374 sbsz = 32; 2375 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2376 &sc->bge_cdata.bge_status_tag, 2377 (uint8_t **)&sc->bge_ldata.bge_status_block, 2378 &sc->bge_cdata.bge_status_map, 2379 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2380 if (error) 2381 return (error); 2382 2383 /* Create tag for statistics block. */ 2384 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2385 &sc->bge_cdata.bge_stats_tag, 2386 (uint8_t **)&sc->bge_ldata.bge_stats, 2387 &sc->bge_cdata.bge_stats_map, 2388 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2389 if (error) 2390 return (error); 2391 2392 /* Create tag for jumbo RX ring. */ 2393 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2394 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2395 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2396 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2397 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2398 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2399 if (error) 2400 return (error); 2401 } 2402 2403 /* Create parent tag for buffers. */ 2404 boundary = 0; 2405 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) 2406 boundary = BGE_DMA_BNDRY; 2407 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2408 1, boundary, lowaddr, BUS_SPACE_MAXADDR, NULL, 2409 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2410 0, NULL, NULL, &sc->bge_cdata.bge_buffer_tag); 2411 if (error != 0) { 2412 device_printf(sc->bge_dev, 2413 "could not allocate buffer dma tag\n"); 2414 return (ENOMEM); 2415 } 2416 /* Create tag for Tx mbufs. */ 2417 if (sc->bge_flags & BGE_FLAG_TSO) { 2418 txsegsz = BGE_TSOSEG_SZ; 2419 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2420 } else { 2421 txsegsz = MCLBYTES; 2422 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2423 } 2424 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2425 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2426 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2427 &sc->bge_cdata.bge_tx_mtag); 2428 2429 if (error) { 2430 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2431 return (ENOMEM); 2432 } 2433 2434 /* Create tag for Rx mbufs. */ 2435 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2436 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 2437 MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2438 2439 if (error) { 2440 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2441 return (ENOMEM); 2442 } 2443 2444 /* Create DMA maps for RX buffers. */ 2445 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2446 &sc->bge_cdata.bge_rx_std_sparemap); 2447 if (error) { 2448 device_printf(sc->bge_dev, 2449 "can't create spare DMA map for RX\n"); 2450 return (ENOMEM); 2451 } 2452 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2453 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2454 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2455 if (error) { 2456 device_printf(sc->bge_dev, 2457 "can't create DMA map for RX\n"); 2458 return (ENOMEM); 2459 } 2460 } 2461 2462 /* Create DMA maps for TX buffers. */ 2463 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2464 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2465 &sc->bge_cdata.bge_tx_dmamap[i]); 2466 if (error) { 2467 device_printf(sc->bge_dev, 2468 "can't create DMA map for TX\n"); 2469 return (ENOMEM); 2470 } 2471 } 2472 2473 /* Create tags for jumbo RX buffers. */ 2474 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2475 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 2476 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2477 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2478 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2479 if (error) { 2480 device_printf(sc->bge_dev, 2481 "could not allocate jumbo dma tag\n"); 2482 return (ENOMEM); 2483 } 2484 /* Create DMA maps for jumbo RX buffers. */ 2485 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2486 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2487 if (error) { 2488 device_printf(sc->bge_dev, 2489 "can't create spare DMA map for jumbo RX\n"); 2490 return (ENOMEM); 2491 } 2492 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2493 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2494 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2495 if (error) { 2496 device_printf(sc->bge_dev, 2497 "can't create DMA map for jumbo RX\n"); 2498 return (ENOMEM); 2499 } 2500 } 2501 } 2502 2503 return (0); 2504 } 2505 2506 /* 2507 * Return true if this device has more than one port. 2508 */ 2509 static int 2510 bge_has_multiple_ports(struct bge_softc *sc) 2511 { 2512 device_t dev = sc->bge_dev; 2513 u_int b, d, f, fscan, s; 2514 2515 d = pci_get_domain(dev); 2516 b = pci_get_bus(dev); 2517 s = pci_get_slot(dev); 2518 f = pci_get_function(dev); 2519 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2520 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2521 return (1); 2522 return (0); 2523 } 2524 2525 /* 2526 * Return true if MSI can be used with this device. 2527 */ 2528 static int 2529 bge_can_use_msi(struct bge_softc *sc) 2530 { 2531 int can_use_msi = 0; 2532 2533 switch (sc->bge_asicrev) { 2534 case BGE_ASICREV_BCM5714_A0: 2535 case BGE_ASICREV_BCM5714: 2536 /* 2537 * Apparently, MSI doesn't work when these chips are 2538 * configured in single-port mode. 2539 */ 2540 if (bge_has_multiple_ports(sc)) 2541 can_use_msi = 1; 2542 break; 2543 case BGE_ASICREV_BCM5750: 2544 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2545 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2546 can_use_msi = 1; 2547 break; 2548 default: 2549 if (BGE_IS_575X_PLUS(sc)) 2550 can_use_msi = 1; 2551 } 2552 return (can_use_msi); 2553 } 2554 2555 static int 2556 bge_attach(device_t dev) 2557 { 2558 struct ifnet *ifp; 2559 struct bge_softc *sc; 2560 uint32_t hwcfg = 0, misccfg; 2561 u_char eaddr[ETHER_ADDR_LEN]; 2562 int error, msicount, phy_addr, reg, rid, trys; 2563 2564 sc = device_get_softc(dev); 2565 sc->bge_dev = dev; 2566 2567 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2568 2569 /* 2570 * Map control/status registers. 2571 */ 2572 pci_enable_busmaster(dev); 2573 2574 rid = PCIR_BAR(0); 2575 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2576 RF_ACTIVE); 2577 2578 if (sc->bge_res == NULL) { 2579 device_printf (sc->bge_dev, "couldn't map memory\n"); 2580 error = ENXIO; 2581 goto fail; 2582 } 2583 2584 /* Save various chip information. */ 2585 sc->bge_chipid = 2586 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2587 BGE_PCIMISCCTL_ASICREV_SHIFT; 2588 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) 2589 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 2590 4); 2591 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2592 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2593 2594 /* Set default PHY address. */ 2595 phy_addr = 1; 2596 2597 /* 2598 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2599 * 5705 A0 and A1 chips. 2600 */ 2601 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2602 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2603 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2604 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2605 sc->bge_phy_flags |= BGE_PHY_WIRESPEED; 2606 2607 if (bge_has_eaddr(sc)) 2608 sc->bge_flags |= BGE_FLAG_EADDR; 2609 2610 /* Save chipset family. */ 2611 switch (sc->bge_asicrev) { 2612 case BGE_ASICREV_BCM5755: 2613 case BGE_ASICREV_BCM5761: 2614 case BGE_ASICREV_BCM5784: 2615 case BGE_ASICREV_BCM5785: 2616 case BGE_ASICREV_BCM5787: 2617 case BGE_ASICREV_BCM57780: 2618 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2619 BGE_FLAG_5705_PLUS; 2620 break; 2621 case BGE_ASICREV_BCM5700: 2622 case BGE_ASICREV_BCM5701: 2623 case BGE_ASICREV_BCM5703: 2624 case BGE_ASICREV_BCM5704: 2625 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2626 break; 2627 case BGE_ASICREV_BCM5714_A0: 2628 case BGE_ASICREV_BCM5780: 2629 case BGE_ASICREV_BCM5714: 2630 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2631 /* FALLTHROUGH */ 2632 case BGE_ASICREV_BCM5750: 2633 case BGE_ASICREV_BCM5752: 2634 case BGE_ASICREV_BCM5906: 2635 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2636 /* FALLTHROUGH */ 2637 case BGE_ASICREV_BCM5705: 2638 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2639 break; 2640 } 2641 2642 /* Set various PHY bug flags. */ 2643 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2644 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2645 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 2646 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2647 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2648 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 2649 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2650 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 2651 if (pci_get_subvendor(dev) == DELL_VENDORID) 2652 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 2653 if ((BGE_IS_5705_PLUS(sc)) && 2654 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2655 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 2656 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 2657 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2658 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2659 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2660 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2661 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 2662 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 2663 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 2664 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 2665 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 2666 } else 2667 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 2668 } 2669 2670 /* Identify the chips that use an CPMU. */ 2671 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2672 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2673 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2674 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2675 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 2676 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 2677 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 2678 else 2679 sc->bge_mi_mode = BGE_MIMODE_BASE; 2680 /* Enable auto polling for BCM570[0-5]. */ 2681 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 2682 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 2683 2684 /* 2685 * All controllers that are not 5755 or higher have 4GB 2686 * boundary DMA bug. 2687 * Whenever an address crosses a multiple of the 4GB boundary 2688 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2689 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2690 * state machine will lockup and cause the device to hang. 2691 */ 2692 if (BGE_IS_5755_PLUS(sc) == 0) 2693 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2694 2695 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 2696 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2697 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2698 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2699 sc->bge_flags |= BGE_FLAG_5788; 2700 } 2701 2702 /* 2703 * Some controllers seem to require a special firmware to use 2704 * TSO. But the firmware is not available to FreeBSD and Linux 2705 * claims that the TSO performed by the firmware is slower than 2706 * hardware based TSO. Moreover the firmware based TSO has one 2707 * known bug which can't handle TSO if ethernet header + IP/TCP 2708 * header is greater than 80 bytes. The workaround for the TSO 2709 * bug exist but it seems it's too expensive than not using 2710 * TSO at all. Some hardwares also have the TSO bug so limit 2711 * the TSO to the controllers that are not affected TSO issues 2712 * (e.g. 5755 or higher). 2713 */ 2714 if (BGE_IS_5755_PLUS(sc)) { 2715 /* 2716 * BCM5754 and BCM5787 shares the same ASIC id so 2717 * explicit device id check is required. 2718 * Due to unknown reason TSO does not work on BCM5755M. 2719 */ 2720 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 2721 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 2722 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 2723 sc->bge_flags |= BGE_FLAG_TSO; 2724 } 2725 2726 /* 2727 * Check if this is a PCI-X or PCI Express device. 2728 */ 2729 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2730 /* 2731 * Found a PCI Express capabilities register, this 2732 * must be a PCI Express device. 2733 */ 2734 sc->bge_flags |= BGE_FLAG_PCIE; 2735 sc->bge_expcap = reg; 2736 if (pci_get_max_read_req(dev) != 4096) 2737 pci_set_max_read_req(dev, 4096); 2738 } else { 2739 /* 2740 * Check if the device is in PCI-X Mode. 2741 * (This bit is not valid on PCI Express controllers.) 2742 */ 2743 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) 2744 sc->bge_pcixcap = reg; 2745 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2746 BGE_PCISTATE_PCI_BUSMODE) == 0) 2747 sc->bge_flags |= BGE_FLAG_PCIX; 2748 } 2749 2750 /* 2751 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2752 * not actually a MAC controller bug but an issue with the embedded 2753 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2754 */ 2755 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2756 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2757 /* 2758 * Allocate the interrupt, using MSI if possible. These devices 2759 * support 8 MSI messages, but only the first one is used in 2760 * normal operation. 2761 */ 2762 rid = 0; 2763 if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { 2764 sc->bge_msicap = reg; 2765 if (bge_can_use_msi(sc)) { 2766 msicount = pci_msi_count(dev); 2767 if (msicount > 1) 2768 msicount = 1; 2769 } else 2770 msicount = 0; 2771 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2772 rid = 1; 2773 sc->bge_flags |= BGE_FLAG_MSI; 2774 } 2775 } 2776 2777 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2778 RF_SHAREABLE | RF_ACTIVE); 2779 2780 if (sc->bge_irq == NULL) { 2781 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2782 error = ENXIO; 2783 goto fail; 2784 } 2785 2786 device_printf(dev, 2787 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2788 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2789 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 2790 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 2791 2792 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2793 2794 /* Try to reset the chip. */ 2795 if (bge_reset(sc)) { 2796 device_printf(sc->bge_dev, "chip reset failed\n"); 2797 error = ENXIO; 2798 goto fail; 2799 } 2800 2801 sc->bge_asf_mode = 0; 2802 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2803 == BGE_MAGIC_NUMBER)) { 2804 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2805 & BGE_HWCFG_ASF) { 2806 sc->bge_asf_mode |= ASF_ENABLE; 2807 sc->bge_asf_mode |= ASF_STACKUP; 2808 if (BGE_IS_575X_PLUS(sc)) 2809 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2810 } 2811 } 2812 2813 /* Try to reset the chip again the nice way. */ 2814 bge_stop_fw(sc); 2815 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2816 if (bge_reset(sc)) { 2817 device_printf(sc->bge_dev, "chip reset failed\n"); 2818 error = ENXIO; 2819 goto fail; 2820 } 2821 2822 bge_sig_legacy(sc, BGE_RESET_STOP); 2823 bge_sig_post_reset(sc, BGE_RESET_STOP); 2824 2825 if (bge_chipinit(sc)) { 2826 device_printf(sc->bge_dev, "chip initialization failed\n"); 2827 error = ENXIO; 2828 goto fail; 2829 } 2830 2831 error = bge_get_eaddr(sc, eaddr); 2832 if (error) { 2833 device_printf(sc->bge_dev, 2834 "failed to read station address\n"); 2835 error = ENXIO; 2836 goto fail; 2837 } 2838 2839 /* 5705 limits RX return ring to 512 entries. */ 2840 if (BGE_IS_5705_PLUS(sc)) 2841 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2842 else 2843 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2844 2845 if (bge_dma_alloc(sc)) { 2846 device_printf(sc->bge_dev, 2847 "failed to allocate DMA resources\n"); 2848 error = ENXIO; 2849 goto fail; 2850 } 2851 2852 bge_add_sysctls(sc); 2853 2854 /* Set default tuneable values. */ 2855 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2856 sc->bge_rx_coal_ticks = 150; 2857 sc->bge_tx_coal_ticks = 150; 2858 sc->bge_rx_max_coal_bds = 10; 2859 sc->bge_tx_max_coal_bds = 10; 2860 2861 /* Initialize checksum features to use. */ 2862 sc->bge_csum_features = BGE_CSUM_FEATURES; 2863 if (sc->bge_forced_udpcsum != 0) 2864 sc->bge_csum_features |= CSUM_UDP; 2865 2866 /* Set up ifnet structure */ 2867 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2868 if (ifp == NULL) { 2869 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2870 error = ENXIO; 2871 goto fail; 2872 } 2873 ifp->if_softc = sc; 2874 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2875 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2876 ifp->if_ioctl = bge_ioctl; 2877 ifp->if_start = bge_start; 2878 ifp->if_init = bge_init; 2879 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2880 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2881 IFQ_SET_READY(&ifp->if_snd); 2882 ifp->if_hwassist = sc->bge_csum_features; 2883 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2884 IFCAP_VLAN_MTU; 2885 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) { 2886 ifp->if_hwassist |= CSUM_TSO; 2887 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 2888 } 2889 #ifdef IFCAP_VLAN_HWCSUM 2890 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2891 #endif 2892 ifp->if_capenable = ifp->if_capabilities; 2893 #ifdef DEVICE_POLLING 2894 ifp->if_capabilities |= IFCAP_POLLING; 2895 #endif 2896 2897 /* 2898 * 5700 B0 chips do not support checksumming correctly due 2899 * to hardware bugs. 2900 */ 2901 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2902 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2903 ifp->if_capenable &= ~IFCAP_HWCSUM; 2904 ifp->if_hwassist = 0; 2905 } 2906 2907 /* 2908 * Figure out what sort of media we have by checking the 2909 * hardware config word in the first 32k of NIC internal memory, 2910 * or fall back to examining the EEPROM if necessary. 2911 * Note: on some BCM5700 cards, this value appears to be unset. 2912 * If that's the case, we have to rely on identifying the NIC 2913 * by its PCI subsystem ID, as we do below for the SysKonnect 2914 * SK-9D41. 2915 */ 2916 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2917 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2918 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2919 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2920 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2921 sizeof(hwcfg))) { 2922 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2923 error = ENXIO; 2924 goto fail; 2925 } 2926 hwcfg = ntohl(hwcfg); 2927 } 2928 2929 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2930 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 2931 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2932 if (BGE_IS_5714_FAMILY(sc)) 2933 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2934 else 2935 sc->bge_flags |= BGE_FLAG_TBI; 2936 } 2937 2938 if (sc->bge_flags & BGE_FLAG_TBI) { 2939 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2940 bge_ifmedia_sts); 2941 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2942 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2943 0, NULL); 2944 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2945 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2946 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2947 } else { 2948 /* 2949 * Do transceiver setup and tell the firmware the 2950 * driver is down so we can try to get access the 2951 * probe if ASF is running. Retry a couple of times 2952 * if we get a conflict with the ASF firmware accessing 2953 * the PHY. 2954 */ 2955 trys = 0; 2956 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2957 again: 2958 bge_asf_driver_up(sc); 2959 2960 error = (mii_attach(dev, &sc->bge_miibus, ifp, 2961 bge_ifmedia_upd, bge_ifmedia_sts, BMSR_DEFCAPMASK, 2962 phy_addr, MII_OFFSET_ANY, 0)); 2963 if (error != 0) { 2964 if (trys++ < 4) { 2965 device_printf(sc->bge_dev, "Try again\n"); 2966 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2967 BMCR_RESET); 2968 goto again; 2969 } 2970 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 2971 goto fail; 2972 } 2973 2974 /* 2975 * Now tell the firmware we are going up after probing the PHY 2976 */ 2977 if (sc->bge_asf_mode & ASF_STACKUP) 2978 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2979 } 2980 2981 /* 2982 * When using the BCM5701 in PCI-X mode, data corruption has 2983 * been observed in the first few bytes of some received packets. 2984 * Aligning the packet buffer in memory eliminates the corruption. 2985 * Unfortunately, this misaligns the packet payloads. On platforms 2986 * which do not support unaligned accesses, we will realign the 2987 * payloads by copying the received packets. 2988 */ 2989 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2990 sc->bge_flags & BGE_FLAG_PCIX) 2991 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2992 2993 /* 2994 * Call MI attach routine. 2995 */ 2996 ether_ifattach(ifp, eaddr); 2997 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2998 2999 /* Tell upper layer we support long frames. */ 3000 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3001 3002 /* 3003 * Hookup IRQ last. 3004 */ 3005 #if __FreeBSD_version > 700030 3006 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3007 /* Take advantage of single-shot MSI. */ 3008 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3009 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3010 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3011 taskqueue_thread_enqueue, &sc->bge_tq); 3012 if (sc->bge_tq == NULL) { 3013 device_printf(dev, "could not create taskqueue.\n"); 3014 ether_ifdetach(ifp); 3015 error = ENXIO; 3016 goto fail; 3017 } 3018 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 3019 device_get_nameunit(sc->bge_dev)); 3020 error = bus_setup_intr(dev, sc->bge_irq, 3021 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3022 &sc->bge_intrhand); 3023 if (error) 3024 ether_ifdetach(ifp); 3025 } else 3026 error = bus_setup_intr(dev, sc->bge_irq, 3027 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3028 &sc->bge_intrhand); 3029 #else 3030 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 3031 bge_intr, sc, &sc->bge_intrhand); 3032 #endif 3033 3034 if (error) { 3035 bge_detach(dev); 3036 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3037 } 3038 3039 return (0); 3040 3041 fail: 3042 bge_release_resources(sc); 3043 3044 return (error); 3045 } 3046 3047 static int 3048 bge_detach(device_t dev) 3049 { 3050 struct bge_softc *sc; 3051 struct ifnet *ifp; 3052 3053 sc = device_get_softc(dev); 3054 ifp = sc->bge_ifp; 3055 3056 #ifdef DEVICE_POLLING 3057 if (ifp->if_capenable & IFCAP_POLLING) 3058 ether_poll_deregister(ifp); 3059 #endif 3060 3061 BGE_LOCK(sc); 3062 bge_stop(sc); 3063 bge_reset(sc); 3064 BGE_UNLOCK(sc); 3065 3066 callout_drain(&sc->bge_stat_ch); 3067 3068 if (sc->bge_tq) 3069 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3070 ether_ifdetach(ifp); 3071 3072 if (sc->bge_flags & BGE_FLAG_TBI) { 3073 ifmedia_removeall(&sc->bge_ifmedia); 3074 } else { 3075 bus_generic_detach(dev); 3076 device_delete_child(dev, sc->bge_miibus); 3077 } 3078 3079 bge_release_resources(sc); 3080 3081 return (0); 3082 } 3083 3084 static void 3085 bge_release_resources(struct bge_softc *sc) 3086 { 3087 device_t dev; 3088 3089 dev = sc->bge_dev; 3090 3091 if (sc->bge_tq != NULL) 3092 taskqueue_free(sc->bge_tq); 3093 3094 if (sc->bge_intrhand != NULL) 3095 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3096 3097 if (sc->bge_irq != NULL) 3098 bus_release_resource(dev, SYS_RES_IRQ, 3099 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3100 3101 if (sc->bge_flags & BGE_FLAG_MSI) 3102 pci_release_msi(dev); 3103 3104 if (sc->bge_res != NULL) 3105 bus_release_resource(dev, SYS_RES_MEMORY, 3106 PCIR_BAR(0), sc->bge_res); 3107 3108 if (sc->bge_ifp != NULL) 3109 if_free(sc->bge_ifp); 3110 3111 bge_dma_free(sc); 3112 3113 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3114 BGE_LOCK_DESTROY(sc); 3115 } 3116 3117 static int 3118 bge_reset(struct bge_softc *sc) 3119 { 3120 device_t dev; 3121 uint32_t cachesize, command, pcistate, reset, val; 3122 void (*write_op)(struct bge_softc *, int, int); 3123 uint16_t devctl; 3124 int i; 3125 3126 dev = sc->bge_dev; 3127 3128 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3129 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3130 if (sc->bge_flags & BGE_FLAG_PCIE) 3131 write_op = bge_writemem_direct; 3132 else 3133 write_op = bge_writemem_ind; 3134 } else 3135 write_op = bge_writereg_ind; 3136 3137 /* Save some important PCI state. */ 3138 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3139 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3140 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3141 3142 pci_write_config(dev, BGE_PCI_MISC_CTL, 3143 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3144 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3145 3146 /* Disable fastboot on controllers that support it. */ 3147 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3148 BGE_IS_5755_PLUS(sc)) { 3149 if (bootverbose) 3150 device_printf(dev, "Disabling fastboot\n"); 3151 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3152 } 3153 3154 /* 3155 * Write the magic number to SRAM at offset 0xB50. 3156 * When firmware finishes its initialization it will 3157 * write ~BGE_MAGIC_NUMBER to the same location. 3158 */ 3159 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3160 3161 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3162 3163 /* XXX: Broadcom Linux driver. */ 3164 if (sc->bge_flags & BGE_FLAG_PCIE) { 3165 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3166 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3167 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3168 /* Prevent PCIE link training during global reset */ 3169 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3170 reset |= 1 << 29; 3171 } 3172 } 3173 3174 /* 3175 * Set GPHY Power Down Override to leave GPHY 3176 * powered up in D0 uninitialized. 3177 */ 3178 if (BGE_IS_5705_PLUS(sc)) 3179 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3180 3181 /* Issue global reset */ 3182 write_op(sc, BGE_MISC_CFG, reset); 3183 3184 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3185 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3186 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3187 val | BGE_VCPU_STATUS_DRV_RESET); 3188 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3189 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3190 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3191 } 3192 3193 DELAY(1000); 3194 3195 /* XXX: Broadcom Linux driver. */ 3196 if (sc->bge_flags & BGE_FLAG_PCIE) { 3197 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3198 DELAY(500000); /* wait for link training to complete */ 3199 val = pci_read_config(dev, 0xC4, 4); 3200 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3201 } 3202 devctl = pci_read_config(dev, 3203 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3204 /* Clear enable no snoop and disable relaxed ordering. */ 3205 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3206 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3207 /* Set PCIE max payload size to 128. */ 3208 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3209 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3210 devctl, 2); 3211 /* Clear error status. */ 3212 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3213 PCIM_EXP_STA_CORRECTABLE_ERROR | 3214 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3215 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3216 } 3217 3218 /* Reset some of the PCI state that got zapped by reset. */ 3219 pci_write_config(dev, BGE_PCI_MISC_CTL, 3220 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3221 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3222 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3223 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3224 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3225 /* 3226 * Disable PCI-X relaxed ordering to ensure status block update 3227 * comes first then packet buffer DMA. Otherwise driver may 3228 * read stale status block. 3229 */ 3230 if (sc->bge_flags & BGE_FLAG_PCIX) { 3231 devctl = pci_read_config(dev, 3232 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3233 devctl &= ~PCIXM_COMMAND_ERO; 3234 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3235 devctl &= ~PCIXM_COMMAND_MAX_READ; 3236 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3237 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3238 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3239 PCIXM_COMMAND_MAX_READ); 3240 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3241 } 3242 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3243 devctl, 2); 3244 } 3245 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 3246 if (BGE_IS_5714_FAMILY(sc)) { 3247 /* This chip disables MSI on reset. */ 3248 if (sc->bge_flags & BGE_FLAG_MSI) { 3249 val = pci_read_config(dev, 3250 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3251 pci_write_config(dev, 3252 sc->bge_msicap + PCIR_MSI_CTRL, 3253 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3254 val = CSR_READ_4(sc, BGE_MSI_MODE); 3255 CSR_WRITE_4(sc, BGE_MSI_MODE, 3256 val | BGE_MSIMODE_ENABLE); 3257 } 3258 val = CSR_READ_4(sc, BGE_MARB_MODE); 3259 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3260 } else 3261 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3262 3263 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3264 for (i = 0; i < BGE_TIMEOUT; i++) { 3265 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3266 if (val & BGE_VCPU_STATUS_INIT_DONE) 3267 break; 3268 DELAY(100); 3269 } 3270 if (i == BGE_TIMEOUT) { 3271 device_printf(dev, "reset timed out\n"); 3272 return (1); 3273 } 3274 } else { 3275 /* 3276 * Poll until we see the 1's complement of the magic number. 3277 * This indicates that the firmware initialization is complete. 3278 * We expect this to fail if no chip containing the Ethernet 3279 * address is fitted though. 3280 */ 3281 for (i = 0; i < BGE_TIMEOUT; i++) { 3282 DELAY(10); 3283 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3284 if (val == ~BGE_MAGIC_NUMBER) 3285 break; 3286 } 3287 3288 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3289 device_printf(dev, 3290 "firmware handshake timed out, found 0x%08x\n", 3291 val); 3292 } 3293 3294 /* 3295 * XXX Wait for the value of the PCISTATE register to 3296 * return to its original pre-reset state. This is a 3297 * fairly good indicator of reset completion. If we don't 3298 * wait for the reset to fully complete, trying to read 3299 * from the device's non-PCI registers may yield garbage 3300 * results. 3301 */ 3302 for (i = 0; i < BGE_TIMEOUT; i++) { 3303 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3304 break; 3305 DELAY(10); 3306 } 3307 3308 /* Fix up byte swapping. */ 3309 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 3310 BGE_MODECTL_BYTESWAP_DATA); 3311 3312 /* Tell the ASF firmware we are up */ 3313 if (sc->bge_asf_mode & ASF_STACKUP) 3314 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3315 3316 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3317 3318 /* 3319 * The 5704 in TBI mode apparently needs some special 3320 * adjustment to insure the SERDES drive level is set 3321 * to 1.2V. 3322 */ 3323 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3324 sc->bge_flags & BGE_FLAG_TBI) { 3325 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3326 val = (val & ~0xFFF) | 0x880; 3327 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3328 } 3329 3330 /* XXX: Broadcom Linux driver. */ 3331 if (sc->bge_flags & BGE_FLAG_PCIE && 3332 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3333 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3334 /* Enable Data FIFO protection. */ 3335 val = CSR_READ_4(sc, 0x7C00); 3336 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3337 } 3338 DELAY(10000); 3339 3340 return (0); 3341 } 3342 3343 static __inline void 3344 bge_rxreuse_std(struct bge_softc *sc, int i) 3345 { 3346 struct bge_rx_bd *r; 3347 3348 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3349 r->bge_flags = BGE_RXBDFLAG_END; 3350 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3351 r->bge_idx = i; 3352 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3353 } 3354 3355 static __inline void 3356 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3357 { 3358 struct bge_extrx_bd *r; 3359 3360 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3361 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3362 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3363 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3364 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3365 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3366 r->bge_idx = i; 3367 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3368 } 3369 3370 /* 3371 * Frame reception handling. This is called if there's a frame 3372 * on the receive return list. 3373 * 3374 * Note: we have to be able to handle two possibilities here: 3375 * 1) the frame is from the jumbo receive ring 3376 * 2) the frame is from the standard receive ring 3377 */ 3378 3379 static int 3380 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3381 { 3382 struct ifnet *ifp; 3383 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3384 uint16_t rx_cons; 3385 3386 rx_cons = sc->bge_rx_saved_considx; 3387 3388 /* Nothing to do. */ 3389 if (rx_cons == rx_prod) 3390 return (rx_npkts); 3391 3392 ifp = sc->bge_ifp; 3393 3394 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3395 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3396 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3397 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3398 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3399 (MCLBYTES - ETHER_ALIGN)) 3400 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3401 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3402 3403 while (rx_cons != rx_prod) { 3404 struct bge_rx_bd *cur_rx; 3405 uint32_t rxidx; 3406 struct mbuf *m = NULL; 3407 uint16_t vlan_tag = 0; 3408 int have_tag = 0; 3409 3410 #ifdef DEVICE_POLLING 3411 if (ifp->if_capenable & IFCAP_POLLING) { 3412 if (sc->rxcycles <= 0) 3413 break; 3414 sc->rxcycles--; 3415 } 3416 #endif 3417 3418 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3419 3420 rxidx = cur_rx->bge_idx; 3421 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3422 3423 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3424 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3425 have_tag = 1; 3426 vlan_tag = cur_rx->bge_vlan_tag; 3427 } 3428 3429 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3430 jumbocnt++; 3431 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3432 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3433 bge_rxreuse_jumbo(sc, rxidx); 3434 continue; 3435 } 3436 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3437 bge_rxreuse_jumbo(sc, rxidx); 3438 ifp->if_iqdrops++; 3439 continue; 3440 } 3441 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3442 } else { 3443 stdcnt++; 3444 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3445 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3446 bge_rxreuse_std(sc, rxidx); 3447 continue; 3448 } 3449 if (bge_newbuf_std(sc, rxidx) != 0) { 3450 bge_rxreuse_std(sc, rxidx); 3451 ifp->if_iqdrops++; 3452 continue; 3453 } 3454 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3455 } 3456 3457 ifp->if_ipackets++; 3458 #ifndef __NO_STRICT_ALIGNMENT 3459 /* 3460 * For architectures with strict alignment we must make sure 3461 * the payload is aligned. 3462 */ 3463 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3464 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3465 cur_rx->bge_len); 3466 m->m_data += ETHER_ALIGN; 3467 } 3468 #endif 3469 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3470 m->m_pkthdr.rcvif = ifp; 3471 3472 if (ifp->if_capenable & IFCAP_RXCSUM) { 3473 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3474 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3475 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3476 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3477 } 3478 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3479 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3480 m->m_pkthdr.csum_data = 3481 cur_rx->bge_tcp_udp_csum; 3482 m->m_pkthdr.csum_flags |= 3483 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3484 } 3485 } 3486 3487 /* 3488 * If we received a packet with a vlan tag, 3489 * attach that information to the packet. 3490 */ 3491 if (have_tag) { 3492 #if __FreeBSD_version > 700022 3493 m->m_pkthdr.ether_vtag = vlan_tag; 3494 m->m_flags |= M_VLANTAG; 3495 #else 3496 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3497 if (m == NULL) 3498 continue; 3499 #endif 3500 } 3501 3502 if (holdlck != 0) { 3503 BGE_UNLOCK(sc); 3504 (*ifp->if_input)(ifp, m); 3505 BGE_LOCK(sc); 3506 } else 3507 (*ifp->if_input)(ifp, m); 3508 rx_npkts++; 3509 3510 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3511 return (rx_npkts); 3512 } 3513 3514 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3515 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3516 if (stdcnt > 0) 3517 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3518 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3519 3520 if (jumbocnt > 0) 3521 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3522 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3523 3524 sc->bge_rx_saved_considx = rx_cons; 3525 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3526 if (stdcnt) 3527 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 3528 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 3529 if (jumbocnt) 3530 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 3531 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 3532 #ifdef notyet 3533 /* 3534 * This register wraps very quickly under heavy packet drops. 3535 * If you need correct statistics, you can enable this check. 3536 */ 3537 if (BGE_IS_5705_PLUS(sc)) 3538 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3539 #endif 3540 return (rx_npkts); 3541 } 3542 3543 static void 3544 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3545 { 3546 struct bge_tx_bd *cur_tx; 3547 struct ifnet *ifp; 3548 3549 BGE_LOCK_ASSERT(sc); 3550 3551 /* Nothing to do. */ 3552 if (sc->bge_tx_saved_considx == tx_cons) 3553 return; 3554 3555 ifp = sc->bge_ifp; 3556 3557 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3558 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3559 /* 3560 * Go through our tx ring and free mbufs for those 3561 * frames that have been sent. 3562 */ 3563 while (sc->bge_tx_saved_considx != tx_cons) { 3564 uint32_t idx; 3565 3566 idx = sc->bge_tx_saved_considx; 3567 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3568 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3569 ifp->if_opackets++; 3570 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3571 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3572 sc->bge_cdata.bge_tx_dmamap[idx], 3573 BUS_DMASYNC_POSTWRITE); 3574 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3575 sc->bge_cdata.bge_tx_dmamap[idx]); 3576 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3577 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3578 } 3579 sc->bge_txcnt--; 3580 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3581 } 3582 3583 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3584 if (sc->bge_txcnt == 0) 3585 sc->bge_timer = 0; 3586 } 3587 3588 #ifdef DEVICE_POLLING 3589 static int 3590 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3591 { 3592 struct bge_softc *sc = ifp->if_softc; 3593 uint16_t rx_prod, tx_cons; 3594 uint32_t statusword; 3595 int rx_npkts = 0; 3596 3597 BGE_LOCK(sc); 3598 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3599 BGE_UNLOCK(sc); 3600 return (rx_npkts); 3601 } 3602 3603 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3604 sc->bge_cdata.bge_status_map, 3605 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3606 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3607 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3608 3609 statusword = sc->bge_ldata.bge_status_block->bge_status; 3610 sc->bge_ldata.bge_status_block->bge_status = 0; 3611 3612 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3613 sc->bge_cdata.bge_status_map, 3614 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3615 3616 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3617 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3618 sc->bge_link_evt++; 3619 3620 if (cmd == POLL_AND_CHECK_STATUS) 3621 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3622 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3623 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3624 bge_link_upd(sc); 3625 3626 sc->rxcycles = count; 3627 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3628 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3629 BGE_UNLOCK(sc); 3630 return (rx_npkts); 3631 } 3632 bge_txeof(sc, tx_cons); 3633 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3634 bge_start_locked(ifp); 3635 3636 BGE_UNLOCK(sc); 3637 return (rx_npkts); 3638 } 3639 #endif /* DEVICE_POLLING */ 3640 3641 static int 3642 bge_msi_intr(void *arg) 3643 { 3644 struct bge_softc *sc; 3645 3646 sc = (struct bge_softc *)arg; 3647 /* 3648 * This interrupt is not shared and controller already 3649 * disabled further interrupt. 3650 */ 3651 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3652 return (FILTER_HANDLED); 3653 } 3654 3655 static void 3656 bge_intr_task(void *arg, int pending) 3657 { 3658 struct bge_softc *sc; 3659 struct ifnet *ifp; 3660 uint32_t status; 3661 uint16_t rx_prod, tx_cons; 3662 3663 sc = (struct bge_softc *)arg; 3664 ifp = sc->bge_ifp; 3665 3666 BGE_LOCK(sc); 3667 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3668 BGE_UNLOCK(sc); 3669 return; 3670 } 3671 3672 /* Get updated status block. */ 3673 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3674 sc->bge_cdata.bge_status_map, 3675 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3676 3677 /* Save producer/consumer indexess. */ 3678 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3679 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3680 status = sc->bge_ldata.bge_status_block->bge_status; 3681 sc->bge_ldata.bge_status_block->bge_status = 0; 3682 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3683 sc->bge_cdata.bge_status_map, 3684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3685 3686 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 3687 bge_link_upd(sc); 3688 3689 /* Let controller work. */ 3690 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3691 3692 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3693 sc->bge_rx_saved_considx != rx_prod) { 3694 /* Check RX return ring producer/consumer. */ 3695 BGE_UNLOCK(sc); 3696 bge_rxeof(sc, rx_prod, 0); 3697 BGE_LOCK(sc); 3698 } 3699 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3700 /* Check TX ring producer/consumer. */ 3701 bge_txeof(sc, tx_cons); 3702 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3703 bge_start_locked(ifp); 3704 } 3705 BGE_UNLOCK(sc); 3706 } 3707 3708 static void 3709 bge_intr(void *xsc) 3710 { 3711 struct bge_softc *sc; 3712 struct ifnet *ifp; 3713 uint32_t statusword; 3714 uint16_t rx_prod, tx_cons; 3715 3716 sc = xsc; 3717 3718 BGE_LOCK(sc); 3719 3720 ifp = sc->bge_ifp; 3721 3722 #ifdef DEVICE_POLLING 3723 if (ifp->if_capenable & IFCAP_POLLING) { 3724 BGE_UNLOCK(sc); 3725 return; 3726 } 3727 #endif 3728 3729 /* 3730 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3731 * disable interrupts by writing nonzero like we used to, since with 3732 * our current organization this just gives complications and 3733 * pessimizations for re-enabling interrupts. We used to have races 3734 * instead of the necessary complications. Disabling interrupts 3735 * would just reduce the chance of a status update while we are 3736 * running (by switching to the interrupt-mode coalescence 3737 * parameters), but this chance is already very low so it is more 3738 * efficient to get another interrupt than prevent it. 3739 * 3740 * We do the ack first to ensure another interrupt if there is a 3741 * status update after the ack. We don't check for the status 3742 * changing later because it is more efficient to get another 3743 * interrupt than prevent it, not quite as above (not checking is 3744 * a smaller optimization than not toggling the interrupt enable, 3745 * since checking doesn't involve PCI accesses and toggling require 3746 * the status check). So toggling would probably be a pessimization 3747 * even with MSI. It would only be needed for using a task queue. 3748 */ 3749 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3750 3751 /* 3752 * Do the mandatory PCI flush as well as get the link status. 3753 */ 3754 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3755 3756 /* Make sure the descriptor ring indexes are coherent. */ 3757 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3758 sc->bge_cdata.bge_status_map, 3759 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3760 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3761 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3762 sc->bge_ldata.bge_status_block->bge_status = 0; 3763 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3764 sc->bge_cdata.bge_status_map, 3765 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3766 3767 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3768 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3769 statusword || sc->bge_link_evt) 3770 bge_link_upd(sc); 3771 3772 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3773 /* Check RX return ring producer/consumer. */ 3774 bge_rxeof(sc, rx_prod, 1); 3775 } 3776 3777 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3778 /* Check TX ring producer/consumer. */ 3779 bge_txeof(sc, tx_cons); 3780 } 3781 3782 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3783 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3784 bge_start_locked(ifp); 3785 3786 BGE_UNLOCK(sc); 3787 } 3788 3789 static void 3790 bge_asf_driver_up(struct bge_softc *sc) 3791 { 3792 if (sc->bge_asf_mode & ASF_STACKUP) { 3793 /* Send ASF heartbeat aprox. every 2s */ 3794 if (sc->bge_asf_count) 3795 sc->bge_asf_count --; 3796 else { 3797 sc->bge_asf_count = 2; 3798 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3799 BGE_FW_DRV_ALIVE); 3800 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3801 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3802 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3803 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3804 } 3805 } 3806 } 3807 3808 static void 3809 bge_tick(void *xsc) 3810 { 3811 struct bge_softc *sc = xsc; 3812 struct mii_data *mii = NULL; 3813 3814 BGE_LOCK_ASSERT(sc); 3815 3816 /* Synchronize with possible callout reset/stop. */ 3817 if (callout_pending(&sc->bge_stat_ch) || 3818 !callout_active(&sc->bge_stat_ch)) 3819 return; 3820 3821 if (BGE_IS_5705_PLUS(sc)) 3822 bge_stats_update_regs(sc); 3823 else 3824 bge_stats_update(sc); 3825 3826 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3827 mii = device_get_softc(sc->bge_miibus); 3828 /* 3829 * Do not touch PHY if we have link up. This could break 3830 * IPMI/ASF mode or produce extra input errors 3831 * (extra errors was reported for bcm5701 & bcm5704). 3832 */ 3833 if (!sc->bge_link) 3834 mii_tick(mii); 3835 } else { 3836 /* 3837 * Since in TBI mode auto-polling can't be used we should poll 3838 * link status manually. Here we register pending link event 3839 * and trigger interrupt. 3840 */ 3841 #ifdef DEVICE_POLLING 3842 /* In polling mode we poll link state in bge_poll(). */ 3843 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3844 #endif 3845 { 3846 sc->bge_link_evt++; 3847 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3848 sc->bge_flags & BGE_FLAG_5788) 3849 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3850 else 3851 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3852 } 3853 } 3854 3855 bge_asf_driver_up(sc); 3856 bge_watchdog(sc); 3857 3858 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3859 } 3860 3861 static void 3862 bge_stats_update_regs(struct bge_softc *sc) 3863 { 3864 struct ifnet *ifp; 3865 struct bge_mac_stats *stats; 3866 3867 ifp = sc->bge_ifp; 3868 stats = &sc->bge_mac_stats; 3869 3870 stats->ifHCOutOctets += 3871 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 3872 stats->etherStatsCollisions += 3873 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 3874 stats->outXonSent += 3875 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 3876 stats->outXoffSent += 3877 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 3878 stats->dot3StatsInternalMacTransmitErrors += 3879 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 3880 stats->dot3StatsSingleCollisionFrames += 3881 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 3882 stats->dot3StatsMultipleCollisionFrames += 3883 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 3884 stats->dot3StatsDeferredTransmissions += 3885 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 3886 stats->dot3StatsExcessiveCollisions += 3887 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 3888 stats->dot3StatsLateCollisions += 3889 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 3890 stats->ifHCOutUcastPkts += 3891 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 3892 stats->ifHCOutMulticastPkts += 3893 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 3894 stats->ifHCOutBroadcastPkts += 3895 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 3896 3897 stats->ifHCInOctets += 3898 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 3899 stats->etherStatsFragments += 3900 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 3901 stats->ifHCInUcastPkts += 3902 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 3903 stats->ifHCInMulticastPkts += 3904 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 3905 stats->ifHCInBroadcastPkts += 3906 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 3907 stats->dot3StatsFCSErrors += 3908 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 3909 stats->dot3StatsAlignmentErrors += 3910 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 3911 stats->xonPauseFramesReceived += 3912 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 3913 stats->xoffPauseFramesReceived += 3914 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 3915 stats->macControlFramesReceived += 3916 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 3917 stats->xoffStateEntered += 3918 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 3919 stats->dot3StatsFramesTooLong += 3920 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 3921 stats->etherStatsJabbers += 3922 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 3923 stats->etherStatsUndersizePkts += 3924 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 3925 3926 stats->FramesDroppedDueToFilters += 3927 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 3928 stats->DmaWriteQueueFull += 3929 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 3930 stats->DmaWriteHighPriQueueFull += 3931 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 3932 stats->NoMoreRxBDs += 3933 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3934 stats->InputDiscards += 3935 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3936 stats->InputErrors += 3937 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3938 stats->RecvThresholdHit += 3939 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 3940 3941 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 3942 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 3943 stats->InputErrors); 3944 } 3945 3946 static void 3947 bge_stats_clear_regs(struct bge_softc *sc) 3948 { 3949 3950 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 3951 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 3952 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 3953 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 3954 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 3955 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 3956 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 3957 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 3958 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 3959 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 3960 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 3961 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 3962 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 3963 3964 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 3965 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 3966 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 3967 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 3968 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 3969 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 3970 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 3971 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 3972 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 3973 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 3974 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 3975 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 3976 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 3977 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 3978 3979 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 3980 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 3981 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 3982 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3983 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3984 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3985 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 3986 } 3987 3988 static void 3989 bge_stats_update(struct bge_softc *sc) 3990 { 3991 struct ifnet *ifp; 3992 bus_size_t stats; 3993 uint32_t cnt; /* current register value */ 3994 3995 ifp = sc->bge_ifp; 3996 3997 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3998 3999 #define READ_STAT(sc, stats, stat) \ 4000 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4001 4002 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4003 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4004 sc->bge_tx_collisions = cnt; 4005 4006 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4007 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4008 sc->bge_rx_discards = cnt; 4009 4010 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4011 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4012 sc->bge_tx_discards = cnt; 4013 4014 #undef READ_STAT 4015 } 4016 4017 /* 4018 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4019 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4020 * but when such padded frames employ the bge IP/TCP checksum offload, 4021 * the hardware checksum assist gives incorrect results (possibly 4022 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4023 * If we pad such runts with zeros, the onboard checksum comes out correct. 4024 */ 4025 static __inline int 4026 bge_cksum_pad(struct mbuf *m) 4027 { 4028 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4029 struct mbuf *last; 4030 4031 /* If there's only the packet-header and we can pad there, use it. */ 4032 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4033 M_TRAILINGSPACE(m) >= padlen) { 4034 last = m; 4035 } else { 4036 /* 4037 * Walk packet chain to find last mbuf. We will either 4038 * pad there, or append a new mbuf and pad it. 4039 */ 4040 for (last = m; last->m_next != NULL; last = last->m_next); 4041 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4042 /* Allocate new empty mbuf, pad it. Compact later. */ 4043 struct mbuf *n; 4044 4045 MGET(n, M_DONTWAIT, MT_DATA); 4046 if (n == NULL) 4047 return (ENOBUFS); 4048 n->m_len = 0; 4049 last->m_next = n; 4050 last = n; 4051 } 4052 } 4053 4054 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4055 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4056 last->m_len += padlen; 4057 m->m_pkthdr.len += padlen; 4058 4059 return (0); 4060 } 4061 4062 static struct mbuf * 4063 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss) 4064 { 4065 struct ip *ip; 4066 struct tcphdr *tcp; 4067 struct mbuf *n; 4068 uint16_t hlen; 4069 uint32_t poff; 4070 4071 if (M_WRITABLE(m) == 0) { 4072 /* Get a writable copy. */ 4073 n = m_dup(m, M_DONTWAIT); 4074 m_freem(m); 4075 if (n == NULL) 4076 return (NULL); 4077 m = n; 4078 } 4079 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 4080 if (m == NULL) 4081 return (NULL); 4082 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4083 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 4084 m = m_pullup(m, poff + sizeof(struct tcphdr)); 4085 if (m == NULL) 4086 return (NULL); 4087 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4088 m = m_pullup(m, poff + (tcp->th_off << 2)); 4089 if (m == NULL) 4090 return (NULL); 4091 /* 4092 * It seems controller doesn't modify IP length and TCP pseudo 4093 * checksum. These checksum computed by upper stack should be 0. 4094 */ 4095 *mss = m->m_pkthdr.tso_segsz; 4096 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4097 ip->ip_sum = 0; 4098 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 4099 /* Clear pseudo checksum computed by TCP stack. */ 4100 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4101 tcp->th_sum = 0; 4102 /* 4103 * Broadcom controllers uses different descriptor format for 4104 * TSO depending on ASIC revision. Due to TSO-capable firmware 4105 * license issue and lower performance of firmware based TSO 4106 * we only support hardware based TSO which is applicable for 4107 * BCM5755 or newer controllers. Hardware based TSO uses 11 4108 * bits to store MSS and upper 5 bits are used to store IP/TCP 4109 * header length(including IP/TCP options). The header length 4110 * is expressed as 32 bits unit. 4111 */ 4112 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 4113 *mss |= (hlen << 11); 4114 return (m); 4115 } 4116 4117 /* 4118 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4119 * pointers to descriptors. 4120 */ 4121 static int 4122 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 4123 { 4124 bus_dma_segment_t segs[BGE_NSEG_NEW]; 4125 bus_dmamap_t map; 4126 struct bge_tx_bd *d; 4127 struct mbuf *m = *m_head; 4128 uint32_t idx = *txidx; 4129 uint16_t csum_flags, mss, vlan_tag; 4130 int nsegs, i, error; 4131 4132 csum_flags = 0; 4133 mss = 0; 4134 vlan_tag = 0; 4135 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 4136 *m_head = m = bge_setup_tso(sc, m, &mss); 4137 if (*m_head == NULL) 4138 return (ENOBUFS); 4139 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 4140 BGE_TXBDFLAG_CPU_POST_DMA; 4141 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 4142 if (m->m_pkthdr.csum_flags & CSUM_IP) 4143 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4144 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 4145 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4146 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 4147 (error = bge_cksum_pad(m)) != 0) { 4148 m_freem(m); 4149 *m_head = NULL; 4150 return (error); 4151 } 4152 } 4153 if (m->m_flags & M_LASTFRAG) 4154 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 4155 else if (m->m_flags & M_FRAG) 4156 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 4157 } 4158 4159 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 4160 sc->bge_forced_collapse > 0 && 4161 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 4162 /* 4163 * Forcedly collapse mbuf chains to overcome hardware 4164 * limitation which only support a single outstanding 4165 * DMA read operation. 4166 */ 4167 if (sc->bge_forced_collapse == 1) 4168 m = m_defrag(m, M_DONTWAIT); 4169 else 4170 m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse); 4171 if (m == NULL) 4172 m = *m_head; 4173 *m_head = m; 4174 } 4175 4176 map = sc->bge_cdata.bge_tx_dmamap[idx]; 4177 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4178 &nsegs, BUS_DMA_NOWAIT); 4179 if (error == EFBIG) { 4180 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4181 if (m == NULL) { 4182 m_freem(*m_head); 4183 *m_head = NULL; 4184 return (ENOBUFS); 4185 } 4186 *m_head = m; 4187 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 4188 m, segs, &nsegs, BUS_DMA_NOWAIT); 4189 if (error) { 4190 m_freem(m); 4191 *m_head = NULL; 4192 return (error); 4193 } 4194 } else if (error != 0) 4195 return (error); 4196 4197 /* Check if we have enough free send BDs. */ 4198 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 4199 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 4200 return (ENOBUFS); 4201 } 4202 4203 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4204 4205 #if __FreeBSD_version > 700022 4206 if (m->m_flags & M_VLANTAG) { 4207 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4208 vlan_tag = m->m_pkthdr.ether_vtag; 4209 } 4210 #else 4211 { 4212 struct m_tag *mtag; 4213 4214 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 4215 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4216 vlan_tag = VLAN_TAG_VALUE(mtag); 4217 } 4218 } 4219 #endif 4220 for (i = 0; ; i++) { 4221 d = &sc->bge_ldata.bge_tx_ring[idx]; 4222 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 4223 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 4224 d->bge_len = segs[i].ds_len; 4225 d->bge_flags = csum_flags; 4226 d->bge_vlan_tag = vlan_tag; 4227 d->bge_mss = mss; 4228 if (i == nsegs - 1) 4229 break; 4230 BGE_INC(idx, BGE_TX_RING_CNT); 4231 } 4232 4233 /* Mark the last segment as end of packet... */ 4234 d->bge_flags |= BGE_TXBDFLAG_END; 4235 4236 /* 4237 * Insure that the map for this transmission 4238 * is placed at the array index of the last descriptor 4239 * in this chain. 4240 */ 4241 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4242 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4243 sc->bge_cdata.bge_tx_chain[idx] = m; 4244 sc->bge_txcnt += nsegs; 4245 4246 BGE_INC(idx, BGE_TX_RING_CNT); 4247 *txidx = idx; 4248 4249 return (0); 4250 } 4251 4252 /* 4253 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4254 * to the mbuf data regions directly in the transmit descriptors. 4255 */ 4256 static void 4257 bge_start_locked(struct ifnet *ifp) 4258 { 4259 struct bge_softc *sc; 4260 struct mbuf *m_head; 4261 uint32_t prodidx; 4262 int count; 4263 4264 sc = ifp->if_softc; 4265 BGE_LOCK_ASSERT(sc); 4266 4267 if (!sc->bge_link || 4268 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4269 IFF_DRV_RUNNING) 4270 return; 4271 4272 prodidx = sc->bge_tx_prodidx; 4273 4274 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4275 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4276 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4277 break; 4278 } 4279 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4280 if (m_head == NULL) 4281 break; 4282 4283 /* 4284 * XXX 4285 * The code inside the if() block is never reached since we 4286 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4287 * requests to checksum TCP/UDP in a fragmented packet. 4288 * 4289 * XXX 4290 * safety overkill. If this is a fragmented packet chain 4291 * with delayed TCP/UDP checksums, then only encapsulate 4292 * it if we have enough descriptors to handle the entire 4293 * chain at once. 4294 * (paranoia -- may not actually be needed) 4295 */ 4296 if (m_head->m_flags & M_FIRSTFRAG && 4297 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4298 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4299 m_head->m_pkthdr.csum_data + 16) { 4300 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4301 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4302 break; 4303 } 4304 } 4305 4306 /* 4307 * Pack the data into the transmit ring. If we 4308 * don't have room, set the OACTIVE flag and wait 4309 * for the NIC to drain the ring. 4310 */ 4311 if (bge_encap(sc, &m_head, &prodidx)) { 4312 if (m_head == NULL) 4313 break; 4314 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4315 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4316 break; 4317 } 4318 ++count; 4319 4320 /* 4321 * If there's a BPF listener, bounce a copy of this frame 4322 * to him. 4323 */ 4324 #ifdef ETHER_BPF_MTAP 4325 ETHER_BPF_MTAP(ifp, m_head); 4326 #else 4327 BPF_MTAP(ifp, m_head); 4328 #endif 4329 } 4330 4331 if (count > 0) { 4332 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4333 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4334 /* Transmit. */ 4335 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4336 /* 5700 b2 errata */ 4337 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4338 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4339 4340 sc->bge_tx_prodidx = prodidx; 4341 4342 /* 4343 * Set a timeout in case the chip goes out to lunch. 4344 */ 4345 sc->bge_timer = 5; 4346 } 4347 } 4348 4349 /* 4350 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4351 * to the mbuf data regions directly in the transmit descriptors. 4352 */ 4353 static void 4354 bge_start(struct ifnet *ifp) 4355 { 4356 struct bge_softc *sc; 4357 4358 sc = ifp->if_softc; 4359 BGE_LOCK(sc); 4360 bge_start_locked(ifp); 4361 BGE_UNLOCK(sc); 4362 } 4363 4364 static void 4365 bge_init_locked(struct bge_softc *sc) 4366 { 4367 struct ifnet *ifp; 4368 uint16_t *m; 4369 4370 BGE_LOCK_ASSERT(sc); 4371 4372 ifp = sc->bge_ifp; 4373 4374 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4375 return; 4376 4377 /* Cancel pending I/O and flush buffers. */ 4378 bge_stop(sc); 4379 4380 bge_stop_fw(sc); 4381 bge_sig_pre_reset(sc, BGE_RESET_START); 4382 bge_reset(sc); 4383 bge_sig_legacy(sc, BGE_RESET_START); 4384 bge_sig_post_reset(sc, BGE_RESET_START); 4385 4386 bge_chipinit(sc); 4387 4388 /* 4389 * Init the various state machines, ring 4390 * control blocks and firmware. 4391 */ 4392 if (bge_blockinit(sc)) { 4393 device_printf(sc->bge_dev, "initialization failure\n"); 4394 return; 4395 } 4396 4397 ifp = sc->bge_ifp; 4398 4399 /* Specify MTU. */ 4400 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4401 ETHER_HDR_LEN + ETHER_CRC_LEN + 4402 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4403 4404 /* Load our MAC address. */ 4405 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4406 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4407 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4408 4409 /* Program promiscuous mode. */ 4410 bge_setpromisc(sc); 4411 4412 /* Program multicast filter. */ 4413 bge_setmulti(sc); 4414 4415 /* Program VLAN tag stripping. */ 4416 bge_setvlan(sc); 4417 4418 /* Override UDP checksum offloading. */ 4419 if (sc->bge_forced_udpcsum == 0) 4420 sc->bge_csum_features &= ~CSUM_UDP; 4421 else 4422 sc->bge_csum_features |= CSUM_UDP; 4423 if (ifp->if_capabilities & IFCAP_TXCSUM && 4424 ifp->if_capenable & IFCAP_TXCSUM) { 4425 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 4426 ifp->if_hwassist |= sc->bge_csum_features; 4427 } 4428 4429 /* Init RX ring. */ 4430 if (bge_init_rx_ring_std(sc) != 0) { 4431 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4432 bge_stop(sc); 4433 return; 4434 } 4435 4436 /* 4437 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4438 * memory to insure that the chip has in fact read the first 4439 * entry of the ring. 4440 */ 4441 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4442 uint32_t v, i; 4443 for (i = 0; i < 10; i++) { 4444 DELAY(20); 4445 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4446 if (v == (MCLBYTES - ETHER_ALIGN)) 4447 break; 4448 } 4449 if (i == 10) 4450 device_printf (sc->bge_dev, 4451 "5705 A0 chip failed to load RX ring\n"); 4452 } 4453 4454 /* Init jumbo RX ring. */ 4455 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4456 (MCLBYTES - ETHER_ALIGN)) { 4457 if (bge_init_rx_ring_jumbo(sc) != 0) { 4458 device_printf(sc->bge_dev, 4459 "no memory for jumbo Rx buffers.\n"); 4460 bge_stop(sc); 4461 return; 4462 } 4463 } 4464 4465 /* Init our RX return ring index. */ 4466 sc->bge_rx_saved_considx = 0; 4467 4468 /* Init our RX/TX stat counters. */ 4469 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4470 4471 /* Init TX ring. */ 4472 bge_init_tx_ring(sc); 4473 4474 /* Turn on transmitter. */ 4475 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4476 4477 /* Turn on receiver. */ 4478 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4479 4480 /* 4481 * Set the number of good frames to receive after RX MBUF 4482 * Low Watermark has been reached. After the RX MAC receives 4483 * this number of frames, it will drop subsequent incoming 4484 * frames until the MBUF High Watermark is reached. 4485 */ 4486 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 4487 4488 /* Clear MAC statistics. */ 4489 if (BGE_IS_5705_PLUS(sc)) 4490 bge_stats_clear_regs(sc); 4491 4492 /* Tell firmware we're alive. */ 4493 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4494 4495 #ifdef DEVICE_POLLING 4496 /* Disable interrupts if we are polling. */ 4497 if (ifp->if_capenable & IFCAP_POLLING) { 4498 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4499 BGE_PCIMISCCTL_MASK_PCI_INTR); 4500 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4501 } else 4502 #endif 4503 4504 /* Enable host interrupts. */ 4505 { 4506 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4507 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4508 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4509 } 4510 4511 bge_ifmedia_upd_locked(ifp); 4512 4513 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4514 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4515 4516 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4517 } 4518 4519 static void 4520 bge_init(void *xsc) 4521 { 4522 struct bge_softc *sc = xsc; 4523 4524 BGE_LOCK(sc); 4525 bge_init_locked(sc); 4526 BGE_UNLOCK(sc); 4527 } 4528 4529 /* 4530 * Set media options. 4531 */ 4532 static int 4533 bge_ifmedia_upd(struct ifnet *ifp) 4534 { 4535 struct bge_softc *sc = ifp->if_softc; 4536 int res; 4537 4538 BGE_LOCK(sc); 4539 res = bge_ifmedia_upd_locked(ifp); 4540 BGE_UNLOCK(sc); 4541 4542 return (res); 4543 } 4544 4545 static int 4546 bge_ifmedia_upd_locked(struct ifnet *ifp) 4547 { 4548 struct bge_softc *sc = ifp->if_softc; 4549 struct mii_data *mii; 4550 struct mii_softc *miisc; 4551 struct ifmedia *ifm; 4552 4553 BGE_LOCK_ASSERT(sc); 4554 4555 ifm = &sc->bge_ifmedia; 4556 4557 /* If this is a 1000baseX NIC, enable the TBI port. */ 4558 if (sc->bge_flags & BGE_FLAG_TBI) { 4559 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4560 return (EINVAL); 4561 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4562 case IFM_AUTO: 4563 /* 4564 * The BCM5704 ASIC appears to have a special 4565 * mechanism for programming the autoneg 4566 * advertisement registers in TBI mode. 4567 */ 4568 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4569 uint32_t sgdig; 4570 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4571 if (sgdig & BGE_SGDIGSTS_DONE) { 4572 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4573 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4574 sgdig |= BGE_SGDIGCFG_AUTO | 4575 BGE_SGDIGCFG_PAUSE_CAP | 4576 BGE_SGDIGCFG_ASYM_PAUSE; 4577 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4578 sgdig | BGE_SGDIGCFG_SEND); 4579 DELAY(5); 4580 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4581 } 4582 } 4583 break; 4584 case IFM_1000_SX: 4585 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4586 BGE_CLRBIT(sc, BGE_MAC_MODE, 4587 BGE_MACMODE_HALF_DUPLEX); 4588 } else { 4589 BGE_SETBIT(sc, BGE_MAC_MODE, 4590 BGE_MACMODE_HALF_DUPLEX); 4591 } 4592 break; 4593 default: 4594 return (EINVAL); 4595 } 4596 return (0); 4597 } 4598 4599 sc->bge_link_evt++; 4600 mii = device_get_softc(sc->bge_miibus); 4601 if (mii->mii_instance) 4602 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4603 mii_phy_reset(miisc); 4604 mii_mediachg(mii); 4605 4606 /* 4607 * Force an interrupt so that we will call bge_link_upd 4608 * if needed and clear any pending link state attention. 4609 * Without this we are not getting any further interrupts 4610 * for link state changes and thus will not UP the link and 4611 * not be able to send in bge_start_locked. The only 4612 * way to get things working was to receive a packet and 4613 * get an RX intr. 4614 * bge_tick should help for fiber cards and we might not 4615 * need to do this here if BGE_FLAG_TBI is set but as 4616 * we poll for fiber anyway it should not harm. 4617 */ 4618 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4619 sc->bge_flags & BGE_FLAG_5788) 4620 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4621 else 4622 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4623 4624 return (0); 4625 } 4626 4627 /* 4628 * Report current media status. 4629 */ 4630 static void 4631 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4632 { 4633 struct bge_softc *sc = ifp->if_softc; 4634 struct mii_data *mii; 4635 4636 BGE_LOCK(sc); 4637 4638 if (sc->bge_flags & BGE_FLAG_TBI) { 4639 ifmr->ifm_status = IFM_AVALID; 4640 ifmr->ifm_active = IFM_ETHER; 4641 if (CSR_READ_4(sc, BGE_MAC_STS) & 4642 BGE_MACSTAT_TBI_PCS_SYNCHED) 4643 ifmr->ifm_status |= IFM_ACTIVE; 4644 else { 4645 ifmr->ifm_active |= IFM_NONE; 4646 BGE_UNLOCK(sc); 4647 return; 4648 } 4649 ifmr->ifm_active |= IFM_1000_SX; 4650 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4651 ifmr->ifm_active |= IFM_HDX; 4652 else 4653 ifmr->ifm_active |= IFM_FDX; 4654 BGE_UNLOCK(sc); 4655 return; 4656 } 4657 4658 mii = device_get_softc(sc->bge_miibus); 4659 mii_pollstat(mii); 4660 ifmr->ifm_active = mii->mii_media_active; 4661 ifmr->ifm_status = mii->mii_media_status; 4662 4663 BGE_UNLOCK(sc); 4664 } 4665 4666 static int 4667 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4668 { 4669 struct bge_softc *sc = ifp->if_softc; 4670 struct ifreq *ifr = (struct ifreq *) data; 4671 struct mii_data *mii; 4672 int flags, mask, error = 0; 4673 4674 switch (command) { 4675 case SIOCSIFMTU: 4676 BGE_LOCK(sc); 4677 if (ifr->ifr_mtu < ETHERMIN || 4678 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4679 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4680 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4681 ifr->ifr_mtu > ETHERMTU)) 4682 error = EINVAL; 4683 else if (ifp->if_mtu != ifr->ifr_mtu) { 4684 ifp->if_mtu = ifr->ifr_mtu; 4685 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4686 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4687 bge_init_locked(sc); 4688 } 4689 } 4690 BGE_UNLOCK(sc); 4691 break; 4692 case SIOCSIFFLAGS: 4693 BGE_LOCK(sc); 4694 if (ifp->if_flags & IFF_UP) { 4695 /* 4696 * If only the state of the PROMISC flag changed, 4697 * then just use the 'set promisc mode' command 4698 * instead of reinitializing the entire NIC. Doing 4699 * a full re-init means reloading the firmware and 4700 * waiting for it to start up, which may take a 4701 * second or two. Similarly for ALLMULTI. 4702 */ 4703 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4704 flags = ifp->if_flags ^ sc->bge_if_flags; 4705 if (flags & IFF_PROMISC) 4706 bge_setpromisc(sc); 4707 if (flags & IFF_ALLMULTI) 4708 bge_setmulti(sc); 4709 } else 4710 bge_init_locked(sc); 4711 } else { 4712 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4713 bge_stop(sc); 4714 } 4715 } 4716 sc->bge_if_flags = ifp->if_flags; 4717 BGE_UNLOCK(sc); 4718 error = 0; 4719 break; 4720 case SIOCADDMULTI: 4721 case SIOCDELMULTI: 4722 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4723 BGE_LOCK(sc); 4724 bge_setmulti(sc); 4725 BGE_UNLOCK(sc); 4726 error = 0; 4727 } 4728 break; 4729 case SIOCSIFMEDIA: 4730 case SIOCGIFMEDIA: 4731 if (sc->bge_flags & BGE_FLAG_TBI) { 4732 error = ifmedia_ioctl(ifp, ifr, 4733 &sc->bge_ifmedia, command); 4734 } else { 4735 mii = device_get_softc(sc->bge_miibus); 4736 error = ifmedia_ioctl(ifp, ifr, 4737 &mii->mii_media, command); 4738 } 4739 break; 4740 case SIOCSIFCAP: 4741 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4742 #ifdef DEVICE_POLLING 4743 if (mask & IFCAP_POLLING) { 4744 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4745 error = ether_poll_register(bge_poll, ifp); 4746 if (error) 4747 return (error); 4748 BGE_LOCK(sc); 4749 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4750 BGE_PCIMISCCTL_MASK_PCI_INTR); 4751 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4752 ifp->if_capenable |= IFCAP_POLLING; 4753 BGE_UNLOCK(sc); 4754 } else { 4755 error = ether_poll_deregister(ifp); 4756 /* Enable interrupt even in error case */ 4757 BGE_LOCK(sc); 4758 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4759 BGE_PCIMISCCTL_MASK_PCI_INTR); 4760 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4761 ifp->if_capenable &= ~IFCAP_POLLING; 4762 BGE_UNLOCK(sc); 4763 } 4764 } 4765 #endif 4766 if ((mask & IFCAP_TXCSUM) != 0 && 4767 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 4768 ifp->if_capenable ^= IFCAP_TXCSUM; 4769 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 4770 ifp->if_hwassist |= sc->bge_csum_features; 4771 else 4772 ifp->if_hwassist &= ~sc->bge_csum_features; 4773 } 4774 4775 if ((mask & IFCAP_RXCSUM) != 0 && 4776 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 4777 ifp->if_capenable ^= IFCAP_RXCSUM; 4778 4779 if ((mask & IFCAP_TSO4) != 0 && 4780 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 4781 ifp->if_capenable ^= IFCAP_TSO4; 4782 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 4783 ifp->if_hwassist |= CSUM_TSO; 4784 else 4785 ifp->if_hwassist &= ~CSUM_TSO; 4786 } 4787 4788 if (mask & IFCAP_VLAN_MTU) { 4789 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4790 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4791 bge_init(sc); 4792 } 4793 4794 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 4795 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 4796 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 4797 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 4798 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 4799 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4800 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 4801 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 4802 BGE_LOCK(sc); 4803 bge_setvlan(sc); 4804 BGE_UNLOCK(sc); 4805 } 4806 #ifdef VLAN_CAPABILITIES 4807 VLAN_CAPABILITIES(ifp); 4808 #endif 4809 break; 4810 default: 4811 error = ether_ioctl(ifp, command, data); 4812 break; 4813 } 4814 4815 return (error); 4816 } 4817 4818 static void 4819 bge_watchdog(struct bge_softc *sc) 4820 { 4821 struct ifnet *ifp; 4822 4823 BGE_LOCK_ASSERT(sc); 4824 4825 if (sc->bge_timer == 0 || --sc->bge_timer) 4826 return; 4827 4828 ifp = sc->bge_ifp; 4829 4830 if_printf(ifp, "watchdog timeout -- resetting\n"); 4831 4832 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4833 bge_init_locked(sc); 4834 4835 ifp->if_oerrors++; 4836 } 4837 4838 /* 4839 * Stop the adapter and free any mbufs allocated to the 4840 * RX and TX lists. 4841 */ 4842 static void 4843 bge_stop(struct bge_softc *sc) 4844 { 4845 struct ifnet *ifp; 4846 4847 BGE_LOCK_ASSERT(sc); 4848 4849 ifp = sc->bge_ifp; 4850 4851 callout_stop(&sc->bge_stat_ch); 4852 4853 /* Disable host interrupts. */ 4854 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4855 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4856 4857 /* 4858 * Tell firmware we're shutting down. 4859 */ 4860 bge_stop_fw(sc); 4861 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4862 4863 /* 4864 * Disable all of the receiver blocks. 4865 */ 4866 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4867 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4868 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4869 if (!(BGE_IS_5705_PLUS(sc))) 4870 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4871 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4872 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4873 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4874 4875 /* 4876 * Disable all of the transmit blocks. 4877 */ 4878 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4879 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4880 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4881 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4882 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4883 if (!(BGE_IS_5705_PLUS(sc))) 4884 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4885 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4886 4887 /* 4888 * Shut down all of the memory managers and related 4889 * state machines. 4890 */ 4891 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4892 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4893 if (!(BGE_IS_5705_PLUS(sc))) 4894 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4895 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4896 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4897 if (!(BGE_IS_5705_PLUS(sc))) { 4898 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4899 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4900 } 4901 /* Update MAC statistics. */ 4902 if (BGE_IS_5705_PLUS(sc)) 4903 bge_stats_update_regs(sc); 4904 4905 bge_reset(sc); 4906 bge_sig_legacy(sc, BGE_RESET_STOP); 4907 bge_sig_post_reset(sc, BGE_RESET_STOP); 4908 4909 /* 4910 * Keep the ASF firmware running if up. 4911 */ 4912 if (sc->bge_asf_mode & ASF_STACKUP) 4913 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4914 else 4915 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4916 4917 /* Free the RX lists. */ 4918 bge_free_rx_ring_std(sc); 4919 4920 /* Free jumbo RX list. */ 4921 if (BGE_IS_JUMBO_CAPABLE(sc)) 4922 bge_free_rx_ring_jumbo(sc); 4923 4924 /* Free TX buffers. */ 4925 bge_free_tx_ring(sc); 4926 4927 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4928 4929 /* Clear MAC's link state (PHY may still have link UP). */ 4930 if (bootverbose && sc->bge_link) 4931 if_printf(sc->bge_ifp, "link DOWN\n"); 4932 sc->bge_link = 0; 4933 4934 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4935 } 4936 4937 /* 4938 * Stop all chip I/O so that the kernel's probe routines don't 4939 * get confused by errant DMAs when rebooting. 4940 */ 4941 static int 4942 bge_shutdown(device_t dev) 4943 { 4944 struct bge_softc *sc; 4945 4946 sc = device_get_softc(dev); 4947 BGE_LOCK(sc); 4948 bge_stop(sc); 4949 bge_reset(sc); 4950 BGE_UNLOCK(sc); 4951 4952 return (0); 4953 } 4954 4955 static int 4956 bge_suspend(device_t dev) 4957 { 4958 struct bge_softc *sc; 4959 4960 sc = device_get_softc(dev); 4961 BGE_LOCK(sc); 4962 bge_stop(sc); 4963 BGE_UNLOCK(sc); 4964 4965 return (0); 4966 } 4967 4968 static int 4969 bge_resume(device_t dev) 4970 { 4971 struct bge_softc *sc; 4972 struct ifnet *ifp; 4973 4974 sc = device_get_softc(dev); 4975 BGE_LOCK(sc); 4976 ifp = sc->bge_ifp; 4977 if (ifp->if_flags & IFF_UP) { 4978 bge_init_locked(sc); 4979 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4980 bge_start_locked(ifp); 4981 } 4982 BGE_UNLOCK(sc); 4983 4984 return (0); 4985 } 4986 4987 static void 4988 bge_link_upd(struct bge_softc *sc) 4989 { 4990 struct mii_data *mii; 4991 uint32_t link, status; 4992 4993 BGE_LOCK_ASSERT(sc); 4994 4995 /* Clear 'pending link event' flag. */ 4996 sc->bge_link_evt = 0; 4997 4998 /* 4999 * Process link state changes. 5000 * Grrr. The link status word in the status block does 5001 * not work correctly on the BCM5700 rev AX and BX chips, 5002 * according to all available information. Hence, we have 5003 * to enable MII interrupts in order to properly obtain 5004 * async link changes. Unfortunately, this also means that 5005 * we have to read the MAC status register to detect link 5006 * changes, thereby adding an additional register access to 5007 * the interrupt handler. 5008 * 5009 * XXX: perhaps link state detection procedure used for 5010 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5011 */ 5012 5013 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5014 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5015 status = CSR_READ_4(sc, BGE_MAC_STS); 5016 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5017 mii = device_get_softc(sc->bge_miibus); 5018 mii_pollstat(mii); 5019 if (!sc->bge_link && 5020 mii->mii_media_status & IFM_ACTIVE && 5021 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5022 sc->bge_link++; 5023 if (bootverbose) 5024 if_printf(sc->bge_ifp, "link UP\n"); 5025 } else if (sc->bge_link && 5026 (!(mii->mii_media_status & IFM_ACTIVE) || 5027 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5028 sc->bge_link = 0; 5029 if (bootverbose) 5030 if_printf(sc->bge_ifp, "link DOWN\n"); 5031 } 5032 5033 /* Clear the interrupt. */ 5034 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5035 BGE_EVTENB_MI_INTERRUPT); 5036 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 5037 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 5038 BRGPHY_INTRS); 5039 } 5040 return; 5041 } 5042 5043 if (sc->bge_flags & BGE_FLAG_TBI) { 5044 status = CSR_READ_4(sc, BGE_MAC_STS); 5045 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5046 if (!sc->bge_link) { 5047 sc->bge_link++; 5048 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 5049 BGE_CLRBIT(sc, BGE_MAC_MODE, 5050 BGE_MACMODE_TBI_SEND_CFGS); 5051 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5052 if (bootverbose) 5053 if_printf(sc->bge_ifp, "link UP\n"); 5054 if_link_state_change(sc->bge_ifp, 5055 LINK_STATE_UP); 5056 } 5057 } else if (sc->bge_link) { 5058 sc->bge_link = 0; 5059 if (bootverbose) 5060 if_printf(sc->bge_ifp, "link DOWN\n"); 5061 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 5062 } 5063 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 5064 /* 5065 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 5066 * in status word always set. Workaround this bug by reading 5067 * PHY link status directly. 5068 */ 5069 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 5070 5071 if (link != sc->bge_link || 5072 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 5073 mii = device_get_softc(sc->bge_miibus); 5074 mii_pollstat(mii); 5075 if (!sc->bge_link && 5076 mii->mii_media_status & IFM_ACTIVE && 5077 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5078 sc->bge_link++; 5079 if (bootverbose) 5080 if_printf(sc->bge_ifp, "link UP\n"); 5081 } else if (sc->bge_link && 5082 (!(mii->mii_media_status & IFM_ACTIVE) || 5083 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5084 sc->bge_link = 0; 5085 if (bootverbose) 5086 if_printf(sc->bge_ifp, "link DOWN\n"); 5087 } 5088 } 5089 } else { 5090 /* 5091 * For controllers that call mii_tick, we have to poll 5092 * link status. 5093 */ 5094 mii = device_get_softc(sc->bge_miibus); 5095 mii_pollstat(mii); 5096 bge_miibus_statchg(sc->bge_dev); 5097 } 5098 5099 /* Clear the attention. */ 5100 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 5101 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 5102 BGE_MACSTAT_LINK_CHANGED); 5103 } 5104 5105 static void 5106 bge_add_sysctls(struct bge_softc *sc) 5107 { 5108 struct sysctl_ctx_list *ctx; 5109 struct sysctl_oid_list *children; 5110 char tn[32]; 5111 int unit; 5112 5113 ctx = device_get_sysctl_ctx(sc->bge_dev); 5114 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 5115 5116 #ifdef BGE_REGISTER_DEBUG 5117 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 5118 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 5119 "Debug Information"); 5120 5121 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 5122 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 5123 "Register Read"); 5124 5125 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 5126 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 5127 "Memory Read"); 5128 5129 #endif 5130 5131 unit = device_get_unit(sc->bge_dev); 5132 /* 5133 * A common design characteristic for many Broadcom client controllers 5134 * is that they only support a single outstanding DMA read operation 5135 * on the PCIe bus. This means that it will take twice as long to fetch 5136 * a TX frame that is split into header and payload buffers as it does 5137 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 5138 * these controllers, coalescing buffers to reduce the number of memory 5139 * reads is effective way to get maximum performance(about 940Mbps). 5140 * Without collapsing TX buffers the maximum TCP bulk transfer 5141 * performance is about 850Mbps. However forcing coalescing mbufs 5142 * consumes a lot of CPU cycles, so leave it off by default. 5143 */ 5144 sc->bge_forced_collapse = 0; 5145 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 5146 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 5147 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 5148 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 5149 "Number of fragmented TX buffers of a frame allowed before " 5150 "forced collapsing"); 5151 5152 /* 5153 * It seems all Broadcom controllers have a bug that can generate UDP 5154 * datagrams with checksum value 0 when TX UDP checksum offloading is 5155 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 5156 * Even though the probability of generating such UDP datagrams is 5157 * low, I don't want to see FreeBSD boxes to inject such datagrams 5158 * into network so disable UDP checksum offloading by default. Users 5159 * still override this behavior by setting a sysctl variable, 5160 * dev.bge.0.forced_udpcsum. 5161 */ 5162 sc->bge_forced_udpcsum = 0; 5163 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 5164 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 5165 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 5166 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 5167 "Enable UDP checksum offloading even if controller can " 5168 "generate UDP checksum value 0"); 5169 5170 if (BGE_IS_5705_PLUS(sc)) 5171 bge_add_sysctl_stats_regs(sc, ctx, children); 5172 else 5173 bge_add_sysctl_stats(sc, ctx, children); 5174 } 5175 5176 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 5177 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 5178 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 5179 desc) 5180 5181 static void 5182 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5183 struct sysctl_oid_list *parent) 5184 { 5185 struct sysctl_oid *tree; 5186 struct sysctl_oid_list *children, *schildren; 5187 5188 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5189 NULL, "BGE Statistics"); 5190 schildren = children = SYSCTL_CHILDREN(tree); 5191 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 5192 children, COSFramesDroppedDueToFilters, 5193 "FramesDroppedDueToFilters"); 5194 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 5195 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 5196 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 5197 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 5198 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 5199 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 5200 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 5201 children, ifInDiscards, "InputDiscards"); 5202 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 5203 children, ifInErrors, "InputErrors"); 5204 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 5205 children, nicRecvThresholdHit, "RecvThresholdHit"); 5206 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 5207 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 5208 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 5209 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 5210 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 5211 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 5212 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 5213 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 5214 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 5215 children, nicRingStatusUpdate, "RingStatusUpdate"); 5216 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 5217 children, nicInterrupts, "Interrupts"); 5218 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 5219 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 5220 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 5221 children, nicSendThresholdHit, "SendThresholdHit"); 5222 5223 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 5224 NULL, "BGE RX Statistics"); 5225 children = SYSCTL_CHILDREN(tree); 5226 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 5227 children, rxstats.ifHCInOctets, "ifHCInOctets"); 5228 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 5229 children, rxstats.etherStatsFragments, "Fragments"); 5230 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 5231 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 5232 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 5233 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 5234 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 5235 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 5236 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 5237 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 5238 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 5239 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 5240 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 5241 children, rxstats.xoffPauseFramesReceived, 5242 "xoffPauseFramesReceived"); 5243 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 5244 children, rxstats.macControlFramesReceived, 5245 "ControlFramesReceived"); 5246 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5247 children, rxstats.xoffStateEntered, "xoffStateEntered"); 5248 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5249 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5250 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5251 children, rxstats.etherStatsJabbers, "Jabbers"); 5252 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5253 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5254 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 5255 children, rxstats.inRangeLengthError, "inRangeLengthError"); 5256 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 5257 children, rxstats.outRangeLengthError, "outRangeLengthError"); 5258 5259 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5260 NULL, "BGE TX Statistics"); 5261 children = SYSCTL_CHILDREN(tree); 5262 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5263 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 5264 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5265 children, txstats.etherStatsCollisions, "Collisions"); 5266 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5267 children, txstats.outXonSent, "XonSent"); 5268 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5269 children, txstats.outXoffSent, "XoffSent"); 5270 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5271 children, txstats.flowControlDone, "flowControlDone"); 5272 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5273 children, txstats.dot3StatsInternalMacTransmitErrors, 5274 "InternalMacTransmitErrors"); 5275 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5276 children, txstats.dot3StatsSingleCollisionFrames, 5277 "SingleCollisionFrames"); 5278 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5279 children, txstats.dot3StatsMultipleCollisionFrames, 5280 "MultipleCollisionFrames"); 5281 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5282 children, txstats.dot3StatsDeferredTransmissions, 5283 "DeferredTransmissions"); 5284 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5285 children, txstats.dot3StatsExcessiveCollisions, 5286 "ExcessiveCollisions"); 5287 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 5288 children, txstats.dot3StatsLateCollisions, 5289 "LateCollisions"); 5290 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5291 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 5292 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5293 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5294 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5295 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5296 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5297 children, txstats.dot3StatsCarrierSenseErrors, 5298 "CarrierSenseErrors"); 5299 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5300 children, txstats.ifOutDiscards, "Discards"); 5301 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5302 children, txstats.ifOutErrors, "Errors"); 5303 } 5304 5305 #undef BGE_SYSCTL_STAT 5306 5307 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 5308 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 5309 5310 static void 5311 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5312 struct sysctl_oid_list *parent) 5313 { 5314 struct sysctl_oid *tree; 5315 struct sysctl_oid_list *child, *schild; 5316 struct bge_mac_stats *stats; 5317 5318 stats = &sc->bge_mac_stats; 5319 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5320 NULL, "BGE Statistics"); 5321 schild = child = SYSCTL_CHILDREN(tree); 5322 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 5323 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 5324 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 5325 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 5326 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 5327 &stats->DmaWriteHighPriQueueFull, 5328 "NIC DMA Write High Priority Queue Full"); 5329 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 5330 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 5331 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 5332 &stats->InputDiscards, "Discarded Input Frames"); 5333 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 5334 &stats->InputErrors, "Input Errors"); 5335 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 5336 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 5337 5338 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 5339 NULL, "BGE RX Statistics"); 5340 child = SYSCTL_CHILDREN(tree); 5341 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 5342 &stats->ifHCInOctets, "Inbound Octets"); 5343 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 5344 &stats->etherStatsFragments, "Fragments"); 5345 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5346 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 5347 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5348 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 5349 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5350 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 5351 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 5352 &stats->dot3StatsFCSErrors, "FCS Errors"); 5353 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 5354 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 5355 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 5356 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 5357 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 5358 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 5359 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 5360 &stats->macControlFramesReceived, "MAC Control Frames Received"); 5361 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 5362 &stats->xoffStateEntered, "XOFF State Entered"); 5363 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 5364 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 5365 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 5366 &stats->etherStatsJabbers, "Jabbers"); 5367 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 5368 &stats->etherStatsUndersizePkts, "Undersized Packets"); 5369 5370 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 5371 NULL, "BGE TX Statistics"); 5372 child = SYSCTL_CHILDREN(tree); 5373 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 5374 &stats->ifHCOutOctets, "Outbound Octets"); 5375 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 5376 &stats->etherStatsCollisions, "TX Collisions"); 5377 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 5378 &stats->outXonSent, "XON Sent"); 5379 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 5380 &stats->outXoffSent, "XOFF Sent"); 5381 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 5382 &stats->dot3StatsInternalMacTransmitErrors, 5383 "Internal MAC TX Errors"); 5384 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 5385 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 5386 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 5387 &stats->dot3StatsMultipleCollisionFrames, 5388 "Multiple Collision Frames"); 5389 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 5390 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 5391 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 5392 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 5393 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 5394 &stats->dot3StatsLateCollisions, "Late Collisions"); 5395 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5396 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 5397 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5398 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 5399 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5400 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 5401 } 5402 5403 #undef BGE_SYSCTL_STAT_ADD64 5404 5405 static int 5406 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5407 { 5408 struct bge_softc *sc; 5409 uint32_t result; 5410 int offset; 5411 5412 sc = (struct bge_softc *)arg1; 5413 offset = arg2; 5414 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5415 offsetof(bge_hostaddr, bge_addr_lo)); 5416 return (sysctl_handle_int(oidp, &result, 0, req)); 5417 } 5418 5419 #ifdef BGE_REGISTER_DEBUG 5420 static int 5421 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5422 { 5423 struct bge_softc *sc; 5424 uint16_t *sbdata; 5425 int error; 5426 int result; 5427 int i, j; 5428 5429 result = -1; 5430 error = sysctl_handle_int(oidp, &result, 0, req); 5431 if (error || (req->newptr == NULL)) 5432 return (error); 5433 5434 if (result == 1) { 5435 sc = (struct bge_softc *)arg1; 5436 5437 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5438 printf("Status Block:\n"); 5439 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 5440 printf("%06x:", i); 5441 for (j = 0; j < 8; j++) { 5442 printf(" %04x", sbdata[i]); 5443 i += 4; 5444 } 5445 printf("\n"); 5446 } 5447 5448 printf("Registers:\n"); 5449 for (i = 0x800; i < 0xA00; ) { 5450 printf("%06x:", i); 5451 for (j = 0; j < 8; j++) { 5452 printf(" %08x", CSR_READ_4(sc, i)); 5453 i += 4; 5454 } 5455 printf("\n"); 5456 } 5457 5458 printf("Hardware Flags:\n"); 5459 if (BGE_IS_5755_PLUS(sc)) 5460 printf(" - 5755 Plus\n"); 5461 if (BGE_IS_575X_PLUS(sc)) 5462 printf(" - 575X Plus\n"); 5463 if (BGE_IS_5705_PLUS(sc)) 5464 printf(" - 5705 Plus\n"); 5465 if (BGE_IS_5714_FAMILY(sc)) 5466 printf(" - 5714 Family\n"); 5467 if (BGE_IS_5700_FAMILY(sc)) 5468 printf(" - 5700 Family\n"); 5469 if (sc->bge_flags & BGE_FLAG_JUMBO) 5470 printf(" - Supports Jumbo Frames\n"); 5471 if (sc->bge_flags & BGE_FLAG_PCIX) 5472 printf(" - PCI-X Bus\n"); 5473 if (sc->bge_flags & BGE_FLAG_PCIE) 5474 printf(" - PCI Express Bus\n"); 5475 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 5476 printf(" - No 3 LEDs\n"); 5477 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5478 printf(" - RX Alignment Bug\n"); 5479 } 5480 5481 return (error); 5482 } 5483 5484 static int 5485 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5486 { 5487 struct bge_softc *sc; 5488 int error; 5489 uint16_t result; 5490 uint32_t val; 5491 5492 result = -1; 5493 error = sysctl_handle_int(oidp, &result, 0, req); 5494 if (error || (req->newptr == NULL)) 5495 return (error); 5496 5497 if (result < 0x8000) { 5498 sc = (struct bge_softc *)arg1; 5499 val = CSR_READ_4(sc, result); 5500 printf("reg 0x%06X = 0x%08X\n", result, val); 5501 } 5502 5503 return (error); 5504 } 5505 5506 static int 5507 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5508 { 5509 struct bge_softc *sc; 5510 int error; 5511 uint16_t result; 5512 uint32_t val; 5513 5514 result = -1; 5515 error = sysctl_handle_int(oidp, &result, 0, req); 5516 if (error || (req->newptr == NULL)) 5517 return (error); 5518 5519 if (result < 0x8000) { 5520 sc = (struct bge_softc *)arg1; 5521 val = bge_readmem_ind(sc, result); 5522 printf("mem 0x%06X = 0x%08X\n", result, val); 5523 } 5524 5525 return (error); 5526 } 5527 #endif 5528 5529 static int 5530 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5531 { 5532 5533 if (sc->bge_flags & BGE_FLAG_EADDR) 5534 return (1); 5535 5536 #ifdef __sparc64__ 5537 OF_getetheraddr(sc->bge_dev, ether_addr); 5538 return (0); 5539 #endif 5540 return (1); 5541 } 5542 5543 static int 5544 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5545 { 5546 uint32_t mac_addr; 5547 5548 mac_addr = bge_readmem_ind(sc, 0x0c14); 5549 if ((mac_addr >> 16) == 0x484b) { 5550 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5551 ether_addr[1] = (uint8_t)mac_addr; 5552 mac_addr = bge_readmem_ind(sc, 0x0c18); 5553 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5554 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5555 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5556 ether_addr[5] = (uint8_t)mac_addr; 5557 return (0); 5558 } 5559 return (1); 5560 } 5561 5562 static int 5563 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5564 { 5565 int mac_offset = BGE_EE_MAC_OFFSET; 5566 5567 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5568 mac_offset = BGE_EE_MAC_OFFSET_5906; 5569 5570 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5571 ETHER_ADDR_LEN)); 5572 } 5573 5574 static int 5575 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5576 { 5577 5578 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5579 return (1); 5580 5581 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5582 ETHER_ADDR_LEN)); 5583 } 5584 5585 static int 5586 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5587 { 5588 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5589 /* NOTE: Order is critical */ 5590 bge_get_eaddr_fw, 5591 bge_get_eaddr_mem, 5592 bge_get_eaddr_nvram, 5593 bge_get_eaddr_eeprom, 5594 NULL 5595 }; 5596 const bge_eaddr_fcn_t *func; 5597 5598 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5599 if ((*func)(sc, eaddr) == 0) 5600 break; 5601 } 5602 return (*func == NULL ? ENXIO : 0); 5603 } 5604