1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #include <sys/cdefs.h> 70 __FBSDID("$FreeBSD$"); 71 72 #include <sys/param.h> 73 #include <sys/endian.h> 74 #include <sys/systm.h> 75 #include <sys/sockio.h> 76 #include <sys/mbuf.h> 77 #include <sys/malloc.h> 78 #include <sys/kernel.h> 79 #include <sys/socket.h> 80 #include <sys/queue.h> 81 82 #include <net/if.h> 83 #include <net/if_arp.h> 84 #include <net/ethernet.h> 85 #include <net/if_dl.h> 86 #include <net/if_media.h> 87 88 #include <net/bpf.h> 89 90 #include <net/if_types.h> 91 #include <net/if_vlan_var.h> 92 93 #include <netinet/in_systm.h> 94 #include <netinet/in.h> 95 #include <netinet/ip.h> 96 97 #include <machine/clock.h> /* for DELAY */ 98 #include <machine/bus_memio.h> 99 #include <machine/bus.h> 100 #include <machine/resource.h> 101 #include <sys/bus.h> 102 #include <sys/rman.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 #include "miidevs.h" 107 #include <dev/mii/brgphyreg.h> 108 109 #include <dev/pci/pcireg.h> 110 #include <dev/pci/pcivar.h> 111 112 #include <dev/bge/if_bgereg.h> 113 114 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 115 116 MODULE_DEPEND(bge, pci, 1, 1, 1); 117 MODULE_DEPEND(bge, ether, 1, 1, 1); 118 MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120 /* "controller miibus0" required. See GENERIC if you get errors here. */ 121 #include "miibus_if.h" 122 123 /* 124 * Various supported device vendors/types and their names. Note: the 125 * spec seems to indicate that the hardware still has Alteon's vendor 126 * ID burned into it, though it will always be overriden by the vendor 127 * ID in the EEPROM. Just to be safe, we cover all possibilities. 128 */ 129 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 130 131 static struct bge_type bge_devs[] = { 132 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 133 "Broadcom BCM5700 Gigabit Ethernet" }, 134 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 135 "Broadcom BCM5701 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702, 141 "Broadcom BCM5702 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 143 "Broadcom BCM5702X Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703, 145 "Broadcom BCM5703 Gigabit Ethernet" }, 146 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 147 "Broadcom BCM5703X Gigabit Ethernet" }, 148 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 149 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 150 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 151 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705, 153 "Broadcom BCM5705 Gigabit Ethernet" }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M, 155 "Broadcom BCM5705M Gigabit Ethernet" }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT, 157 "Broadcom BCM5705M Gigabit Ethernet" }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782, 159 "Broadcom BCM5782 Gigabit Ethernet" }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901, 161 "Broadcom BCM5901 Fast Ethernet" }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2, 163 "Broadcom BCM5901A2 Fast Ethernet" }, 164 { SK_VENDORID, SK_DEVICEID_ALTIMA, 165 "SysKonnect Gigabit Ethernet" }, 166 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 167 "Altima AC1000 Gigabit Ethernet" }, 168 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 169 "Altima AC9100 Gigabit Ethernet" }, 170 { 0, 0, NULL } 171 }; 172 173 static int bge_probe (device_t); 174 static int bge_attach (device_t); 175 static int bge_detach (device_t); 176 static void bge_release_resources 177 (struct bge_softc *); 178 static void bge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 179 static void bge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 180 bus_size_t, int); 181 static int bge_dma_alloc (device_t); 182 static void bge_dma_free (struct bge_softc *); 183 184 static void bge_txeof (struct bge_softc *); 185 static void bge_rxeof (struct bge_softc *); 186 187 static void bge_tick (void *); 188 static void bge_stats_update (struct bge_softc *); 189 static void bge_stats_update_regs 190 (struct bge_softc *); 191 static int bge_encap (struct bge_softc *, struct mbuf *, 192 u_int32_t *); 193 194 static void bge_intr (void *); 195 static void bge_start (struct ifnet *); 196 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 197 static void bge_init (void *); 198 static void bge_stop (struct bge_softc *); 199 static void bge_watchdog (struct ifnet *); 200 static void bge_shutdown (device_t); 201 static int bge_ifmedia_upd (struct ifnet *); 202 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 203 204 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 205 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 206 207 static u_int32_t bge_crc (caddr_t); 208 static void bge_setmulti (struct bge_softc *); 209 210 static void bge_handle_events (struct bge_softc *); 211 static int bge_alloc_jumbo_mem (struct bge_softc *); 212 static void bge_free_jumbo_mem (struct bge_softc *); 213 static void *bge_jalloc (struct bge_softc *); 214 static void bge_jfree (void *, void *); 215 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 216 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 217 static int bge_init_rx_ring_std (struct bge_softc *); 218 static void bge_free_rx_ring_std (struct bge_softc *); 219 static int bge_init_rx_ring_jumbo (struct bge_softc *); 220 static void bge_free_rx_ring_jumbo (struct bge_softc *); 221 static void bge_free_tx_ring (struct bge_softc *); 222 static int bge_init_tx_ring (struct bge_softc *); 223 224 static int bge_chipinit (struct bge_softc *); 225 static int bge_blockinit (struct bge_softc *); 226 227 #ifdef notdef 228 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 229 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 230 static void bge_vpd_read (struct bge_softc *); 231 #endif 232 233 static u_int32_t bge_readmem_ind 234 (struct bge_softc *, int); 235 static void bge_writemem_ind (struct bge_softc *, int, int); 236 #ifdef notdef 237 static u_int32_t bge_readreg_ind 238 (struct bge_softc *, int); 239 #endif 240 static void bge_writereg_ind (struct bge_softc *, int, int); 241 242 static int bge_miibus_readreg (device_t, int, int); 243 static int bge_miibus_writereg (device_t, int, int, int); 244 static void bge_miibus_statchg (device_t); 245 246 static void bge_reset (struct bge_softc *); 247 248 static device_method_t bge_methods[] = { 249 /* Device interface */ 250 DEVMETHOD(device_probe, bge_probe), 251 DEVMETHOD(device_attach, bge_attach), 252 DEVMETHOD(device_detach, bge_detach), 253 DEVMETHOD(device_shutdown, bge_shutdown), 254 255 /* bus interface */ 256 DEVMETHOD(bus_print_child, bus_generic_print_child), 257 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 258 259 /* MII interface */ 260 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 261 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 262 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 263 264 { 0, 0 } 265 }; 266 267 static driver_t bge_driver = { 268 "bge", 269 bge_methods, 270 sizeof(struct bge_softc) 271 }; 272 273 static devclass_t bge_devclass; 274 275 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 276 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 277 278 static u_int32_t 279 bge_readmem_ind(sc, off) 280 struct bge_softc *sc; 281 int off; 282 { 283 device_t dev; 284 285 dev = sc->bge_dev; 286 287 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 288 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 289 } 290 291 static void 292 bge_writemem_ind(sc, off, val) 293 struct bge_softc *sc; 294 int off, val; 295 { 296 device_t dev; 297 298 dev = sc->bge_dev; 299 300 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 301 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 302 303 return; 304 } 305 306 #ifdef notdef 307 static u_int32_t 308 bge_readreg_ind(sc, off) 309 struct bge_softc *sc; 310 int off; 311 { 312 device_t dev; 313 314 dev = sc->bge_dev; 315 316 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 317 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 318 } 319 #endif 320 321 static void 322 bge_writereg_ind(sc, off, val) 323 struct bge_softc *sc; 324 int off, val; 325 { 326 device_t dev; 327 328 dev = sc->bge_dev; 329 330 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 331 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 332 333 return; 334 } 335 336 /* 337 * Map a single buffer address. 338 */ 339 340 static void 341 bge_dma_map_addr(arg, segs, nseg, error) 342 void *arg; 343 bus_dma_segment_t *segs; 344 int nseg; 345 int error; 346 { 347 struct bge_dmamap_arg *ctx; 348 349 if (error) 350 return; 351 352 ctx = arg; 353 354 if (nseg > ctx->bge_maxsegs) { 355 ctx->bge_maxsegs = 0; 356 return; 357 } 358 359 ctx->bge_busaddr = segs->ds_addr; 360 361 return; 362 } 363 364 /* 365 * Map an mbuf chain into an TX ring. 366 */ 367 368 static void 369 bge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 370 void *arg; 371 bus_dma_segment_t *segs; 372 int nseg; 373 bus_size_t mapsize; 374 int error; 375 { 376 struct bge_dmamap_arg *ctx; 377 struct bge_tx_bd *d = NULL; 378 int i = 0, idx; 379 380 if (error) 381 return; 382 383 ctx = arg; 384 385 /* Signal error to caller if there's too many segments */ 386 if (nseg > ctx->bge_maxsegs) { 387 ctx->bge_maxsegs = 0; 388 return; 389 } 390 391 idx = ctx->bge_idx; 392 while(1) { 393 d = &ctx->bge_ring[idx]; 394 d->bge_addr.bge_addr_lo = 395 htole32(BGE_ADDR_LO(segs[i].ds_addr)); 396 d->bge_addr.bge_addr_hi = 397 htole32(BGE_ADDR_HI(segs[i].ds_addr)); 398 d->bge_len = htole16(segs[i].ds_len); 399 d->bge_flags = htole16(ctx->bge_flags); 400 i++; 401 if (i == nseg) 402 break; 403 BGE_INC(idx, BGE_TX_RING_CNT); 404 } 405 406 d->bge_flags |= htole16(BGE_TXBDFLAG_END); 407 ctx->bge_maxsegs = nseg; 408 ctx->bge_idx = idx; 409 410 return; 411 } 412 413 414 #ifdef notdef 415 static u_int8_t 416 bge_vpd_readbyte(sc, addr) 417 struct bge_softc *sc; 418 int addr; 419 { 420 int i; 421 device_t dev; 422 u_int32_t val; 423 424 dev = sc->bge_dev; 425 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 426 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 427 DELAY(10); 428 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 429 break; 430 } 431 432 if (i == BGE_TIMEOUT) { 433 printf("bge%d: VPD read timed out\n", sc->bge_unit); 434 return(0); 435 } 436 437 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 438 439 return((val >> ((addr % 4) * 8)) & 0xFF); 440 } 441 442 static void 443 bge_vpd_read_res(sc, res, addr) 444 struct bge_softc *sc; 445 struct vpd_res *res; 446 int addr; 447 { 448 int i; 449 u_int8_t *ptr; 450 451 ptr = (u_int8_t *)res; 452 for (i = 0; i < sizeof(struct vpd_res); i++) 453 ptr[i] = bge_vpd_readbyte(sc, i + addr); 454 455 return; 456 } 457 458 static void 459 bge_vpd_read(sc) 460 struct bge_softc *sc; 461 { 462 int pos = 0, i; 463 struct vpd_res res; 464 465 if (sc->bge_vpd_prodname != NULL) 466 free(sc->bge_vpd_prodname, M_DEVBUF); 467 if (sc->bge_vpd_readonly != NULL) 468 free(sc->bge_vpd_readonly, M_DEVBUF); 469 sc->bge_vpd_prodname = NULL; 470 sc->bge_vpd_readonly = NULL; 471 472 bge_vpd_read_res(sc, &res, pos); 473 474 if (res.vr_id != VPD_RES_ID) { 475 printf("bge%d: bad VPD resource id: expected %x got %x\n", 476 sc->bge_unit, VPD_RES_ID, res.vr_id); 477 return; 478 } 479 480 pos += sizeof(res); 481 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 482 for (i = 0; i < res.vr_len; i++) 483 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 484 sc->bge_vpd_prodname[i] = '\0'; 485 pos += i; 486 487 bge_vpd_read_res(sc, &res, pos); 488 489 if (res.vr_id != VPD_RES_READ) { 490 printf("bge%d: bad VPD resource id: expected %x got %x\n", 491 sc->bge_unit, VPD_RES_READ, res.vr_id); 492 return; 493 } 494 495 pos += sizeof(res); 496 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 497 for (i = 0; i < res.vr_len + 1; i++) 498 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 499 500 return; 501 } 502 #endif 503 504 /* 505 * Read a byte of data stored in the EEPROM at address 'addr.' The 506 * BCM570x supports both the traditional bitbang interface and an 507 * auto access interface for reading the EEPROM. We use the auto 508 * access method. 509 */ 510 static u_int8_t 511 bge_eeprom_getbyte(sc, addr, dest) 512 struct bge_softc *sc; 513 int addr; 514 u_int8_t *dest; 515 { 516 int i; 517 u_int32_t byte = 0; 518 519 /* 520 * Enable use of auto EEPROM access so we can avoid 521 * having to use the bitbang method. 522 */ 523 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 524 525 /* Reset the EEPROM, load the clock period. */ 526 CSR_WRITE_4(sc, BGE_EE_ADDR, 527 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 528 DELAY(20); 529 530 /* Issue the read EEPROM command. */ 531 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 532 533 /* Wait for completion */ 534 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 535 DELAY(10); 536 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 537 break; 538 } 539 540 if (i == BGE_TIMEOUT) { 541 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 542 return(0); 543 } 544 545 /* Get result. */ 546 byte = CSR_READ_4(sc, BGE_EE_DATA); 547 548 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 549 550 return(0); 551 } 552 553 /* 554 * Read a sequence of bytes from the EEPROM. 555 */ 556 static int 557 bge_read_eeprom(sc, dest, off, cnt) 558 struct bge_softc *sc; 559 caddr_t dest; 560 int off; 561 int cnt; 562 { 563 int err = 0, i; 564 u_int8_t byte = 0; 565 566 for (i = 0; i < cnt; i++) { 567 err = bge_eeprom_getbyte(sc, off + i, &byte); 568 if (err) 569 break; 570 *(dest + i) = byte; 571 } 572 573 return(err ? 1 : 0); 574 } 575 576 static int 577 bge_miibus_readreg(dev, phy, reg) 578 device_t dev; 579 int phy, reg; 580 { 581 struct bge_softc *sc; 582 u_int32_t val, autopoll; 583 int i; 584 585 sc = device_get_softc(dev); 586 587 /* 588 * Broadcom's own driver always assumes the internal 589 * PHY is at GMII address 1. On some chips, the PHY responds 590 * to accesses at all addresses, which could cause us to 591 * bogusly attach the PHY 32 times at probe type. Always 592 * restricting the lookup to address 1 is simpler than 593 * trying to figure out which chips revisions should be 594 * special-cased. 595 */ 596 if (phy != 1) 597 return(0); 598 599 /* Reading with autopolling on may trigger PCI errors */ 600 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 601 if (autopoll & BGE_MIMODE_AUTOPOLL) { 602 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 603 DELAY(40); 604 } 605 606 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 607 BGE_MIPHY(phy)|BGE_MIREG(reg)); 608 609 for (i = 0; i < BGE_TIMEOUT; i++) { 610 val = CSR_READ_4(sc, BGE_MI_COMM); 611 if (!(val & BGE_MICOMM_BUSY)) 612 break; 613 } 614 615 if (i == BGE_TIMEOUT) { 616 printf("bge%d: PHY read timed out\n", sc->bge_unit); 617 val = 0; 618 goto done; 619 } 620 621 val = CSR_READ_4(sc, BGE_MI_COMM); 622 623 done: 624 if (autopoll & BGE_MIMODE_AUTOPOLL) { 625 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 626 DELAY(40); 627 } 628 629 if (val & BGE_MICOMM_READFAIL) 630 return(0); 631 632 return(val & 0xFFFF); 633 } 634 635 static int 636 bge_miibus_writereg(dev, phy, reg, val) 637 device_t dev; 638 int phy, reg, val; 639 { 640 struct bge_softc *sc; 641 u_int32_t autopoll; 642 int i; 643 644 sc = device_get_softc(dev); 645 646 /* Reading with autopolling on may trigger PCI errors */ 647 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 648 if (autopoll & BGE_MIMODE_AUTOPOLL) { 649 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 650 DELAY(40); 651 } 652 653 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 654 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 655 656 for (i = 0; i < BGE_TIMEOUT; i++) { 657 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 658 break; 659 } 660 661 if (autopoll & BGE_MIMODE_AUTOPOLL) { 662 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 663 DELAY(40); 664 } 665 666 if (i == BGE_TIMEOUT) { 667 printf("bge%d: PHY read timed out\n", sc->bge_unit); 668 return(0); 669 } 670 671 return(0); 672 } 673 674 static void 675 bge_miibus_statchg(dev) 676 device_t dev; 677 { 678 struct bge_softc *sc; 679 struct mii_data *mii; 680 681 sc = device_get_softc(dev); 682 mii = device_get_softc(sc->bge_miibus); 683 684 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 685 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 686 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 687 } else { 688 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 689 } 690 691 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 692 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 693 } else { 694 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 695 } 696 697 return; 698 } 699 700 /* 701 * Handle events that have triggered interrupts. 702 */ 703 static void 704 bge_handle_events(sc) 705 struct bge_softc *sc; 706 { 707 708 return; 709 } 710 711 /* 712 * Memory management for jumbo frames. 713 */ 714 715 static int 716 bge_alloc_jumbo_mem(sc) 717 struct bge_softc *sc; 718 { 719 caddr_t ptr; 720 register int i, error; 721 struct bge_jpool_entry *entry; 722 723 /* Create tag for jumbo buffer block */ 724 725 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 726 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 727 NULL, BGE_JMEM, 1, BGE_JMEM, 0, NULL, NULL, 728 &sc->bge_cdata.bge_jumbo_tag); 729 730 if (error) { 731 printf("bge%d: could not allocate jumbo dma tag\n", 732 sc->bge_unit); 733 return (ENOMEM); 734 } 735 736 /* Allocate DMA'able memory for jumbo buffer block */ 737 738 error = bus_dmamem_alloc(sc->bge_cdata.bge_jumbo_tag, 739 (void **)&sc->bge_ldata.bge_jumbo_buf, BUS_DMA_NOWAIT, 740 &sc->bge_cdata.bge_jumbo_map); 741 742 if (error) 743 return (ENOMEM); 744 745 SLIST_INIT(&sc->bge_jfree_listhead); 746 SLIST_INIT(&sc->bge_jinuse_listhead); 747 748 /* 749 * Now divide it up into 9K pieces and save the addresses 750 * in an array. 751 */ 752 ptr = sc->bge_ldata.bge_jumbo_buf; 753 for (i = 0; i < BGE_JSLOTS; i++) { 754 sc->bge_cdata.bge_jslots[i] = ptr; 755 ptr += BGE_JLEN; 756 entry = malloc(sizeof(struct bge_jpool_entry), 757 M_DEVBUF, M_NOWAIT); 758 if (entry == NULL) { 759 bge_free_jumbo_mem(sc); 760 sc->bge_ldata.bge_jumbo_buf = NULL; 761 printf("bge%d: no memory for jumbo " 762 "buffer queue!\n", sc->bge_unit); 763 return(ENOBUFS); 764 } 765 entry->slot = i; 766 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 767 entry, jpool_entries); 768 } 769 770 return(0); 771 } 772 773 static void 774 bge_free_jumbo_mem(sc) 775 struct bge_softc *sc; 776 { 777 int i; 778 struct bge_jpool_entry *entry; 779 780 for (i = 0; i < BGE_JSLOTS; i++) { 781 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 782 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 783 free(entry, M_DEVBUF); 784 } 785 786 /* Destroy jumbo buffer block */ 787 788 if (sc->bge_ldata.bge_rx_jumbo_ring) 789 bus_dmamem_free(sc->bge_cdata.bge_jumbo_tag, 790 sc->bge_ldata.bge_jumbo_buf, 791 sc->bge_cdata.bge_jumbo_map); 792 793 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 794 bus_dmamap_destroy(sc->bge_cdata.bge_jumbo_tag, 795 sc->bge_cdata.bge_jumbo_map); 796 797 if (sc->bge_cdata.bge_jumbo_tag) 798 bus_dma_tag_destroy(sc->bge_cdata.bge_jumbo_tag); 799 800 return; 801 } 802 803 /* 804 * Allocate a jumbo buffer. 805 */ 806 static void * 807 bge_jalloc(sc) 808 struct bge_softc *sc; 809 { 810 struct bge_jpool_entry *entry; 811 812 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 813 814 if (entry == NULL) { 815 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 816 return(NULL); 817 } 818 819 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 820 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 821 return(sc->bge_cdata.bge_jslots[entry->slot]); 822 } 823 824 /* 825 * Release a jumbo buffer. 826 */ 827 static void 828 bge_jfree(buf, args) 829 void *buf; 830 void *args; 831 { 832 struct bge_jpool_entry *entry; 833 struct bge_softc *sc; 834 int i; 835 836 /* Extract the softc struct pointer. */ 837 sc = (struct bge_softc *)args; 838 839 if (sc == NULL) 840 panic("bge_jfree: can't find softc pointer!"); 841 842 /* calculate the slot this buffer belongs to */ 843 844 i = ((vm_offset_t)buf 845 - (vm_offset_t)sc->bge_ldata.bge_jumbo_buf) / BGE_JLEN; 846 847 if ((i < 0) || (i >= BGE_JSLOTS)) 848 panic("bge_jfree: asked to free buffer that we don't manage!"); 849 850 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 851 if (entry == NULL) 852 panic("bge_jfree: buffer not in use!"); 853 entry->slot = i; 854 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 855 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 856 857 return; 858 } 859 860 861 /* 862 * Intialize a standard receive ring descriptor. 863 */ 864 static int 865 bge_newbuf_std(sc, i, m) 866 struct bge_softc *sc; 867 int i; 868 struct mbuf *m; 869 { 870 struct mbuf *m_new = NULL; 871 struct bge_rx_bd *r; 872 struct bge_dmamap_arg ctx; 873 int error; 874 875 if (m == NULL) { 876 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 877 if (m_new == NULL) { 878 return(ENOBUFS); 879 } 880 881 MCLGET(m_new, M_DONTWAIT); 882 if (!(m_new->m_flags & M_EXT)) { 883 m_freem(m_new); 884 return(ENOBUFS); 885 } 886 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 887 } else { 888 m_new = m; 889 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 890 m_new->m_data = m_new->m_ext.ext_buf; 891 } 892 893 if (!sc->bge_rx_alignment_bug) 894 m_adj(m_new, ETHER_ALIGN); 895 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 896 r = &sc->bge_ldata.bge_rx_std_ring[i]; 897 ctx.bge_maxsegs = 1; 898 ctx.sc = sc; 899 error = bus_dmamap_load(sc->bge_cdata.bge_mtag, 900 sc->bge_cdata.bge_rx_std_dmamap[i], mtod(m_new, void *), 901 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 902 if (error || ctx.bge_maxsegs == 0) { 903 if (m == NULL) 904 m_freem(m_new); 905 return(ENOMEM); 906 } 907 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 908 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 909 r->bge_flags = htole16(BGE_RXBDFLAG_END); 910 r->bge_len = htole16(m_new->m_len); 911 r->bge_idx = htole16(i); 912 913 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 914 sc->bge_cdata.bge_rx_std_dmamap[i], 915 BUS_DMASYNC_PREREAD); 916 917 return(0); 918 } 919 920 /* 921 * Initialize a jumbo receive ring descriptor. This allocates 922 * a jumbo buffer from the pool managed internally by the driver. 923 */ 924 static int 925 bge_newbuf_jumbo(sc, i, m) 926 struct bge_softc *sc; 927 int i; 928 struct mbuf *m; 929 { 930 struct mbuf *m_new = NULL; 931 struct bge_rx_bd *r; 932 struct bge_dmamap_arg ctx; 933 int error; 934 935 if (m == NULL) { 936 caddr_t *buf = NULL; 937 938 /* Allocate the mbuf. */ 939 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 940 if (m_new == NULL) { 941 return(ENOBUFS); 942 } 943 944 /* Allocate the jumbo buffer */ 945 buf = bge_jalloc(sc); 946 if (buf == NULL) { 947 m_freem(m_new); 948 printf("bge%d: jumbo allocation failed " 949 "-- packet dropped!\n", sc->bge_unit); 950 return(ENOBUFS); 951 } 952 953 /* Attach the buffer to the mbuf. */ 954 m_new->m_data = (void *) buf; 955 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 956 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 957 (struct bge_softc *)sc, 0, EXT_NET_DRV); 958 } else { 959 m_new = m; 960 m_new->m_data = m_new->m_ext.ext_buf; 961 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 962 } 963 964 if (!sc->bge_rx_alignment_bug) 965 m_adj(m_new, ETHER_ALIGN); 966 /* Set up the descriptor. */ 967 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 968 r = &sc->bge_ldata.bge_rx_jumbo_ring[i]; 969 ctx.bge_maxsegs = 1; 970 ctx.sc = sc; 971 error = bus_dmamap_load(sc->bge_cdata.bge_mtag_jumbo, 972 sc->bge_cdata.bge_rx_jumbo_dmamap[i], mtod(m_new, void *), 973 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 974 if (error || ctx.bge_maxsegs == 0) { 975 if (m == NULL) 976 m_freem(m_new); 977 return(ENOMEM); 978 } 979 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr)); 980 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr)); 981 r->bge_flags = htole16(BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING); 982 r->bge_len = htole16(m_new->m_len); 983 r->bge_idx = htole16(i); 984 985 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 986 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 987 BUS_DMASYNC_PREREAD); 988 989 return(0); 990 } 991 992 /* 993 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 994 * that's 1MB or memory, which is a lot. For now, we fill only the first 995 * 256 ring entries and hope that our CPU is fast enough to keep up with 996 * the NIC. 997 */ 998 static int 999 bge_init_rx_ring_std(sc) 1000 struct bge_softc *sc; 1001 { 1002 int i; 1003 1004 for (i = 0; i < BGE_SSLOTS; i++) { 1005 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 1006 return(ENOBUFS); 1007 }; 1008 1009 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1010 sc->bge_cdata.bge_rx_std_ring_map, 1011 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1012 1013 sc->bge_std = i - 1; 1014 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1015 1016 return(0); 1017 } 1018 1019 static void 1020 bge_free_rx_ring_std(sc) 1021 struct bge_softc *sc; 1022 { 1023 int i; 1024 1025 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1026 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1027 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1028 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1029 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1030 sc->bge_cdata.bge_rx_std_dmamap[i]); 1031 } 1032 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1033 sizeof(struct bge_rx_bd)); 1034 } 1035 1036 return; 1037 } 1038 1039 static int 1040 bge_init_rx_ring_jumbo(sc) 1041 struct bge_softc *sc; 1042 { 1043 int i; 1044 struct bge_rcb *rcb; 1045 1046 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1047 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 1048 return(ENOBUFS); 1049 }; 1050 1051 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1052 sc->bge_cdata.bge_rx_jumbo_ring_map, 1053 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1054 1055 sc->bge_jumbo = i - 1; 1056 1057 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1058 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 1059 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1060 1061 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1062 1063 return(0); 1064 } 1065 1066 static void 1067 bge_free_rx_ring_jumbo(sc) 1068 struct bge_softc *sc; 1069 { 1070 int i; 1071 1072 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1073 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1074 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1075 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1076 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1077 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1078 } 1079 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1080 sizeof(struct bge_rx_bd)); 1081 } 1082 1083 return; 1084 } 1085 1086 static void 1087 bge_free_tx_ring(sc) 1088 struct bge_softc *sc; 1089 { 1090 int i; 1091 1092 if (sc->bge_ldata.bge_tx_ring == NULL) 1093 return; 1094 1095 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1096 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1097 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1098 sc->bge_cdata.bge_tx_chain[i] = NULL; 1099 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 1100 sc->bge_cdata.bge_tx_dmamap[i]); 1101 } 1102 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1103 sizeof(struct bge_tx_bd)); 1104 } 1105 1106 return; 1107 } 1108 1109 static int 1110 bge_init_tx_ring(sc) 1111 struct bge_softc *sc; 1112 { 1113 sc->bge_txcnt = 0; 1114 sc->bge_tx_saved_considx = 0; 1115 1116 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1117 /* 5700 b2 errata */ 1118 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1119 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 1120 1121 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1122 /* 5700 b2 errata */ 1123 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1124 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1125 1126 return(0); 1127 } 1128 1129 #define BGE_POLY 0xEDB88320 1130 1131 static u_int32_t 1132 bge_crc(addr) 1133 caddr_t addr; 1134 { 1135 u_int32_t idx, bit, data, crc; 1136 1137 /* Compute CRC for the address value. */ 1138 crc = 0xFFFFFFFF; /* initial value */ 1139 1140 for (idx = 0; idx < 6; idx++) { 1141 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 1142 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 1143 } 1144 1145 return(crc & 0x7F); 1146 } 1147 1148 static void 1149 bge_setmulti(sc) 1150 struct bge_softc *sc; 1151 { 1152 struct ifnet *ifp; 1153 struct ifmultiaddr *ifma; 1154 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 1155 int h, i; 1156 1157 ifp = &sc->arpcom.ac_if; 1158 1159 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1160 for (i = 0; i < 4; i++) 1161 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1162 return; 1163 } 1164 1165 /* First, zot all the existing filters. */ 1166 for (i = 0; i < 4; i++) 1167 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1168 1169 /* Now program new ones. */ 1170 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1171 if (ifma->ifma_addr->sa_family != AF_LINK) 1172 continue; 1173 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 1174 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1175 } 1176 1177 for (i = 0; i < 4; i++) 1178 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1179 1180 return; 1181 } 1182 1183 /* 1184 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1185 * self-test results. 1186 */ 1187 static int 1188 bge_chipinit(sc) 1189 struct bge_softc *sc; 1190 { 1191 int i; 1192 u_int32_t dma_rw_ctl; 1193 1194 /* Set endianness before we access any non-PCI registers. */ 1195 #if BYTE_ORDER == BIG_ENDIAN 1196 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1197 BGE_BIGENDIAN_INIT, 4); 1198 #else 1199 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1200 BGE_LITTLEENDIAN_INIT, 4); 1201 #endif 1202 1203 /* 1204 * Check the 'ROM failed' bit on the RX CPU to see if 1205 * self-tests passed. 1206 */ 1207 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1208 printf("bge%d: RX CPU self-diagnostics failed!\n", 1209 sc->bge_unit); 1210 return(ENODEV); 1211 } 1212 1213 /* Clear the MAC control register */ 1214 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1215 1216 /* 1217 * Clear the MAC statistics block in the NIC's 1218 * internal memory. 1219 */ 1220 for (i = BGE_STATS_BLOCK; 1221 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1222 BGE_MEMWIN_WRITE(sc, i, 0); 1223 1224 for (i = BGE_STATUS_BLOCK; 1225 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1226 BGE_MEMWIN_WRITE(sc, i, 0); 1227 1228 /* Set up the PCI DMA control register. */ 1229 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1230 BGE_PCISTATE_PCI_BUSMODE) { 1231 /* Conventional PCI bus */ 1232 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1233 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1234 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1235 (0x0F); 1236 } else { 1237 /* PCI-X bus */ 1238 /* 1239 * The 5704 uses a different encoding of read/write 1240 * watermarks. 1241 */ 1242 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1243 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1244 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1245 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1246 else 1247 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1248 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1249 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1250 (0x0F); 1251 1252 /* 1253 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1254 * for hardware bugs. 1255 */ 1256 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1257 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1258 u_int32_t tmp; 1259 1260 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1261 if (tmp == 0x6 || tmp == 0x7) 1262 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1263 } 1264 } 1265 1266 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1267 sc->bge_asicrev == BGE_ASICREV_BCM5704 || 1268 sc->bge_asicrev == BGE_ASICREV_BCM5705) 1269 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1270 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1271 1272 /* 1273 * Set up general mode register. 1274 */ 1275 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1276 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1277 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1278 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM); 1279 1280 /* 1281 * Disable memory write invalidate. Apparently it is not supported 1282 * properly by these devices. 1283 */ 1284 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1285 1286 #ifdef __brokenalpha__ 1287 /* 1288 * Must insure that we do not cross an 8K (bytes) boundary 1289 * for DMA reads. Our highest limit is 1K bytes. This is a 1290 * restriction on some ALPHA platforms with early revision 1291 * 21174 PCI chipsets, such as the AlphaPC 164lx 1292 */ 1293 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1294 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1295 #endif 1296 1297 /* Set the timer prescaler (always 66Mhz) */ 1298 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1299 1300 return(0); 1301 } 1302 1303 static int 1304 bge_blockinit(sc) 1305 struct bge_softc *sc; 1306 { 1307 struct bge_rcb *rcb; 1308 volatile struct bge_rcb *vrcb; 1309 int i; 1310 1311 /* 1312 * Initialize the memory window pointer register so that 1313 * we can access the first 32K of internal NIC RAM. This will 1314 * allow us to set up the TX send ring RCBs and the RX return 1315 * ring RCBs, plus other things which live in NIC memory. 1316 */ 1317 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1318 1319 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1320 1321 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1322 /* Configure mbuf memory pool */ 1323 if (sc->bge_extram) { 1324 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1325 BGE_EXT_SSRAM); 1326 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1327 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1328 else 1329 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1330 } else { 1331 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, 1332 BGE_BUFFPOOL_1); 1333 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1334 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1335 else 1336 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1337 } 1338 1339 /* Configure DMA resource pool */ 1340 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1341 BGE_DMA_DESCRIPTORS); 1342 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1343 } 1344 1345 /* Configure mbuf pool watermarks */ 1346 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 1347 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1348 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1349 } else { 1350 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1351 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1352 } 1353 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1354 1355 /* Configure DMA resource watermarks */ 1356 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1357 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1358 1359 /* Enable buffer manager */ 1360 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1361 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1362 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1363 1364 /* Poll for buffer manager start indication */ 1365 for (i = 0; i < BGE_TIMEOUT; i++) { 1366 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1367 break; 1368 DELAY(10); 1369 } 1370 1371 if (i == BGE_TIMEOUT) { 1372 printf("bge%d: buffer manager failed to start\n", 1373 sc->bge_unit); 1374 return(ENXIO); 1375 } 1376 } 1377 1378 /* Enable flow-through queues */ 1379 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1380 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1381 1382 /* Wait until queue initialization is complete */ 1383 for (i = 0; i < BGE_TIMEOUT; i++) { 1384 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1385 break; 1386 DELAY(10); 1387 } 1388 1389 if (i == BGE_TIMEOUT) { 1390 printf("bge%d: flow-through queue init failed\n", 1391 sc->bge_unit); 1392 return(ENXIO); 1393 } 1394 1395 /* Initialize the standard RX ring control block */ 1396 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1397 rcb->bge_hostaddr.bge_addr_lo = 1398 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1399 rcb->bge_hostaddr.bge_addr_hi = 1400 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1401 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1402 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1403 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 1404 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1405 else 1406 rcb->bge_maxlen_flags = 1407 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1408 if (sc->bge_extram) 1409 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1410 else 1411 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1412 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1413 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1414 1415 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1416 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1417 1418 /* 1419 * Initialize the jumbo RX ring control block 1420 * We set the 'ring disabled' bit in the flags 1421 * field until we're actually ready to start 1422 * using this ring (i.e. once we set the MTU 1423 * high enough to require it). 1424 */ 1425 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1426 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1427 1428 rcb->bge_hostaddr.bge_addr_lo = 1429 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1430 rcb->bge_hostaddr.bge_addr_hi = 1431 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1432 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1433 sc->bge_cdata.bge_rx_jumbo_ring_map, 1434 BUS_DMASYNC_PREREAD); 1435 rcb->bge_maxlen_flags = 1436 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 1437 BGE_RCB_FLAG_RING_DISABLED); 1438 if (sc->bge_extram) 1439 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1440 else 1441 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1442 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1443 rcb->bge_hostaddr.bge_addr_hi); 1444 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1445 rcb->bge_hostaddr.bge_addr_lo); 1446 1447 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1448 rcb->bge_maxlen_flags); 1449 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1450 1451 /* Set up dummy disabled mini ring RCB */ 1452 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1453 rcb->bge_maxlen_flags = 1454 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1455 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1456 rcb->bge_maxlen_flags); 1457 } 1458 1459 /* 1460 * Set the BD ring replentish thresholds. The recommended 1461 * values are 1/8th the number of descriptors allocated to 1462 * each ring. 1463 */ 1464 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1465 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1466 1467 /* 1468 * Disable all unused send rings by setting the 'ring disabled' 1469 * bit in the flags field of all the TX send ring control blocks. 1470 * These are located in NIC memory. 1471 */ 1472 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1473 BGE_SEND_RING_RCB); 1474 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1475 vrcb->bge_maxlen_flags = 1476 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1477 vrcb->bge_nicaddr = 0; 1478 vrcb++; 1479 } 1480 1481 /* Configure TX RCB 0 (we use only the first ring) */ 1482 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1483 BGE_SEND_RING_RCB); 1484 vrcb->bge_hostaddr.bge_addr_lo = 1485 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr)); 1486 vrcb->bge_hostaddr.bge_addr_hi = 1487 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr)); 1488 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1489 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1490 vrcb->bge_maxlen_flags = 1491 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1492 1493 /* Disable all unused RX return rings */ 1494 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1495 BGE_RX_RETURN_RING_RCB); 1496 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1497 vrcb->bge_hostaddr.bge_addr_hi = 0; 1498 vrcb->bge_hostaddr.bge_addr_lo = 0; 1499 vrcb->bge_maxlen_flags = 1500 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1501 BGE_RCB_FLAG_RING_DISABLED); 1502 vrcb->bge_nicaddr = 0; 1503 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1504 (i * (sizeof(u_int64_t))), 0); 1505 vrcb++; 1506 } 1507 1508 /* Initialize RX ring indexes */ 1509 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1510 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1511 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1512 1513 /* 1514 * Set up RX return ring 0 1515 * Note that the NIC address for RX return rings is 0x00000000. 1516 * The return rings live entirely within the host, so the 1517 * nicaddr field in the RCB isn't used. 1518 */ 1519 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1520 BGE_RX_RETURN_RING_RCB); 1521 vrcb->bge_hostaddr.bge_addr_lo = 1522 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr); 1523 vrcb->bge_hostaddr.bge_addr_hi = 1524 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr); 1525 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 1526 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 1527 vrcb->bge_nicaddr = 0x00000000; 1528 vrcb->bge_maxlen_flags = 1529 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0); 1530 1531 /* Set random backoff seed for TX */ 1532 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1533 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1534 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1535 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1536 BGE_TX_BACKOFF_SEED_MASK); 1537 1538 /* Set inter-packet gap */ 1539 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1540 1541 /* 1542 * Specify which ring to use for packets that don't match 1543 * any RX rules. 1544 */ 1545 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1546 1547 /* 1548 * Configure number of RX lists. One interrupt distribution 1549 * list, sixteen active lists, one bad frames class. 1550 */ 1551 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1552 1553 /* Inialize RX list placement stats mask. */ 1554 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1555 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1556 1557 /* Disable host coalescing until we get it set up */ 1558 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1559 1560 /* Poll to make sure it's shut down. */ 1561 for (i = 0; i < BGE_TIMEOUT; i++) { 1562 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1563 break; 1564 DELAY(10); 1565 } 1566 1567 if (i == BGE_TIMEOUT) { 1568 printf("bge%d: host coalescing engine failed to idle\n", 1569 sc->bge_unit); 1570 return(ENXIO); 1571 } 1572 1573 /* Set up host coalescing defaults */ 1574 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1575 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1576 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1577 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1578 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1579 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1580 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1581 } 1582 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1583 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1584 1585 /* Set up address of statistics block */ 1586 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1587 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1588 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1589 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1590 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1591 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1592 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1593 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1594 } 1595 1596 /* Set up address of status block */ 1597 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1598 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1599 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1600 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1601 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1602 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 1603 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx = 0; 1604 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx = 0; 1605 1606 /* Turn on host coalescing state machine */ 1607 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1608 1609 /* Turn on RX BD completion state machine and enable attentions */ 1610 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1611 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1612 1613 /* Turn on RX list placement state machine */ 1614 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1615 1616 /* Turn on RX list selector state machine. */ 1617 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1618 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1619 1620 /* Turn on DMA, clear stats */ 1621 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1622 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1623 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1624 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1625 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1626 1627 /* Set misc. local control, enable interrupts on attentions */ 1628 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1629 1630 #ifdef notdef 1631 /* Assert GPIO pins for PHY reset */ 1632 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1633 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1634 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1635 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1636 #endif 1637 1638 /* Turn on DMA completion state machine */ 1639 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1640 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1641 1642 /* Turn on write DMA state machine */ 1643 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1644 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1645 1646 /* Turn on read DMA state machine */ 1647 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1648 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1649 1650 /* Turn on RX data completion state machine */ 1651 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1652 1653 /* Turn on RX BD initiator state machine */ 1654 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1655 1656 /* Turn on RX data and RX BD initiator state machine */ 1657 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1658 1659 /* Turn on Mbuf cluster free state machine */ 1660 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 1661 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1662 1663 /* Turn on send BD completion state machine */ 1664 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1665 1666 /* Turn on send data completion state machine */ 1667 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1668 1669 /* Turn on send data initiator state machine */ 1670 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1671 1672 /* Turn on send BD initiator state machine */ 1673 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1674 1675 /* Turn on send BD selector state machine */ 1676 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1677 1678 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1679 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1680 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1681 1682 /* ack/clear link change events */ 1683 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1684 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 1685 BGE_MACSTAT_LINK_CHANGED); 1686 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1687 1688 /* Enable PHY auto polling (for MII/GMII only) */ 1689 if (sc->bge_tbi) { 1690 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1691 } else { 1692 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1693 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1694 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1695 BGE_EVTENB_MI_INTERRUPT); 1696 } 1697 1698 /* Enable link state change attentions. */ 1699 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1700 1701 return(0); 1702 } 1703 1704 /* 1705 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1706 * against our list and return its name if we find a match. Note 1707 * that since the Broadcom controller contains VPD support, we 1708 * can get the device name string from the controller itself instead 1709 * of the compiled-in string. This is a little slow, but it guarantees 1710 * we'll always announce the right product name. 1711 */ 1712 static int 1713 bge_probe(dev) 1714 device_t dev; 1715 { 1716 struct bge_type *t; 1717 struct bge_softc *sc; 1718 char *descbuf; 1719 1720 t = bge_devs; 1721 1722 sc = device_get_softc(dev); 1723 bzero(sc, sizeof(struct bge_softc)); 1724 sc->bge_unit = device_get_unit(dev); 1725 sc->bge_dev = dev; 1726 1727 while(t->bge_name != NULL) { 1728 if ((pci_get_vendor(dev) == t->bge_vid) && 1729 (pci_get_device(dev) == t->bge_did)) { 1730 #ifdef notdef 1731 bge_vpd_read(sc); 1732 device_set_desc(dev, sc->bge_vpd_prodname); 1733 #endif 1734 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1735 if (descbuf == NULL) 1736 return(ENOMEM); 1737 snprintf(descbuf, BGE_DEVDESC_MAX, 1738 "%s, ASIC rev. %#04x", t->bge_name, 1739 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1740 device_set_desc_copy(dev, descbuf); 1741 if (pci_get_subvendor(dev) == DELL_VENDORID) 1742 sc->bge_no_3_led = 1; 1743 free(descbuf, M_TEMP); 1744 return(0); 1745 } 1746 t++; 1747 } 1748 1749 return(ENXIO); 1750 } 1751 1752 static void 1753 bge_dma_free(sc) 1754 struct bge_softc *sc; 1755 { 1756 int i; 1757 1758 1759 /* Destroy DMA maps for RX buffers */ 1760 1761 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1762 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 1763 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1764 sc->bge_cdata.bge_rx_std_dmamap[i]); 1765 } 1766 1767 /* Destroy DMA maps for jumbo RX buffers */ 1768 1769 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1770 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 1771 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 1772 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1773 } 1774 1775 /* Destroy DMA maps for TX buffers */ 1776 1777 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1778 if (sc->bge_cdata.bge_tx_dmamap[i]) 1779 bus_dmamap_destroy(sc->bge_cdata.bge_mtag, 1780 sc->bge_cdata.bge_tx_dmamap[i]); 1781 } 1782 1783 if (sc->bge_cdata.bge_mtag) 1784 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag); 1785 1786 1787 /* Destroy standard RX ring */ 1788 1789 if (sc->bge_ldata.bge_rx_std_ring) 1790 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 1791 sc->bge_ldata.bge_rx_std_ring, 1792 sc->bge_cdata.bge_rx_std_ring_map); 1793 1794 if (sc->bge_cdata.bge_rx_std_ring_map) { 1795 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 1796 sc->bge_cdata.bge_rx_std_ring_map); 1797 bus_dmamap_destroy(sc->bge_cdata.bge_rx_std_ring_tag, 1798 sc->bge_cdata.bge_rx_std_ring_map); 1799 } 1800 1801 if (sc->bge_cdata.bge_rx_std_ring_tag) 1802 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 1803 1804 /* Destroy jumbo RX ring */ 1805 1806 if (sc->bge_ldata.bge_rx_jumbo_ring) 1807 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1808 sc->bge_ldata.bge_rx_jumbo_ring, 1809 sc->bge_cdata.bge_rx_jumbo_ring_map); 1810 1811 if (sc->bge_cdata.bge_rx_jumbo_ring_map) { 1812 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1813 sc->bge_cdata.bge_rx_jumbo_ring_map); 1814 bus_dmamap_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1815 sc->bge_cdata.bge_rx_jumbo_ring_map); 1816 } 1817 1818 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 1819 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 1820 1821 /* Destroy RX return ring */ 1822 1823 if (sc->bge_ldata.bge_rx_return_ring) 1824 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 1825 sc->bge_ldata.bge_rx_return_ring, 1826 sc->bge_cdata.bge_rx_return_ring_map); 1827 1828 if (sc->bge_cdata.bge_rx_return_ring_map) { 1829 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 1830 sc->bge_cdata.bge_rx_return_ring_map); 1831 bus_dmamap_destroy(sc->bge_cdata.bge_rx_return_ring_tag, 1832 sc->bge_cdata.bge_rx_return_ring_map); 1833 } 1834 1835 if (sc->bge_cdata.bge_rx_return_ring_tag) 1836 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 1837 1838 /* Destroy TX ring */ 1839 1840 if (sc->bge_ldata.bge_tx_ring) 1841 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 1842 sc->bge_ldata.bge_tx_ring, 1843 sc->bge_cdata.bge_tx_ring_map); 1844 1845 if (sc->bge_cdata.bge_tx_ring_map) { 1846 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 1847 sc->bge_cdata.bge_tx_ring_map); 1848 bus_dmamap_destroy(sc->bge_cdata.bge_tx_ring_tag, 1849 sc->bge_cdata.bge_tx_ring_map); 1850 } 1851 1852 if (sc->bge_cdata.bge_tx_ring_tag) 1853 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 1854 1855 /* Destroy status block */ 1856 1857 if (sc->bge_ldata.bge_status_block) 1858 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 1859 sc->bge_ldata.bge_status_block, 1860 sc->bge_cdata.bge_status_map); 1861 1862 if (sc->bge_cdata.bge_status_map) { 1863 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 1864 sc->bge_cdata.bge_status_map); 1865 bus_dmamap_destroy(sc->bge_cdata.bge_status_tag, 1866 sc->bge_cdata.bge_status_map); 1867 } 1868 1869 if (sc->bge_cdata.bge_status_tag) 1870 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 1871 1872 /* Destroy statistics block */ 1873 1874 if (sc->bge_ldata.bge_stats) 1875 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 1876 sc->bge_ldata.bge_stats, 1877 sc->bge_cdata.bge_stats_map); 1878 1879 if (sc->bge_cdata.bge_stats_map) { 1880 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 1881 sc->bge_cdata.bge_stats_map); 1882 bus_dmamap_destroy(sc->bge_cdata.bge_stats_tag, 1883 sc->bge_cdata.bge_stats_map); 1884 } 1885 1886 if (sc->bge_cdata.bge_stats_tag) 1887 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 1888 1889 /* Destroy the parent tag */ 1890 1891 if (sc->bge_cdata.bge_parent_tag) 1892 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 1893 1894 return; 1895 } 1896 1897 static int 1898 bge_dma_alloc(dev) 1899 device_t dev; 1900 { 1901 struct bge_softc *sc; 1902 int nseg, i, error; 1903 struct bge_dmamap_arg ctx; 1904 1905 sc = device_get_softc(dev); 1906 1907 /* 1908 * Allocate the parent bus DMA tag appropriate for PCI. 1909 */ 1910 #define BGE_NSEG_NEW 32 1911 error = bus_dma_tag_create(NULL, /* parent */ 1912 PAGE_SIZE, 0, /* alignment, boundary */ 1913 BUS_SPACE_MAXADDR, /* lowaddr */ 1914 BUS_SPACE_MAXADDR_32BIT,/* highaddr */ 1915 NULL, NULL, /* filter, filterarg */ 1916 MAXBSIZE, BGE_NSEG_NEW, /* maxsize, nsegments */ 1917 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1918 BUS_DMA_ALLOCNOW, /* flags */ 1919 NULL, NULL, /* lockfunc, lockarg */ 1920 &sc->bge_cdata.bge_parent_tag); 1921 1922 /* 1923 * Create tag for RX mbufs. 1924 */ 1925 nseg = 32; 1926 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, ETHER_ALIGN, 1927 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1928 NULL, MCLBYTES * nseg, nseg, MCLBYTES, 0, NULL, NULL, 1929 &sc->bge_cdata.bge_mtag); 1930 1931 if (error) { 1932 device_printf(dev, "could not allocate dma tag\n"); 1933 return (ENOMEM); 1934 } 1935 1936 /* Create DMA maps for RX buffers */ 1937 1938 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1939 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1940 &sc->bge_cdata.bge_rx_std_dmamap[i]); 1941 if (error) { 1942 device_printf(dev, "can't create DMA map for RX\n"); 1943 return(ENOMEM); 1944 } 1945 } 1946 1947 /* Create DMA maps for TX buffers */ 1948 1949 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1950 error = bus_dmamap_create(sc->bge_cdata.bge_mtag, 0, 1951 &sc->bge_cdata.bge_tx_dmamap[i]); 1952 if (error) { 1953 device_printf(dev, "can't create DMA map for RX\n"); 1954 return(ENOMEM); 1955 } 1956 } 1957 1958 /* Create tag for standard RX ring */ 1959 1960 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1961 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1962 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 1963 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 1964 1965 if (error) { 1966 device_printf(dev, "could not allocate dma tag\n"); 1967 return (ENOMEM); 1968 } 1969 1970 /* Allocate DMA'able memory for standard RX ring */ 1971 1972 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 1973 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 1974 &sc->bge_cdata.bge_rx_std_ring_map); 1975 if (error) 1976 return (ENOMEM); 1977 1978 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1979 1980 /* Load the address of the standard RX ring */ 1981 1982 ctx.bge_maxsegs = 1; 1983 ctx.sc = sc; 1984 1985 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 1986 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 1987 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 1988 1989 if (error) 1990 return (ENOMEM); 1991 1992 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 1993 1994 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 1995 1996 /* 1997 * Create tag for jumbo mbufs. 1998 * This is really a bit of a kludge. We allocate a special 1999 * jumbo buffer pool which (thanks to the way our DMA 2000 * memory allocation works) will consist of contiguous 2001 * pages. This means that even though a jumbo buffer might 2002 * be larger than a page size, we don't really need to 2003 * map it into more than one DMA segment. However, the 2004 * default mbuf tag will result in multi-segment mappings, 2005 * so we have to create a special jumbo mbuf tag that 2006 * lets us get away with mapping the jumbo buffers as 2007 * a single segment. I think eventually the driver should 2008 * be changed so that it uses ordinary mbufs and cluster 2009 * buffers, i.e. jumbo frames can span multiple DMA 2010 * descriptors. But that's a project for another day. 2011 */ 2012 2013 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2014 ETHER_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2015 NULL, MCLBYTES * nseg, nseg, BGE_JLEN, 0, NULL, NULL, 2016 &sc->bge_cdata.bge_mtag_jumbo); 2017 2018 if (error) { 2019 device_printf(dev, "could not allocate dma tag\n"); 2020 return (ENOMEM); 2021 } 2022 2023 /* Create tag for jumbo RX ring */ 2024 2025 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2026 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2027 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2028 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2029 2030 if (error) { 2031 device_printf(dev, "could not allocate dma tag\n"); 2032 return (ENOMEM); 2033 } 2034 2035 /* Allocate DMA'able memory for jumbo RX ring */ 2036 2037 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2038 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, BUS_DMA_NOWAIT, 2039 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2040 if (error) 2041 return (ENOMEM); 2042 2043 bzero((char *)sc->bge_ldata.bge_rx_jumbo_ring, 2044 BGE_JUMBO_RX_RING_SZ); 2045 2046 /* Load the address of the jumbo RX ring */ 2047 2048 ctx.bge_maxsegs = 1; 2049 ctx.sc = sc; 2050 2051 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2052 sc->bge_cdata.bge_rx_jumbo_ring_map, 2053 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2054 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2055 2056 if (error) 2057 return (ENOMEM); 2058 2059 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2060 2061 /* Create DMA maps for jumbo RX buffers */ 2062 2063 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2064 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2065 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2066 if (error) { 2067 device_printf(dev, 2068 "can't create DMA map for RX\n"); 2069 return(ENOMEM); 2070 } 2071 } 2072 2073 } 2074 2075 /* Create tag for RX return ring */ 2076 2077 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2078 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2079 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2080 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2081 2082 if (error) { 2083 device_printf(dev, "could not allocate dma tag\n"); 2084 return (ENOMEM); 2085 } 2086 2087 /* Allocate DMA'able memory for RX return ring */ 2088 2089 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2090 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2091 &sc->bge_cdata.bge_rx_return_ring_map); 2092 if (error) 2093 return (ENOMEM); 2094 2095 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2096 BGE_RX_RTN_RING_SZ(sc)); 2097 2098 /* Load the address of the RX return ring */ 2099 2100 ctx.bge_maxsegs = 1; 2101 ctx.sc = sc; 2102 2103 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2104 sc->bge_cdata.bge_rx_return_ring_map, 2105 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2106 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2107 2108 if (error) 2109 return (ENOMEM); 2110 2111 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2112 2113 /* Create tag for TX ring */ 2114 2115 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2116 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2117 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2118 &sc->bge_cdata.bge_tx_ring_tag); 2119 2120 if (error) { 2121 device_printf(dev, "could not allocate dma tag\n"); 2122 return (ENOMEM); 2123 } 2124 2125 /* Allocate DMA'able memory for TX ring */ 2126 2127 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2128 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2129 &sc->bge_cdata.bge_tx_ring_map); 2130 if (error) 2131 return (ENOMEM); 2132 2133 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2134 2135 /* Load the address of the TX ring */ 2136 2137 ctx.bge_maxsegs = 1; 2138 ctx.sc = sc; 2139 2140 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2141 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2142 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2143 2144 if (error) 2145 return (ENOMEM); 2146 2147 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2148 2149 /* Create tag for status block */ 2150 2151 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2152 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2153 NULL, BGE_STATUS_BLK_SZ, 1, BGE_STATUS_BLK_SZ, 0, 2154 NULL, NULL, &sc->bge_cdata.bge_status_tag); 2155 2156 if (error) { 2157 device_printf(dev, "could not allocate dma tag\n"); 2158 return (ENOMEM); 2159 } 2160 2161 /* Allocate DMA'able memory for status block */ 2162 2163 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2164 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2165 &sc->bge_cdata.bge_status_map); 2166 if (error) 2167 return (ENOMEM); 2168 2169 bzero((char *)sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2170 2171 /* Load the address of the status block */ 2172 2173 ctx.sc = sc; 2174 ctx.bge_maxsegs = 1; 2175 2176 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2177 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2178 BGE_STATUS_BLK_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2179 2180 if (error) 2181 return (ENOMEM); 2182 2183 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2184 2185 /* Create tag for statistics block */ 2186 2187 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2188 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2189 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2190 &sc->bge_cdata.bge_stats_tag); 2191 2192 if (error) { 2193 device_printf(dev, "could not allocate dma tag\n"); 2194 return (ENOMEM); 2195 } 2196 2197 /* Allocate DMA'able memory for statistics block */ 2198 2199 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2200 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2201 &sc->bge_cdata.bge_stats_map); 2202 if (error) 2203 return (ENOMEM); 2204 2205 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2206 2207 /* Load the address of the statstics block */ 2208 2209 ctx.sc = sc; 2210 ctx.bge_maxsegs = 1; 2211 2212 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2213 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2214 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2215 2216 if (error) 2217 return (ENOMEM); 2218 2219 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2220 2221 return(0); 2222 } 2223 2224 static int 2225 bge_attach(dev) 2226 device_t dev; 2227 { 2228 int s; 2229 struct ifnet *ifp; 2230 struct bge_softc *sc; 2231 u_int32_t hwcfg = 0; 2232 u_int32_t mac_addr = 0; 2233 int unit, error = 0, rid; 2234 2235 s = splimp(); 2236 2237 sc = device_get_softc(dev); 2238 unit = device_get_unit(dev); 2239 sc->bge_dev = dev; 2240 sc->bge_unit = unit; 2241 2242 /* 2243 * Map control/status registers. 2244 */ 2245 pci_enable_busmaster(dev); 2246 2247 rid = BGE_PCI_BAR0; 2248 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 2249 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 2250 2251 if (sc->bge_res == NULL) { 2252 printf ("bge%d: couldn't map memory\n", unit); 2253 error = ENXIO; 2254 goto fail; 2255 } 2256 2257 sc->bge_btag = rman_get_bustag(sc->bge_res); 2258 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 2259 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 2260 2261 /* Allocate interrupt */ 2262 rid = 0; 2263 2264 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 2265 RF_SHAREABLE | RF_ACTIVE); 2266 2267 if (sc->bge_irq == NULL) { 2268 printf("bge%d: couldn't map interrupt\n", unit); 2269 error = ENXIO; 2270 goto fail; 2271 } 2272 2273 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 2274 bge_intr, sc, &sc->bge_intrhand); 2275 2276 if (error) { 2277 bge_release_resources(sc); 2278 printf("bge%d: couldn't set up irq\n", unit); 2279 goto fail; 2280 } 2281 2282 sc->bge_unit = unit; 2283 2284 /* Try to reset the chip. */ 2285 bge_reset(sc); 2286 2287 if (bge_chipinit(sc)) { 2288 printf("bge%d: chip initialization failed\n", sc->bge_unit); 2289 bge_release_resources(sc); 2290 error = ENXIO; 2291 goto fail; 2292 } 2293 2294 /* 2295 * Get station address from the EEPROM. 2296 */ 2297 mac_addr = bge_readmem_ind(sc, 0x0c14); 2298 if ((mac_addr >> 16) == 0x484b) { 2299 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 2300 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 2301 mac_addr = bge_readmem_ind(sc, 0x0c18); 2302 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 2303 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 2304 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 2305 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 2306 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 2307 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 2308 printf("bge%d: failed to read station address\n", unit); 2309 bge_release_resources(sc); 2310 error = ENXIO; 2311 goto fail; 2312 } 2313 2314 /* 2315 * A Broadcom chip was detected. Inform the world. 2316 */ 2317 printf("bge%d: Ethernet address: %6D\n", unit, 2318 sc->arpcom.ac_enaddr, ":"); 2319 2320 /* Save ASIC rev. */ 2321 2322 sc->bge_chipid = 2323 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 2324 BGE_PCIMISCCTL_ASICREV; 2325 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2326 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2327 2328 /* 5705 limits RX return ring to 512 entries. */ 2329 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2330 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2331 else 2332 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2333 2334 if (bge_dma_alloc(dev)) { 2335 printf ("bge%d: failed to allocate DMA resources\n", 2336 sc->bge_unit); 2337 bge_release_resources(sc); 2338 error = ENXIO; 2339 goto fail; 2340 } 2341 2342 /* 2343 * Try to allocate memory for jumbo buffers. 2344 * The 5705 does not appear to support jumbo frames. 2345 */ 2346 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2347 if (bge_alloc_jumbo_mem(sc)) { 2348 printf("bge%d: jumbo buffer allocation " 2349 "failed\n", sc->bge_unit); 2350 bge_release_resources(sc); 2351 error = ENXIO; 2352 goto fail; 2353 } 2354 } 2355 2356 /* Set default tuneable values. */ 2357 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2358 sc->bge_rx_coal_ticks = 150; 2359 sc->bge_tx_coal_ticks = 150; 2360 sc->bge_rx_max_coal_bds = 64; 2361 sc->bge_tx_max_coal_bds = 128; 2362 2363 /* Set up ifnet structure */ 2364 ifp = &sc->arpcom.ac_if; 2365 ifp->if_softc = sc; 2366 ifp->if_unit = sc->bge_unit; 2367 ifp->if_name = "bge"; 2368 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2369 ifp->if_ioctl = bge_ioctl; 2370 ifp->if_output = ether_output; 2371 ifp->if_start = bge_start; 2372 ifp->if_watchdog = bge_watchdog; 2373 ifp->if_init = bge_init; 2374 ifp->if_mtu = ETHERMTU; 2375 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 2376 ifp->if_hwassist = BGE_CSUM_FEATURES; 2377 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2378 IFCAP_VLAN_MTU; 2379 ifp->if_capenable = ifp->if_capabilities; 2380 2381 /* 2382 * Figure out what sort of media we have by checking the 2383 * hardware config word in the first 32k of NIC internal memory, 2384 * or fall back to examining the EEPROM if necessary. 2385 * Note: on some BCM5700 cards, this value appears to be unset. 2386 * If that's the case, we have to rely on identifying the NIC 2387 * by its PCI subsystem ID, as we do below for the SysKonnect 2388 * SK-9D41. 2389 */ 2390 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2391 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2392 else { 2393 bge_read_eeprom(sc, (caddr_t)&hwcfg, 2394 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 2395 hwcfg = ntohl(hwcfg); 2396 } 2397 2398 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 2399 sc->bge_tbi = 1; 2400 2401 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2402 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 2403 sc->bge_tbi = 1; 2404 2405 if (sc->bge_tbi) { 2406 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 2407 bge_ifmedia_upd, bge_ifmedia_sts); 2408 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 2409 ifmedia_add(&sc->bge_ifmedia, 2410 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 2411 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 2412 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 2413 } else { 2414 /* 2415 * Do transceiver setup. 2416 */ 2417 if (mii_phy_probe(dev, &sc->bge_miibus, 2418 bge_ifmedia_upd, bge_ifmedia_sts)) { 2419 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 2420 bge_release_resources(sc); 2421 bge_free_jumbo_mem(sc); 2422 error = ENXIO; 2423 goto fail; 2424 } 2425 } 2426 2427 /* 2428 * When using the BCM5701 in PCI-X mode, data corruption has 2429 * been observed in the first few bytes of some received packets. 2430 * Aligning the packet buffer in memory eliminates the corruption. 2431 * Unfortunately, this misaligns the packet payloads. On platforms 2432 * which do not support unaligned accesses, we will realign the 2433 * payloads by copying the received packets. 2434 */ 2435 switch (sc->bge_chipid) { 2436 case BGE_CHIPID_BCM5701_A0: 2437 case BGE_CHIPID_BCM5701_B0: 2438 case BGE_CHIPID_BCM5701_B2: 2439 case BGE_CHIPID_BCM5701_B5: 2440 /* If in PCI-X mode, work around the alignment bug. */ 2441 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2442 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 2443 BGE_PCISTATE_PCI_BUSSPEED) 2444 sc->bge_rx_alignment_bug = 1; 2445 break; 2446 } 2447 2448 /* 2449 * Call MI attach routine. 2450 */ 2451 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 2452 callout_handle_init(&sc->bge_stat_ch); 2453 2454 fail: 2455 splx(s); 2456 2457 return(error); 2458 } 2459 2460 static int 2461 bge_detach(dev) 2462 device_t dev; 2463 { 2464 struct bge_softc *sc; 2465 struct ifnet *ifp; 2466 int s; 2467 2468 s = splimp(); 2469 2470 sc = device_get_softc(dev); 2471 ifp = &sc->arpcom.ac_if; 2472 2473 ether_ifdetach(ifp); 2474 bge_stop(sc); 2475 bge_reset(sc); 2476 2477 if (sc->bge_tbi) { 2478 ifmedia_removeall(&sc->bge_ifmedia); 2479 } else { 2480 bus_generic_detach(dev); 2481 device_delete_child(dev, sc->bge_miibus); 2482 } 2483 2484 bge_release_resources(sc); 2485 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2486 bge_free_jumbo_mem(sc); 2487 2488 splx(s); 2489 2490 return(0); 2491 } 2492 2493 static void 2494 bge_release_resources(sc) 2495 struct bge_softc *sc; 2496 { 2497 device_t dev; 2498 2499 dev = sc->bge_dev; 2500 2501 if (sc->bge_vpd_prodname != NULL) 2502 free(sc->bge_vpd_prodname, M_DEVBUF); 2503 2504 if (sc->bge_vpd_readonly != NULL) 2505 free(sc->bge_vpd_readonly, M_DEVBUF); 2506 2507 if (sc->bge_intrhand != NULL) 2508 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 2509 2510 if (sc->bge_irq != NULL) 2511 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 2512 2513 if (sc->bge_res != NULL) 2514 bus_release_resource(dev, SYS_RES_MEMORY, 2515 BGE_PCI_BAR0, sc->bge_res); 2516 2517 bge_dma_free(sc); 2518 2519 return; 2520 } 2521 2522 static void 2523 bge_reset(sc) 2524 struct bge_softc *sc; 2525 { 2526 device_t dev; 2527 u_int32_t cachesize, command, pcistate; 2528 int i, val = 0; 2529 2530 dev = sc->bge_dev; 2531 2532 /* Save some important PCI state. */ 2533 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 2534 command = pci_read_config(dev, BGE_PCI_CMD, 4); 2535 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 2536 2537 pci_write_config(dev, BGE_PCI_MISC_CTL, 2538 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2539 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2540 2541 /* Issue global reset */ 2542 bge_writereg_ind(sc, BGE_MISC_CFG, 2543 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 2544 2545 DELAY(1000); 2546 2547 /* Reset some of the PCI state that got zapped by reset */ 2548 pci_write_config(dev, BGE_PCI_MISC_CTL, 2549 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 2550 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 2551 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 2552 pci_write_config(dev, BGE_PCI_CMD, command, 4); 2553 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 2554 2555 /* 2556 * Prevent PXE restart: write a magic number to the 2557 * general communications memory at 0xB50. 2558 */ 2559 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 2560 /* 2561 * Poll the value location we just wrote until 2562 * we see the 1's complement of the magic number. 2563 * This indicates that the firmware initialization 2564 * is complete. 2565 */ 2566 for (i = 0; i < BGE_TIMEOUT; i++) { 2567 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 2568 if (val == ~BGE_MAGIC_NUMBER) 2569 break; 2570 DELAY(10); 2571 } 2572 2573 if (i == BGE_TIMEOUT) { 2574 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 2575 return; 2576 } 2577 2578 /* 2579 * XXX Wait for the value of the PCISTATE register to 2580 * return to its original pre-reset state. This is a 2581 * fairly good indicator of reset completion. If we don't 2582 * wait for the reset to fully complete, trying to read 2583 * from the device's non-PCI registers may yield garbage 2584 * results. 2585 */ 2586 for (i = 0; i < BGE_TIMEOUT; i++) { 2587 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 2588 break; 2589 DELAY(10); 2590 } 2591 2592 /* Enable memory arbiter. */ 2593 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 2594 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2595 2596 /* Fix up byte swapping */ 2597 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 2598 BGE_MODECTL_BYTESWAP_DATA); 2599 2600 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 2601 2602 DELAY(10000); 2603 2604 return; 2605 } 2606 2607 /* 2608 * Frame reception handling. This is called if there's a frame 2609 * on the receive return list. 2610 * 2611 * Note: we have to be able to handle two possibilities here: 2612 * 1) the frame is from the jumbo recieve ring 2613 * 2) the frame is from the standard receive ring 2614 */ 2615 2616 static void 2617 bge_rxeof(sc) 2618 struct bge_softc *sc; 2619 { 2620 struct ifnet *ifp; 2621 int stdcnt = 0, jumbocnt = 0; 2622 2623 ifp = &sc->arpcom.ac_if; 2624 2625 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2626 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTWRITE); 2627 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2628 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTREAD); 2629 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2630 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2631 sc->bge_cdata.bge_rx_jumbo_ring_map, 2632 BUS_DMASYNC_POSTREAD); 2633 } 2634 2635 while(sc->bge_rx_saved_considx != 2636 sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx) { 2637 struct bge_rx_bd *cur_rx; 2638 u_int32_t rxidx; 2639 struct ether_header *eh; 2640 struct mbuf *m = NULL; 2641 u_int16_t vlan_tag = 0; 2642 int have_tag = 0; 2643 2644 cur_rx = 2645 &sc->bge_ldata.bge_rx_return_ring[sc->bge_rx_saved_considx]; 2646 2647 rxidx = cur_rx->bge_idx; 2648 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt); 2649 2650 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 2651 have_tag = 1; 2652 vlan_tag = cur_rx->bge_vlan_tag; 2653 } 2654 2655 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 2656 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 2657 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 2658 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx], 2659 BUS_DMASYNC_POSTREAD); 2660 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 2661 sc->bge_cdata.bge_rx_jumbo_dmamap[rxidx]); 2662 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 2663 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 2664 jumbocnt++; 2665 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2666 ifp->if_ierrors++; 2667 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2668 continue; 2669 } 2670 if (bge_newbuf_jumbo(sc, 2671 sc->bge_jumbo, NULL) == ENOBUFS) { 2672 ifp->if_ierrors++; 2673 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 2674 continue; 2675 } 2676 } else { 2677 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 2678 bus_dmamap_sync(sc->bge_cdata.bge_mtag, 2679 sc->bge_cdata.bge_rx_std_dmamap[rxidx], 2680 BUS_DMASYNC_POSTREAD); 2681 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2682 sc->bge_cdata.bge_rx_std_dmamap[rxidx]); 2683 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 2684 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 2685 stdcnt++; 2686 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 2687 ifp->if_ierrors++; 2688 bge_newbuf_std(sc, sc->bge_std, m); 2689 continue; 2690 } 2691 if (bge_newbuf_std(sc, sc->bge_std, 2692 NULL) == ENOBUFS) { 2693 ifp->if_ierrors++; 2694 bge_newbuf_std(sc, sc->bge_std, m); 2695 continue; 2696 } 2697 } 2698 2699 ifp->if_ipackets++; 2700 #ifndef __i386__ 2701 /* 2702 * The i386 allows unaligned accesses, but for other 2703 * platforms we must make sure the payload is aligned. 2704 */ 2705 if (sc->bge_rx_alignment_bug) { 2706 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 2707 cur_rx->bge_len); 2708 m->m_data += ETHER_ALIGN; 2709 } 2710 #endif 2711 eh = mtod(m, struct ether_header *); 2712 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 2713 m->m_pkthdr.rcvif = ifp; 2714 2715 #if 0 /* currently broken for some packets, possibly related to TCP options */ 2716 if (ifp->if_hwassist) { 2717 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2718 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 2719 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2720 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 2721 m->m_pkthdr.csum_data = 2722 cur_rx->bge_tcp_udp_csum; 2723 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 2724 } 2725 } 2726 #endif 2727 2728 /* 2729 * If we received a packet with a vlan tag, 2730 * attach that information to the packet. 2731 */ 2732 if (have_tag) 2733 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 2734 2735 (*ifp->if_input)(ifp, m); 2736 } 2737 2738 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 2739 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE); 2740 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2741 sc->bge_cdata.bge_rx_std_ring_map, 2742 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_PREWRITE); 2743 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 2744 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2745 sc->bge_cdata.bge_rx_jumbo_ring_map, 2746 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 2747 } 2748 2749 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 2750 if (stdcnt) 2751 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 2752 if (jumbocnt) 2753 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2754 2755 return; 2756 } 2757 2758 static void 2759 bge_txeof(sc) 2760 struct bge_softc *sc; 2761 { 2762 struct bge_tx_bd *cur_tx = NULL; 2763 struct ifnet *ifp; 2764 2765 ifp = &sc->arpcom.ac_if; 2766 2767 /* 2768 * Go through our tx ring and free mbufs for those 2769 * frames that have been sent. 2770 */ 2771 while (sc->bge_tx_saved_considx != 2772 sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx) { 2773 u_int32_t idx = 0; 2774 2775 idx = sc->bge_tx_saved_considx; 2776 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 2777 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2778 ifp->if_opackets++; 2779 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2780 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2781 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2782 bus_dmamap_unload(sc->bge_cdata.bge_mtag, 2783 sc->bge_cdata.bge_tx_dmamap[idx]); 2784 } 2785 sc->bge_txcnt--; 2786 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2787 ifp->if_timer = 0; 2788 } 2789 2790 if (cur_tx != NULL) 2791 ifp->if_flags &= ~IFF_OACTIVE; 2792 2793 return; 2794 } 2795 2796 static void 2797 bge_intr(xsc) 2798 void *xsc; 2799 { 2800 struct bge_softc *sc; 2801 struct ifnet *ifp; 2802 u_int32_t statusword; 2803 u_int32_t status; 2804 2805 sc = xsc; 2806 ifp = &sc->arpcom.ac_if; 2807 2808 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2809 sc->bge_cdata.bge_status_map, BUS_DMASYNC_POSTWRITE); 2810 2811 statusword = 2812 atomic_readandclear_32(&sc->bge_ldata.bge_status_block->bge_status); 2813 2814 #ifdef notdef 2815 /* Avoid this for now -- checking this register is expensive. */ 2816 /* Make sure this is really our interrupt. */ 2817 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2818 return; 2819 #endif 2820 /* Ack interrupt and stop others from occuring. */ 2821 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2822 2823 /* 2824 * Process link state changes. 2825 * Grrr. The link status word in the status block does 2826 * not work correctly on the BCM5700 rev AX and BX chips, 2827 * according to all avaibable information. Hence, we have 2828 * to enable MII interrupts in order to properly obtain 2829 * async link changes. Unfortunately, this also means that 2830 * we have to read the MAC status register to detect link 2831 * changes, thereby adding an additional register access to 2832 * the interrupt handler. 2833 */ 2834 2835 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2836 2837 status = CSR_READ_4(sc, BGE_MAC_STS); 2838 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2839 sc->bge_link = 0; 2840 untimeout(bge_tick, sc, sc->bge_stat_ch); 2841 bge_tick(sc); 2842 /* Clear the interrupt */ 2843 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2844 BGE_EVTENB_MI_INTERRUPT); 2845 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2846 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2847 BRGPHY_INTRS); 2848 } 2849 } else { 2850 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2851 /* 2852 * Sometimes PCS encoding errors are detected in 2853 * TBI mode (on fiber NICs), and for some reason 2854 * the chip will signal them as link changes. 2855 * If we get a link change event, but the 'PCS 2856 * encoding error' bit in the MAC status register 2857 * is set, don't bother doing a link check. 2858 * This avoids spurious "gigabit link up" messages 2859 * that sometimes appear on fiber NICs during 2860 * periods of heavy traffic. (There should be no 2861 * effect on copper NICs.) 2862 */ 2863 status = CSR_READ_4(sc, BGE_MAC_STS); 2864 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR| 2865 BGE_MACSTAT_MI_COMPLETE))) { 2866 sc->bge_link = 0; 2867 untimeout(bge_tick, sc, sc->bge_stat_ch); 2868 bge_tick(sc); 2869 } 2870 /* Clear the interrupt */ 2871 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2872 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE| 2873 BGE_MACSTAT_LINK_CHANGED); 2874 2875 /* Force flush the status block cached by PCI bridge */ 2876 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2877 } 2878 } 2879 2880 if (ifp->if_flags & IFF_RUNNING) { 2881 /* Check RX return ring producer/consumer */ 2882 bge_rxeof(sc); 2883 2884 /* Check TX ring producer/consumer */ 2885 bge_txeof(sc); 2886 } 2887 2888 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2889 sc->bge_cdata.bge_status_map, BUS_DMASYNC_PREWRITE); 2890 2891 bge_handle_events(sc); 2892 2893 /* Re-enable interrupts. */ 2894 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2895 2896 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2897 bge_start(ifp); 2898 2899 return; 2900 } 2901 2902 static void 2903 bge_tick(xsc) 2904 void *xsc; 2905 { 2906 struct bge_softc *sc; 2907 struct mii_data *mii = NULL; 2908 struct ifmedia *ifm = NULL; 2909 struct ifnet *ifp; 2910 int s; 2911 2912 sc = xsc; 2913 ifp = &sc->arpcom.ac_if; 2914 2915 s = splimp(); 2916 2917 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) 2918 bge_stats_update_regs(sc); 2919 else 2920 bge_stats_update(sc); 2921 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2922 if (sc->bge_link) { 2923 splx(s); 2924 return; 2925 } 2926 2927 if (sc->bge_tbi) { 2928 ifm = &sc->bge_ifmedia; 2929 if (CSR_READ_4(sc, BGE_MAC_STS) & 2930 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2931 sc->bge_link++; 2932 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2933 printf("bge%d: gigabit link up\n", sc->bge_unit); 2934 if (ifp->if_snd.ifq_head != NULL) 2935 bge_start(ifp); 2936 } 2937 splx(s); 2938 return; 2939 } 2940 2941 mii = device_get_softc(sc->bge_miibus); 2942 mii_tick(mii); 2943 2944 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2945 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2946 sc->bge_link++; 2947 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2948 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2949 printf("bge%d: gigabit link up\n", 2950 sc->bge_unit); 2951 if (ifp->if_snd.ifq_head != NULL) 2952 bge_start(ifp); 2953 } 2954 2955 splx(s); 2956 2957 return; 2958 } 2959 2960 static void 2961 bge_stats_update_regs(sc) 2962 struct bge_softc *sc; 2963 { 2964 struct ifnet *ifp; 2965 struct bge_mac_stats_regs stats; 2966 u_int32_t *s; 2967 int i; 2968 2969 ifp = &sc->arpcom.ac_if; 2970 2971 s = (u_int32_t *)&stats; 2972 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) { 2973 *s = CSR_READ_4(sc, BGE_RX_STATS + i); 2974 s++; 2975 } 2976 2977 ifp->if_collisions += 2978 (stats.dot3StatsSingleCollisionFrames + 2979 stats.dot3StatsMultipleCollisionFrames + 2980 stats.dot3StatsExcessiveCollisions + 2981 stats.dot3StatsLateCollisions) - 2982 ifp->if_collisions; 2983 2984 return; 2985 } 2986 2987 static void 2988 bge_stats_update(sc) 2989 struct bge_softc *sc; 2990 { 2991 struct ifnet *ifp; 2992 struct bge_stats *stats; 2993 2994 ifp = &sc->arpcom.ac_if; 2995 2996 stats = (struct bge_stats *)(sc->bge_vhandle + 2997 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2998 2999 ifp->if_collisions += 3000 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo + 3001 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo + 3002 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo + 3003 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) - 3004 ifp->if_collisions; 3005 3006 #ifdef notdef 3007 ifp->if_collisions += 3008 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 3009 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 3010 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 3011 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 3012 ifp->if_collisions; 3013 #endif 3014 3015 return; 3016 } 3017 3018 /* 3019 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3020 * pointers to descriptors. 3021 */ 3022 static int 3023 bge_encap(sc, m_head, txidx) 3024 struct bge_softc *sc; 3025 struct mbuf *m_head; 3026 u_int32_t *txidx; 3027 { 3028 struct bge_tx_bd *f = NULL; 3029 u_int16_t csum_flags = 0; 3030 struct m_tag *mtag; 3031 struct bge_dmamap_arg ctx; 3032 bus_dmamap_t map; 3033 int error; 3034 3035 3036 if (m_head->m_pkthdr.csum_flags) { 3037 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 3038 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3039 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 3040 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3041 if (m_head->m_flags & M_LASTFRAG) 3042 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3043 else if (m_head->m_flags & M_FRAG) 3044 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3045 } 3046 3047 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m_head); 3048 3049 ctx.sc = sc; 3050 ctx.bge_idx = *txidx; 3051 ctx.bge_ring = sc->bge_ldata.bge_tx_ring; 3052 ctx.bge_flags = csum_flags; 3053 /* 3054 * Sanity check: avoid coming within 16 descriptors 3055 * of the end of the ring. 3056 */ 3057 ctx.bge_maxsegs = (BGE_TX_RING_CNT - sc->bge_txcnt) - 16; 3058 3059 map = sc->bge_cdata.bge_tx_dmamap[*txidx]; 3060 error = bus_dmamap_load_mbuf(sc->bge_cdata.bge_mtag, map, 3061 m_head, bge_dma_map_tx_desc, &ctx, BUS_DMA_NOWAIT); 3062 3063 if (error || ctx.bge_maxsegs == 0 /*|| 3064 ctx.bge_idx == sc->bge_tx_saved_considx*/) 3065 return (ENOBUFS); 3066 3067 /* 3068 * Insure that the map for this transmission 3069 * is placed at the array index of the last descriptor 3070 * in this chain. 3071 */ 3072 sc->bge_cdata.bge_tx_dmamap[*txidx] = 3073 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx]; 3074 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map; 3075 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head; 3076 sc->bge_txcnt += ctx.bge_maxsegs; 3077 f = &sc->bge_ldata.bge_tx_ring[*txidx]; 3078 if (mtag != NULL) { 3079 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG); 3080 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag)); 3081 } else { 3082 f->bge_vlan_tag = 0; 3083 } 3084 3085 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT); 3086 *txidx = ctx.bge_idx; 3087 3088 return(0); 3089 } 3090 3091 /* 3092 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 3093 * to the mbuf data regions directly in the transmit descriptors. 3094 */ 3095 static void 3096 bge_start(ifp) 3097 struct ifnet *ifp; 3098 { 3099 struct bge_softc *sc; 3100 struct mbuf *m_head = NULL; 3101 u_int32_t prodidx = 0; 3102 3103 sc = ifp->if_softc; 3104 3105 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 3106 return; 3107 3108 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 3109 3110 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 3111 IF_DEQUEUE(&ifp->if_snd, m_head); 3112 if (m_head == NULL) 3113 break; 3114 3115 /* 3116 * XXX 3117 * safety overkill. If this is a fragmented packet chain 3118 * with delayed TCP/UDP checksums, then only encapsulate 3119 * it if we have enough descriptors to handle the entire 3120 * chain at once. 3121 * (paranoia -- may not actually be needed) 3122 */ 3123 if (m_head->m_flags & M_FIRSTFRAG && 3124 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 3125 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 3126 m_head->m_pkthdr.csum_data + 16) { 3127 IF_PREPEND(&ifp->if_snd, m_head); 3128 ifp->if_flags |= IFF_OACTIVE; 3129 break; 3130 } 3131 } 3132 3133 /* 3134 * Pack the data into the transmit ring. If we 3135 * don't have room, set the OACTIVE flag and wait 3136 * for the NIC to drain the ring. 3137 */ 3138 if (bge_encap(sc, m_head, &prodidx)) { 3139 IF_PREPEND(&ifp->if_snd, m_head); 3140 ifp->if_flags |= IFF_OACTIVE; 3141 break; 3142 } 3143 3144 /* 3145 * If there's a BPF listener, bounce a copy of this frame 3146 * to him. 3147 */ 3148 BPF_MTAP(ifp, m_head); 3149 } 3150 3151 /* Transmit */ 3152 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3153 /* 5700 b2 errata */ 3154 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 3155 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 3156 3157 /* 3158 * Set a timeout in case the chip goes out to lunch. 3159 */ 3160 ifp->if_timer = 5; 3161 3162 return; 3163 } 3164 3165 static void 3166 bge_init(xsc) 3167 void *xsc; 3168 { 3169 struct bge_softc *sc = xsc; 3170 struct ifnet *ifp; 3171 u_int16_t *m; 3172 int s; 3173 3174 s = splimp(); 3175 3176 ifp = &sc->arpcom.ac_if; 3177 3178 if (ifp->if_flags & IFF_RUNNING) { 3179 splx(s); 3180 return; 3181 } 3182 3183 /* Cancel pending I/O and flush buffers. */ 3184 bge_stop(sc); 3185 bge_reset(sc); 3186 bge_chipinit(sc); 3187 3188 /* 3189 * Init the various state machines, ring 3190 * control blocks and firmware. 3191 */ 3192 if (bge_blockinit(sc)) { 3193 printf("bge%d: initialization failure\n", sc->bge_unit); 3194 splx(s); 3195 return; 3196 } 3197 3198 ifp = &sc->arpcom.ac_if; 3199 3200 /* Specify MTU. */ 3201 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 3202 ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN); 3203 3204 /* Load our MAC address. */ 3205 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 3206 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 3207 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 3208 3209 /* Enable or disable promiscuous mode as needed. */ 3210 if (ifp->if_flags & IFF_PROMISC) { 3211 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3212 } else { 3213 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 3214 } 3215 3216 /* Program multicast filter. */ 3217 bge_setmulti(sc); 3218 3219 /* Init RX ring. */ 3220 bge_init_rx_ring_std(sc); 3221 3222 /* 3223 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 3224 * memory to insure that the chip has in fact read the first 3225 * entry of the ring. 3226 */ 3227 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 3228 u_int32_t v, i; 3229 for (i = 0; i < 10; i++) { 3230 DELAY(20); 3231 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 3232 if (v == (MCLBYTES - ETHER_ALIGN)) 3233 break; 3234 } 3235 if (i == 10) 3236 printf ("bge%d: 5705 A0 chip failed to load RX ring\n", 3237 sc->bge_unit); 3238 } 3239 3240 /* Init jumbo RX ring. */ 3241 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 3242 bge_init_rx_ring_jumbo(sc); 3243 3244 /* Init our RX return ring index */ 3245 sc->bge_rx_saved_considx = 0; 3246 3247 /* Init TX ring. */ 3248 bge_init_tx_ring(sc); 3249 3250 /* Turn on transmitter */ 3251 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 3252 3253 /* Turn on receiver */ 3254 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3255 3256 /* Tell firmware we're alive. */ 3257 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3258 3259 /* Enable host interrupts. */ 3260 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 3261 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3262 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 3263 3264 bge_ifmedia_upd(ifp); 3265 3266 ifp->if_flags |= IFF_RUNNING; 3267 ifp->if_flags &= ~IFF_OACTIVE; 3268 3269 splx(s); 3270 3271 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 3272 3273 return; 3274 } 3275 3276 /* 3277 * Set media options. 3278 */ 3279 static int 3280 bge_ifmedia_upd(ifp) 3281 struct ifnet *ifp; 3282 { 3283 struct bge_softc *sc; 3284 struct mii_data *mii; 3285 struct ifmedia *ifm; 3286 3287 sc = ifp->if_softc; 3288 ifm = &sc->bge_ifmedia; 3289 3290 /* If this is a 1000baseX NIC, enable the TBI port. */ 3291 if (sc->bge_tbi) { 3292 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 3293 return(EINVAL); 3294 switch(IFM_SUBTYPE(ifm->ifm_media)) { 3295 case IFM_AUTO: 3296 break; 3297 case IFM_1000_SX: 3298 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 3299 BGE_CLRBIT(sc, BGE_MAC_MODE, 3300 BGE_MACMODE_HALF_DUPLEX); 3301 } else { 3302 BGE_SETBIT(sc, BGE_MAC_MODE, 3303 BGE_MACMODE_HALF_DUPLEX); 3304 } 3305 break; 3306 default: 3307 return(EINVAL); 3308 } 3309 return(0); 3310 } 3311 3312 mii = device_get_softc(sc->bge_miibus); 3313 sc->bge_link = 0; 3314 if (mii->mii_instance) { 3315 struct mii_softc *miisc; 3316 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 3317 miisc = LIST_NEXT(miisc, mii_list)) 3318 mii_phy_reset(miisc); 3319 } 3320 mii_mediachg(mii); 3321 3322 return(0); 3323 } 3324 3325 /* 3326 * Report current media status. 3327 */ 3328 static void 3329 bge_ifmedia_sts(ifp, ifmr) 3330 struct ifnet *ifp; 3331 struct ifmediareq *ifmr; 3332 { 3333 struct bge_softc *sc; 3334 struct mii_data *mii; 3335 3336 sc = ifp->if_softc; 3337 3338 if (sc->bge_tbi) { 3339 ifmr->ifm_status = IFM_AVALID; 3340 ifmr->ifm_active = IFM_ETHER; 3341 if (CSR_READ_4(sc, BGE_MAC_STS) & 3342 BGE_MACSTAT_TBI_PCS_SYNCHED) 3343 ifmr->ifm_status |= IFM_ACTIVE; 3344 ifmr->ifm_active |= IFM_1000_SX; 3345 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 3346 ifmr->ifm_active |= IFM_HDX; 3347 else 3348 ifmr->ifm_active |= IFM_FDX; 3349 return; 3350 } 3351 3352 mii = device_get_softc(sc->bge_miibus); 3353 mii_pollstat(mii); 3354 ifmr->ifm_active = mii->mii_media_active; 3355 ifmr->ifm_status = mii->mii_media_status; 3356 3357 return; 3358 } 3359 3360 static int 3361 bge_ioctl(ifp, command, data) 3362 struct ifnet *ifp; 3363 u_long command; 3364 caddr_t data; 3365 { 3366 struct bge_softc *sc = ifp->if_softc; 3367 struct ifreq *ifr = (struct ifreq *) data; 3368 int s, mask, error = 0; 3369 struct mii_data *mii; 3370 3371 s = splimp(); 3372 3373 switch(command) { 3374 case SIOCSIFMTU: 3375 /* Disallow jumbo frames on 5705. */ 3376 if ((sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3377 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU) 3378 error = EINVAL; 3379 else { 3380 ifp->if_mtu = ifr->ifr_mtu; 3381 ifp->if_flags &= ~IFF_RUNNING; 3382 bge_init(sc); 3383 } 3384 break; 3385 case SIOCSIFFLAGS: 3386 if (ifp->if_flags & IFF_UP) { 3387 /* 3388 * If only the state of the PROMISC flag changed, 3389 * then just use the 'set promisc mode' command 3390 * instead of reinitializing the entire NIC. Doing 3391 * a full re-init means reloading the firmware and 3392 * waiting for it to start up, which may take a 3393 * second or two. 3394 */ 3395 if (ifp->if_flags & IFF_RUNNING && 3396 ifp->if_flags & IFF_PROMISC && 3397 !(sc->bge_if_flags & IFF_PROMISC)) { 3398 BGE_SETBIT(sc, BGE_RX_MODE, 3399 BGE_RXMODE_RX_PROMISC); 3400 } else if (ifp->if_flags & IFF_RUNNING && 3401 !(ifp->if_flags & IFF_PROMISC) && 3402 sc->bge_if_flags & IFF_PROMISC) { 3403 BGE_CLRBIT(sc, BGE_RX_MODE, 3404 BGE_RXMODE_RX_PROMISC); 3405 } else 3406 bge_init(sc); 3407 } else { 3408 if (ifp->if_flags & IFF_RUNNING) { 3409 bge_stop(sc); 3410 } 3411 } 3412 sc->bge_if_flags = ifp->if_flags; 3413 error = 0; 3414 break; 3415 case SIOCADDMULTI: 3416 case SIOCDELMULTI: 3417 if (ifp->if_flags & IFF_RUNNING) { 3418 bge_setmulti(sc); 3419 error = 0; 3420 } 3421 break; 3422 case SIOCSIFMEDIA: 3423 case SIOCGIFMEDIA: 3424 if (sc->bge_tbi) { 3425 error = ifmedia_ioctl(ifp, ifr, 3426 &sc->bge_ifmedia, command); 3427 } else { 3428 mii = device_get_softc(sc->bge_miibus); 3429 error = ifmedia_ioctl(ifp, ifr, 3430 &mii->mii_media, command); 3431 } 3432 break; 3433 case SIOCSIFCAP: 3434 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3435 if (mask & IFCAP_HWCSUM) { 3436 if (IFCAP_HWCSUM & ifp->if_capenable) 3437 ifp->if_capenable &= ~IFCAP_HWCSUM; 3438 else 3439 ifp->if_capenable |= IFCAP_HWCSUM; 3440 } 3441 error = 0; 3442 break; 3443 default: 3444 error = ether_ioctl(ifp, command, data); 3445 break; 3446 } 3447 3448 (void)splx(s); 3449 3450 return(error); 3451 } 3452 3453 static void 3454 bge_watchdog(ifp) 3455 struct ifnet *ifp; 3456 { 3457 struct bge_softc *sc; 3458 3459 sc = ifp->if_softc; 3460 3461 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 3462 3463 ifp->if_flags &= ~IFF_RUNNING; 3464 bge_init(sc); 3465 3466 ifp->if_oerrors++; 3467 3468 return; 3469 } 3470 3471 /* 3472 * Stop the adapter and free any mbufs allocated to the 3473 * RX and TX lists. 3474 */ 3475 static void 3476 bge_stop(sc) 3477 struct bge_softc *sc; 3478 { 3479 struct ifnet *ifp; 3480 struct ifmedia_entry *ifm; 3481 struct mii_data *mii = NULL; 3482 int mtmp, itmp; 3483 3484 ifp = &sc->arpcom.ac_if; 3485 3486 if (!sc->bge_tbi) 3487 mii = device_get_softc(sc->bge_miibus); 3488 3489 untimeout(bge_tick, sc, sc->bge_stat_ch); 3490 3491 /* 3492 * Disable all of the receiver blocks 3493 */ 3494 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 3495 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 3496 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 3497 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3498 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 3499 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 3500 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 3501 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 3502 3503 /* 3504 * Disable all of the transmit blocks 3505 */ 3506 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 3507 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 3508 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 3509 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 3510 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 3511 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3512 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 3513 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 3514 3515 /* 3516 * Shut down all of the memory managers and related 3517 * state machines. 3518 */ 3519 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 3520 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 3521 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3522 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 3523 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 3524 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 3525 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) { 3526 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 3527 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3528 } 3529 3530 /* Disable host interrupts. */ 3531 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 3532 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 3533 3534 /* 3535 * Tell firmware we're shutting down. 3536 */ 3537 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3538 3539 /* Free the RX lists. */ 3540 bge_free_rx_ring_std(sc); 3541 3542 /* Free jumbo RX list. */ 3543 if (sc->bge_asicrev != BGE_ASICREV_BCM5705) 3544 bge_free_rx_ring_jumbo(sc); 3545 3546 /* Free TX buffers. */ 3547 bge_free_tx_ring(sc); 3548 3549 /* 3550 * Isolate/power down the PHY, but leave the media selection 3551 * unchanged so that things will be put back to normal when 3552 * we bring the interface back up. 3553 */ 3554 if (!sc->bge_tbi) { 3555 itmp = ifp->if_flags; 3556 ifp->if_flags |= IFF_UP; 3557 ifm = mii->mii_media.ifm_cur; 3558 mtmp = ifm->ifm_media; 3559 ifm->ifm_media = IFM_ETHER|IFM_NONE; 3560 mii_mediachg(mii); 3561 ifm->ifm_media = mtmp; 3562 ifp->if_flags = itmp; 3563 } 3564 3565 sc->bge_link = 0; 3566 3567 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 3568 3569 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 3570 3571 return; 3572 } 3573 3574 /* 3575 * Stop all chip I/O so that the kernel's probe routines don't 3576 * get confused by errant DMAs when rebooting. 3577 */ 3578 static void 3579 bge_shutdown(dev) 3580 device_t dev; 3581 { 3582 struct bge_softc *sc; 3583 3584 sc = device_get_softc(dev); 3585 3586 bge_stop(sc); 3587 bge_reset(sc); 3588 3589 return; 3590 } 3591