1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } const bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 227 228 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 229 230 { TC_VENDORID, TC_DEVICEID_3C996 }, 231 232 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 233 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 234 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 235 236 { 0, 0 } 237 }; 238 239 static const struct bge_vendor { 240 uint16_t v_id; 241 const char *v_name; 242 } const bge_vendors[] = { 243 { ALTEON_VENDORID, "Alteon" }, 244 { ALTIMA_VENDORID, "Altima" }, 245 { APPLE_VENDORID, "Apple" }, 246 { BCOM_VENDORID, "Broadcom" }, 247 { SK_VENDORID, "SysKonnect" }, 248 { TC_VENDORID, "3Com" }, 249 { FJTSU_VENDORID, "Fujitsu" }, 250 251 { 0, NULL } 252 }; 253 254 static const struct bge_revision { 255 uint32_t br_chipid; 256 const char *br_name; 257 } const bge_revisions[] = { 258 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 259 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 260 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 261 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 262 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 263 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 264 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 265 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 266 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 267 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 268 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 269 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 270 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 271 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 272 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 273 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 274 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 275 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 276 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 277 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 278 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 279 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 280 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 281 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 282 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 283 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 284 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 285 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 286 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 287 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 288 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 289 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 290 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 291 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 292 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 293 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 294 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 295 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 296 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 297 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 298 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 299 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 300 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 301 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 302 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 303 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 304 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 305 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 306 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 307 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 308 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 309 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 310 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 311 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 312 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 313 /* 5754 and 5787 share the same ASIC ID */ 314 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 315 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 316 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 317 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 318 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 319 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 320 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 321 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 322 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 323 324 { 0, NULL } 325 }; 326 327 /* 328 * Some defaults for major revisions, so that newer steppings 329 * that we don't know about have a shot at working. 330 */ 331 static const struct bge_revision const bge_majorrevs[] = { 332 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 333 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 334 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 335 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 336 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 337 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 338 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 339 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 340 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 341 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 342 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 343 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 344 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 345 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 346 /* 5754 and 5787 share the same ASIC ID */ 347 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 348 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 349 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 350 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 351 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 352 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 353 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 354 355 { 0, NULL } 356 }; 357 358 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 359 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 360 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 361 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 362 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 363 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 364 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 365 366 const struct bge_revision * bge_lookup_rev(uint32_t); 367 const struct bge_vendor * bge_lookup_vendor(uint16_t); 368 369 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 370 371 static int bge_probe(device_t); 372 static int bge_attach(device_t); 373 static int bge_detach(device_t); 374 static int bge_suspend(device_t); 375 static int bge_resume(device_t); 376 static void bge_release_resources(struct bge_softc *); 377 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 378 static int bge_dma_alloc(struct bge_softc *); 379 static void bge_dma_free(struct bge_softc *); 380 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 381 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 382 383 static void bge_devinfo(struct bge_softc *); 384 static int bge_mbox_reorder(struct bge_softc *); 385 386 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 387 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 388 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 389 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 390 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 391 392 static void bge_txeof(struct bge_softc *, uint16_t); 393 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 394 static int bge_rxeof(struct bge_softc *, uint16_t, int); 395 396 static void bge_asf_driver_up (struct bge_softc *); 397 static void bge_tick(void *); 398 static void bge_stats_clear_regs(struct bge_softc *); 399 static void bge_stats_update(struct bge_softc *); 400 static void bge_stats_update_regs(struct bge_softc *); 401 static struct mbuf *bge_check_short_dma(struct mbuf *); 402 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 403 uint16_t *, uint16_t *); 404 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 405 406 static void bge_intr(void *); 407 static int bge_msi_intr(void *); 408 static void bge_intr_task(void *, int); 409 static void bge_start_locked(struct ifnet *); 410 static void bge_start(struct ifnet *); 411 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 412 static void bge_init_locked(struct bge_softc *); 413 static void bge_init(void *); 414 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 415 static void bge_stop(struct bge_softc *); 416 static void bge_watchdog(struct bge_softc *); 417 static int bge_shutdown(device_t); 418 static int bge_ifmedia_upd_locked(struct ifnet *); 419 static int bge_ifmedia_upd(struct ifnet *); 420 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 421 422 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 423 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 424 425 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 426 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 427 428 static void bge_setpromisc(struct bge_softc *); 429 static void bge_setmulti(struct bge_softc *); 430 static void bge_setvlan(struct bge_softc *); 431 432 static __inline void bge_rxreuse_std(struct bge_softc *, int); 433 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 434 static int bge_newbuf_std(struct bge_softc *, int); 435 static int bge_newbuf_jumbo(struct bge_softc *, int); 436 static int bge_init_rx_ring_std(struct bge_softc *); 437 static void bge_free_rx_ring_std(struct bge_softc *); 438 static int bge_init_rx_ring_jumbo(struct bge_softc *); 439 static void bge_free_rx_ring_jumbo(struct bge_softc *); 440 static void bge_free_tx_ring(struct bge_softc *); 441 static int bge_init_tx_ring(struct bge_softc *); 442 443 static int bge_chipinit(struct bge_softc *); 444 static int bge_blockinit(struct bge_softc *); 445 static uint32_t bge_dma_swap_options(struct bge_softc *); 446 447 static int bge_has_eaddr(struct bge_softc *); 448 static uint32_t bge_readmem_ind(struct bge_softc *, int); 449 static void bge_writemem_ind(struct bge_softc *, int, int); 450 static void bge_writembx(struct bge_softc *, int, int); 451 #ifdef notdef 452 static uint32_t bge_readreg_ind(struct bge_softc *, int); 453 #endif 454 static void bge_writemem_direct(struct bge_softc *, int, int); 455 static void bge_writereg_ind(struct bge_softc *, int, int); 456 457 static int bge_miibus_readreg(device_t, int, int); 458 static int bge_miibus_writereg(device_t, int, int, int); 459 static void bge_miibus_statchg(device_t); 460 #ifdef DEVICE_POLLING 461 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 462 #endif 463 464 #define BGE_RESET_START 1 465 #define BGE_RESET_STOP 2 466 static void bge_sig_post_reset(struct bge_softc *, int); 467 static void bge_sig_legacy(struct bge_softc *, int); 468 static void bge_sig_pre_reset(struct bge_softc *, int); 469 static void bge_stop_fw(struct bge_softc *); 470 static int bge_reset(struct bge_softc *); 471 static void bge_link_upd(struct bge_softc *); 472 473 /* 474 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 475 * leak information to untrusted users. It is also known to cause alignment 476 * traps on certain architectures. 477 */ 478 #ifdef BGE_REGISTER_DEBUG 479 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 480 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 481 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 482 #endif 483 static void bge_add_sysctls(struct bge_softc *); 484 static void bge_add_sysctl_stats_regs(struct bge_softc *, 485 struct sysctl_ctx_list *, struct sysctl_oid_list *); 486 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 487 struct sysctl_oid_list *); 488 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 489 490 static device_method_t bge_methods[] = { 491 /* Device interface */ 492 DEVMETHOD(device_probe, bge_probe), 493 DEVMETHOD(device_attach, bge_attach), 494 DEVMETHOD(device_detach, bge_detach), 495 DEVMETHOD(device_shutdown, bge_shutdown), 496 DEVMETHOD(device_suspend, bge_suspend), 497 DEVMETHOD(device_resume, bge_resume), 498 499 /* MII interface */ 500 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 501 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 502 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 503 504 DEVMETHOD_END 505 }; 506 507 static driver_t bge_driver = { 508 "bge", 509 bge_methods, 510 sizeof(struct bge_softc) 511 }; 512 513 static devclass_t bge_devclass; 514 515 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 516 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 517 518 static int bge_allow_asf = 1; 519 520 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 521 522 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 523 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 524 "Allow ASF mode if available"); 525 526 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 527 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 528 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 529 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 530 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 531 532 static int 533 bge_has_eaddr(struct bge_softc *sc) 534 { 535 #ifdef __sparc64__ 536 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 537 device_t dev; 538 uint32_t subvendor; 539 540 dev = sc->bge_dev; 541 542 /* 543 * The on-board BGEs found in sun4u machines aren't fitted with 544 * an EEPROM which means that we have to obtain the MAC address 545 * via OFW and that some tests will always fail. We distinguish 546 * such BGEs by the subvendor ID, which also has to be obtained 547 * from OFW instead of the PCI configuration space as the latter 548 * indicates Broadcom as the subvendor of the netboot interface. 549 * For early Blade 1500 and 2500 we even have to check the OFW 550 * device path as the subvendor ID always defaults to Broadcom 551 * there. 552 */ 553 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 554 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 555 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 556 return (0); 557 memset(buf, 0, sizeof(buf)); 558 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 559 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 560 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 561 return (0); 562 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 563 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 564 return (0); 565 } 566 #endif 567 return (1); 568 } 569 570 static uint32_t 571 bge_readmem_ind(struct bge_softc *sc, int off) 572 { 573 device_t dev; 574 uint32_t val; 575 576 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 577 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 578 return (0); 579 580 dev = sc->bge_dev; 581 582 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 583 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 584 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 585 return (val); 586 } 587 588 static void 589 bge_writemem_ind(struct bge_softc *sc, int off, int val) 590 { 591 device_t dev; 592 593 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 594 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 595 return; 596 597 dev = sc->bge_dev; 598 599 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 600 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 601 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 602 } 603 604 #ifdef notdef 605 static uint32_t 606 bge_readreg_ind(struct bge_softc *sc, int off) 607 { 608 device_t dev; 609 610 dev = sc->bge_dev; 611 612 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 613 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 614 } 615 #endif 616 617 static void 618 bge_writereg_ind(struct bge_softc *sc, int off, int val) 619 { 620 device_t dev; 621 622 dev = sc->bge_dev; 623 624 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 625 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 626 } 627 628 static void 629 bge_writemem_direct(struct bge_softc *sc, int off, int val) 630 { 631 CSR_WRITE_4(sc, off, val); 632 } 633 634 static void 635 bge_writembx(struct bge_softc *sc, int off, int val) 636 { 637 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 638 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 639 640 CSR_WRITE_4(sc, off, val); 641 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 642 CSR_READ_4(sc, off); 643 } 644 645 /* 646 * Map a single buffer address. 647 */ 648 649 static void 650 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 651 { 652 struct bge_dmamap_arg *ctx; 653 654 if (error) 655 return; 656 657 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 658 659 ctx = arg; 660 ctx->bge_busaddr = segs->ds_addr; 661 } 662 663 static uint8_t 664 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 665 { 666 uint32_t access, byte = 0; 667 int i; 668 669 /* Lock. */ 670 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 671 for (i = 0; i < 8000; i++) { 672 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 673 break; 674 DELAY(20); 675 } 676 if (i == 8000) 677 return (1); 678 679 /* Enable access. */ 680 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 681 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 682 683 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 684 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 685 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 686 DELAY(10); 687 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 688 DELAY(10); 689 break; 690 } 691 } 692 693 if (i == BGE_TIMEOUT * 10) { 694 if_printf(sc->bge_ifp, "nvram read timed out\n"); 695 return (1); 696 } 697 698 /* Get result. */ 699 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 700 701 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 702 703 /* Disable access. */ 704 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 705 706 /* Unlock. */ 707 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 708 CSR_READ_4(sc, BGE_NVRAM_SWARB); 709 710 return (0); 711 } 712 713 /* 714 * Read a sequence of bytes from NVRAM. 715 */ 716 static int 717 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 718 { 719 int err = 0, i; 720 uint8_t byte = 0; 721 722 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 723 return (1); 724 725 for (i = 0; i < cnt; i++) { 726 err = bge_nvram_getbyte(sc, off + i, &byte); 727 if (err) 728 break; 729 *(dest + i) = byte; 730 } 731 732 return (err ? 1 : 0); 733 } 734 735 /* 736 * Read a byte of data stored in the EEPROM at address 'addr.' The 737 * BCM570x supports both the traditional bitbang interface and an 738 * auto access interface for reading the EEPROM. We use the auto 739 * access method. 740 */ 741 static uint8_t 742 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 743 { 744 int i; 745 uint32_t byte = 0; 746 747 /* 748 * Enable use of auto EEPROM access so we can avoid 749 * having to use the bitbang method. 750 */ 751 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 752 753 /* Reset the EEPROM, load the clock period. */ 754 CSR_WRITE_4(sc, BGE_EE_ADDR, 755 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 756 DELAY(20); 757 758 /* Issue the read EEPROM command. */ 759 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 760 761 /* Wait for completion */ 762 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 763 DELAY(10); 764 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 765 break; 766 } 767 768 if (i == BGE_TIMEOUT * 10) { 769 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 770 return (1); 771 } 772 773 /* Get result. */ 774 byte = CSR_READ_4(sc, BGE_EE_DATA); 775 776 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 777 778 return (0); 779 } 780 781 /* 782 * Read a sequence of bytes from the EEPROM. 783 */ 784 static int 785 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 786 { 787 int i, error = 0; 788 uint8_t byte = 0; 789 790 for (i = 0; i < cnt; i++) { 791 error = bge_eeprom_getbyte(sc, off + i, &byte); 792 if (error) 793 break; 794 *(dest + i) = byte; 795 } 796 797 return (error ? 1 : 0); 798 } 799 800 static int 801 bge_miibus_readreg(device_t dev, int phy, int reg) 802 { 803 struct bge_softc *sc; 804 uint32_t val; 805 int i; 806 807 sc = device_get_softc(dev); 808 809 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 810 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 811 CSR_WRITE_4(sc, BGE_MI_MODE, 812 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 813 DELAY(80); 814 } 815 816 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 817 BGE_MIPHY(phy) | BGE_MIREG(reg)); 818 819 /* Poll for the PHY register access to complete. */ 820 for (i = 0; i < BGE_TIMEOUT; i++) { 821 DELAY(10); 822 val = CSR_READ_4(sc, BGE_MI_COMM); 823 if ((val & BGE_MICOMM_BUSY) == 0) { 824 DELAY(5); 825 val = CSR_READ_4(sc, BGE_MI_COMM); 826 break; 827 } 828 } 829 830 if (i == BGE_TIMEOUT) { 831 device_printf(sc->bge_dev, 832 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 833 phy, reg, val); 834 val = 0; 835 } 836 837 /* Restore the autopoll bit if necessary. */ 838 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 839 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 840 DELAY(80); 841 } 842 843 if (val & BGE_MICOMM_READFAIL) 844 return (0); 845 846 return (val & 0xFFFF); 847 } 848 849 static int 850 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 851 { 852 struct bge_softc *sc; 853 int i; 854 855 sc = device_get_softc(dev); 856 857 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 858 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 859 return (0); 860 861 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 862 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 863 CSR_WRITE_4(sc, BGE_MI_MODE, 864 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 865 DELAY(80); 866 } 867 868 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 869 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 870 871 for (i = 0; i < BGE_TIMEOUT; i++) { 872 DELAY(10); 873 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 874 DELAY(5); 875 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 876 break; 877 } 878 } 879 880 /* Restore the autopoll bit if necessary. */ 881 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 882 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 883 DELAY(80); 884 } 885 886 if (i == BGE_TIMEOUT) 887 device_printf(sc->bge_dev, 888 "PHY write timed out (phy %d, reg %d, val %d)\n", 889 phy, reg, val); 890 891 return (0); 892 } 893 894 static void 895 bge_miibus_statchg(device_t dev) 896 { 897 struct bge_softc *sc; 898 struct mii_data *mii; 899 sc = device_get_softc(dev); 900 mii = device_get_softc(sc->bge_miibus); 901 902 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 903 (IFM_ACTIVE | IFM_AVALID)) { 904 switch (IFM_SUBTYPE(mii->mii_media_active)) { 905 case IFM_10_T: 906 case IFM_100_TX: 907 sc->bge_link = 1; 908 break; 909 case IFM_1000_T: 910 case IFM_1000_SX: 911 case IFM_2500_SX: 912 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 913 sc->bge_link = 1; 914 else 915 sc->bge_link = 0; 916 break; 917 default: 918 sc->bge_link = 0; 919 break; 920 } 921 } else 922 sc->bge_link = 0; 923 if (sc->bge_link == 0) 924 return; 925 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 926 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 927 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 928 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 929 else 930 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 931 932 if (IFM_OPTIONS(mii->mii_media_active & IFM_FDX) != 0) { 933 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 934 if ((IFM_OPTIONS(mii->mii_media_active) & 935 IFM_ETH_TXPAUSE) != 0) 936 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 937 else 938 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 939 if ((IFM_OPTIONS(mii->mii_media_active) & 940 IFM_ETH_RXPAUSE) != 0) 941 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 942 else 943 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 944 } else { 945 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 946 BGE_CLRBIT(sc, BGE_TX_MODE, BGE_TXMODE_FLOWCTL_ENABLE); 947 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_FLOWCTL_ENABLE); 948 } 949 } 950 951 /* 952 * Intialize a standard receive ring descriptor. 953 */ 954 static int 955 bge_newbuf_std(struct bge_softc *sc, int i) 956 { 957 struct mbuf *m; 958 struct bge_rx_bd *r; 959 bus_dma_segment_t segs[1]; 960 bus_dmamap_t map; 961 int error, nsegs; 962 963 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 964 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 965 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 966 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 967 if (m == NULL) 968 return (ENOBUFS); 969 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 970 } else { 971 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 972 if (m == NULL) 973 return (ENOBUFS); 974 m->m_len = m->m_pkthdr.len = MCLBYTES; 975 } 976 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 977 m_adj(m, ETHER_ALIGN); 978 979 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 980 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 981 if (error != 0) { 982 m_freem(m); 983 return (error); 984 } 985 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 986 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 987 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 988 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 989 sc->bge_cdata.bge_rx_std_dmamap[i]); 990 } 991 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 992 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 993 sc->bge_cdata.bge_rx_std_sparemap = map; 994 sc->bge_cdata.bge_rx_std_chain[i] = m; 995 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 996 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 997 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 998 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 999 r->bge_flags = BGE_RXBDFLAG_END; 1000 r->bge_len = segs[0].ds_len; 1001 r->bge_idx = i; 1002 1003 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1004 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1005 1006 return (0); 1007 } 1008 1009 /* 1010 * Initialize a jumbo receive ring descriptor. This allocates 1011 * a jumbo buffer from the pool managed internally by the driver. 1012 */ 1013 static int 1014 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1015 { 1016 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1017 bus_dmamap_t map; 1018 struct bge_extrx_bd *r; 1019 struct mbuf *m; 1020 int error, nsegs; 1021 1022 MGETHDR(m, M_DONTWAIT, MT_DATA); 1023 if (m == NULL) 1024 return (ENOBUFS); 1025 1026 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 1027 if (!(m->m_flags & M_EXT)) { 1028 m_freem(m); 1029 return (ENOBUFS); 1030 } 1031 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1032 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1033 m_adj(m, ETHER_ALIGN); 1034 1035 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1036 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1037 if (error != 0) { 1038 m_freem(m); 1039 return (error); 1040 } 1041 1042 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1043 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1044 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1045 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1046 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1047 } 1048 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1049 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1050 sc->bge_cdata.bge_rx_jumbo_sparemap; 1051 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1052 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1053 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1054 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1055 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1056 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1057 1058 /* 1059 * Fill in the extended RX buffer descriptor. 1060 */ 1061 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1062 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1063 r->bge_idx = i; 1064 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1065 switch (nsegs) { 1066 case 4: 1067 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1068 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1069 r->bge_len3 = segs[3].ds_len; 1070 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1071 case 3: 1072 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1073 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1074 r->bge_len2 = segs[2].ds_len; 1075 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1076 case 2: 1077 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1078 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1079 r->bge_len1 = segs[1].ds_len; 1080 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1081 case 1: 1082 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1083 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1084 r->bge_len0 = segs[0].ds_len; 1085 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1086 break; 1087 default: 1088 panic("%s: %d segments\n", __func__, nsegs); 1089 } 1090 1091 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1092 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1093 1094 return (0); 1095 } 1096 1097 static int 1098 bge_init_rx_ring_std(struct bge_softc *sc) 1099 { 1100 int error, i; 1101 1102 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1103 sc->bge_std = 0; 1104 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1105 if ((error = bge_newbuf_std(sc, i)) != 0) 1106 return (error); 1107 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1108 } 1109 1110 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1111 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1112 1113 sc->bge_std = 0; 1114 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1115 1116 return (0); 1117 } 1118 1119 static void 1120 bge_free_rx_ring_std(struct bge_softc *sc) 1121 { 1122 int i; 1123 1124 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1125 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1126 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1127 sc->bge_cdata.bge_rx_std_dmamap[i], 1128 BUS_DMASYNC_POSTREAD); 1129 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1130 sc->bge_cdata.bge_rx_std_dmamap[i]); 1131 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1132 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1133 } 1134 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1135 sizeof(struct bge_rx_bd)); 1136 } 1137 } 1138 1139 static int 1140 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1141 { 1142 struct bge_rcb *rcb; 1143 int error, i; 1144 1145 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1146 sc->bge_jumbo = 0; 1147 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1148 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1149 return (error); 1150 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1151 } 1152 1153 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1154 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1155 1156 sc->bge_jumbo = 0; 1157 1158 /* Enable the jumbo receive producer ring. */ 1159 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1160 rcb->bge_maxlen_flags = 1161 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1162 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1163 1164 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1165 1166 return (0); 1167 } 1168 1169 static void 1170 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1171 { 1172 int i; 1173 1174 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1175 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1176 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1177 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1178 BUS_DMASYNC_POSTREAD); 1179 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1180 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1181 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1182 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1183 } 1184 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1185 sizeof(struct bge_extrx_bd)); 1186 } 1187 } 1188 1189 static void 1190 bge_free_tx_ring(struct bge_softc *sc) 1191 { 1192 int i; 1193 1194 if (sc->bge_ldata.bge_tx_ring == NULL) 1195 return; 1196 1197 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1198 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1199 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1200 sc->bge_cdata.bge_tx_dmamap[i], 1201 BUS_DMASYNC_POSTWRITE); 1202 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1203 sc->bge_cdata.bge_tx_dmamap[i]); 1204 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1205 sc->bge_cdata.bge_tx_chain[i] = NULL; 1206 } 1207 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1208 sizeof(struct bge_tx_bd)); 1209 } 1210 } 1211 1212 static int 1213 bge_init_tx_ring(struct bge_softc *sc) 1214 { 1215 sc->bge_txcnt = 0; 1216 sc->bge_tx_saved_considx = 0; 1217 1218 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1219 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1220 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1221 1222 /* Initialize transmit producer index for host-memory send ring. */ 1223 sc->bge_tx_prodidx = 0; 1224 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1225 1226 /* 5700 b2 errata */ 1227 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1228 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1229 1230 /* NIC-memory send ring not used; initialize to zero. */ 1231 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1232 /* 5700 b2 errata */ 1233 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1234 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1235 1236 return (0); 1237 } 1238 1239 static void 1240 bge_setpromisc(struct bge_softc *sc) 1241 { 1242 struct ifnet *ifp; 1243 1244 BGE_LOCK_ASSERT(sc); 1245 1246 ifp = sc->bge_ifp; 1247 1248 /* Enable or disable promiscuous mode as needed. */ 1249 if (ifp->if_flags & IFF_PROMISC) 1250 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1251 else 1252 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1253 } 1254 1255 static void 1256 bge_setmulti(struct bge_softc *sc) 1257 { 1258 struct ifnet *ifp; 1259 struct ifmultiaddr *ifma; 1260 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1261 int h, i; 1262 1263 BGE_LOCK_ASSERT(sc); 1264 1265 ifp = sc->bge_ifp; 1266 1267 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1268 for (i = 0; i < 4; i++) 1269 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1270 return; 1271 } 1272 1273 /* First, zot all the existing filters. */ 1274 for (i = 0; i < 4; i++) 1275 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1276 1277 /* Now program new ones. */ 1278 if_maddr_rlock(ifp); 1279 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1280 if (ifma->ifma_addr->sa_family != AF_LINK) 1281 continue; 1282 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1283 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1284 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1285 } 1286 if_maddr_runlock(ifp); 1287 1288 for (i = 0; i < 4; i++) 1289 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1290 } 1291 1292 static void 1293 bge_setvlan(struct bge_softc *sc) 1294 { 1295 struct ifnet *ifp; 1296 1297 BGE_LOCK_ASSERT(sc); 1298 1299 ifp = sc->bge_ifp; 1300 1301 /* Enable or disable VLAN tag stripping as needed. */ 1302 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1303 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1304 else 1305 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1306 } 1307 1308 static void 1309 bge_sig_pre_reset(struct bge_softc *sc, int type) 1310 { 1311 1312 /* 1313 * Some chips don't like this so only do this if ASF is enabled 1314 */ 1315 if (sc->bge_asf_mode) 1316 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1317 1318 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1319 switch (type) { 1320 case BGE_RESET_START: 1321 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1322 BGE_FW_DRV_STATE_START); 1323 break; 1324 case BGE_RESET_STOP: 1325 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1326 BGE_FW_DRV_STATE_UNLOAD); 1327 break; 1328 } 1329 } 1330 } 1331 1332 static void 1333 bge_sig_post_reset(struct bge_softc *sc, int type) 1334 { 1335 1336 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1337 switch (type) { 1338 case BGE_RESET_START: 1339 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1340 BGE_FW_DRV_STATE_START_DONE); 1341 /* START DONE */ 1342 break; 1343 case BGE_RESET_STOP: 1344 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1345 BGE_FW_DRV_STATE_UNLOAD_DONE); 1346 break; 1347 } 1348 } 1349 } 1350 1351 static void 1352 bge_sig_legacy(struct bge_softc *sc, int type) 1353 { 1354 1355 if (sc->bge_asf_mode) { 1356 switch (type) { 1357 case BGE_RESET_START: 1358 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1359 BGE_FW_DRV_STATE_START); 1360 break; 1361 case BGE_RESET_STOP: 1362 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1363 BGE_FW_DRV_STATE_UNLOAD); 1364 break; 1365 } 1366 } 1367 } 1368 1369 static void 1370 bge_stop_fw(struct bge_softc *sc) 1371 { 1372 int i; 1373 1374 if (sc->bge_asf_mode) { 1375 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1376 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1377 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1378 1379 for (i = 0; i < 100; i++ ) { 1380 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1381 BGE_RX_CPU_DRV_EVENT)) 1382 break; 1383 DELAY(10); 1384 } 1385 } 1386 } 1387 1388 static uint32_t 1389 bge_dma_swap_options(struct bge_softc *sc) 1390 { 1391 uint32_t dma_options; 1392 1393 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1394 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1395 #if BYTE_ORDER == BIG_ENDIAN 1396 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1397 #endif 1398 if ((sc)->bge_asicrev == BGE_ASICREV_BCM5720) 1399 dma_options |= BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1400 BGE_MODECTL_WORDSWAP_B2HRX_DATA | BGE_MODECTL_B2HRX_ENABLE | 1401 BGE_MODECTL_HTX2B_ENABLE; 1402 1403 return (dma_options); 1404 } 1405 1406 /* 1407 * Do endian, PCI and DMA initialization. 1408 */ 1409 static int 1410 bge_chipinit(struct bge_softc *sc) 1411 { 1412 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1413 uint16_t val; 1414 int i; 1415 1416 /* Set endianness before we access any non-PCI registers. */ 1417 misc_ctl = BGE_INIT; 1418 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1419 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1420 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1421 1422 /* Clear the MAC control register */ 1423 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1424 1425 /* 1426 * Clear the MAC statistics block in the NIC's 1427 * internal memory. 1428 */ 1429 for (i = BGE_STATS_BLOCK; 1430 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1431 BGE_MEMWIN_WRITE(sc, i, 0); 1432 1433 for (i = BGE_STATUS_BLOCK; 1434 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1435 BGE_MEMWIN_WRITE(sc, i, 0); 1436 1437 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1438 /* 1439 * Fix data corruption caused by non-qword write with WB. 1440 * Fix master abort in PCI mode. 1441 * Fix PCI latency timer. 1442 */ 1443 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1444 val |= (1 << 10) | (1 << 12) | (1 << 13); 1445 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1446 } 1447 1448 /* 1449 * Set up the PCI DMA control register. 1450 */ 1451 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1452 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1453 if (sc->bge_flags & BGE_FLAG_PCIE) { 1454 /* Read watermark not used, 128 bytes for write. */ 1455 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1456 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1457 if (BGE_IS_5714_FAMILY(sc)) { 1458 /* 256 bytes for read and write. */ 1459 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1460 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1461 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1462 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1463 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1464 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1465 /* 1466 * In the BCM5703, the DMA read watermark should 1467 * be set to less than or equal to the maximum 1468 * memory read byte count of the PCI-X command 1469 * register. 1470 */ 1471 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1472 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1473 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1474 /* 1536 bytes for read, 384 bytes for write. */ 1475 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1476 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1477 } else { 1478 /* 384 bytes for read and write. */ 1479 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1480 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1481 0x0F; 1482 } 1483 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1484 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1485 uint32_t tmp; 1486 1487 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1488 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1489 if (tmp == 6 || tmp == 7) 1490 dma_rw_ctl |= 1491 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1492 1493 /* Set PCI-X DMA write workaround. */ 1494 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1495 } 1496 } else { 1497 /* Conventional PCI bus: 256 bytes for read and write. */ 1498 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1499 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1500 1501 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1502 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1503 dma_rw_ctl |= 0x0F; 1504 } 1505 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1506 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1507 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1508 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1509 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1510 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1511 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1512 if (BGE_IS_5717_PLUS(sc)) { 1513 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1514 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1515 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1516 /* 1517 * Enable HW workaround for controllers that misinterpret 1518 * a status tag update and leave interrupts permanently 1519 * disabled. 1520 */ 1521 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1522 sc->bge_asicrev != BGE_ASICREV_BCM57765) 1523 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1524 } 1525 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1526 1527 /* 1528 * Set up general mode register. 1529 */ 1530 mode_ctl = bge_dma_swap_options(sc) | BGE_MODECTL_MAC_ATTN_INTR | 1531 BGE_MODECTL_HOST_SEND_BDS | BGE_MODECTL_TX_NO_PHDR_CSUM; 1532 1533 /* 1534 * BCM5701 B5 have a bug causing data corruption when using 1535 * 64-bit DMA reads, which can be terminated early and then 1536 * completed later as 32-bit accesses, in combination with 1537 * certain bridges. 1538 */ 1539 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1540 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1541 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1542 1543 /* 1544 * Tell the firmware the driver is running 1545 */ 1546 if (sc->bge_asf_mode & ASF_STACKUP) 1547 mode_ctl |= BGE_MODECTL_STACKUP; 1548 1549 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1550 1551 /* 1552 * Disable memory write invalidate. Apparently it is not supported 1553 * properly by these devices. Also ensure that INTx isn't disabled, 1554 * as these chips need it even when using MSI. 1555 */ 1556 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1557 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1558 1559 /* Set the timer prescaler (always 66Mhz) */ 1560 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1561 1562 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1563 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1564 DELAY(40); /* XXX */ 1565 1566 /* Put PHY into ready state */ 1567 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1568 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1569 DELAY(40); 1570 } 1571 1572 return (0); 1573 } 1574 1575 static int 1576 bge_blockinit(struct bge_softc *sc) 1577 { 1578 struct bge_rcb *rcb; 1579 bus_size_t vrcb; 1580 bge_hostaddr taddr; 1581 uint32_t dmactl, val; 1582 int i, limit; 1583 1584 /* 1585 * Initialize the memory window pointer register so that 1586 * we can access the first 32K of internal NIC RAM. This will 1587 * allow us to set up the TX send ring RCBs and the RX return 1588 * ring RCBs, plus other things which live in NIC memory. 1589 */ 1590 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1591 1592 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1593 1594 if (!(BGE_IS_5705_PLUS(sc))) { 1595 /* Configure mbuf memory pool */ 1596 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1597 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1598 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1599 else 1600 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1601 1602 /* Configure DMA resource pool */ 1603 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1604 BGE_DMA_DESCRIPTORS); 1605 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1606 } 1607 1608 /* Configure mbuf pool watermarks */ 1609 if (BGE_IS_5717_PLUS(sc)) { 1610 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1611 if (sc->bge_ifp->if_mtu > ETHERMTU) { 1612 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 1613 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 1614 } else { 1615 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 1616 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 1617 } 1618 } else if (!BGE_IS_5705_PLUS(sc)) { 1619 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1620 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1621 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1622 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1623 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1624 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1625 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1626 } else { 1627 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1628 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1629 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1630 } 1631 1632 /* Configure DMA resource watermarks */ 1633 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1634 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1635 1636 /* Enable buffer manager */ 1637 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 1638 /* 1639 * Change the arbitration algorithm of TXMBUF read request to 1640 * round-robin instead of priority based for BCM5719. When 1641 * TXFIFO is almost empty, RDMA will hold its request until 1642 * TXFIFO is not almost empty. 1643 */ 1644 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 1645 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 1646 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 1647 1648 /* Poll for buffer manager start indication */ 1649 for (i = 0; i < BGE_TIMEOUT; i++) { 1650 DELAY(10); 1651 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1652 break; 1653 } 1654 1655 if (i == BGE_TIMEOUT) { 1656 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 1657 return (ENXIO); 1658 } 1659 1660 /* Enable flow-through queues */ 1661 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1662 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1663 1664 /* Wait until queue initialization is complete */ 1665 for (i = 0; i < BGE_TIMEOUT; i++) { 1666 DELAY(10); 1667 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1668 break; 1669 } 1670 1671 if (i == BGE_TIMEOUT) { 1672 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1673 return (ENXIO); 1674 } 1675 1676 /* 1677 * Summary of rings supported by the controller: 1678 * 1679 * Standard Receive Producer Ring 1680 * - This ring is used to feed receive buffers for "standard" 1681 * sized frames (typically 1536 bytes) to the controller. 1682 * 1683 * Jumbo Receive Producer Ring 1684 * - This ring is used to feed receive buffers for jumbo sized 1685 * frames (i.e. anything bigger than the "standard" frames) 1686 * to the controller. 1687 * 1688 * Mini Receive Producer Ring 1689 * - This ring is used to feed receive buffers for "mini" 1690 * sized frames to the controller. 1691 * - This feature required external memory for the controller 1692 * but was never used in a production system. Should always 1693 * be disabled. 1694 * 1695 * Receive Return Ring 1696 * - After the controller has placed an incoming frame into a 1697 * receive buffer that buffer is moved into a receive return 1698 * ring. The driver is then responsible to passing the 1699 * buffer up to the stack. Many versions of the controller 1700 * support multiple RR rings. 1701 * 1702 * Send Ring 1703 * - This ring is used for outgoing frames. Many versions of 1704 * the controller support multiple send rings. 1705 */ 1706 1707 /* Initialize the standard receive producer ring control block. */ 1708 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1709 rcb->bge_hostaddr.bge_addr_lo = 1710 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1711 rcb->bge_hostaddr.bge_addr_hi = 1712 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1713 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1714 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1715 if (BGE_IS_5717_PLUS(sc)) { 1716 /* 1717 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 1718 * Bits 15-2 : Maximum RX frame size 1719 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 1720 * Bit 0 : Reserved 1721 */ 1722 rcb->bge_maxlen_flags = 1723 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 1724 } else if (BGE_IS_5705_PLUS(sc)) { 1725 /* 1726 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 1727 * Bits 15-2 : Reserved (should be 0) 1728 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1729 * Bit 0 : Reserved 1730 */ 1731 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1732 } else { 1733 /* 1734 * Ring size is always XXX entries 1735 * Bits 31-16: Maximum RX frame size 1736 * Bits 15-2 : Reserved (should be 0) 1737 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 1738 * Bit 0 : Reserved 1739 */ 1740 rcb->bge_maxlen_flags = 1741 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1742 } 1743 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1744 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1745 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1746 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 1747 else 1748 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1749 /* Write the standard receive producer ring control block. */ 1750 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1751 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1752 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1753 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1754 1755 /* Reset the standard receive producer ring producer index. */ 1756 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1757 1758 /* 1759 * Initialize the jumbo RX producer ring control 1760 * block. We set the 'ring disabled' bit in the 1761 * flags field until we're actually ready to start 1762 * using this ring (i.e. once we set the MTU 1763 * high enough to require it). 1764 */ 1765 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1766 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1767 /* Get the jumbo receive producer ring RCB parameters. */ 1768 rcb->bge_hostaddr.bge_addr_lo = 1769 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1770 rcb->bge_hostaddr.bge_addr_hi = 1771 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1772 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1773 sc->bge_cdata.bge_rx_jumbo_ring_map, 1774 BUS_DMASYNC_PREREAD); 1775 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1776 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1777 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1778 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1779 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1780 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 1781 else 1782 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1783 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1784 rcb->bge_hostaddr.bge_addr_hi); 1785 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1786 rcb->bge_hostaddr.bge_addr_lo); 1787 /* Program the jumbo receive producer ring RCB parameters. */ 1788 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1789 rcb->bge_maxlen_flags); 1790 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1791 /* Reset the jumbo receive producer ring producer index. */ 1792 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1793 } 1794 1795 /* Disable the mini receive producer ring RCB. */ 1796 if (BGE_IS_5700_FAMILY(sc)) { 1797 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1798 rcb->bge_maxlen_flags = 1799 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1800 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1801 rcb->bge_maxlen_flags); 1802 /* Reset the mini receive producer ring producer index. */ 1803 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1804 } 1805 1806 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 1807 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1808 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 1809 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 1810 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 1811 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 1812 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 1813 } 1814 /* 1815 * The BD ring replenish thresholds control how often the 1816 * hardware fetches new BD's from the producer rings in host 1817 * memory. Setting the value too low on a busy system can 1818 * starve the hardware and recue the throughpout. 1819 * 1820 * Set the BD ring replentish thresholds. The recommended 1821 * values are 1/8th the number of descriptors allocated to 1822 * each ring. 1823 * XXX The 5754 requires a lower threshold, so it might be a 1824 * requirement of all 575x family chips. The Linux driver sets 1825 * the lower threshold for all 5705 family chips as well, but there 1826 * are reports that it might not need to be so strict. 1827 * 1828 * XXX Linux does some extra fiddling here for the 5906 parts as 1829 * well. 1830 */ 1831 if (BGE_IS_5705_PLUS(sc)) 1832 val = 8; 1833 else 1834 val = BGE_STD_RX_RING_CNT / 8; 1835 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1836 if (BGE_IS_JUMBO_CAPABLE(sc)) 1837 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1838 BGE_JUMBO_RX_RING_CNT/8); 1839 if (BGE_IS_5717_PLUS(sc)) { 1840 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 1841 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 1842 } 1843 1844 /* 1845 * Disable all send rings by setting the 'ring disabled' bit 1846 * in the flags field of all the TX send ring control blocks, 1847 * located in NIC memory. 1848 */ 1849 if (!BGE_IS_5705_PLUS(sc)) 1850 /* 5700 to 5704 had 16 send rings. */ 1851 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 1852 else 1853 limit = 1; 1854 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1855 for (i = 0; i < limit; i++) { 1856 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1857 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1858 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1859 vrcb += sizeof(struct bge_rcb); 1860 } 1861 1862 /* Configure send ring RCB 0 (we use only the first ring) */ 1863 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1864 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1865 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1866 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1867 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1868 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1869 sc->bge_asicrev == BGE_ASICREV_BCM5720) 1870 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 1871 else 1872 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1873 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1874 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1875 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1876 1877 /* 1878 * Disable all receive return rings by setting the 1879 * 'ring diabled' bit in the flags field of all the receive 1880 * return ring control blocks, located in NIC memory. 1881 */ 1882 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 1883 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 1884 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 1885 /* Should be 17, use 16 until we get an SRAM map. */ 1886 limit = 16; 1887 } else if (!BGE_IS_5705_PLUS(sc)) 1888 limit = BGE_RX_RINGS_MAX; 1889 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 1890 sc->bge_asicrev == BGE_ASICREV_BCM57765) 1891 limit = 4; 1892 else 1893 limit = 1; 1894 /* Disable all receive return rings. */ 1895 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1896 for (i = 0; i < limit; i++) { 1897 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1898 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1899 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1900 BGE_RCB_FLAG_RING_DISABLED); 1901 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1902 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1903 (i * (sizeof(uint64_t))), 0); 1904 vrcb += sizeof(struct bge_rcb); 1905 } 1906 1907 /* 1908 * Set up receive return ring 0. Note that the NIC address 1909 * for RX return rings is 0x0. The return rings live entirely 1910 * within the host, so the nicaddr field in the RCB isn't used. 1911 */ 1912 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1913 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1914 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1915 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1916 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1917 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1918 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1919 1920 /* Set random backoff seed for TX */ 1921 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1922 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1923 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1924 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1925 BGE_TX_BACKOFF_SEED_MASK); 1926 1927 /* Set inter-packet gap */ 1928 val = 0x2620; 1929 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 1930 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 1931 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 1932 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 1933 1934 /* 1935 * Specify which ring to use for packets that don't match 1936 * any RX rules. 1937 */ 1938 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1939 1940 /* 1941 * Configure number of RX lists. One interrupt distribution 1942 * list, sixteen active lists, one bad frames class. 1943 */ 1944 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1945 1946 /* Inialize RX list placement stats mask. */ 1947 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1948 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1949 1950 /* Disable host coalescing until we get it set up */ 1951 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1952 1953 /* Poll to make sure it's shut down. */ 1954 for (i = 0; i < BGE_TIMEOUT; i++) { 1955 DELAY(10); 1956 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1957 break; 1958 } 1959 1960 if (i == BGE_TIMEOUT) { 1961 device_printf(sc->bge_dev, 1962 "host coalescing engine failed to idle\n"); 1963 return (ENXIO); 1964 } 1965 1966 /* Set up host coalescing defaults */ 1967 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1968 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1969 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1970 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1971 if (!(BGE_IS_5705_PLUS(sc))) { 1972 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1973 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1974 } 1975 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1976 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1977 1978 /* Set up address of statistics block */ 1979 if (!(BGE_IS_5705_PLUS(sc))) { 1980 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1981 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1982 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1983 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1984 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1985 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1986 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1987 } 1988 1989 /* Set up address of status block */ 1990 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1991 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1992 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1993 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1994 1995 /* Set up status block size. */ 1996 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1997 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1998 val = BGE_STATBLKSZ_FULL; 1999 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2000 } else { 2001 val = BGE_STATBLKSZ_32BYTE; 2002 bzero(sc->bge_ldata.bge_status_block, 32); 2003 } 2004 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2005 sc->bge_cdata.bge_status_map, 2006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2007 2008 /* Turn on host coalescing state machine */ 2009 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2010 2011 /* Turn on RX BD completion state machine and enable attentions */ 2012 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2013 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2014 2015 /* Turn on RX list placement state machine */ 2016 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2017 2018 /* Turn on RX list selector state machine. */ 2019 if (!(BGE_IS_5705_PLUS(sc))) 2020 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2021 2022 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2023 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2024 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2025 BGE_MACMODE_FRMHDR_DMA_ENB; 2026 2027 if (sc->bge_flags & BGE_FLAG_TBI) 2028 val |= BGE_PORTMODE_TBI; 2029 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2030 val |= BGE_PORTMODE_GMII; 2031 else 2032 val |= BGE_PORTMODE_MII; 2033 2034 /* Turn on DMA, clear stats */ 2035 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2036 2037 /* Set misc. local control, enable interrupts on attentions */ 2038 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2039 2040 #ifdef notdef 2041 /* Assert GPIO pins for PHY reset */ 2042 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2043 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2044 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2045 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2046 #endif 2047 2048 /* Turn on DMA completion state machine */ 2049 if (!(BGE_IS_5705_PLUS(sc))) 2050 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2051 2052 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2053 2054 /* Enable host coalescing bug fix. */ 2055 if (BGE_IS_5755_PLUS(sc)) 2056 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2057 2058 /* Request larger DMA burst size to get better performance. */ 2059 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2060 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2061 2062 /* Turn on write DMA state machine */ 2063 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2064 DELAY(40); 2065 2066 /* Turn on read DMA state machine */ 2067 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2068 2069 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2070 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2071 2072 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2073 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2074 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2075 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2076 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2077 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2078 if (sc->bge_flags & BGE_FLAG_PCIE) 2079 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2080 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2081 val |= BGE_RDMAMODE_TSO4_ENABLE; 2082 if (sc->bge_flags & BGE_FLAG_TSO3 || 2083 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2084 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2085 val |= BGE_RDMAMODE_TSO6_ENABLE; 2086 } 2087 2088 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2089 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2090 BGE_RDMAMODE_H2BNC_VLAN_DET; 2091 /* 2092 * Allow multiple outstanding read requests from 2093 * non-LSO read DMA engine. 2094 */ 2095 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2096 } 2097 2098 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2099 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2100 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2101 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2102 BGE_IS_5717_PLUS(sc)) { 2103 dmactl = CSR_READ_4(sc, BGE_RDMA_RSRVCTRL); 2104 /* 2105 * Adjust tx margin to prevent TX data corruption and 2106 * fix internal FIFO overflow. 2107 */ 2108 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2109 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2110 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2111 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2112 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2113 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2114 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2115 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2116 } 2117 /* 2118 * Enable fix for read DMA FIFO overruns. 2119 * The fix is to limit the number of RX BDs 2120 * the hardware would fetch at a fime. 2121 */ 2122 CSR_WRITE_4(sc, BGE_RDMA_RSRVCTRL, dmactl | 2123 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2124 } 2125 2126 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2127 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2128 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2129 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2130 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2131 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2132 /* 2133 * Allow 4KB burst length reads for non-LSO frames. 2134 * Enable 512B burst length reads for buffer descriptors. 2135 */ 2136 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2137 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2138 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2139 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2140 } 2141 2142 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2143 DELAY(40); 2144 2145 /* Turn on RX data completion state machine */ 2146 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2147 2148 /* Turn on RX BD initiator state machine */ 2149 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2150 2151 /* Turn on RX data and RX BD initiator state machine */ 2152 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2153 2154 /* Turn on Mbuf cluster free state machine */ 2155 if (!(BGE_IS_5705_PLUS(sc))) 2156 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2157 2158 /* Turn on send BD completion state machine */ 2159 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2160 2161 /* Turn on send data completion state machine */ 2162 val = BGE_SDCMODE_ENABLE; 2163 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2164 val |= BGE_SDCMODE_CDELAY; 2165 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2166 2167 /* Turn on send data initiator state machine */ 2168 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2169 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2170 BGE_SDIMODE_HW_LSO_PRE_DMA); 2171 else 2172 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2173 2174 /* Turn on send BD initiator state machine */ 2175 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2176 2177 /* Turn on send BD selector state machine */ 2178 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2179 2180 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2181 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2182 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2183 2184 /* ack/clear link change events */ 2185 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2186 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2187 BGE_MACSTAT_LINK_CHANGED); 2188 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2189 2190 /* 2191 * Enable attention when the link has changed state for 2192 * devices that use auto polling. 2193 */ 2194 if (sc->bge_flags & BGE_FLAG_TBI) { 2195 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2196 } else { 2197 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2198 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2199 DELAY(80); 2200 } 2201 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2202 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2203 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2204 BGE_EVTENB_MI_INTERRUPT); 2205 } 2206 2207 /* 2208 * Clear any pending link state attention. 2209 * Otherwise some link state change events may be lost until attention 2210 * is cleared by bge_intr() -> bge_link_upd() sequence. 2211 * It's not necessary on newer BCM chips - perhaps enabling link 2212 * state change attentions implies clearing pending attention. 2213 */ 2214 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2215 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2216 BGE_MACSTAT_LINK_CHANGED); 2217 2218 /* Enable link state change attentions. */ 2219 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2220 2221 return (0); 2222 } 2223 2224 const struct bge_revision * 2225 bge_lookup_rev(uint32_t chipid) 2226 { 2227 const struct bge_revision *br; 2228 2229 for (br = bge_revisions; br->br_name != NULL; br++) { 2230 if (br->br_chipid == chipid) 2231 return (br); 2232 } 2233 2234 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2235 if (br->br_chipid == BGE_ASICREV(chipid)) 2236 return (br); 2237 } 2238 2239 return (NULL); 2240 } 2241 2242 const struct bge_vendor * 2243 bge_lookup_vendor(uint16_t vid) 2244 { 2245 const struct bge_vendor *v; 2246 2247 for (v = bge_vendors; v->v_name != NULL; v++) 2248 if (v->v_id == vid) 2249 return (v); 2250 2251 panic("%s: unknown vendor %d", __func__, vid); 2252 return (NULL); 2253 } 2254 2255 /* 2256 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2257 * against our list and return its name if we find a match. 2258 * 2259 * Note that since the Broadcom controller contains VPD support, we 2260 * try to get the device name string from the controller itself instead 2261 * of the compiled-in string. It guarantees we'll always announce the 2262 * right product name. We fall back to the compiled-in string when 2263 * VPD is unavailable or corrupt. 2264 */ 2265 static int 2266 bge_probe(device_t dev) 2267 { 2268 char buf[96]; 2269 char model[64]; 2270 const struct bge_revision *br; 2271 const char *pname; 2272 struct bge_softc *sc = device_get_softc(dev); 2273 const struct bge_type *t = bge_devs; 2274 const struct bge_vendor *v; 2275 uint32_t id; 2276 uint16_t did, vid; 2277 2278 sc->bge_dev = dev; 2279 vid = pci_get_vendor(dev); 2280 did = pci_get_device(dev); 2281 while(t->bge_vid != 0) { 2282 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2283 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2284 BGE_PCIMISCCTL_ASICREV_SHIFT; 2285 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2286 /* 2287 * Find the ASCI revision. Different chips 2288 * use different registers. 2289 */ 2290 switch (pci_get_device(dev)) { 2291 case BCOM_DEVICEID_BCM5717: 2292 case BCOM_DEVICEID_BCM5718: 2293 case BCOM_DEVICEID_BCM5719: 2294 case BCOM_DEVICEID_BCM5720: 2295 id = pci_read_config(dev, 2296 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2297 break; 2298 case BCOM_DEVICEID_BCM57761: 2299 case BCOM_DEVICEID_BCM57765: 2300 case BCOM_DEVICEID_BCM57781: 2301 case BCOM_DEVICEID_BCM57785: 2302 case BCOM_DEVICEID_BCM57791: 2303 case BCOM_DEVICEID_BCM57795: 2304 id = pci_read_config(dev, 2305 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2306 break; 2307 default: 2308 id = pci_read_config(dev, 2309 BGE_PCI_PRODID_ASICREV, 4); 2310 } 2311 } 2312 br = bge_lookup_rev(id); 2313 v = bge_lookup_vendor(vid); 2314 if (bge_has_eaddr(sc) && 2315 pci_get_vpd_ident(dev, &pname) == 0) 2316 snprintf(model, 64, "%s", pname); 2317 else 2318 snprintf(model, 64, "%s %s", v->v_name, 2319 br != NULL ? br->br_name : 2320 "NetXtreme Ethernet Controller"); 2321 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 2322 br != NULL ? "" : "unknown ", id); 2323 device_set_desc_copy(dev, buf); 2324 return (0); 2325 } 2326 t++; 2327 } 2328 2329 return (ENXIO); 2330 } 2331 2332 static void 2333 bge_dma_free(struct bge_softc *sc) 2334 { 2335 int i; 2336 2337 /* Destroy DMA maps for RX buffers. */ 2338 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2339 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2340 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2341 sc->bge_cdata.bge_rx_std_dmamap[i]); 2342 } 2343 if (sc->bge_cdata.bge_rx_std_sparemap) 2344 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2345 sc->bge_cdata.bge_rx_std_sparemap); 2346 2347 /* Destroy DMA maps for jumbo RX buffers. */ 2348 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2349 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2350 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2351 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2352 } 2353 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2354 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2355 sc->bge_cdata.bge_rx_jumbo_sparemap); 2356 2357 /* Destroy DMA maps for TX buffers. */ 2358 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2359 if (sc->bge_cdata.bge_tx_dmamap[i]) 2360 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2361 sc->bge_cdata.bge_tx_dmamap[i]); 2362 } 2363 2364 if (sc->bge_cdata.bge_rx_mtag) 2365 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2366 if (sc->bge_cdata.bge_mtag_jumbo) 2367 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2368 if (sc->bge_cdata.bge_tx_mtag) 2369 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2370 2371 /* Destroy standard RX ring. */ 2372 if (sc->bge_cdata.bge_rx_std_ring_map) 2373 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2374 sc->bge_cdata.bge_rx_std_ring_map); 2375 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2376 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2377 sc->bge_ldata.bge_rx_std_ring, 2378 sc->bge_cdata.bge_rx_std_ring_map); 2379 2380 if (sc->bge_cdata.bge_rx_std_ring_tag) 2381 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2382 2383 /* Destroy jumbo RX ring. */ 2384 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2385 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2386 sc->bge_cdata.bge_rx_jumbo_ring_map); 2387 2388 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2389 sc->bge_ldata.bge_rx_jumbo_ring) 2390 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2391 sc->bge_ldata.bge_rx_jumbo_ring, 2392 sc->bge_cdata.bge_rx_jumbo_ring_map); 2393 2394 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2395 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2396 2397 /* Destroy RX return ring. */ 2398 if (sc->bge_cdata.bge_rx_return_ring_map) 2399 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2400 sc->bge_cdata.bge_rx_return_ring_map); 2401 2402 if (sc->bge_cdata.bge_rx_return_ring_map && 2403 sc->bge_ldata.bge_rx_return_ring) 2404 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2405 sc->bge_ldata.bge_rx_return_ring, 2406 sc->bge_cdata.bge_rx_return_ring_map); 2407 2408 if (sc->bge_cdata.bge_rx_return_ring_tag) 2409 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2410 2411 /* Destroy TX ring. */ 2412 if (sc->bge_cdata.bge_tx_ring_map) 2413 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2414 sc->bge_cdata.bge_tx_ring_map); 2415 2416 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2417 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2418 sc->bge_ldata.bge_tx_ring, 2419 sc->bge_cdata.bge_tx_ring_map); 2420 2421 if (sc->bge_cdata.bge_tx_ring_tag) 2422 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2423 2424 /* Destroy status block. */ 2425 if (sc->bge_cdata.bge_status_map) 2426 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2427 sc->bge_cdata.bge_status_map); 2428 2429 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2430 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2431 sc->bge_ldata.bge_status_block, 2432 sc->bge_cdata.bge_status_map); 2433 2434 if (sc->bge_cdata.bge_status_tag) 2435 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2436 2437 /* Destroy statistics block. */ 2438 if (sc->bge_cdata.bge_stats_map) 2439 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2440 sc->bge_cdata.bge_stats_map); 2441 2442 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2443 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2444 sc->bge_ldata.bge_stats, 2445 sc->bge_cdata.bge_stats_map); 2446 2447 if (sc->bge_cdata.bge_stats_tag) 2448 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2449 2450 if (sc->bge_cdata.bge_buffer_tag) 2451 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2452 2453 /* Destroy the parent tag. */ 2454 if (sc->bge_cdata.bge_parent_tag) 2455 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2456 } 2457 2458 static int 2459 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2460 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2461 bus_addr_t *paddr, const char *msg) 2462 { 2463 struct bge_dmamap_arg ctx; 2464 int error; 2465 2466 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2467 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2468 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2469 if (error != 0) { 2470 device_printf(sc->bge_dev, 2471 "could not create %s dma tag\n", msg); 2472 return (ENOMEM); 2473 } 2474 /* Allocate DMA'able memory for ring. */ 2475 error = bus_dmamem_alloc(*tag, (void **)ring, 2476 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2477 if (error != 0) { 2478 device_printf(sc->bge_dev, 2479 "could not allocate DMA'able memory for %s\n", msg); 2480 return (ENOMEM); 2481 } 2482 /* Load the address of the ring. */ 2483 ctx.bge_busaddr = 0; 2484 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2485 &ctx, BUS_DMA_NOWAIT); 2486 if (error != 0) { 2487 device_printf(sc->bge_dev, 2488 "could not load DMA'able memory for %s\n", msg); 2489 return (ENOMEM); 2490 } 2491 *paddr = ctx.bge_busaddr; 2492 return (0); 2493 } 2494 2495 static int 2496 bge_dma_alloc(struct bge_softc *sc) 2497 { 2498 bus_addr_t lowaddr; 2499 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2500 int i, error; 2501 2502 lowaddr = BUS_SPACE_MAXADDR; 2503 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2504 lowaddr = BGE_DMA_MAXADDR; 2505 /* 2506 * Allocate the parent bus DMA tag appropriate for PCI. 2507 */ 2508 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2509 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2510 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2511 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2512 if (error != 0) { 2513 device_printf(sc->bge_dev, 2514 "could not allocate parent dma tag\n"); 2515 return (ENOMEM); 2516 } 2517 2518 /* Create tag for standard RX ring. */ 2519 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2520 &sc->bge_cdata.bge_rx_std_ring_tag, 2521 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2522 &sc->bge_cdata.bge_rx_std_ring_map, 2523 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2524 if (error) 2525 return (error); 2526 2527 /* Create tag for RX return ring. */ 2528 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2529 &sc->bge_cdata.bge_rx_return_ring_tag, 2530 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2531 &sc->bge_cdata.bge_rx_return_ring_map, 2532 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2533 if (error) 2534 return (error); 2535 2536 /* Create tag for TX ring. */ 2537 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2538 &sc->bge_cdata.bge_tx_ring_tag, 2539 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2540 &sc->bge_cdata.bge_tx_ring_map, 2541 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2542 if (error) 2543 return (error); 2544 2545 /* 2546 * Create tag for status block. 2547 * Because we only use single Tx/Rx/Rx return ring, use 2548 * minimum status block size except BCM5700 AX/BX which 2549 * seems to want to see full status block size regardless 2550 * of configured number of ring. 2551 */ 2552 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2553 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2554 sbsz = BGE_STATUS_BLK_SZ; 2555 else 2556 sbsz = 32; 2557 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 2558 &sc->bge_cdata.bge_status_tag, 2559 (uint8_t **)&sc->bge_ldata.bge_status_block, 2560 &sc->bge_cdata.bge_status_map, 2561 &sc->bge_ldata.bge_status_block_paddr, "status block"); 2562 if (error) 2563 return (error); 2564 2565 /* Create tag for statistics block. */ 2566 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 2567 &sc->bge_cdata.bge_stats_tag, 2568 (uint8_t **)&sc->bge_ldata.bge_stats, 2569 &sc->bge_cdata.bge_stats_map, 2570 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 2571 if (error) 2572 return (error); 2573 2574 /* Create tag for jumbo RX ring. */ 2575 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2576 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 2577 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 2578 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 2579 &sc->bge_cdata.bge_rx_jumbo_ring_map, 2580 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 2581 if (error) 2582 return (error); 2583 } 2584 2585 /* Create parent tag for buffers. */ 2586 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 2587 /* 2588 * XXX 2589 * watchdog timeout issue was observed on BCM5704 which 2590 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 2591 * Both limiting DMA address space to 32bits and flushing 2592 * mailbox write seem to address the issue. 2593 */ 2594 if (sc->bge_pcixcap != 0) 2595 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2596 } 2597 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 2598 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 2599 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 2600 &sc->bge_cdata.bge_buffer_tag); 2601 if (error != 0) { 2602 device_printf(sc->bge_dev, 2603 "could not allocate buffer dma tag\n"); 2604 return (ENOMEM); 2605 } 2606 /* Create tag for Tx mbufs. */ 2607 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2608 txsegsz = BGE_TSOSEG_SZ; 2609 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2610 } else { 2611 txsegsz = MCLBYTES; 2612 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2613 } 2614 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 2615 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2616 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2617 &sc->bge_cdata.bge_tx_mtag); 2618 2619 if (error) { 2620 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2621 return (ENOMEM); 2622 } 2623 2624 /* Create tag for Rx mbufs. */ 2625 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 2626 rxmaxsegsz = MJUM9BYTES; 2627 else 2628 rxmaxsegsz = MCLBYTES; 2629 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 2630 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 2631 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2632 2633 if (error) { 2634 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2635 return (ENOMEM); 2636 } 2637 2638 /* Create DMA maps for RX buffers. */ 2639 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2640 &sc->bge_cdata.bge_rx_std_sparemap); 2641 if (error) { 2642 device_printf(sc->bge_dev, 2643 "can't create spare DMA map for RX\n"); 2644 return (ENOMEM); 2645 } 2646 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2647 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2648 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2649 if (error) { 2650 device_printf(sc->bge_dev, 2651 "can't create DMA map for RX\n"); 2652 return (ENOMEM); 2653 } 2654 } 2655 2656 /* Create DMA maps for TX buffers. */ 2657 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2658 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2659 &sc->bge_cdata.bge_tx_dmamap[i]); 2660 if (error) { 2661 device_printf(sc->bge_dev, 2662 "can't create DMA map for TX\n"); 2663 return (ENOMEM); 2664 } 2665 } 2666 2667 /* Create tags for jumbo RX buffers. */ 2668 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2669 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 2670 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2671 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2672 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2673 if (error) { 2674 device_printf(sc->bge_dev, 2675 "could not allocate jumbo dma tag\n"); 2676 return (ENOMEM); 2677 } 2678 /* Create DMA maps for jumbo RX buffers. */ 2679 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2680 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2681 if (error) { 2682 device_printf(sc->bge_dev, 2683 "can't create spare DMA map for jumbo RX\n"); 2684 return (ENOMEM); 2685 } 2686 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2687 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2688 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2689 if (error) { 2690 device_printf(sc->bge_dev, 2691 "can't create DMA map for jumbo RX\n"); 2692 return (ENOMEM); 2693 } 2694 } 2695 } 2696 2697 return (0); 2698 } 2699 2700 /* 2701 * Return true if this device has more than one port. 2702 */ 2703 static int 2704 bge_has_multiple_ports(struct bge_softc *sc) 2705 { 2706 device_t dev = sc->bge_dev; 2707 u_int b, d, f, fscan, s; 2708 2709 d = pci_get_domain(dev); 2710 b = pci_get_bus(dev); 2711 s = pci_get_slot(dev); 2712 f = pci_get_function(dev); 2713 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2714 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2715 return (1); 2716 return (0); 2717 } 2718 2719 /* 2720 * Return true if MSI can be used with this device. 2721 */ 2722 static int 2723 bge_can_use_msi(struct bge_softc *sc) 2724 { 2725 int can_use_msi = 0; 2726 2727 if (sc->bge_msi == 0) 2728 return (0); 2729 2730 /* Disable MSI for polling(4). */ 2731 #ifdef DEVICE_POLLING 2732 return (0); 2733 #endif 2734 switch (sc->bge_asicrev) { 2735 case BGE_ASICREV_BCM5714_A0: 2736 case BGE_ASICREV_BCM5714: 2737 /* 2738 * Apparently, MSI doesn't work when these chips are 2739 * configured in single-port mode. 2740 */ 2741 if (bge_has_multiple_ports(sc)) 2742 can_use_msi = 1; 2743 break; 2744 case BGE_ASICREV_BCM5750: 2745 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2746 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2747 can_use_msi = 1; 2748 break; 2749 default: 2750 if (BGE_IS_575X_PLUS(sc)) 2751 can_use_msi = 1; 2752 } 2753 return (can_use_msi); 2754 } 2755 2756 static int 2757 bge_mbox_reorder(struct bge_softc *sc) 2758 { 2759 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 2760 static const struct mbox_reorder { 2761 const uint16_t vendor; 2762 const uint16_t device; 2763 const char *desc; 2764 } const mbox_reorder_lists[] = { 2765 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 2766 }; 2767 devclass_t pci, pcib; 2768 device_t bus, dev; 2769 int i; 2770 2771 pci = devclass_find("pci"); 2772 pcib = devclass_find("pcib"); 2773 dev = sc->bge_dev; 2774 bus = device_get_parent(dev); 2775 for (;;) { 2776 dev = device_get_parent(bus); 2777 bus = device_get_parent(dev); 2778 if (device_get_devclass(dev) != pcib) 2779 break; 2780 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 2781 if (pci_get_vendor(dev) == 2782 mbox_reorder_lists[i].vendor && 2783 pci_get_device(dev) == 2784 mbox_reorder_lists[i].device) { 2785 device_printf(sc->bge_dev, 2786 "enabling MBOX workaround for %s\n", 2787 mbox_reorder_lists[i].desc); 2788 return (1); 2789 } 2790 } 2791 if (device_get_devclass(bus) != pci) 2792 break; 2793 } 2794 return (0); 2795 } 2796 2797 static void 2798 bge_devinfo(struct bge_softc *sc) 2799 { 2800 uint32_t cfg, clk; 2801 2802 device_printf(sc->bge_dev, 2803 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 2804 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 2805 if (sc->bge_flags & BGE_FLAG_PCIE) 2806 printf("PCI-E\n"); 2807 else if (sc->bge_flags & BGE_FLAG_PCIX) { 2808 printf("PCI-X "); 2809 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 2810 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 2811 clk = 133; 2812 else { 2813 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 2814 switch (clk) { 2815 case 0: 2816 clk = 33; 2817 break; 2818 case 2: 2819 clk = 50; 2820 break; 2821 case 4: 2822 clk = 66; 2823 break; 2824 case 6: 2825 clk = 100; 2826 break; 2827 case 7: 2828 clk = 133; 2829 break; 2830 } 2831 } 2832 printf("%u MHz\n", clk); 2833 } else { 2834 if (sc->bge_pcixcap != 0) 2835 printf("PCI on PCI-X "); 2836 else 2837 printf("PCI "); 2838 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 2839 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 2840 clk = 66; 2841 else 2842 clk = 33; 2843 if (cfg & BGE_PCISTATE_32BIT_BUS) 2844 printf("%u MHz; 32bit\n", clk); 2845 else 2846 printf("%u MHz; 64bit\n", clk); 2847 } 2848 } 2849 2850 static int 2851 bge_attach(device_t dev) 2852 { 2853 struct ifnet *ifp; 2854 struct bge_softc *sc; 2855 uint32_t hwcfg = 0, misccfg; 2856 u_char eaddr[ETHER_ADDR_LEN]; 2857 int capmask, error, f, msicount, phy_addr, reg, rid, trys; 2858 2859 sc = device_get_softc(dev); 2860 sc->bge_dev = dev; 2861 2862 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2863 2864 /* 2865 * Map control/status registers. 2866 */ 2867 pci_enable_busmaster(dev); 2868 2869 rid = PCIR_BAR(0); 2870 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2871 RF_ACTIVE); 2872 2873 if (sc->bge_res == NULL) { 2874 device_printf (sc->bge_dev, "couldn't map memory\n"); 2875 error = ENXIO; 2876 goto fail; 2877 } 2878 2879 /* Save various chip information. */ 2880 sc->bge_chipid = 2881 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2882 BGE_PCIMISCCTL_ASICREV_SHIFT; 2883 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) { 2884 /* 2885 * Find the ASCI revision. Different chips use different 2886 * registers. 2887 */ 2888 switch (pci_get_device(dev)) { 2889 case BCOM_DEVICEID_BCM5717: 2890 case BCOM_DEVICEID_BCM5718: 2891 case BCOM_DEVICEID_BCM5719: 2892 case BCOM_DEVICEID_BCM5720: 2893 sc->bge_chipid = pci_read_config(dev, 2894 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2895 break; 2896 case BCOM_DEVICEID_BCM57761: 2897 case BCOM_DEVICEID_BCM57765: 2898 case BCOM_DEVICEID_BCM57781: 2899 case BCOM_DEVICEID_BCM57785: 2900 case BCOM_DEVICEID_BCM57791: 2901 case BCOM_DEVICEID_BCM57795: 2902 sc->bge_chipid = pci_read_config(dev, 2903 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2904 break; 2905 default: 2906 sc->bge_chipid = pci_read_config(dev, 2907 BGE_PCI_PRODID_ASICREV, 4); 2908 } 2909 } 2910 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2911 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2912 2913 /* Set default PHY address. */ 2914 phy_addr = 1; 2915 /* 2916 * PHY address mapping for various devices. 2917 * 2918 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 2919 * ---------+-------+-------+-------+-------+ 2920 * BCM57XX | 1 | X | X | X | 2921 * BCM5704 | 1 | X | 1 | X | 2922 * BCM5717 | 1 | 8 | 2 | 9 | 2923 * BCM5719 | 1 | 8 | 2 | 9 | 2924 * BCM5720 | 1 | 8 | 2 | 9 | 2925 * 2926 * Other addresses may respond but they are not 2927 * IEEE compliant PHYs and should be ignored. 2928 */ 2929 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2930 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2931 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2932 f = pci_get_function(dev); 2933 if (sc->bge_chipid == BGE_CHIPID_BCM5717_A0) { 2934 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 2935 BGE_SGDIGSTS_IS_SERDES) 2936 phy_addr = f + 8; 2937 else 2938 phy_addr = f + 1; 2939 } else { 2940 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 2941 BGE_CPMU_PHY_STRAP_IS_SERDES) 2942 phy_addr = f + 8; 2943 else 2944 phy_addr = f + 1; 2945 } 2946 } 2947 2948 /* 2949 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2950 * 5705 A0 and A1 chips. 2951 */ 2952 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 2953 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 2954 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2955 sc->bge_chipid != BGE_CHIPID_BCM5705_A1)) || 2956 sc->bge_asicrev == BGE_ASICREV_BCM5906) 2957 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 2958 2959 if (bge_has_eaddr(sc)) 2960 sc->bge_flags |= BGE_FLAG_EADDR; 2961 2962 /* Save chipset family. */ 2963 switch (sc->bge_asicrev) { 2964 case BGE_ASICREV_BCM5717: 2965 case BGE_ASICREV_BCM5719: 2966 case BGE_ASICREV_BCM5720: 2967 case BGE_ASICREV_BCM57765: 2968 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 2969 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 2970 BGE_FLAG_JUMBO_FRAME; 2971 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 2972 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 2973 /* Jumbo frame on BCM5719 A0 does not work. */ 2974 sc->bge_flags &= ~BGE_FLAG_JUMBO; 2975 } 2976 break; 2977 case BGE_ASICREV_BCM5755: 2978 case BGE_ASICREV_BCM5761: 2979 case BGE_ASICREV_BCM5784: 2980 case BGE_ASICREV_BCM5785: 2981 case BGE_ASICREV_BCM5787: 2982 case BGE_ASICREV_BCM57780: 2983 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2984 BGE_FLAG_5705_PLUS; 2985 break; 2986 case BGE_ASICREV_BCM5700: 2987 case BGE_ASICREV_BCM5701: 2988 case BGE_ASICREV_BCM5703: 2989 case BGE_ASICREV_BCM5704: 2990 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2991 break; 2992 case BGE_ASICREV_BCM5714_A0: 2993 case BGE_ASICREV_BCM5780: 2994 case BGE_ASICREV_BCM5714: 2995 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 2996 /* FALLTHROUGH */ 2997 case BGE_ASICREV_BCM5750: 2998 case BGE_ASICREV_BCM5752: 2999 case BGE_ASICREV_BCM5906: 3000 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3001 /* FALLTHROUGH */ 3002 case BGE_ASICREV_BCM5705: 3003 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3004 break; 3005 } 3006 3007 /* Add SYSCTLs, requires the chipset family to be set. */ 3008 bge_add_sysctls(sc); 3009 3010 /* Set various PHY bug flags. */ 3011 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3012 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3013 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3014 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3015 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3016 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3017 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3018 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3019 if (pci_get_subvendor(dev) == DELL_VENDORID) 3020 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3021 if ((BGE_IS_5705_PLUS(sc)) && 3022 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3023 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 3024 sc->bge_asicrev != BGE_ASICREV_BCM5719 && 3025 sc->bge_asicrev != BGE_ASICREV_BCM5720 && 3026 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3027 sc->bge_asicrev != BGE_ASICREV_BCM57765 && 3028 sc->bge_asicrev != BGE_ASICREV_BCM57780) { 3029 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3030 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3031 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3032 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3033 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3034 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3035 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3036 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3037 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3038 } else 3039 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3040 } 3041 3042 /* Identify the chips that use an CPMU. */ 3043 if (BGE_IS_5717_PLUS(sc) || 3044 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3045 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3046 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3047 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3048 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3049 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3050 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3051 else 3052 sc->bge_mi_mode = BGE_MIMODE_BASE; 3053 /* Enable auto polling for BCM570[0-5]. */ 3054 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3055 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3056 3057 /* 3058 * All Broadcom controllers have 4GB boundary DMA bug. 3059 * Whenever an address crosses a multiple of the 4GB boundary 3060 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3061 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3062 * state machine will lockup and cause the device to hang. 3063 */ 3064 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3065 3066 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3067 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3068 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3069 3070 /* 3071 * BCM5719 cannot handle DMA requests for DMA segments that 3072 * have larger than 4KB in size. However the maximum DMA 3073 * segment size created in DMA tag is 4KB for TSO, so we 3074 * wouldn't encounter the issue here. 3075 */ 3076 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3077 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3078 3079 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3080 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3081 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3082 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3083 sc->bge_flags |= BGE_FLAG_5788; 3084 } 3085 3086 capmask = BMSR_DEFCAPMASK; 3087 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3088 (misccfg == 0x4000 || misccfg == 0x8000)) || 3089 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3090 pci_get_vendor(dev) == BCOM_VENDORID && 3091 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3092 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3093 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3094 (pci_get_vendor(dev) == BCOM_VENDORID && 3095 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3096 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3097 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3098 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3099 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3100 /* These chips are 10/100 only. */ 3101 capmask &= ~BMSR_EXTSTAT; 3102 } 3103 3104 /* 3105 * Some controllers seem to require a special firmware to use 3106 * TSO. But the firmware is not available to FreeBSD and Linux 3107 * claims that the TSO performed by the firmware is slower than 3108 * hardware based TSO. Moreover the firmware based TSO has one 3109 * known bug which can't handle TSO if ethernet header + IP/TCP 3110 * header is greater than 80 bytes. The workaround for the TSO 3111 * bug exist but it seems it's too expensive than not using 3112 * TSO at all. Some hardwares also have the TSO bug so limit 3113 * the TSO to the controllers that are not affected TSO issues 3114 * (e.g. 5755 or higher). 3115 */ 3116 if (BGE_IS_5717_PLUS(sc)) { 3117 /* BCM5717 requires different TSO configuration. */ 3118 sc->bge_flags |= BGE_FLAG_TSO3; 3119 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3120 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3121 /* TSO on BCM5719 A0 does not work. */ 3122 sc->bge_flags &= ~BGE_FLAG_TSO3; 3123 } 3124 } else if (BGE_IS_5755_PLUS(sc)) { 3125 /* 3126 * BCM5754 and BCM5787 shares the same ASIC id so 3127 * explicit device id check is required. 3128 * Due to unknown reason TSO does not work on BCM5755M. 3129 */ 3130 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3131 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3132 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3133 sc->bge_flags |= BGE_FLAG_TSO; 3134 } 3135 3136 /* 3137 * Check if this is a PCI-X or PCI Express device. 3138 */ 3139 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3140 /* 3141 * Found a PCI Express capabilities register, this 3142 * must be a PCI Express device. 3143 */ 3144 sc->bge_flags |= BGE_FLAG_PCIE; 3145 sc->bge_expcap = reg; 3146 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3147 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3148 pci_set_max_read_req(dev, 2048); 3149 else if (pci_get_max_read_req(dev) != 4096) 3150 pci_set_max_read_req(dev, 4096); 3151 } else { 3152 /* 3153 * Check if the device is in PCI-X Mode. 3154 * (This bit is not valid on PCI Express controllers.) 3155 */ 3156 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3157 sc->bge_pcixcap = reg; 3158 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3159 BGE_PCISTATE_PCI_BUSMODE) == 0) 3160 sc->bge_flags |= BGE_FLAG_PCIX; 3161 } 3162 3163 /* 3164 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3165 * not actually a MAC controller bug but an issue with the embedded 3166 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3167 */ 3168 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3169 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3170 /* 3171 * Some PCI-X bridges are known to trigger write reordering to 3172 * the mailbox registers. Typical phenomena is watchdog timeouts 3173 * caused by out-of-order TX completions. Enable workaround for 3174 * PCI-X devices that live behind these bridges. 3175 * Note, PCI-X controllers can run in PCI mode so we can't use 3176 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3177 */ 3178 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3179 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3180 /* 3181 * Allocate the interrupt, using MSI if possible. These devices 3182 * support 8 MSI messages, but only the first one is used in 3183 * normal operation. 3184 */ 3185 rid = 0; 3186 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3187 sc->bge_msicap = reg; 3188 if (bge_can_use_msi(sc)) { 3189 msicount = pci_msi_count(dev); 3190 if (msicount > 1) 3191 msicount = 1; 3192 } else 3193 msicount = 0; 3194 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 3195 rid = 1; 3196 sc->bge_flags |= BGE_FLAG_MSI; 3197 } 3198 } 3199 3200 /* 3201 * All controllers except BCM5700 supports tagged status but 3202 * we use tagged status only for MSI case on BCM5717. Otherwise 3203 * MSI on BCM5717 does not work. 3204 */ 3205 #ifndef DEVICE_POLLING 3206 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3207 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3208 #endif 3209 3210 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3211 RF_SHAREABLE | RF_ACTIVE); 3212 3213 if (sc->bge_irq == NULL) { 3214 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3215 error = ENXIO; 3216 goto fail; 3217 } 3218 3219 bge_devinfo(sc); 3220 3221 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3222 3223 /* Try to reset the chip. */ 3224 if (bge_reset(sc)) { 3225 device_printf(sc->bge_dev, "chip reset failed\n"); 3226 error = ENXIO; 3227 goto fail; 3228 } 3229 3230 sc->bge_asf_mode = 0; 3231 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3232 BGE_SRAM_DATA_SIG_MAGIC)) { 3233 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) 3234 & BGE_HWCFG_ASF) { 3235 sc->bge_asf_mode |= ASF_ENABLE; 3236 sc->bge_asf_mode |= ASF_STACKUP; 3237 if (BGE_IS_575X_PLUS(sc)) 3238 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3239 } 3240 } 3241 3242 /* Try to reset the chip again the nice way. */ 3243 bge_stop_fw(sc); 3244 bge_sig_pre_reset(sc, BGE_RESET_STOP); 3245 if (bge_reset(sc)) { 3246 device_printf(sc->bge_dev, "chip reset failed\n"); 3247 error = ENXIO; 3248 goto fail; 3249 } 3250 3251 bge_sig_legacy(sc, BGE_RESET_STOP); 3252 bge_sig_post_reset(sc, BGE_RESET_STOP); 3253 3254 if (bge_chipinit(sc)) { 3255 device_printf(sc->bge_dev, "chip initialization failed\n"); 3256 error = ENXIO; 3257 goto fail; 3258 } 3259 3260 error = bge_get_eaddr(sc, eaddr); 3261 if (error) { 3262 device_printf(sc->bge_dev, 3263 "failed to read station address\n"); 3264 error = ENXIO; 3265 goto fail; 3266 } 3267 3268 /* 5705 limits RX return ring to 512 entries. */ 3269 if (BGE_IS_5717_PLUS(sc)) 3270 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3271 else if (BGE_IS_5705_PLUS(sc)) 3272 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3273 else 3274 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3275 3276 if (bge_dma_alloc(sc)) { 3277 device_printf(sc->bge_dev, 3278 "failed to allocate DMA resources\n"); 3279 error = ENXIO; 3280 goto fail; 3281 } 3282 3283 /* Set default tuneable values. */ 3284 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3285 sc->bge_rx_coal_ticks = 150; 3286 sc->bge_tx_coal_ticks = 150; 3287 sc->bge_rx_max_coal_bds = 10; 3288 sc->bge_tx_max_coal_bds = 10; 3289 3290 /* Initialize checksum features to use. */ 3291 sc->bge_csum_features = BGE_CSUM_FEATURES; 3292 if (sc->bge_forced_udpcsum != 0) 3293 sc->bge_csum_features |= CSUM_UDP; 3294 3295 /* Set up ifnet structure */ 3296 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3297 if (ifp == NULL) { 3298 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3299 error = ENXIO; 3300 goto fail; 3301 } 3302 ifp->if_softc = sc; 3303 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3304 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3305 ifp->if_ioctl = bge_ioctl; 3306 ifp->if_start = bge_start; 3307 ifp->if_init = bge_init; 3308 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3309 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3310 IFQ_SET_READY(&ifp->if_snd); 3311 ifp->if_hwassist = sc->bge_csum_features; 3312 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3313 IFCAP_VLAN_MTU; 3314 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3315 ifp->if_hwassist |= CSUM_TSO; 3316 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3317 } 3318 #ifdef IFCAP_VLAN_HWCSUM 3319 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3320 #endif 3321 ifp->if_capenable = ifp->if_capabilities; 3322 #ifdef DEVICE_POLLING 3323 ifp->if_capabilities |= IFCAP_POLLING; 3324 #endif 3325 3326 /* 3327 * 5700 B0 chips do not support checksumming correctly due 3328 * to hardware bugs. 3329 */ 3330 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3331 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3332 ifp->if_capenable &= ~IFCAP_HWCSUM; 3333 ifp->if_hwassist = 0; 3334 } 3335 3336 /* 3337 * Figure out what sort of media we have by checking the 3338 * hardware config word in the first 32k of NIC internal memory, 3339 * or fall back to examining the EEPROM if necessary. 3340 * Note: on some BCM5700 cards, this value appears to be unset. 3341 * If that's the case, we have to rely on identifying the NIC 3342 * by its PCI subsystem ID, as we do below for the SysKonnect 3343 * SK-9D41. 3344 */ 3345 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3346 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3347 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3348 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3349 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3350 sizeof(hwcfg))) { 3351 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3352 error = ENXIO; 3353 goto fail; 3354 } 3355 hwcfg = ntohl(hwcfg); 3356 } 3357 3358 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3359 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3360 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3361 if (BGE_IS_5714_FAMILY(sc)) 3362 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3363 else 3364 sc->bge_flags |= BGE_FLAG_TBI; 3365 } 3366 3367 if (sc->bge_flags & BGE_FLAG_TBI) { 3368 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3369 bge_ifmedia_sts); 3370 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3371 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3372 0, NULL); 3373 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3374 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3375 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3376 } else { 3377 /* 3378 * Do transceiver setup and tell the firmware the 3379 * driver is down so we can try to get access the 3380 * probe if ASF is running. Retry a couple of times 3381 * if we get a conflict with the ASF firmware accessing 3382 * the PHY. 3383 */ 3384 trys = 0; 3385 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3386 again: 3387 bge_asf_driver_up(sc); 3388 3389 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3390 bge_ifmedia_sts, capmask, phy_addr, MII_OFFSET_ANY, 3391 MIIF_DOPAUSE); 3392 if (error != 0) { 3393 if (trys++ < 4) { 3394 device_printf(sc->bge_dev, "Try again\n"); 3395 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 3396 BMCR_RESET); 3397 goto again; 3398 } 3399 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3400 goto fail; 3401 } 3402 3403 /* 3404 * Now tell the firmware we are going up after probing the PHY 3405 */ 3406 if (sc->bge_asf_mode & ASF_STACKUP) 3407 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3408 } 3409 3410 /* 3411 * When using the BCM5701 in PCI-X mode, data corruption has 3412 * been observed in the first few bytes of some received packets. 3413 * Aligning the packet buffer in memory eliminates the corruption. 3414 * Unfortunately, this misaligns the packet payloads. On platforms 3415 * which do not support unaligned accesses, we will realign the 3416 * payloads by copying the received packets. 3417 */ 3418 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3419 sc->bge_flags & BGE_FLAG_PCIX) 3420 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3421 3422 /* 3423 * Call MI attach routine. 3424 */ 3425 ether_ifattach(ifp, eaddr); 3426 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3427 3428 /* Tell upper layer we support long frames. */ 3429 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3430 3431 /* 3432 * Hookup IRQ last. 3433 */ 3434 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3435 /* Take advantage of single-shot MSI. */ 3436 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3437 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3438 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3439 taskqueue_thread_enqueue, &sc->bge_tq); 3440 if (sc->bge_tq == NULL) { 3441 device_printf(dev, "could not create taskqueue.\n"); 3442 ether_ifdetach(ifp); 3443 error = ENXIO; 3444 goto fail; 3445 } 3446 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 3447 device_get_nameunit(sc->bge_dev)); 3448 error = bus_setup_intr(dev, sc->bge_irq, 3449 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3450 &sc->bge_intrhand); 3451 if (error) 3452 ether_ifdetach(ifp); 3453 } else 3454 error = bus_setup_intr(dev, sc->bge_irq, 3455 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3456 &sc->bge_intrhand); 3457 3458 if (error) { 3459 bge_detach(dev); 3460 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3461 } 3462 3463 return (0); 3464 3465 fail: 3466 bge_release_resources(sc); 3467 3468 return (error); 3469 } 3470 3471 static int 3472 bge_detach(device_t dev) 3473 { 3474 struct bge_softc *sc; 3475 struct ifnet *ifp; 3476 3477 sc = device_get_softc(dev); 3478 ifp = sc->bge_ifp; 3479 3480 #ifdef DEVICE_POLLING 3481 if (ifp->if_capenable & IFCAP_POLLING) 3482 ether_poll_deregister(ifp); 3483 #endif 3484 3485 BGE_LOCK(sc); 3486 bge_stop(sc); 3487 bge_reset(sc); 3488 BGE_UNLOCK(sc); 3489 3490 callout_drain(&sc->bge_stat_ch); 3491 3492 if (sc->bge_tq) 3493 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3494 ether_ifdetach(ifp); 3495 3496 if (sc->bge_flags & BGE_FLAG_TBI) { 3497 ifmedia_removeall(&sc->bge_ifmedia); 3498 } else { 3499 bus_generic_detach(dev); 3500 device_delete_child(dev, sc->bge_miibus); 3501 } 3502 3503 bge_release_resources(sc); 3504 3505 return (0); 3506 } 3507 3508 static void 3509 bge_release_resources(struct bge_softc *sc) 3510 { 3511 device_t dev; 3512 3513 dev = sc->bge_dev; 3514 3515 if (sc->bge_tq != NULL) 3516 taskqueue_free(sc->bge_tq); 3517 3518 if (sc->bge_intrhand != NULL) 3519 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3520 3521 if (sc->bge_irq != NULL) 3522 bus_release_resource(dev, SYS_RES_IRQ, 3523 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3524 3525 if (sc->bge_flags & BGE_FLAG_MSI) 3526 pci_release_msi(dev); 3527 3528 if (sc->bge_res != NULL) 3529 bus_release_resource(dev, SYS_RES_MEMORY, 3530 PCIR_BAR(0), sc->bge_res); 3531 3532 if (sc->bge_ifp != NULL) 3533 if_free(sc->bge_ifp); 3534 3535 bge_dma_free(sc); 3536 3537 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3538 BGE_LOCK_DESTROY(sc); 3539 } 3540 3541 static int 3542 bge_reset(struct bge_softc *sc) 3543 { 3544 device_t dev; 3545 uint32_t cachesize, command, pcistate, reset, val; 3546 void (*write_op)(struct bge_softc *, int, int); 3547 uint16_t devctl; 3548 int i; 3549 3550 dev = sc->bge_dev; 3551 3552 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3553 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3554 if (sc->bge_flags & BGE_FLAG_PCIE) 3555 write_op = bge_writemem_direct; 3556 else 3557 write_op = bge_writemem_ind; 3558 } else 3559 write_op = bge_writereg_ind; 3560 3561 /* Save some important PCI state. */ 3562 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3563 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3564 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3565 3566 pci_write_config(dev, BGE_PCI_MISC_CTL, 3567 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3568 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3569 3570 /* Disable fastboot on controllers that support it. */ 3571 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3572 BGE_IS_5755_PLUS(sc)) { 3573 if (bootverbose) 3574 device_printf(dev, "Disabling fastboot\n"); 3575 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3576 } 3577 3578 /* 3579 * Write the magic number to SRAM at offset 0xB50. 3580 * When firmware finishes its initialization it will 3581 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 3582 */ 3583 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 3584 3585 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3586 3587 /* XXX: Broadcom Linux driver. */ 3588 if (sc->bge_flags & BGE_FLAG_PCIE) { 3589 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3590 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3591 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3592 /* Prevent PCIE link training during global reset */ 3593 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3594 reset |= 1 << 29; 3595 } 3596 } 3597 3598 /* 3599 * Set GPHY Power Down Override to leave GPHY 3600 * powered up in D0 uninitialized. 3601 */ 3602 if (BGE_IS_5705_PLUS(sc) && 3603 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 3604 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3605 3606 /* Issue global reset */ 3607 write_op(sc, BGE_MISC_CFG, reset); 3608 3609 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3610 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3611 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3612 val | BGE_VCPU_STATUS_DRV_RESET); 3613 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3614 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3615 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3616 } 3617 3618 DELAY(1000); 3619 3620 /* XXX: Broadcom Linux driver. */ 3621 if (sc->bge_flags & BGE_FLAG_PCIE) { 3622 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3623 DELAY(500000); /* wait for link training to complete */ 3624 val = pci_read_config(dev, 0xC4, 4); 3625 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3626 } 3627 devctl = pci_read_config(dev, 3628 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3629 /* Clear enable no snoop and disable relaxed ordering. */ 3630 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3631 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3632 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3633 devctl, 2); 3634 /* Clear error status. */ 3635 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3636 PCIM_EXP_STA_CORRECTABLE_ERROR | 3637 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3638 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3639 } 3640 3641 /* Reset some of the PCI state that got zapped by reset. */ 3642 pci_write_config(dev, BGE_PCI_MISC_CTL, 3643 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3644 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3645 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3646 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3647 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3648 /* 3649 * Disable PCI-X relaxed ordering to ensure status block update 3650 * comes first then packet buffer DMA. Otherwise driver may 3651 * read stale status block. 3652 */ 3653 if (sc->bge_flags & BGE_FLAG_PCIX) { 3654 devctl = pci_read_config(dev, 3655 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3656 devctl &= ~PCIXM_COMMAND_ERO; 3657 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3658 devctl &= ~PCIXM_COMMAND_MAX_READ; 3659 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3660 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3661 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3662 PCIXM_COMMAND_MAX_READ); 3663 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3664 } 3665 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3666 devctl, 2); 3667 } 3668 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 3669 if (BGE_IS_5714_FAMILY(sc)) { 3670 /* This chip disables MSI on reset. */ 3671 if (sc->bge_flags & BGE_FLAG_MSI) { 3672 val = pci_read_config(dev, 3673 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3674 pci_write_config(dev, 3675 sc->bge_msicap + PCIR_MSI_CTRL, 3676 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3677 val = CSR_READ_4(sc, BGE_MSI_MODE); 3678 CSR_WRITE_4(sc, BGE_MSI_MODE, 3679 val | BGE_MSIMODE_ENABLE); 3680 } 3681 val = CSR_READ_4(sc, BGE_MARB_MODE); 3682 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3683 } else 3684 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3685 3686 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3687 for (i = 0; i < BGE_TIMEOUT; i++) { 3688 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3689 if (val & BGE_VCPU_STATUS_INIT_DONE) 3690 break; 3691 DELAY(100); 3692 } 3693 if (i == BGE_TIMEOUT) { 3694 device_printf(dev, "reset timed out\n"); 3695 return (1); 3696 } 3697 } else { 3698 /* 3699 * Poll until we see the 1's complement of the magic number. 3700 * This indicates that the firmware initialization is complete. 3701 * We expect this to fail if no chip containing the Ethernet 3702 * address is fitted though. 3703 */ 3704 for (i = 0; i < BGE_TIMEOUT; i++) { 3705 DELAY(10); 3706 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 3707 if (val == ~BGE_SRAM_FW_MB_MAGIC) 3708 break; 3709 } 3710 3711 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3712 device_printf(dev, 3713 "firmware handshake timed out, found 0x%08x\n", 3714 val); 3715 /* BCM57765 A0 needs additional time before accessing. */ 3716 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 3717 DELAY(10 * 1000); /* XXX */ 3718 } 3719 3720 /* 3721 * XXX Wait for the value of the PCISTATE register to 3722 * return to its original pre-reset state. This is a 3723 * fairly good indicator of reset completion. If we don't 3724 * wait for the reset to fully complete, trying to read 3725 * from the device's non-PCI registers may yield garbage 3726 * results. 3727 */ 3728 for (i = 0; i < BGE_TIMEOUT; i++) { 3729 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3730 break; 3731 DELAY(10); 3732 } 3733 3734 /* Fix up byte swapping. */ 3735 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 3736 3737 /* Tell the ASF firmware we are up */ 3738 if (sc->bge_asf_mode & ASF_STACKUP) 3739 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3740 3741 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3742 3743 /* 3744 * The 5704 in TBI mode apparently needs some special 3745 * adjustment to insure the SERDES drive level is set 3746 * to 1.2V. 3747 */ 3748 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3749 sc->bge_flags & BGE_FLAG_TBI) { 3750 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3751 val = (val & ~0xFFF) | 0x880; 3752 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3753 } 3754 3755 /* XXX: Broadcom Linux driver. */ 3756 if (sc->bge_flags & BGE_FLAG_PCIE && 3757 !BGE_IS_5717_PLUS(sc) && 3758 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3759 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3760 /* Enable Data FIFO protection. */ 3761 val = CSR_READ_4(sc, 0x7C00); 3762 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3763 } 3764 DELAY(10000); 3765 3766 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 3767 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 3768 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 3769 3770 return (0); 3771 } 3772 3773 static __inline void 3774 bge_rxreuse_std(struct bge_softc *sc, int i) 3775 { 3776 struct bge_rx_bd *r; 3777 3778 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3779 r->bge_flags = BGE_RXBDFLAG_END; 3780 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3781 r->bge_idx = i; 3782 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3783 } 3784 3785 static __inline void 3786 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3787 { 3788 struct bge_extrx_bd *r; 3789 3790 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3791 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3792 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3793 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3794 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3795 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3796 r->bge_idx = i; 3797 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3798 } 3799 3800 /* 3801 * Frame reception handling. This is called if there's a frame 3802 * on the receive return list. 3803 * 3804 * Note: we have to be able to handle two possibilities here: 3805 * 1) the frame is from the jumbo receive ring 3806 * 2) the frame is from the standard receive ring 3807 */ 3808 3809 static int 3810 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3811 { 3812 struct ifnet *ifp; 3813 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3814 uint16_t rx_cons; 3815 3816 rx_cons = sc->bge_rx_saved_considx; 3817 3818 /* Nothing to do. */ 3819 if (rx_cons == rx_prod) 3820 return (rx_npkts); 3821 3822 ifp = sc->bge_ifp; 3823 3824 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3825 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3826 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3827 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3828 if (BGE_IS_JUMBO_CAPABLE(sc) && 3829 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3830 (MCLBYTES - ETHER_ALIGN)) 3831 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3832 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3833 3834 while (rx_cons != rx_prod) { 3835 struct bge_rx_bd *cur_rx; 3836 uint32_t rxidx; 3837 struct mbuf *m = NULL; 3838 uint16_t vlan_tag = 0; 3839 int have_tag = 0; 3840 3841 #ifdef DEVICE_POLLING 3842 if (ifp->if_capenable & IFCAP_POLLING) { 3843 if (sc->rxcycles <= 0) 3844 break; 3845 sc->rxcycles--; 3846 } 3847 #endif 3848 3849 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3850 3851 rxidx = cur_rx->bge_idx; 3852 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3853 3854 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3855 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3856 have_tag = 1; 3857 vlan_tag = cur_rx->bge_vlan_tag; 3858 } 3859 3860 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3861 jumbocnt++; 3862 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3863 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3864 bge_rxreuse_jumbo(sc, rxidx); 3865 continue; 3866 } 3867 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3868 bge_rxreuse_jumbo(sc, rxidx); 3869 ifp->if_iqdrops++; 3870 continue; 3871 } 3872 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3873 } else { 3874 stdcnt++; 3875 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3876 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3877 bge_rxreuse_std(sc, rxidx); 3878 continue; 3879 } 3880 if (bge_newbuf_std(sc, rxidx) != 0) { 3881 bge_rxreuse_std(sc, rxidx); 3882 ifp->if_iqdrops++; 3883 continue; 3884 } 3885 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3886 } 3887 3888 ifp->if_ipackets++; 3889 #ifndef __NO_STRICT_ALIGNMENT 3890 /* 3891 * For architectures with strict alignment we must make sure 3892 * the payload is aligned. 3893 */ 3894 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3895 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3896 cur_rx->bge_len); 3897 m->m_data += ETHER_ALIGN; 3898 } 3899 #endif 3900 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3901 m->m_pkthdr.rcvif = ifp; 3902 3903 if (ifp->if_capenable & IFCAP_RXCSUM) 3904 bge_rxcsum(sc, cur_rx, m); 3905 3906 /* 3907 * If we received a packet with a vlan tag, 3908 * attach that information to the packet. 3909 */ 3910 if (have_tag) { 3911 m->m_pkthdr.ether_vtag = vlan_tag; 3912 m->m_flags |= M_VLANTAG; 3913 } 3914 3915 if (holdlck != 0) { 3916 BGE_UNLOCK(sc); 3917 (*ifp->if_input)(ifp, m); 3918 BGE_LOCK(sc); 3919 } else 3920 (*ifp->if_input)(ifp, m); 3921 rx_npkts++; 3922 3923 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3924 return (rx_npkts); 3925 } 3926 3927 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3928 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3929 if (stdcnt > 0) 3930 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3931 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3932 3933 if (jumbocnt > 0) 3934 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3935 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3936 3937 sc->bge_rx_saved_considx = rx_cons; 3938 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3939 if (stdcnt) 3940 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 3941 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 3942 if (jumbocnt) 3943 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 3944 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 3945 #ifdef notyet 3946 /* 3947 * This register wraps very quickly under heavy packet drops. 3948 * If you need correct statistics, you can enable this check. 3949 */ 3950 if (BGE_IS_5705_PLUS(sc)) 3951 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3952 #endif 3953 return (rx_npkts); 3954 } 3955 3956 static void 3957 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 3958 { 3959 3960 if (BGE_IS_5717_PLUS(sc)) { 3961 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 3962 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3963 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3964 if ((cur_rx->bge_error_flag & 3965 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 3966 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3967 } 3968 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 3969 m->m_pkthdr.csum_data = 3970 cur_rx->bge_tcp_udp_csum; 3971 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3972 CSUM_PSEUDO_HDR; 3973 } 3974 } 3975 } else { 3976 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3977 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3978 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3979 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3980 } 3981 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3982 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3983 m->m_pkthdr.csum_data = 3984 cur_rx->bge_tcp_udp_csum; 3985 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3986 CSUM_PSEUDO_HDR; 3987 } 3988 } 3989 } 3990 3991 static void 3992 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3993 { 3994 struct bge_tx_bd *cur_tx; 3995 struct ifnet *ifp; 3996 3997 BGE_LOCK_ASSERT(sc); 3998 3999 /* Nothing to do. */ 4000 if (sc->bge_tx_saved_considx == tx_cons) 4001 return; 4002 4003 ifp = sc->bge_ifp; 4004 4005 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4006 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4007 /* 4008 * Go through our tx ring and free mbufs for those 4009 * frames that have been sent. 4010 */ 4011 while (sc->bge_tx_saved_considx != tx_cons) { 4012 uint32_t idx; 4013 4014 idx = sc->bge_tx_saved_considx; 4015 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4016 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4017 ifp->if_opackets++; 4018 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4019 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4020 sc->bge_cdata.bge_tx_dmamap[idx], 4021 BUS_DMASYNC_POSTWRITE); 4022 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4023 sc->bge_cdata.bge_tx_dmamap[idx]); 4024 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4025 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4026 } 4027 sc->bge_txcnt--; 4028 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4029 } 4030 4031 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4032 if (sc->bge_txcnt == 0) 4033 sc->bge_timer = 0; 4034 } 4035 4036 #ifdef DEVICE_POLLING 4037 static int 4038 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4039 { 4040 struct bge_softc *sc = ifp->if_softc; 4041 uint16_t rx_prod, tx_cons; 4042 uint32_t statusword; 4043 int rx_npkts = 0; 4044 4045 BGE_LOCK(sc); 4046 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4047 BGE_UNLOCK(sc); 4048 return (rx_npkts); 4049 } 4050 4051 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4052 sc->bge_cdata.bge_status_map, 4053 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4054 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4055 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4056 4057 statusword = sc->bge_ldata.bge_status_block->bge_status; 4058 sc->bge_ldata.bge_status_block->bge_status = 0; 4059 4060 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4061 sc->bge_cdata.bge_status_map, 4062 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4063 4064 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4065 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4066 sc->bge_link_evt++; 4067 4068 if (cmd == POLL_AND_CHECK_STATUS) 4069 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4070 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4071 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4072 bge_link_upd(sc); 4073 4074 sc->rxcycles = count; 4075 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4076 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4077 BGE_UNLOCK(sc); 4078 return (rx_npkts); 4079 } 4080 bge_txeof(sc, tx_cons); 4081 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4082 bge_start_locked(ifp); 4083 4084 BGE_UNLOCK(sc); 4085 return (rx_npkts); 4086 } 4087 #endif /* DEVICE_POLLING */ 4088 4089 static int 4090 bge_msi_intr(void *arg) 4091 { 4092 struct bge_softc *sc; 4093 4094 sc = (struct bge_softc *)arg; 4095 /* 4096 * This interrupt is not shared and controller already 4097 * disabled further interrupt. 4098 */ 4099 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4100 return (FILTER_HANDLED); 4101 } 4102 4103 static void 4104 bge_intr_task(void *arg, int pending) 4105 { 4106 struct bge_softc *sc; 4107 struct ifnet *ifp; 4108 uint32_t status, status_tag; 4109 uint16_t rx_prod, tx_cons; 4110 4111 sc = (struct bge_softc *)arg; 4112 ifp = sc->bge_ifp; 4113 4114 BGE_LOCK(sc); 4115 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4116 BGE_UNLOCK(sc); 4117 return; 4118 } 4119 4120 /* Get updated status block. */ 4121 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4122 sc->bge_cdata.bge_status_map, 4123 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4124 4125 /* Save producer/consumer indexess. */ 4126 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4127 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4128 status = sc->bge_ldata.bge_status_block->bge_status; 4129 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4130 sc->bge_ldata.bge_status_block->bge_status = 0; 4131 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4132 sc->bge_cdata.bge_status_map, 4133 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4134 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4135 status_tag = 0; 4136 4137 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4138 bge_link_upd(sc); 4139 4140 /* Let controller work. */ 4141 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4142 4143 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4144 sc->bge_rx_saved_considx != rx_prod) { 4145 /* Check RX return ring producer/consumer. */ 4146 BGE_UNLOCK(sc); 4147 bge_rxeof(sc, rx_prod, 0); 4148 BGE_LOCK(sc); 4149 } 4150 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4151 /* Check TX ring producer/consumer. */ 4152 bge_txeof(sc, tx_cons); 4153 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4154 bge_start_locked(ifp); 4155 } 4156 BGE_UNLOCK(sc); 4157 } 4158 4159 static void 4160 bge_intr(void *xsc) 4161 { 4162 struct bge_softc *sc; 4163 struct ifnet *ifp; 4164 uint32_t statusword; 4165 uint16_t rx_prod, tx_cons; 4166 4167 sc = xsc; 4168 4169 BGE_LOCK(sc); 4170 4171 ifp = sc->bge_ifp; 4172 4173 #ifdef DEVICE_POLLING 4174 if (ifp->if_capenable & IFCAP_POLLING) { 4175 BGE_UNLOCK(sc); 4176 return; 4177 } 4178 #endif 4179 4180 /* 4181 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4182 * disable interrupts by writing nonzero like we used to, since with 4183 * our current organization this just gives complications and 4184 * pessimizations for re-enabling interrupts. We used to have races 4185 * instead of the necessary complications. Disabling interrupts 4186 * would just reduce the chance of a status update while we are 4187 * running (by switching to the interrupt-mode coalescence 4188 * parameters), but this chance is already very low so it is more 4189 * efficient to get another interrupt than prevent it. 4190 * 4191 * We do the ack first to ensure another interrupt if there is a 4192 * status update after the ack. We don't check for the status 4193 * changing later because it is more efficient to get another 4194 * interrupt than prevent it, not quite as above (not checking is 4195 * a smaller optimization than not toggling the interrupt enable, 4196 * since checking doesn't involve PCI accesses and toggling require 4197 * the status check). So toggling would probably be a pessimization 4198 * even with MSI. It would only be needed for using a task queue. 4199 */ 4200 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4201 4202 /* 4203 * Do the mandatory PCI flush as well as get the link status. 4204 */ 4205 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4206 4207 /* Make sure the descriptor ring indexes are coherent. */ 4208 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4209 sc->bge_cdata.bge_status_map, 4210 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4211 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4212 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4213 sc->bge_ldata.bge_status_block->bge_status = 0; 4214 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4215 sc->bge_cdata.bge_status_map, 4216 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4217 4218 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4219 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4220 statusword || sc->bge_link_evt) 4221 bge_link_upd(sc); 4222 4223 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4224 /* Check RX return ring producer/consumer. */ 4225 bge_rxeof(sc, rx_prod, 1); 4226 } 4227 4228 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4229 /* Check TX ring producer/consumer. */ 4230 bge_txeof(sc, tx_cons); 4231 } 4232 4233 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4234 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4235 bge_start_locked(ifp); 4236 4237 BGE_UNLOCK(sc); 4238 } 4239 4240 static void 4241 bge_asf_driver_up(struct bge_softc *sc) 4242 { 4243 if (sc->bge_asf_mode & ASF_STACKUP) { 4244 /* Send ASF heartbeat aprox. every 2s */ 4245 if (sc->bge_asf_count) 4246 sc->bge_asf_count --; 4247 else { 4248 sc->bge_asf_count = 2; 4249 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4250 BGE_FW_CMD_DRV_ALIVE); 4251 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4252 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4253 BGE_FW_HB_TIMEOUT_SEC); 4254 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4255 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4256 BGE_RX_CPU_DRV_EVENT); 4257 } 4258 } 4259 } 4260 4261 static void 4262 bge_tick(void *xsc) 4263 { 4264 struct bge_softc *sc = xsc; 4265 struct mii_data *mii = NULL; 4266 4267 BGE_LOCK_ASSERT(sc); 4268 4269 /* Synchronize with possible callout reset/stop. */ 4270 if (callout_pending(&sc->bge_stat_ch) || 4271 !callout_active(&sc->bge_stat_ch)) 4272 return; 4273 4274 if (BGE_IS_5705_PLUS(sc)) 4275 bge_stats_update_regs(sc); 4276 else 4277 bge_stats_update(sc); 4278 4279 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4280 mii = device_get_softc(sc->bge_miibus); 4281 /* 4282 * Do not touch PHY if we have link up. This could break 4283 * IPMI/ASF mode or produce extra input errors 4284 * (extra errors was reported for bcm5701 & bcm5704). 4285 */ 4286 if (!sc->bge_link) 4287 mii_tick(mii); 4288 } else { 4289 /* 4290 * Since in TBI mode auto-polling can't be used we should poll 4291 * link status manually. Here we register pending link event 4292 * and trigger interrupt. 4293 */ 4294 #ifdef DEVICE_POLLING 4295 /* In polling mode we poll link state in bge_poll(). */ 4296 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4297 #endif 4298 { 4299 sc->bge_link_evt++; 4300 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4301 sc->bge_flags & BGE_FLAG_5788) 4302 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4303 else 4304 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4305 } 4306 } 4307 4308 bge_asf_driver_up(sc); 4309 bge_watchdog(sc); 4310 4311 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4312 } 4313 4314 static void 4315 bge_stats_update_regs(struct bge_softc *sc) 4316 { 4317 struct ifnet *ifp; 4318 struct bge_mac_stats *stats; 4319 4320 ifp = sc->bge_ifp; 4321 stats = &sc->bge_mac_stats; 4322 4323 stats->ifHCOutOctets += 4324 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4325 stats->etherStatsCollisions += 4326 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4327 stats->outXonSent += 4328 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4329 stats->outXoffSent += 4330 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4331 stats->dot3StatsInternalMacTransmitErrors += 4332 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4333 stats->dot3StatsSingleCollisionFrames += 4334 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4335 stats->dot3StatsMultipleCollisionFrames += 4336 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4337 stats->dot3StatsDeferredTransmissions += 4338 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4339 stats->dot3StatsExcessiveCollisions += 4340 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4341 stats->dot3StatsLateCollisions += 4342 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4343 stats->ifHCOutUcastPkts += 4344 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4345 stats->ifHCOutMulticastPkts += 4346 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4347 stats->ifHCOutBroadcastPkts += 4348 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4349 4350 stats->ifHCInOctets += 4351 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4352 stats->etherStatsFragments += 4353 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4354 stats->ifHCInUcastPkts += 4355 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4356 stats->ifHCInMulticastPkts += 4357 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4358 stats->ifHCInBroadcastPkts += 4359 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4360 stats->dot3StatsFCSErrors += 4361 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4362 stats->dot3StatsAlignmentErrors += 4363 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4364 stats->xonPauseFramesReceived += 4365 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4366 stats->xoffPauseFramesReceived += 4367 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4368 stats->macControlFramesReceived += 4369 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4370 stats->xoffStateEntered += 4371 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4372 stats->dot3StatsFramesTooLong += 4373 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4374 stats->etherStatsJabbers += 4375 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4376 stats->etherStatsUndersizePkts += 4377 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4378 4379 stats->FramesDroppedDueToFilters += 4380 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4381 stats->DmaWriteQueueFull += 4382 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4383 stats->DmaWriteHighPriQueueFull += 4384 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4385 stats->NoMoreRxBDs += 4386 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4387 /* 4388 * XXX 4389 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4390 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4391 * includes number of unwanted multicast frames. This comes 4392 * from silicon bug and known workaround to get rough(not 4393 * exact) counter is to enable interrupt on MBUF low water 4394 * attention. This can be accomplished by setting 4395 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4396 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4397 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4398 * However that change would generate more interrupts and 4399 * there are still possibilities of losing multiple frames 4400 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4401 * Given that the workaround still would not get correct 4402 * counter I don't think it's worth to implement it. So 4403 * ignore reading the counter on controllers that have the 4404 * silicon bug. 4405 */ 4406 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4407 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4408 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4409 stats->InputDiscards += 4410 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4411 stats->InputErrors += 4412 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4413 stats->RecvThresholdHit += 4414 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4415 4416 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4417 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4418 stats->InputErrors); 4419 } 4420 4421 static void 4422 bge_stats_clear_regs(struct bge_softc *sc) 4423 { 4424 4425 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4426 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4427 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4428 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4429 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4430 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4431 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4432 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4433 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4434 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4435 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4436 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4437 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4438 4439 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4440 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4441 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4442 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4443 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4444 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4445 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4446 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4447 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4448 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4449 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4450 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4451 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4452 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4453 4454 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4455 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4456 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4457 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4458 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4459 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4460 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4461 } 4462 4463 static void 4464 bge_stats_update(struct bge_softc *sc) 4465 { 4466 struct ifnet *ifp; 4467 bus_size_t stats; 4468 uint32_t cnt; /* current register value */ 4469 4470 ifp = sc->bge_ifp; 4471 4472 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4473 4474 #define READ_STAT(sc, stats, stat) \ 4475 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4476 4477 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4478 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4479 sc->bge_tx_collisions = cnt; 4480 4481 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4482 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4483 sc->bge_rx_nobds = cnt; 4484 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 4485 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 4486 sc->bge_rx_inerrs = cnt; 4487 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 4488 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 4489 sc->bge_rx_discards = cnt; 4490 4491 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 4492 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 4493 sc->bge_tx_discards = cnt; 4494 4495 #undef READ_STAT 4496 } 4497 4498 /* 4499 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 4500 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 4501 * but when such padded frames employ the bge IP/TCP checksum offload, 4502 * the hardware checksum assist gives incorrect results (possibly 4503 * from incorporating its own padding into the UDP/TCP checksum; who knows). 4504 * If we pad such runts with zeros, the onboard checksum comes out correct. 4505 */ 4506 static __inline int 4507 bge_cksum_pad(struct mbuf *m) 4508 { 4509 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 4510 struct mbuf *last; 4511 4512 /* If there's only the packet-header and we can pad there, use it. */ 4513 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 4514 M_TRAILINGSPACE(m) >= padlen) { 4515 last = m; 4516 } else { 4517 /* 4518 * Walk packet chain to find last mbuf. We will either 4519 * pad there, or append a new mbuf and pad it. 4520 */ 4521 for (last = m; last->m_next != NULL; last = last->m_next); 4522 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 4523 /* Allocate new empty mbuf, pad it. Compact later. */ 4524 struct mbuf *n; 4525 4526 MGET(n, M_DONTWAIT, MT_DATA); 4527 if (n == NULL) 4528 return (ENOBUFS); 4529 n->m_len = 0; 4530 last->m_next = n; 4531 last = n; 4532 } 4533 } 4534 4535 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 4536 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 4537 last->m_len += padlen; 4538 m->m_pkthdr.len += padlen; 4539 4540 return (0); 4541 } 4542 4543 static struct mbuf * 4544 bge_check_short_dma(struct mbuf *m) 4545 { 4546 struct mbuf *n; 4547 int found; 4548 4549 /* 4550 * If device receive two back-to-back send BDs with less than 4551 * or equal to 8 total bytes then the device may hang. The two 4552 * back-to-back send BDs must in the same frame for this failure 4553 * to occur. Scan mbuf chains and see whether two back-to-back 4554 * send BDs are there. If this is the case, allocate new mbuf 4555 * and copy the frame to workaround the silicon bug. 4556 */ 4557 for (n = m, found = 0; n != NULL; n = n->m_next) { 4558 if (n->m_len < 8) { 4559 found++; 4560 if (found > 1) 4561 break; 4562 continue; 4563 } 4564 found = 0; 4565 } 4566 4567 if (found > 1) { 4568 n = m_defrag(m, M_DONTWAIT); 4569 if (n == NULL) 4570 m_freem(m); 4571 } else 4572 n = m; 4573 return (n); 4574 } 4575 4576 static struct mbuf * 4577 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 4578 uint16_t *flags) 4579 { 4580 struct ip *ip; 4581 struct tcphdr *tcp; 4582 struct mbuf *n; 4583 uint16_t hlen; 4584 uint32_t poff; 4585 4586 if (M_WRITABLE(m) == 0) { 4587 /* Get a writable copy. */ 4588 n = m_dup(m, M_DONTWAIT); 4589 m_freem(m); 4590 if (n == NULL) 4591 return (NULL); 4592 m = n; 4593 } 4594 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 4595 if (m == NULL) 4596 return (NULL); 4597 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4598 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 4599 m = m_pullup(m, poff + sizeof(struct tcphdr)); 4600 if (m == NULL) 4601 return (NULL); 4602 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4603 m = m_pullup(m, poff + (tcp->th_off << 2)); 4604 if (m == NULL) 4605 return (NULL); 4606 /* 4607 * It seems controller doesn't modify IP length and TCP pseudo 4608 * checksum. These checksum computed by upper stack should be 0. 4609 */ 4610 *mss = m->m_pkthdr.tso_segsz; 4611 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 4612 ip->ip_sum = 0; 4613 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 4614 /* Clear pseudo checksum computed by TCP stack. */ 4615 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 4616 tcp->th_sum = 0; 4617 /* 4618 * Broadcom controllers uses different descriptor format for 4619 * TSO depending on ASIC revision. Due to TSO-capable firmware 4620 * license issue and lower performance of firmware based TSO 4621 * we only support hardware based TSO. 4622 */ 4623 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 4624 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 4625 if (sc->bge_flags & BGE_FLAG_TSO3) { 4626 /* 4627 * For BCM5717 and newer controllers, hardware based TSO 4628 * uses the 14 lower bits of the bge_mss field to store the 4629 * MSS and the upper 2 bits to store the lowest 2 bits of 4630 * the IP/TCP header length. The upper 6 bits of the header 4631 * length are stored in the bge_flags[14:10,4] field. Jumbo 4632 * frames are supported. 4633 */ 4634 *mss |= ((hlen & 0x3) << 14); 4635 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 4636 } else { 4637 /* 4638 * For BCM5755 and newer controllers, hardware based TSO uses 4639 * the lower 11 bits to store the MSS and the upper 5 bits to 4640 * store the IP/TCP header length. Jumbo frames are not 4641 * supported. 4642 */ 4643 *mss |= (hlen << 11); 4644 } 4645 return (m); 4646 } 4647 4648 /* 4649 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 4650 * pointers to descriptors. 4651 */ 4652 static int 4653 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 4654 { 4655 bus_dma_segment_t segs[BGE_NSEG_NEW]; 4656 bus_dmamap_t map; 4657 struct bge_tx_bd *d; 4658 struct mbuf *m = *m_head; 4659 uint32_t idx = *txidx; 4660 uint16_t csum_flags, mss, vlan_tag; 4661 int nsegs, i, error; 4662 4663 csum_flags = 0; 4664 mss = 0; 4665 vlan_tag = 0; 4666 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 4667 m->m_next != NULL) { 4668 *m_head = bge_check_short_dma(m); 4669 if (*m_head == NULL) 4670 return (ENOBUFS); 4671 m = *m_head; 4672 } 4673 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 4674 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 4675 if (*m_head == NULL) 4676 return (ENOBUFS); 4677 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 4678 BGE_TXBDFLAG_CPU_POST_DMA; 4679 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 4680 if (m->m_pkthdr.csum_flags & CSUM_IP) 4681 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 4682 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 4683 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 4684 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 4685 (error = bge_cksum_pad(m)) != 0) { 4686 m_freem(m); 4687 *m_head = NULL; 4688 return (error); 4689 } 4690 } 4691 if (m->m_flags & M_LASTFRAG) 4692 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 4693 else if (m->m_flags & M_FRAG) 4694 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 4695 } 4696 4697 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 4698 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 4699 m->m_pkthdr.len > ETHER_MAX_LEN) 4700 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 4701 if (sc->bge_forced_collapse > 0 && 4702 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 4703 /* 4704 * Forcedly collapse mbuf chains to overcome hardware 4705 * limitation which only support a single outstanding 4706 * DMA read operation. 4707 */ 4708 if (sc->bge_forced_collapse == 1) 4709 m = m_defrag(m, M_DONTWAIT); 4710 else 4711 m = m_collapse(m, M_DONTWAIT, 4712 sc->bge_forced_collapse); 4713 if (m == NULL) 4714 m = *m_head; 4715 *m_head = m; 4716 } 4717 } 4718 4719 map = sc->bge_cdata.bge_tx_dmamap[idx]; 4720 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4721 &nsegs, BUS_DMA_NOWAIT); 4722 if (error == EFBIG) { 4723 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4724 if (m == NULL) { 4725 m_freem(*m_head); 4726 *m_head = NULL; 4727 return (ENOBUFS); 4728 } 4729 *m_head = m; 4730 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 4731 m, segs, &nsegs, BUS_DMA_NOWAIT); 4732 if (error) { 4733 m_freem(m); 4734 *m_head = NULL; 4735 return (error); 4736 } 4737 } else if (error != 0) 4738 return (error); 4739 4740 /* Check if we have enough free send BDs. */ 4741 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 4742 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 4743 return (ENOBUFS); 4744 } 4745 4746 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4747 4748 if (m->m_flags & M_VLANTAG) { 4749 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4750 vlan_tag = m->m_pkthdr.ether_vtag; 4751 } 4752 for (i = 0; ; i++) { 4753 d = &sc->bge_ldata.bge_tx_ring[idx]; 4754 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 4755 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 4756 d->bge_len = segs[i].ds_len; 4757 d->bge_flags = csum_flags; 4758 d->bge_vlan_tag = vlan_tag; 4759 d->bge_mss = mss; 4760 if (i == nsegs - 1) 4761 break; 4762 BGE_INC(idx, BGE_TX_RING_CNT); 4763 } 4764 4765 /* Mark the last segment as end of packet... */ 4766 d->bge_flags |= BGE_TXBDFLAG_END; 4767 4768 /* 4769 * Insure that the map for this transmission 4770 * is placed at the array index of the last descriptor 4771 * in this chain. 4772 */ 4773 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4774 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4775 sc->bge_cdata.bge_tx_chain[idx] = m; 4776 sc->bge_txcnt += nsegs; 4777 4778 BGE_INC(idx, BGE_TX_RING_CNT); 4779 *txidx = idx; 4780 4781 return (0); 4782 } 4783 4784 /* 4785 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4786 * to the mbuf data regions directly in the transmit descriptors. 4787 */ 4788 static void 4789 bge_start_locked(struct ifnet *ifp) 4790 { 4791 struct bge_softc *sc; 4792 struct mbuf *m_head; 4793 uint32_t prodidx; 4794 int count; 4795 4796 sc = ifp->if_softc; 4797 BGE_LOCK_ASSERT(sc); 4798 4799 if (!sc->bge_link || 4800 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4801 IFF_DRV_RUNNING) 4802 return; 4803 4804 prodidx = sc->bge_tx_prodidx; 4805 4806 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4807 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4808 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4809 break; 4810 } 4811 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4812 if (m_head == NULL) 4813 break; 4814 4815 /* 4816 * XXX 4817 * The code inside the if() block is never reached since we 4818 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4819 * requests to checksum TCP/UDP in a fragmented packet. 4820 * 4821 * XXX 4822 * safety overkill. If this is a fragmented packet chain 4823 * with delayed TCP/UDP checksums, then only encapsulate 4824 * it if we have enough descriptors to handle the entire 4825 * chain at once. 4826 * (paranoia -- may not actually be needed) 4827 */ 4828 if (m_head->m_flags & M_FIRSTFRAG && 4829 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4830 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4831 m_head->m_pkthdr.csum_data + 16) { 4832 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4833 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4834 break; 4835 } 4836 } 4837 4838 /* 4839 * Pack the data into the transmit ring. If we 4840 * don't have room, set the OACTIVE flag and wait 4841 * for the NIC to drain the ring. 4842 */ 4843 if (bge_encap(sc, &m_head, &prodidx)) { 4844 if (m_head == NULL) 4845 break; 4846 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4847 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4848 break; 4849 } 4850 ++count; 4851 4852 /* 4853 * If there's a BPF listener, bounce a copy of this frame 4854 * to him. 4855 */ 4856 #ifdef ETHER_BPF_MTAP 4857 ETHER_BPF_MTAP(ifp, m_head); 4858 #else 4859 BPF_MTAP(ifp, m_head); 4860 #endif 4861 } 4862 4863 if (count > 0) { 4864 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4865 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4866 /* Transmit. */ 4867 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4868 /* 5700 b2 errata */ 4869 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4870 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4871 4872 sc->bge_tx_prodidx = prodidx; 4873 4874 /* 4875 * Set a timeout in case the chip goes out to lunch. 4876 */ 4877 sc->bge_timer = 5; 4878 } 4879 } 4880 4881 /* 4882 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4883 * to the mbuf data regions directly in the transmit descriptors. 4884 */ 4885 static void 4886 bge_start(struct ifnet *ifp) 4887 { 4888 struct bge_softc *sc; 4889 4890 sc = ifp->if_softc; 4891 BGE_LOCK(sc); 4892 bge_start_locked(ifp); 4893 BGE_UNLOCK(sc); 4894 } 4895 4896 static void 4897 bge_init_locked(struct bge_softc *sc) 4898 { 4899 struct ifnet *ifp; 4900 uint16_t *m; 4901 uint32_t mode; 4902 4903 BGE_LOCK_ASSERT(sc); 4904 4905 ifp = sc->bge_ifp; 4906 4907 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4908 return; 4909 4910 /* Cancel pending I/O and flush buffers. */ 4911 bge_stop(sc); 4912 4913 bge_stop_fw(sc); 4914 bge_sig_pre_reset(sc, BGE_RESET_START); 4915 bge_reset(sc); 4916 bge_sig_legacy(sc, BGE_RESET_START); 4917 bge_sig_post_reset(sc, BGE_RESET_START); 4918 4919 bge_chipinit(sc); 4920 4921 /* 4922 * Init the various state machines, ring 4923 * control blocks and firmware. 4924 */ 4925 if (bge_blockinit(sc)) { 4926 device_printf(sc->bge_dev, "initialization failure\n"); 4927 return; 4928 } 4929 4930 ifp = sc->bge_ifp; 4931 4932 /* Specify MTU. */ 4933 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4934 ETHER_HDR_LEN + ETHER_CRC_LEN + 4935 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4936 4937 /* Load our MAC address. */ 4938 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4939 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4940 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4941 4942 /* Program promiscuous mode. */ 4943 bge_setpromisc(sc); 4944 4945 /* Program multicast filter. */ 4946 bge_setmulti(sc); 4947 4948 /* Program VLAN tag stripping. */ 4949 bge_setvlan(sc); 4950 4951 /* Override UDP checksum offloading. */ 4952 if (sc->bge_forced_udpcsum == 0) 4953 sc->bge_csum_features &= ~CSUM_UDP; 4954 else 4955 sc->bge_csum_features |= CSUM_UDP; 4956 if (ifp->if_capabilities & IFCAP_TXCSUM && 4957 ifp->if_capenable & IFCAP_TXCSUM) { 4958 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 4959 ifp->if_hwassist |= sc->bge_csum_features; 4960 } 4961 4962 /* Init RX ring. */ 4963 if (bge_init_rx_ring_std(sc) != 0) { 4964 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4965 bge_stop(sc); 4966 return; 4967 } 4968 4969 /* 4970 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4971 * memory to insure that the chip has in fact read the first 4972 * entry of the ring. 4973 */ 4974 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4975 uint32_t v, i; 4976 for (i = 0; i < 10; i++) { 4977 DELAY(20); 4978 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4979 if (v == (MCLBYTES - ETHER_ALIGN)) 4980 break; 4981 } 4982 if (i == 10) 4983 device_printf (sc->bge_dev, 4984 "5705 A0 chip failed to load RX ring\n"); 4985 } 4986 4987 /* Init jumbo RX ring. */ 4988 if (BGE_IS_JUMBO_CAPABLE(sc) && 4989 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4990 (MCLBYTES - ETHER_ALIGN)) { 4991 if (bge_init_rx_ring_jumbo(sc) != 0) { 4992 device_printf(sc->bge_dev, 4993 "no memory for jumbo Rx buffers.\n"); 4994 bge_stop(sc); 4995 return; 4996 } 4997 } 4998 4999 /* Init our RX return ring index. */ 5000 sc->bge_rx_saved_considx = 0; 5001 5002 /* Init our RX/TX stat counters. */ 5003 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5004 5005 /* Init TX ring. */ 5006 bge_init_tx_ring(sc); 5007 5008 /* Enable TX MAC state machine lockup fix. */ 5009 mode = CSR_READ_4(sc, BGE_TX_MODE); 5010 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5011 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5012 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 5013 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5014 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5015 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5016 } 5017 /* Turn on transmitter. */ 5018 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5019 5020 /* Turn on receiver. */ 5021 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5022 5023 /* 5024 * Set the number of good frames to receive after RX MBUF 5025 * Low Watermark has been reached. After the RX MAC receives 5026 * this number of frames, it will drop subsequent incoming 5027 * frames until the MBUF High Watermark is reached. 5028 */ 5029 if (sc->bge_asicrev == BGE_ASICREV_BCM57765) 5030 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5031 else 5032 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5033 5034 /* Clear MAC statistics. */ 5035 if (BGE_IS_5705_PLUS(sc)) 5036 bge_stats_clear_regs(sc); 5037 5038 /* Tell firmware we're alive. */ 5039 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5040 5041 #ifdef DEVICE_POLLING 5042 /* Disable interrupts if we are polling. */ 5043 if (ifp->if_capenable & IFCAP_POLLING) { 5044 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5045 BGE_PCIMISCCTL_MASK_PCI_INTR); 5046 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5047 } else 5048 #endif 5049 5050 /* Enable host interrupts. */ 5051 { 5052 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5053 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5054 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5055 } 5056 5057 bge_ifmedia_upd_locked(ifp); 5058 5059 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5060 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5061 5062 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5063 } 5064 5065 static void 5066 bge_init(void *xsc) 5067 { 5068 struct bge_softc *sc = xsc; 5069 5070 BGE_LOCK(sc); 5071 bge_init_locked(sc); 5072 BGE_UNLOCK(sc); 5073 } 5074 5075 /* 5076 * Set media options. 5077 */ 5078 static int 5079 bge_ifmedia_upd(struct ifnet *ifp) 5080 { 5081 struct bge_softc *sc = ifp->if_softc; 5082 int res; 5083 5084 BGE_LOCK(sc); 5085 res = bge_ifmedia_upd_locked(ifp); 5086 BGE_UNLOCK(sc); 5087 5088 return (res); 5089 } 5090 5091 static int 5092 bge_ifmedia_upd_locked(struct ifnet *ifp) 5093 { 5094 struct bge_softc *sc = ifp->if_softc; 5095 struct mii_data *mii; 5096 struct mii_softc *miisc; 5097 struct ifmedia *ifm; 5098 5099 BGE_LOCK_ASSERT(sc); 5100 5101 ifm = &sc->bge_ifmedia; 5102 5103 /* If this is a 1000baseX NIC, enable the TBI port. */ 5104 if (sc->bge_flags & BGE_FLAG_TBI) { 5105 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5106 return (EINVAL); 5107 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5108 case IFM_AUTO: 5109 /* 5110 * The BCM5704 ASIC appears to have a special 5111 * mechanism for programming the autoneg 5112 * advertisement registers in TBI mode. 5113 */ 5114 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5115 uint32_t sgdig; 5116 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5117 if (sgdig & BGE_SGDIGSTS_DONE) { 5118 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5119 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5120 sgdig |= BGE_SGDIGCFG_AUTO | 5121 BGE_SGDIGCFG_PAUSE_CAP | 5122 BGE_SGDIGCFG_ASYM_PAUSE; 5123 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5124 sgdig | BGE_SGDIGCFG_SEND); 5125 DELAY(5); 5126 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5127 } 5128 } 5129 break; 5130 case IFM_1000_SX: 5131 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5132 BGE_CLRBIT(sc, BGE_MAC_MODE, 5133 BGE_MACMODE_HALF_DUPLEX); 5134 } else { 5135 BGE_SETBIT(sc, BGE_MAC_MODE, 5136 BGE_MACMODE_HALF_DUPLEX); 5137 } 5138 break; 5139 default: 5140 return (EINVAL); 5141 } 5142 return (0); 5143 } 5144 5145 sc->bge_link_evt++; 5146 mii = device_get_softc(sc->bge_miibus); 5147 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5148 PHY_RESET(miisc); 5149 mii_mediachg(mii); 5150 5151 /* 5152 * Force an interrupt so that we will call bge_link_upd 5153 * if needed and clear any pending link state attention. 5154 * Without this we are not getting any further interrupts 5155 * for link state changes and thus will not UP the link and 5156 * not be able to send in bge_start_locked. The only 5157 * way to get things working was to receive a packet and 5158 * get an RX intr. 5159 * bge_tick should help for fiber cards and we might not 5160 * need to do this here if BGE_FLAG_TBI is set but as 5161 * we poll for fiber anyway it should not harm. 5162 */ 5163 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5164 sc->bge_flags & BGE_FLAG_5788) 5165 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5166 else 5167 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5168 5169 return (0); 5170 } 5171 5172 /* 5173 * Report current media status. 5174 */ 5175 static void 5176 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5177 { 5178 struct bge_softc *sc = ifp->if_softc; 5179 struct mii_data *mii; 5180 5181 BGE_LOCK(sc); 5182 5183 if (sc->bge_flags & BGE_FLAG_TBI) { 5184 ifmr->ifm_status = IFM_AVALID; 5185 ifmr->ifm_active = IFM_ETHER; 5186 if (CSR_READ_4(sc, BGE_MAC_STS) & 5187 BGE_MACSTAT_TBI_PCS_SYNCHED) 5188 ifmr->ifm_status |= IFM_ACTIVE; 5189 else { 5190 ifmr->ifm_active |= IFM_NONE; 5191 BGE_UNLOCK(sc); 5192 return; 5193 } 5194 ifmr->ifm_active |= IFM_1000_SX; 5195 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5196 ifmr->ifm_active |= IFM_HDX; 5197 else 5198 ifmr->ifm_active |= IFM_FDX; 5199 BGE_UNLOCK(sc); 5200 return; 5201 } 5202 5203 mii = device_get_softc(sc->bge_miibus); 5204 mii_pollstat(mii); 5205 ifmr->ifm_active = mii->mii_media_active; 5206 ifmr->ifm_status = mii->mii_media_status; 5207 5208 BGE_UNLOCK(sc); 5209 } 5210 5211 static int 5212 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5213 { 5214 struct bge_softc *sc = ifp->if_softc; 5215 struct ifreq *ifr = (struct ifreq *) data; 5216 struct mii_data *mii; 5217 int flags, mask, error = 0; 5218 5219 switch (command) { 5220 case SIOCSIFMTU: 5221 if (BGE_IS_JUMBO_CAPABLE(sc) || 5222 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5223 if (ifr->ifr_mtu < ETHERMIN || 5224 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5225 error = EINVAL; 5226 break; 5227 } 5228 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5229 error = EINVAL; 5230 break; 5231 } 5232 BGE_LOCK(sc); 5233 if (ifp->if_mtu != ifr->ifr_mtu) { 5234 ifp->if_mtu = ifr->ifr_mtu; 5235 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5236 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5237 bge_init_locked(sc); 5238 } 5239 } 5240 BGE_UNLOCK(sc); 5241 break; 5242 case SIOCSIFFLAGS: 5243 BGE_LOCK(sc); 5244 if (ifp->if_flags & IFF_UP) { 5245 /* 5246 * If only the state of the PROMISC flag changed, 5247 * then just use the 'set promisc mode' command 5248 * instead of reinitializing the entire NIC. Doing 5249 * a full re-init means reloading the firmware and 5250 * waiting for it to start up, which may take a 5251 * second or two. Similarly for ALLMULTI. 5252 */ 5253 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5254 flags = ifp->if_flags ^ sc->bge_if_flags; 5255 if (flags & IFF_PROMISC) 5256 bge_setpromisc(sc); 5257 if (flags & IFF_ALLMULTI) 5258 bge_setmulti(sc); 5259 } else 5260 bge_init_locked(sc); 5261 } else { 5262 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5263 bge_stop(sc); 5264 } 5265 } 5266 sc->bge_if_flags = ifp->if_flags; 5267 BGE_UNLOCK(sc); 5268 error = 0; 5269 break; 5270 case SIOCADDMULTI: 5271 case SIOCDELMULTI: 5272 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5273 BGE_LOCK(sc); 5274 bge_setmulti(sc); 5275 BGE_UNLOCK(sc); 5276 error = 0; 5277 } 5278 break; 5279 case SIOCSIFMEDIA: 5280 case SIOCGIFMEDIA: 5281 if (sc->bge_flags & BGE_FLAG_TBI) { 5282 error = ifmedia_ioctl(ifp, ifr, 5283 &sc->bge_ifmedia, command); 5284 } else { 5285 mii = device_get_softc(sc->bge_miibus); 5286 error = ifmedia_ioctl(ifp, ifr, 5287 &mii->mii_media, command); 5288 } 5289 break; 5290 case SIOCSIFCAP: 5291 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5292 #ifdef DEVICE_POLLING 5293 if (mask & IFCAP_POLLING) { 5294 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5295 error = ether_poll_register(bge_poll, ifp); 5296 if (error) 5297 return (error); 5298 BGE_LOCK(sc); 5299 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5300 BGE_PCIMISCCTL_MASK_PCI_INTR); 5301 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5302 ifp->if_capenable |= IFCAP_POLLING; 5303 BGE_UNLOCK(sc); 5304 } else { 5305 error = ether_poll_deregister(ifp); 5306 /* Enable interrupt even in error case */ 5307 BGE_LOCK(sc); 5308 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5309 BGE_PCIMISCCTL_MASK_PCI_INTR); 5310 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5311 ifp->if_capenable &= ~IFCAP_POLLING; 5312 BGE_UNLOCK(sc); 5313 } 5314 } 5315 #endif 5316 if ((mask & IFCAP_TXCSUM) != 0 && 5317 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5318 ifp->if_capenable ^= IFCAP_TXCSUM; 5319 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5320 ifp->if_hwassist |= sc->bge_csum_features; 5321 else 5322 ifp->if_hwassist &= ~sc->bge_csum_features; 5323 } 5324 5325 if ((mask & IFCAP_RXCSUM) != 0 && 5326 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5327 ifp->if_capenable ^= IFCAP_RXCSUM; 5328 5329 if ((mask & IFCAP_TSO4) != 0 && 5330 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5331 ifp->if_capenable ^= IFCAP_TSO4; 5332 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5333 ifp->if_hwassist |= CSUM_TSO; 5334 else 5335 ifp->if_hwassist &= ~CSUM_TSO; 5336 } 5337 5338 if (mask & IFCAP_VLAN_MTU) { 5339 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5340 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5341 bge_init(sc); 5342 } 5343 5344 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5345 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5346 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5347 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5348 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5349 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5350 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5351 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5352 BGE_LOCK(sc); 5353 bge_setvlan(sc); 5354 BGE_UNLOCK(sc); 5355 } 5356 #ifdef VLAN_CAPABILITIES 5357 VLAN_CAPABILITIES(ifp); 5358 #endif 5359 break; 5360 default: 5361 error = ether_ioctl(ifp, command, data); 5362 break; 5363 } 5364 5365 return (error); 5366 } 5367 5368 static void 5369 bge_watchdog(struct bge_softc *sc) 5370 { 5371 struct ifnet *ifp; 5372 5373 BGE_LOCK_ASSERT(sc); 5374 5375 if (sc->bge_timer == 0 || --sc->bge_timer) 5376 return; 5377 5378 ifp = sc->bge_ifp; 5379 5380 if_printf(ifp, "watchdog timeout -- resetting\n"); 5381 5382 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5383 bge_init_locked(sc); 5384 5385 ifp->if_oerrors++; 5386 } 5387 5388 static void 5389 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5390 { 5391 int i; 5392 5393 BGE_CLRBIT(sc, reg, bit); 5394 5395 for (i = 0; i < BGE_TIMEOUT; i++) { 5396 if ((CSR_READ_4(sc, reg) & bit) == 0) 5397 return; 5398 DELAY(100); 5399 } 5400 } 5401 5402 /* 5403 * Stop the adapter and free any mbufs allocated to the 5404 * RX and TX lists. 5405 */ 5406 static void 5407 bge_stop(struct bge_softc *sc) 5408 { 5409 struct ifnet *ifp; 5410 5411 BGE_LOCK_ASSERT(sc); 5412 5413 ifp = sc->bge_ifp; 5414 5415 callout_stop(&sc->bge_stat_ch); 5416 5417 /* Disable host interrupts. */ 5418 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5419 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5420 5421 /* 5422 * Tell firmware we're shutting down. 5423 */ 5424 bge_stop_fw(sc); 5425 bge_sig_pre_reset(sc, BGE_RESET_STOP); 5426 5427 /* 5428 * Disable all of the receiver blocks. 5429 */ 5430 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5431 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5432 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5433 if (BGE_IS_5700_FAMILY(sc)) 5434 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5435 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5436 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 5437 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 5438 5439 /* 5440 * Disable all of the transmit blocks. 5441 */ 5442 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 5443 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 5444 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 5445 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 5446 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 5447 if (BGE_IS_5700_FAMILY(sc)) 5448 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 5449 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 5450 5451 /* 5452 * Shut down all of the memory managers and related 5453 * state machines. 5454 */ 5455 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 5456 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 5457 if (BGE_IS_5700_FAMILY(sc)) 5458 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 5459 5460 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 5461 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 5462 if (!(BGE_IS_5705_PLUS(sc))) { 5463 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 5464 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 5465 } 5466 /* Update MAC statistics. */ 5467 if (BGE_IS_5705_PLUS(sc)) 5468 bge_stats_update_regs(sc); 5469 5470 bge_reset(sc); 5471 bge_sig_legacy(sc, BGE_RESET_STOP); 5472 bge_sig_post_reset(sc, BGE_RESET_STOP); 5473 5474 /* 5475 * Keep the ASF firmware running if up. 5476 */ 5477 if (sc->bge_asf_mode & ASF_STACKUP) 5478 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5479 else 5480 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5481 5482 /* Free the RX lists. */ 5483 bge_free_rx_ring_std(sc); 5484 5485 /* Free jumbo RX list. */ 5486 if (BGE_IS_JUMBO_CAPABLE(sc)) 5487 bge_free_rx_ring_jumbo(sc); 5488 5489 /* Free TX buffers. */ 5490 bge_free_tx_ring(sc); 5491 5492 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 5493 5494 /* Clear MAC's link state (PHY may still have link UP). */ 5495 if (bootverbose && sc->bge_link) 5496 if_printf(sc->bge_ifp, "link DOWN\n"); 5497 sc->bge_link = 0; 5498 5499 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 5500 } 5501 5502 /* 5503 * Stop all chip I/O so that the kernel's probe routines don't 5504 * get confused by errant DMAs when rebooting. 5505 */ 5506 static int 5507 bge_shutdown(device_t dev) 5508 { 5509 struct bge_softc *sc; 5510 5511 sc = device_get_softc(dev); 5512 BGE_LOCK(sc); 5513 bge_stop(sc); 5514 bge_reset(sc); 5515 BGE_UNLOCK(sc); 5516 5517 return (0); 5518 } 5519 5520 static int 5521 bge_suspend(device_t dev) 5522 { 5523 struct bge_softc *sc; 5524 5525 sc = device_get_softc(dev); 5526 BGE_LOCK(sc); 5527 bge_stop(sc); 5528 BGE_UNLOCK(sc); 5529 5530 return (0); 5531 } 5532 5533 static int 5534 bge_resume(device_t dev) 5535 { 5536 struct bge_softc *sc; 5537 struct ifnet *ifp; 5538 5539 sc = device_get_softc(dev); 5540 BGE_LOCK(sc); 5541 ifp = sc->bge_ifp; 5542 if (ifp->if_flags & IFF_UP) { 5543 bge_init_locked(sc); 5544 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5545 bge_start_locked(ifp); 5546 } 5547 BGE_UNLOCK(sc); 5548 5549 return (0); 5550 } 5551 5552 static void 5553 bge_link_upd(struct bge_softc *sc) 5554 { 5555 struct mii_data *mii; 5556 uint32_t link, status; 5557 5558 BGE_LOCK_ASSERT(sc); 5559 5560 /* Clear 'pending link event' flag. */ 5561 sc->bge_link_evt = 0; 5562 5563 /* 5564 * Process link state changes. 5565 * Grrr. The link status word in the status block does 5566 * not work correctly on the BCM5700 rev AX and BX chips, 5567 * according to all available information. Hence, we have 5568 * to enable MII interrupts in order to properly obtain 5569 * async link changes. Unfortunately, this also means that 5570 * we have to read the MAC status register to detect link 5571 * changes, thereby adding an additional register access to 5572 * the interrupt handler. 5573 * 5574 * XXX: perhaps link state detection procedure used for 5575 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 5576 */ 5577 5578 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 5579 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 5580 status = CSR_READ_4(sc, BGE_MAC_STS); 5581 if (status & BGE_MACSTAT_MI_INTERRUPT) { 5582 mii = device_get_softc(sc->bge_miibus); 5583 mii_pollstat(mii); 5584 if (!sc->bge_link && 5585 mii->mii_media_status & IFM_ACTIVE && 5586 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5587 sc->bge_link++; 5588 if (bootverbose) 5589 if_printf(sc->bge_ifp, "link UP\n"); 5590 } else if (sc->bge_link && 5591 (!(mii->mii_media_status & IFM_ACTIVE) || 5592 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5593 sc->bge_link = 0; 5594 if (bootverbose) 5595 if_printf(sc->bge_ifp, "link DOWN\n"); 5596 } 5597 5598 /* Clear the interrupt. */ 5599 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 5600 BGE_EVTENB_MI_INTERRUPT); 5601 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 5602 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 5603 BRGPHY_INTRS); 5604 } 5605 return; 5606 } 5607 5608 if (sc->bge_flags & BGE_FLAG_TBI) { 5609 status = CSR_READ_4(sc, BGE_MAC_STS); 5610 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 5611 if (!sc->bge_link) { 5612 sc->bge_link++; 5613 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 5614 BGE_CLRBIT(sc, BGE_MAC_MODE, 5615 BGE_MACMODE_TBI_SEND_CFGS); 5616 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 5617 if (bootverbose) 5618 if_printf(sc->bge_ifp, "link UP\n"); 5619 if_link_state_change(sc->bge_ifp, 5620 LINK_STATE_UP); 5621 } 5622 } else if (sc->bge_link) { 5623 sc->bge_link = 0; 5624 if (bootverbose) 5625 if_printf(sc->bge_ifp, "link DOWN\n"); 5626 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 5627 } 5628 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 5629 /* 5630 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 5631 * in status word always set. Workaround this bug by reading 5632 * PHY link status directly. 5633 */ 5634 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 5635 5636 if (link != sc->bge_link || 5637 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 5638 mii = device_get_softc(sc->bge_miibus); 5639 mii_pollstat(mii); 5640 if (!sc->bge_link && 5641 mii->mii_media_status & IFM_ACTIVE && 5642 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 5643 sc->bge_link++; 5644 if (bootverbose) 5645 if_printf(sc->bge_ifp, "link UP\n"); 5646 } else if (sc->bge_link && 5647 (!(mii->mii_media_status & IFM_ACTIVE) || 5648 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 5649 sc->bge_link = 0; 5650 if (bootverbose) 5651 if_printf(sc->bge_ifp, "link DOWN\n"); 5652 } 5653 } 5654 } else { 5655 /* 5656 * For controllers that call mii_tick, we have to poll 5657 * link status. 5658 */ 5659 mii = device_get_softc(sc->bge_miibus); 5660 mii_pollstat(mii); 5661 bge_miibus_statchg(sc->bge_dev); 5662 } 5663 5664 /* Clear the attention. */ 5665 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 5666 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 5667 BGE_MACSTAT_LINK_CHANGED); 5668 } 5669 5670 static void 5671 bge_add_sysctls(struct bge_softc *sc) 5672 { 5673 struct sysctl_ctx_list *ctx; 5674 struct sysctl_oid_list *children; 5675 char tn[32]; 5676 int unit; 5677 5678 ctx = device_get_sysctl_ctx(sc->bge_dev); 5679 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 5680 5681 #ifdef BGE_REGISTER_DEBUG 5682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 5683 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 5684 "Debug Information"); 5685 5686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 5687 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 5688 "Register Read"); 5689 5690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 5691 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 5692 "Memory Read"); 5693 5694 #endif 5695 5696 unit = device_get_unit(sc->bge_dev); 5697 /* 5698 * A common design characteristic for many Broadcom client controllers 5699 * is that they only support a single outstanding DMA read operation 5700 * on the PCIe bus. This means that it will take twice as long to fetch 5701 * a TX frame that is split into header and payload buffers as it does 5702 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 5703 * these controllers, coalescing buffers to reduce the number of memory 5704 * reads is effective way to get maximum performance(about 940Mbps). 5705 * Without collapsing TX buffers the maximum TCP bulk transfer 5706 * performance is about 850Mbps. However forcing coalescing mbufs 5707 * consumes a lot of CPU cycles, so leave it off by default. 5708 */ 5709 sc->bge_forced_collapse = 0; 5710 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 5711 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 5712 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 5713 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 5714 "Number of fragmented TX buffers of a frame allowed before " 5715 "forced collapsing"); 5716 5717 sc->bge_msi = 1; 5718 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 5719 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 5720 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 5721 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 5722 5723 /* 5724 * It seems all Broadcom controllers have a bug that can generate UDP 5725 * datagrams with checksum value 0 when TX UDP checksum offloading is 5726 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 5727 * Even though the probability of generating such UDP datagrams is 5728 * low, I don't want to see FreeBSD boxes to inject such datagrams 5729 * into network so disable UDP checksum offloading by default. Users 5730 * still override this behavior by setting a sysctl variable, 5731 * dev.bge.0.forced_udpcsum. 5732 */ 5733 sc->bge_forced_udpcsum = 0; 5734 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 5735 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 5736 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 5737 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 5738 "Enable UDP checksum offloading even if controller can " 5739 "generate UDP checksum value 0"); 5740 5741 if (BGE_IS_5705_PLUS(sc)) 5742 bge_add_sysctl_stats_regs(sc, ctx, children); 5743 else 5744 bge_add_sysctl_stats(sc, ctx, children); 5745 } 5746 5747 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 5748 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 5749 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 5750 desc) 5751 5752 static void 5753 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5754 struct sysctl_oid_list *parent) 5755 { 5756 struct sysctl_oid *tree; 5757 struct sysctl_oid_list *children, *schildren; 5758 5759 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5760 NULL, "BGE Statistics"); 5761 schildren = children = SYSCTL_CHILDREN(tree); 5762 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 5763 children, COSFramesDroppedDueToFilters, 5764 "FramesDroppedDueToFilters"); 5765 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 5766 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 5767 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 5768 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 5769 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 5770 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 5771 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 5772 children, ifInDiscards, "InputDiscards"); 5773 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 5774 children, ifInErrors, "InputErrors"); 5775 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 5776 children, nicRecvThresholdHit, "RecvThresholdHit"); 5777 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 5778 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 5779 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 5780 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 5781 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 5782 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 5783 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 5784 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 5785 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 5786 children, nicRingStatusUpdate, "RingStatusUpdate"); 5787 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 5788 children, nicInterrupts, "Interrupts"); 5789 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 5790 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 5791 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 5792 children, nicSendThresholdHit, "SendThresholdHit"); 5793 5794 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 5795 NULL, "BGE RX Statistics"); 5796 children = SYSCTL_CHILDREN(tree); 5797 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 5798 children, rxstats.ifHCInOctets, "ifHCInOctets"); 5799 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 5800 children, rxstats.etherStatsFragments, "Fragments"); 5801 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 5802 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 5803 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 5804 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 5805 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 5806 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 5807 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 5808 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 5809 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 5810 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 5811 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 5812 children, rxstats.xoffPauseFramesReceived, 5813 "xoffPauseFramesReceived"); 5814 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 5815 children, rxstats.macControlFramesReceived, 5816 "ControlFramesReceived"); 5817 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5818 children, rxstats.xoffStateEntered, "xoffStateEntered"); 5819 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5820 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5821 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5822 children, rxstats.etherStatsJabbers, "Jabbers"); 5823 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5824 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5825 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 5826 children, rxstats.inRangeLengthError, "inRangeLengthError"); 5827 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 5828 children, rxstats.outRangeLengthError, "outRangeLengthError"); 5829 5830 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5831 NULL, "BGE TX Statistics"); 5832 children = SYSCTL_CHILDREN(tree); 5833 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5834 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 5835 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5836 children, txstats.etherStatsCollisions, "Collisions"); 5837 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5838 children, txstats.outXonSent, "XonSent"); 5839 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5840 children, txstats.outXoffSent, "XoffSent"); 5841 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5842 children, txstats.flowControlDone, "flowControlDone"); 5843 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5844 children, txstats.dot3StatsInternalMacTransmitErrors, 5845 "InternalMacTransmitErrors"); 5846 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5847 children, txstats.dot3StatsSingleCollisionFrames, 5848 "SingleCollisionFrames"); 5849 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5850 children, txstats.dot3StatsMultipleCollisionFrames, 5851 "MultipleCollisionFrames"); 5852 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5853 children, txstats.dot3StatsDeferredTransmissions, 5854 "DeferredTransmissions"); 5855 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5856 children, txstats.dot3StatsExcessiveCollisions, 5857 "ExcessiveCollisions"); 5858 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 5859 children, txstats.dot3StatsLateCollisions, 5860 "LateCollisions"); 5861 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5862 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 5863 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5864 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5865 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5866 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5867 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5868 children, txstats.dot3StatsCarrierSenseErrors, 5869 "CarrierSenseErrors"); 5870 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5871 children, txstats.ifOutDiscards, "Discards"); 5872 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5873 children, txstats.ifOutErrors, "Errors"); 5874 } 5875 5876 #undef BGE_SYSCTL_STAT 5877 5878 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 5879 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 5880 5881 static void 5882 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 5883 struct sysctl_oid_list *parent) 5884 { 5885 struct sysctl_oid *tree; 5886 struct sysctl_oid_list *child, *schild; 5887 struct bge_mac_stats *stats; 5888 5889 stats = &sc->bge_mac_stats; 5890 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 5891 NULL, "BGE Statistics"); 5892 schild = child = SYSCTL_CHILDREN(tree); 5893 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 5894 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 5895 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 5896 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 5897 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 5898 &stats->DmaWriteHighPriQueueFull, 5899 "NIC DMA Write High Priority Queue Full"); 5900 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 5901 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 5902 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 5903 &stats->InputDiscards, "Discarded Input Frames"); 5904 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 5905 &stats->InputErrors, "Input Errors"); 5906 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 5907 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 5908 5909 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 5910 NULL, "BGE RX Statistics"); 5911 child = SYSCTL_CHILDREN(tree); 5912 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 5913 &stats->ifHCInOctets, "Inbound Octets"); 5914 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 5915 &stats->etherStatsFragments, "Fragments"); 5916 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5917 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 5918 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5919 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 5920 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5921 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 5922 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 5923 &stats->dot3StatsFCSErrors, "FCS Errors"); 5924 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 5925 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 5926 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 5927 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 5928 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 5929 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 5930 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 5931 &stats->macControlFramesReceived, "MAC Control Frames Received"); 5932 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 5933 &stats->xoffStateEntered, "XOFF State Entered"); 5934 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 5935 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 5936 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 5937 &stats->etherStatsJabbers, "Jabbers"); 5938 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 5939 &stats->etherStatsUndersizePkts, "Undersized Packets"); 5940 5941 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 5942 NULL, "BGE TX Statistics"); 5943 child = SYSCTL_CHILDREN(tree); 5944 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 5945 &stats->ifHCOutOctets, "Outbound Octets"); 5946 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 5947 &stats->etherStatsCollisions, "TX Collisions"); 5948 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 5949 &stats->outXonSent, "XON Sent"); 5950 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 5951 &stats->outXoffSent, "XOFF Sent"); 5952 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 5953 &stats->dot3StatsInternalMacTransmitErrors, 5954 "Internal MAC TX Errors"); 5955 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 5956 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 5957 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 5958 &stats->dot3StatsMultipleCollisionFrames, 5959 "Multiple Collision Frames"); 5960 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 5961 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 5962 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 5963 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 5964 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 5965 &stats->dot3StatsLateCollisions, "Late Collisions"); 5966 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 5967 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 5968 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 5969 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 5970 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 5971 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 5972 } 5973 5974 #undef BGE_SYSCTL_STAT_ADD64 5975 5976 static int 5977 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5978 { 5979 struct bge_softc *sc; 5980 uint32_t result; 5981 int offset; 5982 5983 sc = (struct bge_softc *)arg1; 5984 offset = arg2; 5985 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5986 offsetof(bge_hostaddr, bge_addr_lo)); 5987 return (sysctl_handle_int(oidp, &result, 0, req)); 5988 } 5989 5990 #ifdef BGE_REGISTER_DEBUG 5991 static int 5992 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5993 { 5994 struct bge_softc *sc; 5995 uint16_t *sbdata; 5996 int error, result, sbsz; 5997 int i, j; 5998 5999 result = -1; 6000 error = sysctl_handle_int(oidp, &result, 0, req); 6001 if (error || (req->newptr == NULL)) 6002 return (error); 6003 6004 if (result == 1) { 6005 sc = (struct bge_softc *)arg1; 6006 6007 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6008 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6009 sbsz = BGE_STATUS_BLK_SZ; 6010 else 6011 sbsz = 32; 6012 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6013 printf("Status Block:\n"); 6014 BGE_LOCK(sc); 6015 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6016 sc->bge_cdata.bge_status_map, 6017 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6018 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6019 printf("%06x:", i); 6020 for (j = 0; j < 8; j++) 6021 printf(" %04x", sbdata[i++]); 6022 printf("\n"); 6023 } 6024 6025 printf("Registers:\n"); 6026 for (i = 0x800; i < 0xA00; ) { 6027 printf("%06x:", i); 6028 for (j = 0; j < 8; j++) { 6029 printf(" %08x", CSR_READ_4(sc, i)); 6030 i += 4; 6031 } 6032 printf("\n"); 6033 } 6034 BGE_UNLOCK(sc); 6035 6036 printf("Hardware Flags:\n"); 6037 if (BGE_IS_5717_PLUS(sc)) 6038 printf(" - 5717 Plus\n"); 6039 if (BGE_IS_5755_PLUS(sc)) 6040 printf(" - 5755 Plus\n"); 6041 if (BGE_IS_575X_PLUS(sc)) 6042 printf(" - 575X Plus\n"); 6043 if (BGE_IS_5705_PLUS(sc)) 6044 printf(" - 5705 Plus\n"); 6045 if (BGE_IS_5714_FAMILY(sc)) 6046 printf(" - 5714 Family\n"); 6047 if (BGE_IS_5700_FAMILY(sc)) 6048 printf(" - 5700 Family\n"); 6049 if (sc->bge_flags & BGE_FLAG_JUMBO) 6050 printf(" - Supports Jumbo Frames\n"); 6051 if (sc->bge_flags & BGE_FLAG_PCIX) 6052 printf(" - PCI-X Bus\n"); 6053 if (sc->bge_flags & BGE_FLAG_PCIE) 6054 printf(" - PCI Express Bus\n"); 6055 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6056 printf(" - No 3 LEDs\n"); 6057 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6058 printf(" - RX Alignment Bug\n"); 6059 } 6060 6061 return (error); 6062 } 6063 6064 static int 6065 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6066 { 6067 struct bge_softc *sc; 6068 int error; 6069 uint16_t result; 6070 uint32_t val; 6071 6072 result = -1; 6073 error = sysctl_handle_int(oidp, &result, 0, req); 6074 if (error || (req->newptr == NULL)) 6075 return (error); 6076 6077 if (result < 0x8000) { 6078 sc = (struct bge_softc *)arg1; 6079 val = CSR_READ_4(sc, result); 6080 printf("reg 0x%06X = 0x%08X\n", result, val); 6081 } 6082 6083 return (error); 6084 } 6085 6086 static int 6087 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6088 { 6089 struct bge_softc *sc; 6090 int error; 6091 uint16_t result; 6092 uint32_t val; 6093 6094 result = -1; 6095 error = sysctl_handle_int(oidp, &result, 0, req); 6096 if (error || (req->newptr == NULL)) 6097 return (error); 6098 6099 if (result < 0x8000) { 6100 sc = (struct bge_softc *)arg1; 6101 val = bge_readmem_ind(sc, result); 6102 printf("mem 0x%06X = 0x%08X\n", result, val); 6103 } 6104 6105 return (error); 6106 } 6107 #endif 6108 6109 static int 6110 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6111 { 6112 6113 if (sc->bge_flags & BGE_FLAG_EADDR) 6114 return (1); 6115 6116 #ifdef __sparc64__ 6117 OF_getetheraddr(sc->bge_dev, ether_addr); 6118 return (0); 6119 #endif 6120 return (1); 6121 } 6122 6123 static int 6124 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6125 { 6126 uint32_t mac_addr; 6127 6128 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6129 if ((mac_addr >> 16) == 0x484b) { 6130 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6131 ether_addr[1] = (uint8_t)mac_addr; 6132 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6133 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6134 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6135 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6136 ether_addr[5] = (uint8_t)mac_addr; 6137 return (0); 6138 } 6139 return (1); 6140 } 6141 6142 static int 6143 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6144 { 6145 int mac_offset = BGE_EE_MAC_OFFSET; 6146 6147 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6148 mac_offset = BGE_EE_MAC_OFFSET_5906; 6149 6150 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6151 ETHER_ADDR_LEN)); 6152 } 6153 6154 static int 6155 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6156 { 6157 6158 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6159 return (1); 6160 6161 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6162 ETHER_ADDR_LEN)); 6163 } 6164 6165 static int 6166 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6167 { 6168 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6169 /* NOTE: Order is critical */ 6170 bge_get_eaddr_fw, 6171 bge_get_eaddr_mem, 6172 bge_get_eaddr_nvram, 6173 bge_get_eaddr_eeprom, 6174 NULL 6175 }; 6176 const bge_eaddr_fcn_t *func; 6177 6178 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6179 if ((*func)(sc, eaddr) == 0) 6180 break; 6181 } 6182 return (*func == NULL ? ENXIO : 0); 6183 } 6184