1 /* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 36 * 37 * The Broadcom BCM5700 is based on technology originally developed by 38 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 39 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 40 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 41 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 42 * frames, highly configurable RX filtering, and 16 RX and TX queues 43 * (which, along with RX filter rules, can be used for QOS applications). 44 * Other features, such as TCP segmentation, may be available as part 45 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 46 * firmware images can be stored in hardware and need not be compiled 47 * into the driver. 48 * 49 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 50 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 51 * 52 * The BCM5701 is a single-chip solution incorporating both the BCM5700 53 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 54 * does not support external SSRAM. 55 * 56 * Broadcom also produces a variation of the BCM5700 under the "Altima" 57 * brand name, which is functionally similar but lacks PCI-X support. 58 * 59 * Without external SSRAM, you can only have at most 4 TX rings, 60 * and the use of the mini RX ring is disabled. This seems to imply 61 * that these features are simply not available on the BCM5701. As a 62 * result, this driver does not implement any support for the mini RX 63 * ring. 64 */ 65 66 #include <sys/cdefs.h> 67 __FBSDID("$FreeBSD$"); 68 69 #include <sys/param.h> 70 #include <sys/systm.h> 71 #include <sys/sockio.h> 72 #include <sys/mbuf.h> 73 #include <sys/malloc.h> 74 #include <sys/kernel.h> 75 #include <sys/socket.h> 76 #include <sys/queue.h> 77 78 #include <net/if.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_dl.h> 82 #include <net/if_media.h> 83 84 #include <net/bpf.h> 85 86 #include <net/if_types.h> 87 #include <net/if_vlan_var.h> 88 89 #include <netinet/in_systm.h> 90 #include <netinet/in.h> 91 #include <netinet/ip.h> 92 93 #include <vm/vm.h> /* for vtophys */ 94 #include <vm/pmap.h> /* for vtophys */ 95 #include <machine/clock.h> /* for DELAY */ 96 #include <machine/bus_memio.h> 97 #include <machine/bus.h> 98 #include <machine/resource.h> 99 #include <sys/bus.h> 100 #include <sys/rman.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 #include "miidevs.h" 105 #include <dev/mii/brgphyreg.h> 106 107 #include <pci/pcireg.h> 108 #include <pci/pcivar.h> 109 110 #include <dev/bge/if_bgereg.h> 111 112 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 113 114 MODULE_DEPEND(bge, pci, 1, 1, 1); 115 MODULE_DEPEND(bge, ether, 1, 1, 1); 116 MODULE_DEPEND(bge, miibus, 1, 1, 1); 117 118 /* "controller miibus0" required. See GENERIC if you get errors here. */ 119 #include "miibus_if.h" 120 121 /* 122 * Various supported device vendors/types and their names. Note: the 123 * spec seems to indicate that the hardware still has Alteon's vendor 124 * ID burned into it, though it will always be overriden by the vendor 125 * ID in the EEPROM. Just to be safe, we cover all possibilities. 126 */ 127 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */ 128 129 static struct bge_type bge_devs[] = { 130 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 131 "Broadcom BCM5700 Gigabit Ethernet" }, 132 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 133 "Broadcom BCM5701 Gigabit Ethernet" }, 134 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 135 "Broadcom BCM5700 Gigabit Ethernet" }, 136 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 137 "Broadcom BCM5701 Gigabit Ethernet" }, 138 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X, 139 "Broadcom BCM5702X Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X, 141 "Broadcom BCM5703X Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C, 143 "Broadcom BCM5704C Dual Gigabit Ethernet" }, 144 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S, 145 "Broadcom BCM5704S Dual Gigabit Ethernet" }, 146 { SK_VENDORID, SK_DEVICEID_ALTIMA, 147 "SysKonnect Gigabit Ethernet" }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 149 "Altima AC1000 Gigabit Ethernet" }, 150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 151 "Altima AC9100 Gigabit Ethernet" }, 152 { 0, 0, NULL } 153 }; 154 155 static int bge_probe (device_t); 156 static int bge_attach (device_t); 157 static int bge_detach (device_t); 158 static void bge_release_resources 159 (struct bge_softc *); 160 static void bge_txeof (struct bge_softc *); 161 static void bge_rxeof (struct bge_softc *); 162 163 static void bge_tick (void *); 164 static void bge_stats_update (struct bge_softc *); 165 static int bge_encap (struct bge_softc *, struct mbuf *, 166 u_int32_t *); 167 168 static void bge_intr (void *); 169 static void bge_start (struct ifnet *); 170 static int bge_ioctl (struct ifnet *, u_long, caddr_t); 171 static void bge_init (void *); 172 static void bge_stop (struct bge_softc *); 173 static void bge_watchdog (struct ifnet *); 174 static void bge_shutdown (device_t); 175 static int bge_ifmedia_upd (struct ifnet *); 176 static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 177 178 static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 179 static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 180 181 static u_int32_t bge_crc (caddr_t); 182 static void bge_setmulti (struct bge_softc *); 183 184 static void bge_handle_events (struct bge_softc *); 185 static int bge_alloc_jumbo_mem (struct bge_softc *); 186 static void bge_free_jumbo_mem (struct bge_softc *); 187 static void *bge_jalloc (struct bge_softc *); 188 static void bge_jfree (void *, void *); 189 static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 190 static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 191 static int bge_init_rx_ring_std (struct bge_softc *); 192 static void bge_free_rx_ring_std (struct bge_softc *); 193 static int bge_init_rx_ring_jumbo (struct bge_softc *); 194 static void bge_free_rx_ring_jumbo (struct bge_softc *); 195 static void bge_free_tx_ring (struct bge_softc *); 196 static int bge_init_tx_ring (struct bge_softc *); 197 198 static int bge_chipinit (struct bge_softc *); 199 static int bge_blockinit (struct bge_softc *); 200 201 #ifdef notdef 202 static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 203 static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 204 static void bge_vpd_read (struct bge_softc *); 205 #endif 206 207 static u_int32_t bge_readmem_ind 208 (struct bge_softc *, int); 209 static void bge_writemem_ind (struct bge_softc *, int, int); 210 #ifdef notdef 211 static u_int32_t bge_readreg_ind 212 (struct bge_softc *, int); 213 #endif 214 static void bge_writereg_ind (struct bge_softc *, int, int); 215 216 static int bge_miibus_readreg (device_t, int, int); 217 static int bge_miibus_writereg (device_t, int, int, int); 218 static void bge_miibus_statchg (device_t); 219 220 static void bge_reset (struct bge_softc *); 221 222 static device_method_t bge_methods[] = { 223 /* Device interface */ 224 DEVMETHOD(device_probe, bge_probe), 225 DEVMETHOD(device_attach, bge_attach), 226 DEVMETHOD(device_detach, bge_detach), 227 DEVMETHOD(device_shutdown, bge_shutdown), 228 229 /* bus interface */ 230 DEVMETHOD(bus_print_child, bus_generic_print_child), 231 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 232 233 /* MII interface */ 234 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 235 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 236 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 237 238 { 0, 0 } 239 }; 240 241 static driver_t bge_driver = { 242 "bge", 243 bge_methods, 244 sizeof(struct bge_softc) 245 }; 246 247 static devclass_t bge_devclass; 248 249 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 250 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 251 252 static u_int32_t 253 bge_readmem_ind(sc, off) 254 struct bge_softc *sc; 255 int off; 256 { 257 device_t dev; 258 259 dev = sc->bge_dev; 260 261 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 262 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 263 } 264 265 static void 266 bge_writemem_ind(sc, off, val) 267 struct bge_softc *sc; 268 int off, val; 269 { 270 device_t dev; 271 272 dev = sc->bge_dev; 273 274 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 275 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 276 277 return; 278 } 279 280 #ifdef notdef 281 static u_int32_t 282 bge_readreg_ind(sc, off) 283 struct bge_softc *sc; 284 int off; 285 { 286 device_t dev; 287 288 dev = sc->bge_dev; 289 290 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 291 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 292 } 293 #endif 294 295 static void 296 bge_writereg_ind(sc, off, val) 297 struct bge_softc *sc; 298 int off, val; 299 { 300 device_t dev; 301 302 dev = sc->bge_dev; 303 304 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 305 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 306 307 return; 308 } 309 310 #ifdef notdef 311 static u_int8_t 312 bge_vpd_readbyte(sc, addr) 313 struct bge_softc *sc; 314 int addr; 315 { 316 int i; 317 device_t dev; 318 u_int32_t val; 319 320 dev = sc->bge_dev; 321 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 322 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 323 DELAY(10); 324 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 325 break; 326 } 327 328 if (i == BGE_TIMEOUT) { 329 printf("bge%d: VPD read timed out\n", sc->bge_unit); 330 return(0); 331 } 332 333 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 334 335 return((val >> ((addr % 4) * 8)) & 0xFF); 336 } 337 338 static void 339 bge_vpd_read_res(sc, res, addr) 340 struct bge_softc *sc; 341 struct vpd_res *res; 342 int addr; 343 { 344 int i; 345 u_int8_t *ptr; 346 347 ptr = (u_int8_t *)res; 348 for (i = 0; i < sizeof(struct vpd_res); i++) 349 ptr[i] = bge_vpd_readbyte(sc, i + addr); 350 351 return; 352 } 353 354 static void 355 bge_vpd_read(sc) 356 struct bge_softc *sc; 357 { 358 int pos = 0, i; 359 struct vpd_res res; 360 361 if (sc->bge_vpd_prodname != NULL) 362 free(sc->bge_vpd_prodname, M_DEVBUF); 363 if (sc->bge_vpd_readonly != NULL) 364 free(sc->bge_vpd_readonly, M_DEVBUF); 365 sc->bge_vpd_prodname = NULL; 366 sc->bge_vpd_readonly = NULL; 367 368 bge_vpd_read_res(sc, &res, pos); 369 370 if (res.vr_id != VPD_RES_ID) { 371 printf("bge%d: bad VPD resource id: expected %x got %x\n", 372 sc->bge_unit, VPD_RES_ID, res.vr_id); 373 return; 374 } 375 376 pos += sizeof(res); 377 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 378 for (i = 0; i < res.vr_len; i++) 379 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 380 sc->bge_vpd_prodname[i] = '\0'; 381 pos += i; 382 383 bge_vpd_read_res(sc, &res, pos); 384 385 if (res.vr_id != VPD_RES_READ) { 386 printf("bge%d: bad VPD resource id: expected %x got %x\n", 387 sc->bge_unit, VPD_RES_READ, res.vr_id); 388 return; 389 } 390 391 pos += sizeof(res); 392 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 393 for (i = 0; i < res.vr_len + 1; i++) 394 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 395 396 return; 397 } 398 #endif 399 400 /* 401 * Read a byte of data stored in the EEPROM at address 'addr.' The 402 * BCM570x supports both the traditional bitbang interface and an 403 * auto access interface for reading the EEPROM. We use the auto 404 * access method. 405 */ 406 static u_int8_t 407 bge_eeprom_getbyte(sc, addr, dest) 408 struct bge_softc *sc; 409 int addr; 410 u_int8_t *dest; 411 { 412 int i; 413 u_int32_t byte = 0; 414 415 /* 416 * Enable use of auto EEPROM access so we can avoid 417 * having to use the bitbang method. 418 */ 419 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 420 421 /* Reset the EEPROM, load the clock period. */ 422 CSR_WRITE_4(sc, BGE_EE_ADDR, 423 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 424 DELAY(20); 425 426 /* Issue the read EEPROM command. */ 427 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 428 429 /* Wait for completion */ 430 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 431 DELAY(10); 432 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 433 break; 434 } 435 436 if (i == BGE_TIMEOUT) { 437 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 438 return(0); 439 } 440 441 /* Get result. */ 442 byte = CSR_READ_4(sc, BGE_EE_DATA); 443 444 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 445 446 return(0); 447 } 448 449 /* 450 * Read a sequence of bytes from the EEPROM. 451 */ 452 static int 453 bge_read_eeprom(sc, dest, off, cnt) 454 struct bge_softc *sc; 455 caddr_t dest; 456 int off; 457 int cnt; 458 { 459 int err = 0, i; 460 u_int8_t byte = 0; 461 462 for (i = 0; i < cnt; i++) { 463 err = bge_eeprom_getbyte(sc, off + i, &byte); 464 if (err) 465 break; 466 *(dest + i) = byte; 467 } 468 469 return(err ? 1 : 0); 470 } 471 472 static int 473 bge_miibus_readreg(dev, phy, reg) 474 device_t dev; 475 int phy, reg; 476 { 477 struct bge_softc *sc; 478 u_int32_t val, autopoll; 479 int i; 480 481 sc = device_get_softc(dev); 482 483 if (phy != 1) 484 switch(sc->bge_chipid) { 485 case BGE_CHIPID_BCM5701_B5: 486 case BGE_CHIPID_BCM5703_A2: 487 case BGE_CHIPID_BCM5704_A0: 488 return(0); 489 } 490 491 /* Reading with autopolling on may trigger PCI errors */ 492 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 493 if (autopoll & BGE_MIMODE_AUTOPOLL) { 494 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 495 DELAY(40); 496 } 497 498 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 499 BGE_MIPHY(phy)|BGE_MIREG(reg)); 500 501 for (i = 0; i < BGE_TIMEOUT; i++) { 502 val = CSR_READ_4(sc, BGE_MI_COMM); 503 if (!(val & BGE_MICOMM_BUSY)) 504 break; 505 } 506 507 if (i == BGE_TIMEOUT) { 508 printf("bge%d: PHY read timed out\n", sc->bge_unit); 509 val = 0; 510 goto done; 511 } 512 513 val = CSR_READ_4(sc, BGE_MI_COMM); 514 515 done: 516 if (autopoll & BGE_MIMODE_AUTOPOLL) { 517 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 518 DELAY(40); 519 } 520 521 if (val & BGE_MICOMM_READFAIL) 522 return(0); 523 524 return(val & 0xFFFF); 525 } 526 527 static int 528 bge_miibus_writereg(dev, phy, reg, val) 529 device_t dev; 530 int phy, reg, val; 531 { 532 struct bge_softc *sc; 533 u_int32_t autopoll; 534 int i; 535 536 sc = device_get_softc(dev); 537 538 /* Reading with autopolling on may trigger PCI errors */ 539 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 540 if (autopoll & BGE_MIMODE_AUTOPOLL) { 541 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 542 DELAY(40); 543 } 544 545 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 546 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 547 548 for (i = 0; i < BGE_TIMEOUT; i++) { 549 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 550 break; 551 } 552 553 if (autopoll & BGE_MIMODE_AUTOPOLL) { 554 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 555 DELAY(40); 556 } 557 558 if (i == BGE_TIMEOUT) { 559 printf("bge%d: PHY read timed out\n", sc->bge_unit); 560 return(0); 561 } 562 563 return(0); 564 } 565 566 static void 567 bge_miibus_statchg(dev) 568 device_t dev; 569 { 570 struct bge_softc *sc; 571 struct mii_data *mii; 572 573 sc = device_get_softc(dev); 574 mii = device_get_softc(sc->bge_miibus); 575 576 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 577 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 578 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 579 } else { 580 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 581 } 582 583 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 584 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 585 } else { 586 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 587 } 588 589 return; 590 } 591 592 /* 593 * Handle events that have triggered interrupts. 594 */ 595 static void 596 bge_handle_events(sc) 597 struct bge_softc *sc; 598 { 599 600 return; 601 } 602 603 /* 604 * Memory management for jumbo frames. 605 */ 606 607 static int 608 bge_alloc_jumbo_mem(sc) 609 struct bge_softc *sc; 610 { 611 caddr_t ptr; 612 register int i; 613 struct bge_jpool_entry *entry; 614 615 /* Grab a big chunk o' storage. */ 616 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 617 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 618 619 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 620 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 621 return(ENOBUFS); 622 } 623 624 SLIST_INIT(&sc->bge_jfree_listhead); 625 SLIST_INIT(&sc->bge_jinuse_listhead); 626 627 /* 628 * Now divide it up into 9K pieces and save the addresses 629 * in an array. 630 */ 631 ptr = sc->bge_cdata.bge_jumbo_buf; 632 for (i = 0; i < BGE_JSLOTS; i++) { 633 sc->bge_cdata.bge_jslots[i] = ptr; 634 ptr += BGE_JLEN; 635 entry = malloc(sizeof(struct bge_jpool_entry), 636 M_DEVBUF, M_NOWAIT); 637 if (entry == NULL) { 638 contigfree(sc->bge_cdata.bge_jumbo_buf, 639 BGE_JMEM, M_DEVBUF); 640 sc->bge_cdata.bge_jumbo_buf = NULL; 641 printf("bge%d: no memory for jumbo " 642 "buffer queue!\n", sc->bge_unit); 643 return(ENOBUFS); 644 } 645 entry->slot = i; 646 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 647 entry, jpool_entries); 648 } 649 650 return(0); 651 } 652 653 static void 654 bge_free_jumbo_mem(sc) 655 struct bge_softc *sc; 656 { 657 int i; 658 struct bge_jpool_entry *entry; 659 660 for (i = 0; i < BGE_JSLOTS; i++) { 661 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 662 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 663 free(entry, M_DEVBUF); 664 } 665 666 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 667 668 return; 669 } 670 671 /* 672 * Allocate a jumbo buffer. 673 */ 674 static void * 675 bge_jalloc(sc) 676 struct bge_softc *sc; 677 { 678 struct bge_jpool_entry *entry; 679 680 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 681 682 if (entry == NULL) { 683 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 684 return(NULL); 685 } 686 687 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 688 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 689 return(sc->bge_cdata.bge_jslots[entry->slot]); 690 } 691 692 /* 693 * Release a jumbo buffer. 694 */ 695 static void 696 bge_jfree(buf, args) 697 void *buf; 698 void *args; 699 { 700 struct bge_jpool_entry *entry; 701 struct bge_softc *sc; 702 int i; 703 704 /* Extract the softc struct pointer. */ 705 sc = (struct bge_softc *)args; 706 707 if (sc == NULL) 708 panic("bge_jfree: can't find softc pointer!"); 709 710 /* calculate the slot this buffer belongs to */ 711 712 i = ((vm_offset_t)buf 713 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 714 715 if ((i < 0) || (i >= BGE_JSLOTS)) 716 panic("bge_jfree: asked to free buffer that we don't manage!"); 717 718 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 719 if (entry == NULL) 720 panic("bge_jfree: buffer not in use!"); 721 entry->slot = i; 722 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 723 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 724 725 return; 726 } 727 728 729 /* 730 * Intialize a standard receive ring descriptor. 731 */ 732 static int 733 bge_newbuf_std(sc, i, m) 734 struct bge_softc *sc; 735 int i; 736 struct mbuf *m; 737 { 738 struct mbuf *m_new = NULL; 739 struct bge_rx_bd *r; 740 741 if (m == NULL) { 742 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 743 if (m_new == NULL) { 744 return(ENOBUFS); 745 } 746 747 MCLGET(m_new, M_DONTWAIT); 748 if (!(m_new->m_flags & M_EXT)) { 749 m_freem(m_new); 750 return(ENOBUFS); 751 } 752 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 753 } else { 754 m_new = m; 755 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 756 m_new->m_data = m_new->m_ext.ext_buf; 757 } 758 759 if (!sc->bge_rx_alignment_bug) 760 m_adj(m_new, ETHER_ALIGN); 761 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 762 r = &sc->bge_rdata->bge_rx_std_ring[i]; 763 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 764 r->bge_flags = BGE_RXBDFLAG_END; 765 r->bge_len = m_new->m_len; 766 r->bge_idx = i; 767 768 return(0); 769 } 770 771 /* 772 * Initialize a jumbo receive ring descriptor. This allocates 773 * a jumbo buffer from the pool managed internally by the driver. 774 */ 775 static int 776 bge_newbuf_jumbo(sc, i, m) 777 struct bge_softc *sc; 778 int i; 779 struct mbuf *m; 780 { 781 struct mbuf *m_new = NULL; 782 struct bge_rx_bd *r; 783 784 if (m == NULL) { 785 caddr_t *buf = NULL; 786 787 /* Allocate the mbuf. */ 788 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 789 if (m_new == NULL) { 790 return(ENOBUFS); 791 } 792 793 /* Allocate the jumbo buffer */ 794 buf = bge_jalloc(sc); 795 if (buf == NULL) { 796 m_freem(m_new); 797 printf("bge%d: jumbo allocation failed " 798 "-- packet dropped!\n", sc->bge_unit); 799 return(ENOBUFS); 800 } 801 802 /* Attach the buffer to the mbuf. */ 803 m_new->m_data = (void *) buf; 804 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 805 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 806 (struct bge_softc *)sc, 0, EXT_NET_DRV); 807 } else { 808 m_new = m; 809 m_new->m_data = m_new->m_ext.ext_buf; 810 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 811 } 812 813 if (!sc->bge_rx_alignment_bug) 814 m_adj(m_new, ETHER_ALIGN); 815 /* Set up the descriptor. */ 816 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 817 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 818 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t))); 819 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 820 r->bge_len = m_new->m_len; 821 r->bge_idx = i; 822 823 return(0); 824 } 825 826 /* 827 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 828 * that's 1MB or memory, which is a lot. For now, we fill only the first 829 * 256 ring entries and hope that our CPU is fast enough to keep up with 830 * the NIC. 831 */ 832 static int 833 bge_init_rx_ring_std(sc) 834 struct bge_softc *sc; 835 { 836 int i; 837 838 for (i = 0; i < BGE_SSLOTS; i++) { 839 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 840 return(ENOBUFS); 841 }; 842 843 sc->bge_std = i - 1; 844 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 845 846 return(0); 847 } 848 849 static void 850 bge_free_rx_ring_std(sc) 851 struct bge_softc *sc; 852 { 853 int i; 854 855 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 856 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 857 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 858 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 859 } 860 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 861 sizeof(struct bge_rx_bd)); 862 } 863 864 return; 865 } 866 867 static int 868 bge_init_rx_ring_jumbo(sc) 869 struct bge_softc *sc; 870 { 871 int i; 872 struct bge_rcb *rcb; 873 874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 875 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 876 return(ENOBUFS); 877 }; 878 879 sc->bge_jumbo = i - 1; 880 881 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 882 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 883 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 884 885 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 886 887 return(0); 888 } 889 890 static void 891 bge_free_rx_ring_jumbo(sc) 892 struct bge_softc *sc; 893 { 894 int i; 895 896 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 897 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 898 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 899 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 900 } 901 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 902 sizeof(struct bge_rx_bd)); 903 } 904 905 return; 906 } 907 908 static void 909 bge_free_tx_ring(sc) 910 struct bge_softc *sc; 911 { 912 int i; 913 914 if (sc->bge_rdata->bge_tx_ring == NULL) 915 return; 916 917 for (i = 0; i < BGE_TX_RING_CNT; i++) { 918 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 919 m_freem(sc->bge_cdata.bge_tx_chain[i]); 920 sc->bge_cdata.bge_tx_chain[i] = NULL; 921 } 922 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 923 sizeof(struct bge_tx_bd)); 924 } 925 926 return; 927 } 928 929 static int 930 bge_init_tx_ring(sc) 931 struct bge_softc *sc; 932 { 933 sc->bge_txcnt = 0; 934 sc->bge_tx_saved_considx = 0; 935 936 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 937 /* 5700 b2 errata */ 938 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 939 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 940 941 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 942 /* 5700 b2 errata */ 943 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 944 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 945 946 return(0); 947 } 948 949 #define BGE_POLY 0xEDB88320 950 951 static u_int32_t 952 bge_crc(addr) 953 caddr_t addr; 954 { 955 u_int32_t idx, bit, data, crc; 956 957 /* Compute CRC for the address value. */ 958 crc = 0xFFFFFFFF; /* initial value */ 959 960 for (idx = 0; idx < 6; idx++) { 961 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 962 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 963 } 964 965 return(crc & 0x7F); 966 } 967 968 static void 969 bge_setmulti(sc) 970 struct bge_softc *sc; 971 { 972 struct ifnet *ifp; 973 struct ifmultiaddr *ifma; 974 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 975 int h, i; 976 977 ifp = &sc->arpcom.ac_if; 978 979 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 980 for (i = 0; i < 4; i++) 981 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 982 return; 983 } 984 985 /* First, zot all the existing filters. */ 986 for (i = 0; i < 4; i++) 987 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 988 989 /* Now program new ones. */ 990 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 991 if (ifma->ifma_addr->sa_family != AF_LINK) 992 continue; 993 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 994 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 995 } 996 997 for (i = 0; i < 4; i++) 998 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 999 1000 return; 1001 } 1002 1003 /* 1004 * Do endian, PCI and DMA initialization. Also check the on-board ROM 1005 * self-test results. 1006 */ 1007 static int 1008 bge_chipinit(sc) 1009 struct bge_softc *sc; 1010 { 1011 int i; 1012 u_int32_t dma_rw_ctl; 1013 1014 /* Set endianness before we access any non-PCI registers. */ 1015 #if BYTE_ORDER == BIG_ENDIAN 1016 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1017 BGE_BIGENDIAN_INIT, 4); 1018 #else 1019 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 1020 BGE_LITTLEENDIAN_INIT, 4); 1021 #endif 1022 1023 /* 1024 * Check the 'ROM failed' bit on the RX CPU to see if 1025 * self-tests passed. 1026 */ 1027 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 1028 printf("bge%d: RX CPU self-diagnostics failed!\n", 1029 sc->bge_unit); 1030 return(ENODEV); 1031 } 1032 1033 /* Clear the MAC control register */ 1034 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1035 1036 /* 1037 * Clear the MAC statistics block in the NIC's 1038 * internal memory. 1039 */ 1040 for (i = BGE_STATS_BLOCK; 1041 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1042 BGE_MEMWIN_WRITE(sc, i, 0); 1043 1044 for (i = BGE_STATUS_BLOCK; 1045 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1046 BGE_MEMWIN_WRITE(sc, i, 0); 1047 1048 /* Set up the PCI DMA control register. */ 1049 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1050 BGE_PCISTATE_PCI_BUSMODE) { 1051 /* Conventional PCI bus */ 1052 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1053 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1054 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1055 (0x0F); 1056 } else { 1057 /* PCI-X bus */ 1058 /* 1059 * The 5704 uses a different encoding of read/write 1060 * watermarks. 1061 */ 1062 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1063 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1064 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1065 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT); 1066 else 1067 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD | 1068 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) | 1069 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) | 1070 (0x0F); 1071 1072 /* 1073 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround 1074 * for hardware bugs. 1075 */ 1076 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1077 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1078 u_int32_t tmp; 1079 1080 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f; 1081 if (tmp == 0x6 || tmp == 0x7) 1082 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE; 1083 } 1084 } 1085 1086 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1087 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1088 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1089 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1090 1091 /* 1092 * Set up general mode register. 1093 */ 1094 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1095 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1096 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1097 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1098 BGE_MODECTL_RX_NO_PHDR_CSUM); 1099 1100 /* 1101 * Disable memory write invalidate. Apparently it is not supported 1102 * properly by these devices. 1103 */ 1104 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1105 1106 #ifdef __brokenalpha__ 1107 /* 1108 * Must insure that we do not cross an 8K (bytes) boundary 1109 * for DMA reads. Our highest limit is 1K bytes. This is a 1110 * restriction on some ALPHA platforms with early revision 1111 * 21174 PCI chipsets, such as the AlphaPC 164lx 1112 */ 1113 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1114 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1115 #endif 1116 1117 /* Set the timer prescaler (always 66Mhz) */ 1118 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1119 1120 return(0); 1121 } 1122 1123 static int 1124 bge_blockinit(sc) 1125 struct bge_softc *sc; 1126 { 1127 struct bge_rcb *rcb; 1128 volatile struct bge_rcb *vrcb; 1129 int i; 1130 1131 /* 1132 * Initialize the memory window pointer register so that 1133 * we can access the first 32K of internal NIC RAM. This will 1134 * allow us to set up the TX send ring RCBs and the RX return 1135 * ring RCBs, plus other things which live in NIC memory. 1136 */ 1137 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1138 1139 /* Configure mbuf memory pool */ 1140 if (sc->bge_extram) { 1141 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1142 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1143 } else { 1144 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1145 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1146 } 1147 1148 /* Configure DMA resource pool */ 1149 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1150 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1151 1152 /* Configure mbuf pool watermarks */ 1153 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1154 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1155 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1156 1157 /* Configure DMA resource watermarks */ 1158 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1159 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1160 1161 /* Enable buffer manager */ 1162 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1163 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1164 1165 /* Poll for buffer manager start indication */ 1166 for (i = 0; i < BGE_TIMEOUT; i++) { 1167 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1168 break; 1169 DELAY(10); 1170 } 1171 1172 if (i == BGE_TIMEOUT) { 1173 printf("bge%d: buffer manager failed to start\n", 1174 sc->bge_unit); 1175 return(ENXIO); 1176 } 1177 1178 /* Enable flow-through queues */ 1179 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1180 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1181 1182 /* Wait until queue initialization is complete */ 1183 for (i = 0; i < BGE_TIMEOUT; i++) { 1184 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1185 break; 1186 DELAY(10); 1187 } 1188 1189 if (i == BGE_TIMEOUT) { 1190 printf("bge%d: flow-through queue init failed\n", 1191 sc->bge_unit); 1192 return(ENXIO); 1193 } 1194 1195 /* Initialize the standard RX ring control block */ 1196 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1197 BGE_HOSTADDR(rcb->bge_hostaddr, 1198 vtophys(&sc->bge_rdata->bge_rx_std_ring)); 1199 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1200 if (sc->bge_extram) 1201 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1202 else 1203 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1204 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1205 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1206 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1207 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1208 1209 /* 1210 * Initialize the jumbo RX ring control block 1211 * We set the 'ring disabled' bit in the flags 1212 * field until we're actually ready to start 1213 * using this ring (i.e. once we set the MTU 1214 * high enough to require it). 1215 */ 1216 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1217 BGE_HOSTADDR(rcb->bge_hostaddr, 1218 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring)); 1219 rcb->bge_maxlen_flags = 1220 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1221 if (sc->bge_extram) 1222 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1223 else 1224 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1225 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1226 rcb->bge_hostaddr.bge_addr_hi); 1227 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1228 rcb->bge_hostaddr.bge_addr_lo); 1229 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1230 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1231 1232 /* Set up dummy disabled mini ring RCB */ 1233 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1234 rcb->bge_maxlen_flags = 1235 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1236 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1237 1238 /* 1239 * Set the BD ring replentish thresholds. The recommended 1240 * values are 1/8th the number of descriptors allocated to 1241 * each ring. 1242 */ 1243 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1244 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1245 1246 /* 1247 * Disable all unused send rings by setting the 'ring disabled' 1248 * bit in the flags field of all the TX send ring control blocks. 1249 * These are located in NIC memory. 1250 */ 1251 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1252 BGE_SEND_RING_RCB); 1253 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1254 vrcb->bge_maxlen_flags = 1255 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1256 vrcb->bge_nicaddr = 0; 1257 vrcb++; 1258 } 1259 1260 /* Configure TX RCB 0 (we use only the first ring) */ 1261 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1262 BGE_SEND_RING_RCB); 1263 vrcb->bge_hostaddr.bge_addr_hi = 0; 1264 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring)); 1265 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1266 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1267 1268 /* Disable all unused RX return rings */ 1269 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1270 BGE_RX_RETURN_RING_RCB); 1271 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1272 vrcb->bge_hostaddr.bge_addr_hi = 0; 1273 vrcb->bge_hostaddr.bge_addr_lo = 0; 1274 vrcb->bge_maxlen_flags = 1275 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1276 BGE_RCB_FLAG_RING_DISABLED); 1277 vrcb->bge_nicaddr = 0; 1278 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1279 (i * (sizeof(u_int64_t))), 0); 1280 vrcb++; 1281 } 1282 1283 /* Initialize RX ring indexes */ 1284 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1285 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1286 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1287 1288 /* 1289 * Set up RX return ring 0 1290 * Note that the NIC address for RX return rings is 0x00000000. 1291 * The return rings live entirely within the host, so the 1292 * nicaddr field in the RCB isn't used. 1293 */ 1294 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1295 BGE_RX_RETURN_RING_RCB); 1296 vrcb->bge_hostaddr.bge_addr_hi = 0; 1297 BGE_HOSTADDR(vrcb->bge_hostaddr, 1298 vtophys(&sc->bge_rdata->bge_rx_return_ring)); 1299 vrcb->bge_nicaddr = 0x00000000; 1300 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1301 1302 /* Set random backoff seed for TX */ 1303 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1304 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1305 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1306 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1307 BGE_TX_BACKOFF_SEED_MASK); 1308 1309 /* Set inter-packet gap */ 1310 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1311 1312 /* 1313 * Specify which ring to use for packets that don't match 1314 * any RX rules. 1315 */ 1316 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1317 1318 /* 1319 * Configure number of RX lists. One interrupt distribution 1320 * list, sixteen active lists, one bad frames class. 1321 */ 1322 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1323 1324 /* Inialize RX list placement stats mask. */ 1325 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1326 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1327 1328 /* Disable host coalescing until we get it set up */ 1329 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1330 1331 /* Poll to make sure it's shut down. */ 1332 for (i = 0; i < BGE_TIMEOUT; i++) { 1333 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1334 break; 1335 DELAY(10); 1336 } 1337 1338 if (i == BGE_TIMEOUT) { 1339 printf("bge%d: host coalescing engine failed to idle\n", 1340 sc->bge_unit); 1341 return(ENXIO); 1342 } 1343 1344 /* Set up host coalescing defaults */ 1345 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1346 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1347 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1348 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1349 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1350 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1351 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1352 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1353 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1354 1355 /* Set up address of statistics block */ 1356 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1357 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1358 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1359 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1360 1361 /* Set up address of status block */ 1362 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1363 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1364 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1365 vtophys(&sc->bge_rdata->bge_status_block)); 1366 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1367 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1368 1369 /* Turn on host coalescing state machine */ 1370 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1371 1372 /* Turn on RX BD completion state machine and enable attentions */ 1373 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1374 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1375 1376 /* Turn on RX list placement state machine */ 1377 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1378 1379 /* Turn on RX list selector state machine. */ 1380 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1381 1382 /* Turn on DMA, clear stats */ 1383 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1384 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1385 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1386 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1387 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1388 1389 /* Set misc. local control, enable interrupts on attentions */ 1390 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1391 1392 #ifdef notdef 1393 /* Assert GPIO pins for PHY reset */ 1394 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1395 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1396 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1397 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1398 #endif 1399 1400 /* Turn on DMA completion state machine */ 1401 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1402 1403 /* Turn on write DMA state machine */ 1404 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1405 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1406 1407 /* Turn on read DMA state machine */ 1408 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1409 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1410 1411 /* Turn on RX data completion state machine */ 1412 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1413 1414 /* Turn on RX BD initiator state machine */ 1415 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1416 1417 /* Turn on RX data and RX BD initiator state machine */ 1418 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1419 1420 /* Turn on Mbuf cluster free state machine */ 1421 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1422 1423 /* Turn on send BD completion state machine */ 1424 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1425 1426 /* Turn on send data completion state machine */ 1427 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1428 1429 /* Turn on send data initiator state machine */ 1430 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1431 1432 /* Turn on send BD initiator state machine */ 1433 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1434 1435 /* Turn on send BD selector state machine */ 1436 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1437 1438 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1439 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1440 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1441 1442 /* ack/clear link change events */ 1443 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1444 BGE_MACSTAT_CFG_CHANGED); 1445 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1446 1447 /* Enable PHY auto polling (for MII/GMII only) */ 1448 if (sc->bge_tbi) { 1449 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1450 } else { 1451 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1452 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1453 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1454 BGE_EVTENB_MI_INTERRUPT); 1455 } 1456 1457 /* Enable link state change attentions. */ 1458 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1459 1460 return(0); 1461 } 1462 1463 /* 1464 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1465 * against our list and return its name if we find a match. Note 1466 * that since the Broadcom controller contains VPD support, we 1467 * can get the device name string from the controller itself instead 1468 * of the compiled-in string. This is a little slow, but it guarantees 1469 * we'll always announce the right product name. 1470 */ 1471 static int 1472 bge_probe(dev) 1473 device_t dev; 1474 { 1475 struct bge_type *t; 1476 struct bge_softc *sc; 1477 char *descbuf; 1478 1479 t = bge_devs; 1480 1481 sc = device_get_softc(dev); 1482 bzero(sc, sizeof(struct bge_softc)); 1483 sc->bge_unit = device_get_unit(dev); 1484 sc->bge_dev = dev; 1485 1486 while(t->bge_name != NULL) { 1487 if ((pci_get_vendor(dev) == t->bge_vid) && 1488 (pci_get_device(dev) == t->bge_did)) { 1489 #ifdef notdef 1490 bge_vpd_read(sc); 1491 device_set_desc(dev, sc->bge_vpd_prodname); 1492 #endif 1493 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1494 if (descbuf == NULL) 1495 return(ENOMEM); 1496 snprintf(descbuf, BGE_DEVDESC_MAX, 1497 "%s, ASIC rev. %#04x", t->bge_name, 1498 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1499 device_set_desc_copy(dev, descbuf); 1500 free(descbuf, M_TEMP); 1501 return(0); 1502 } 1503 t++; 1504 } 1505 1506 return(ENXIO); 1507 } 1508 1509 static int 1510 bge_attach(dev) 1511 device_t dev; 1512 { 1513 int s; 1514 struct ifnet *ifp; 1515 struct bge_softc *sc; 1516 u_int32_t hwcfg = 0; 1517 u_int32_t mac_addr = 0; 1518 int unit, error = 0, rid; 1519 1520 s = splimp(); 1521 1522 sc = device_get_softc(dev); 1523 unit = device_get_unit(dev); 1524 sc->bge_dev = dev; 1525 sc->bge_unit = unit; 1526 1527 /* 1528 * Map control/status registers. 1529 */ 1530 pci_enable_busmaster(dev); 1531 1532 rid = BGE_PCI_BAR0; 1533 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1534 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1535 1536 if (sc->bge_res == NULL) { 1537 printf ("bge%d: couldn't map memory\n", unit); 1538 error = ENXIO; 1539 goto fail; 1540 } 1541 1542 sc->bge_btag = rman_get_bustag(sc->bge_res); 1543 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1544 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1545 1546 /* Allocate interrupt */ 1547 rid = 0; 1548 1549 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1550 RF_SHAREABLE | RF_ACTIVE); 1551 1552 if (sc->bge_irq == NULL) { 1553 printf("bge%d: couldn't map interrupt\n", unit); 1554 error = ENXIO; 1555 goto fail; 1556 } 1557 1558 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1559 bge_intr, sc, &sc->bge_intrhand); 1560 1561 if (error) { 1562 bge_release_resources(sc); 1563 printf("bge%d: couldn't set up irq\n", unit); 1564 goto fail; 1565 } 1566 1567 sc->bge_unit = unit; 1568 1569 /* Try to reset the chip. */ 1570 bge_reset(sc); 1571 1572 if (bge_chipinit(sc)) { 1573 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1574 bge_release_resources(sc); 1575 error = ENXIO; 1576 goto fail; 1577 } 1578 1579 /* 1580 * Get station address from the EEPROM. 1581 */ 1582 mac_addr = bge_readmem_ind(sc, 0x0c14); 1583 if ((mac_addr >> 16) == 0x484b) { 1584 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1585 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1586 mac_addr = bge_readmem_ind(sc, 0x0c18); 1587 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1588 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1589 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1590 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1591 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1592 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1593 printf("bge%d: failed to read station address\n", unit); 1594 bge_release_resources(sc); 1595 error = ENXIO; 1596 goto fail; 1597 } 1598 1599 /* 1600 * A Broadcom chip was detected. Inform the world. 1601 */ 1602 printf("bge%d: Ethernet address: %6D\n", unit, 1603 sc->arpcom.ac_enaddr, ":"); 1604 1605 /* Allocate the general information block and ring buffers. */ 1606 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1607 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1608 1609 if (sc->bge_rdata == NULL) { 1610 bge_release_resources(sc); 1611 error = ENXIO; 1612 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1613 goto fail; 1614 } 1615 1616 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1617 1618 /* Try to allocate memory for jumbo buffers. */ 1619 if (bge_alloc_jumbo_mem(sc)) { 1620 printf("bge%d: jumbo buffer allocation " 1621 "failed\n", sc->bge_unit); 1622 bge_release_resources(sc); 1623 error = ENXIO; 1624 goto fail; 1625 } 1626 1627 /* Set default tuneable values. */ 1628 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1629 sc->bge_rx_coal_ticks = 150; 1630 sc->bge_tx_coal_ticks = 150; 1631 sc->bge_rx_max_coal_bds = 64; 1632 sc->bge_tx_max_coal_bds = 128; 1633 1634 /* Set up ifnet structure */ 1635 ifp = &sc->arpcom.ac_if; 1636 ifp->if_softc = sc; 1637 ifp->if_unit = sc->bge_unit; 1638 ifp->if_name = "bge"; 1639 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1640 ifp->if_ioctl = bge_ioctl; 1641 ifp->if_output = ether_output; 1642 ifp->if_start = bge_start; 1643 ifp->if_watchdog = bge_watchdog; 1644 ifp->if_init = bge_init; 1645 ifp->if_mtu = ETHERMTU; 1646 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1647 ifp->if_hwassist = BGE_CSUM_FEATURES; 1648 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1649 ifp->if_capenable = ifp->if_capabilities; 1650 1651 /* Save ASIC rev. */ 1652 1653 sc->bge_chipid = 1654 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1655 BGE_PCIMISCCTL_ASICREV; 1656 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 1657 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 1658 1659 /* 1660 * Figure out what sort of media we have by checking the 1661 * hardware config word in the first 32k of NIC internal memory, 1662 * or fall back to examining the EEPROM if necessary. 1663 * Note: on some BCM5700 cards, this value appears to be unset. 1664 * If that's the case, we have to rely on identifying the NIC 1665 * by its PCI subsystem ID, as we do below for the SysKonnect 1666 * SK-9D41. 1667 */ 1668 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1669 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1670 else { 1671 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1672 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1673 hwcfg = ntohl(hwcfg); 1674 } 1675 1676 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1677 sc->bge_tbi = 1; 1678 1679 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1680 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1681 sc->bge_tbi = 1; 1682 1683 if (sc->bge_tbi) { 1684 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1685 bge_ifmedia_upd, bge_ifmedia_sts); 1686 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1687 ifmedia_add(&sc->bge_ifmedia, 1688 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1689 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1690 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1691 } else { 1692 /* 1693 * Do transceiver setup. 1694 */ 1695 if (mii_phy_probe(dev, &sc->bge_miibus, 1696 bge_ifmedia_upd, bge_ifmedia_sts)) { 1697 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1698 bge_release_resources(sc); 1699 bge_free_jumbo_mem(sc); 1700 error = ENXIO; 1701 goto fail; 1702 } 1703 } 1704 1705 /* 1706 * When using the BCM5701 in PCI-X mode, data corruption has 1707 * been observed in the first few bytes of some received packets. 1708 * Aligning the packet buffer in memory eliminates the corruption. 1709 * Unfortunately, this misaligns the packet payloads. On platforms 1710 * which do not support unaligned accesses, we will realign the 1711 * payloads by copying the received packets. 1712 */ 1713 switch (sc->bge_chipid) { 1714 case BGE_CHIPID_BCM5701_A0: 1715 case BGE_CHIPID_BCM5701_B0: 1716 case BGE_CHIPID_BCM5701_B2: 1717 case BGE_CHIPID_BCM5701_B5: 1718 /* If in PCI-X mode, work around the alignment bug. */ 1719 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1720 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1721 BGE_PCISTATE_PCI_BUSSPEED) 1722 sc->bge_rx_alignment_bug = 1; 1723 break; 1724 } 1725 1726 /* 1727 * Call MI attach routine. 1728 */ 1729 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1730 callout_handle_init(&sc->bge_stat_ch); 1731 1732 fail: 1733 splx(s); 1734 1735 return(error); 1736 } 1737 1738 static int 1739 bge_detach(dev) 1740 device_t dev; 1741 { 1742 struct bge_softc *sc; 1743 struct ifnet *ifp; 1744 int s; 1745 1746 s = splimp(); 1747 1748 sc = device_get_softc(dev); 1749 ifp = &sc->arpcom.ac_if; 1750 1751 ether_ifdetach(ifp); 1752 bge_stop(sc); 1753 bge_reset(sc); 1754 1755 if (sc->bge_tbi) { 1756 ifmedia_removeall(&sc->bge_ifmedia); 1757 } else { 1758 bus_generic_detach(dev); 1759 device_delete_child(dev, sc->bge_miibus); 1760 } 1761 1762 bge_release_resources(sc); 1763 bge_free_jumbo_mem(sc); 1764 1765 splx(s); 1766 1767 return(0); 1768 } 1769 1770 static void 1771 bge_release_resources(sc) 1772 struct bge_softc *sc; 1773 { 1774 device_t dev; 1775 1776 dev = sc->bge_dev; 1777 1778 if (sc->bge_vpd_prodname != NULL) 1779 free(sc->bge_vpd_prodname, M_DEVBUF); 1780 1781 if (sc->bge_vpd_readonly != NULL) 1782 free(sc->bge_vpd_readonly, M_DEVBUF); 1783 1784 if (sc->bge_intrhand != NULL) 1785 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1786 1787 if (sc->bge_irq != NULL) 1788 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1789 1790 if (sc->bge_res != NULL) 1791 bus_release_resource(dev, SYS_RES_MEMORY, 1792 BGE_PCI_BAR0, sc->bge_res); 1793 1794 if (sc->bge_rdata != NULL) 1795 contigfree(sc->bge_rdata, 1796 sizeof(struct bge_ring_data), M_DEVBUF); 1797 1798 return; 1799 } 1800 1801 static void 1802 bge_reset(sc) 1803 struct bge_softc *sc; 1804 { 1805 device_t dev; 1806 u_int32_t cachesize, command, pcistate; 1807 int i, val = 0; 1808 1809 dev = sc->bge_dev; 1810 1811 /* Save some important PCI state. */ 1812 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1813 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1814 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1815 1816 pci_write_config(dev, BGE_PCI_MISC_CTL, 1817 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1818 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1819 1820 /* Issue global reset */ 1821 bge_writereg_ind(sc, BGE_MISC_CFG, 1822 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1823 1824 DELAY(1000); 1825 1826 /* Reset some of the PCI state that got zapped by reset */ 1827 pci_write_config(dev, BGE_PCI_MISC_CTL, 1828 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1829 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1830 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1831 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1832 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1833 1834 /* 1835 * Prevent PXE restart: write a magic number to the 1836 * general communications memory at 0xB50. 1837 */ 1838 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1839 /* 1840 * Poll the value location we just wrote until 1841 * we see the 1's complement of the magic number. 1842 * This indicates that the firmware initialization 1843 * is complete. 1844 */ 1845 for (i = 0; i < BGE_TIMEOUT; i++) { 1846 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1847 if (val == ~BGE_MAGIC_NUMBER) 1848 break; 1849 DELAY(10); 1850 } 1851 1852 if (i == BGE_TIMEOUT) { 1853 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1854 return; 1855 } 1856 1857 /* 1858 * XXX Wait for the value of the PCISTATE register to 1859 * return to its original pre-reset state. This is a 1860 * fairly good indicator of reset completion. If we don't 1861 * wait for the reset to fully complete, trying to read 1862 * from the device's non-PCI registers may yield garbage 1863 * results. 1864 */ 1865 for (i = 0; i < BGE_TIMEOUT; i++) { 1866 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1867 break; 1868 DELAY(10); 1869 } 1870 1871 /* Enable memory arbiter. */ 1872 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1873 1874 /* Fix up byte swapping */ 1875 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1876 BGE_MODECTL_BYTESWAP_DATA); 1877 1878 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1879 1880 DELAY(10000); 1881 1882 return; 1883 } 1884 1885 /* 1886 * Frame reception handling. This is called if there's a frame 1887 * on the receive return list. 1888 * 1889 * Note: we have to be able to handle two possibilities here: 1890 * 1) the frame is from the jumbo recieve ring 1891 * 2) the frame is from the standard receive ring 1892 */ 1893 1894 static void 1895 bge_rxeof(sc) 1896 struct bge_softc *sc; 1897 { 1898 struct ifnet *ifp; 1899 int stdcnt = 0, jumbocnt = 0; 1900 1901 ifp = &sc->arpcom.ac_if; 1902 1903 while(sc->bge_rx_saved_considx != 1904 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1905 struct bge_rx_bd *cur_rx; 1906 u_int32_t rxidx; 1907 struct ether_header *eh; 1908 struct mbuf *m = NULL; 1909 u_int16_t vlan_tag = 0; 1910 int have_tag = 0; 1911 1912 cur_rx = 1913 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1914 1915 rxidx = cur_rx->bge_idx; 1916 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1917 1918 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1919 have_tag = 1; 1920 vlan_tag = cur_rx->bge_vlan_tag; 1921 } 1922 1923 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1924 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1925 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1926 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1927 jumbocnt++; 1928 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1929 ifp->if_ierrors++; 1930 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1931 continue; 1932 } 1933 if (bge_newbuf_jumbo(sc, 1934 sc->bge_jumbo, NULL) == ENOBUFS) { 1935 ifp->if_ierrors++; 1936 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1937 continue; 1938 } 1939 } else { 1940 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1941 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1942 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1943 stdcnt++; 1944 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1945 ifp->if_ierrors++; 1946 bge_newbuf_std(sc, sc->bge_std, m); 1947 continue; 1948 } 1949 if (bge_newbuf_std(sc, sc->bge_std, 1950 NULL) == ENOBUFS) { 1951 ifp->if_ierrors++; 1952 bge_newbuf_std(sc, sc->bge_std, m); 1953 continue; 1954 } 1955 } 1956 1957 ifp->if_ipackets++; 1958 #ifndef __i386__ 1959 /* 1960 * The i386 allows unaligned accesses, but for other 1961 * platforms we must make sure the payload is aligned. 1962 */ 1963 if (sc->bge_rx_alignment_bug) { 1964 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1965 cur_rx->bge_len); 1966 m->m_data += ETHER_ALIGN; 1967 } 1968 #endif 1969 eh = mtod(m, struct ether_header *); 1970 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1971 m->m_pkthdr.rcvif = ifp; 1972 1973 #if 0 /* currently broken for some packets, possibly related to TCP options */ 1974 if (ifp->if_hwassist) { 1975 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1976 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1977 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1978 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1979 m->m_pkthdr.csum_data = 1980 cur_rx->bge_tcp_udp_csum; 1981 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1982 } 1983 } 1984 #endif 1985 1986 /* 1987 * If we received a packet with a vlan tag, 1988 * attach that information to the packet. 1989 */ 1990 if (have_tag) 1991 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1992 1993 (*ifp->if_input)(ifp, m); 1994 } 1995 1996 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1997 if (stdcnt) 1998 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1999 if (jumbocnt) 2000 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 2001 2002 return; 2003 } 2004 2005 static void 2006 bge_txeof(sc) 2007 struct bge_softc *sc; 2008 { 2009 struct bge_tx_bd *cur_tx = NULL; 2010 struct ifnet *ifp; 2011 2012 ifp = &sc->arpcom.ac_if; 2013 2014 /* 2015 * Go through our tx ring and free mbufs for those 2016 * frames that have been sent. 2017 */ 2018 while (sc->bge_tx_saved_considx != 2019 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 2020 u_int32_t idx = 0; 2021 2022 idx = sc->bge_tx_saved_considx; 2023 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 2024 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 2025 ifp->if_opackets++; 2026 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 2027 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 2028 sc->bge_cdata.bge_tx_chain[idx] = NULL; 2029 } 2030 sc->bge_txcnt--; 2031 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 2032 ifp->if_timer = 0; 2033 } 2034 2035 if (cur_tx != NULL) 2036 ifp->if_flags &= ~IFF_OACTIVE; 2037 2038 return; 2039 } 2040 2041 static void 2042 bge_intr(xsc) 2043 void *xsc; 2044 { 2045 struct bge_softc *sc; 2046 struct ifnet *ifp; 2047 u_int32_t statusword; 2048 2049 sc = xsc; 2050 ifp = &sc->arpcom.ac_if; 2051 statusword = 2052 atomic_readandclear_32(&sc->bge_rdata->bge_status_block.bge_status); 2053 2054 #ifdef notdef 2055 /* Avoid this for now -- checking this register is expensive. */ 2056 /* Make sure this is really our interrupt. */ 2057 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2058 return; 2059 #endif 2060 /* Ack interrupt and stop others from occuring. */ 2061 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2062 2063 /* 2064 * Process link state changes. 2065 * Grrr. The link status word in the status block does 2066 * not work correctly on the BCM5700 rev AX and BX chips, 2067 * according to all avaibable information. Hence, we have 2068 * to enable MII interrupts in order to properly obtain 2069 * async link changes. Unfortunately, this also means that 2070 * we have to read the MAC status register to detect link 2071 * changes, thereby adding an additional register access to 2072 * the interrupt handler. 2073 */ 2074 2075 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2076 u_int32_t status; 2077 2078 status = CSR_READ_4(sc, BGE_MAC_STS); 2079 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2080 sc->bge_link = 0; 2081 untimeout(bge_tick, sc, sc->bge_stat_ch); 2082 bge_tick(sc); 2083 /* Clear the interrupt */ 2084 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2085 BGE_EVTENB_MI_INTERRUPT); 2086 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2087 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2088 BRGPHY_INTRS); 2089 } 2090 } else { 2091 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) { 2092 sc->bge_link = 0; 2093 untimeout(bge_tick, sc, sc->bge_stat_ch); 2094 bge_tick(sc); 2095 /* Clear the interrupt */ 2096 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2097 BGE_MACSTAT_CFG_CHANGED); 2098 2099 /* Force flush the status block cached by PCI bridge */ 2100 CSR_READ_4(sc, BGE_MBX_IRQ0_LO); 2101 } 2102 } 2103 2104 if (ifp->if_flags & IFF_RUNNING) { 2105 /* Check RX return ring producer/consumer */ 2106 bge_rxeof(sc); 2107 2108 /* Check TX ring producer/consumer */ 2109 bge_txeof(sc); 2110 } 2111 2112 bge_handle_events(sc); 2113 2114 /* Re-enable interrupts. */ 2115 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2116 2117 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2118 bge_start(ifp); 2119 2120 return; 2121 } 2122 2123 static void 2124 bge_tick(xsc) 2125 void *xsc; 2126 { 2127 struct bge_softc *sc; 2128 struct mii_data *mii = NULL; 2129 struct ifmedia *ifm = NULL; 2130 struct ifnet *ifp; 2131 int s; 2132 2133 sc = xsc; 2134 ifp = &sc->arpcom.ac_if; 2135 2136 s = splimp(); 2137 2138 bge_stats_update(sc); 2139 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2140 if (sc->bge_link) { 2141 splx(s); 2142 return; 2143 } 2144 2145 if (sc->bge_tbi) { 2146 ifm = &sc->bge_ifmedia; 2147 if (CSR_READ_4(sc, BGE_MAC_STS) & 2148 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2149 sc->bge_link++; 2150 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2151 printf("bge%d: gigabit link up\n", sc->bge_unit); 2152 if (ifp->if_snd.ifq_head != NULL) 2153 bge_start(ifp); 2154 } 2155 splx(s); 2156 return; 2157 } 2158 2159 mii = device_get_softc(sc->bge_miibus); 2160 mii_tick(mii); 2161 2162 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2163 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2164 sc->bge_link++; 2165 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2166 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2167 printf("bge%d: gigabit link up\n", 2168 sc->bge_unit); 2169 if (ifp->if_snd.ifq_head != NULL) 2170 bge_start(ifp); 2171 } 2172 2173 splx(s); 2174 2175 return; 2176 } 2177 2178 static void 2179 bge_stats_update(sc) 2180 struct bge_softc *sc; 2181 { 2182 struct ifnet *ifp; 2183 struct bge_stats *stats; 2184 2185 ifp = &sc->arpcom.ac_if; 2186 2187 stats = (struct bge_stats *)(sc->bge_vhandle + 2188 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2189 2190 ifp->if_collisions += 2191 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2192 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2193 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2194 stats->dot3StatsLateCollisions.bge_addr_lo) - 2195 ifp->if_collisions; 2196 2197 #ifdef notdef 2198 ifp->if_collisions += 2199 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2200 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2201 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2202 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2203 ifp->if_collisions; 2204 #endif 2205 2206 return; 2207 } 2208 2209 /* 2210 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2211 * pointers to descriptors. 2212 */ 2213 static int 2214 bge_encap(sc, m_head, txidx) 2215 struct bge_softc *sc; 2216 struct mbuf *m_head; 2217 u_int32_t *txidx; 2218 { 2219 struct bge_tx_bd *f = NULL; 2220 struct mbuf *m; 2221 u_int32_t frag, cur, cnt = 0; 2222 u_int16_t csum_flags = 0; 2223 struct m_tag *mtag; 2224 2225 m = m_head; 2226 cur = frag = *txidx; 2227 2228 if (m_head->m_pkthdr.csum_flags) { 2229 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2230 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2231 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2232 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2233 if (m_head->m_flags & M_LASTFRAG) 2234 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2235 else if (m_head->m_flags & M_FRAG) 2236 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2237 } 2238 2239 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2240 2241 /* 2242 * Start packing the mbufs in this chain into 2243 * the fragment pointers. Stop when we run out 2244 * of fragments or hit the end of the mbuf chain. 2245 */ 2246 for (m = m_head; m != NULL; m = m->m_next) { 2247 if (m->m_len != 0) { 2248 f = &sc->bge_rdata->bge_tx_ring[frag]; 2249 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2250 break; 2251 BGE_HOSTADDR(f->bge_addr, 2252 vtophys(mtod(m, vm_offset_t))); 2253 f->bge_len = m->m_len; 2254 f->bge_flags = csum_flags; 2255 if (mtag != NULL) { 2256 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2257 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2258 } else { 2259 f->bge_vlan_tag = 0; 2260 } 2261 /* 2262 * Sanity check: avoid coming within 16 descriptors 2263 * of the end of the ring. 2264 */ 2265 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2266 return(ENOBUFS); 2267 cur = frag; 2268 BGE_INC(frag, BGE_TX_RING_CNT); 2269 cnt++; 2270 } 2271 } 2272 2273 if (m != NULL) 2274 return(ENOBUFS); 2275 2276 if (frag == sc->bge_tx_saved_considx) 2277 return(ENOBUFS); 2278 2279 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2280 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2281 sc->bge_txcnt += cnt; 2282 2283 *txidx = frag; 2284 2285 return(0); 2286 } 2287 2288 /* 2289 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2290 * to the mbuf data regions directly in the transmit descriptors. 2291 */ 2292 static void 2293 bge_start(ifp) 2294 struct ifnet *ifp; 2295 { 2296 struct bge_softc *sc; 2297 struct mbuf *m_head = NULL; 2298 u_int32_t prodidx = 0; 2299 2300 sc = ifp->if_softc; 2301 2302 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2303 return; 2304 2305 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2306 2307 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2308 IF_DEQUEUE(&ifp->if_snd, m_head); 2309 if (m_head == NULL) 2310 break; 2311 2312 /* 2313 * XXX 2314 * safety overkill. If this is a fragmented packet chain 2315 * with delayed TCP/UDP checksums, then only encapsulate 2316 * it if we have enough descriptors to handle the entire 2317 * chain at once. 2318 * (paranoia -- may not actually be needed) 2319 */ 2320 if (m_head->m_flags & M_FIRSTFRAG && 2321 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2322 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2323 m_head->m_pkthdr.csum_data + 16) { 2324 IF_PREPEND(&ifp->if_snd, m_head); 2325 ifp->if_flags |= IFF_OACTIVE; 2326 break; 2327 } 2328 } 2329 2330 /* 2331 * Pack the data into the transmit ring. If we 2332 * don't have room, set the OACTIVE flag and wait 2333 * for the NIC to drain the ring. 2334 */ 2335 if (bge_encap(sc, m_head, &prodidx)) { 2336 IF_PREPEND(&ifp->if_snd, m_head); 2337 ifp->if_flags |= IFF_OACTIVE; 2338 break; 2339 } 2340 2341 /* 2342 * If there's a BPF listener, bounce a copy of this frame 2343 * to him. 2344 */ 2345 BPF_MTAP(ifp, m_head); 2346 } 2347 2348 /* Transmit */ 2349 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2350 /* 5700 b2 errata */ 2351 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 2352 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2353 2354 /* 2355 * Set a timeout in case the chip goes out to lunch. 2356 */ 2357 ifp->if_timer = 5; 2358 2359 return; 2360 } 2361 2362 static void 2363 bge_init(xsc) 2364 void *xsc; 2365 { 2366 struct bge_softc *sc = xsc; 2367 struct ifnet *ifp; 2368 u_int16_t *m; 2369 int s; 2370 2371 s = splimp(); 2372 2373 ifp = &sc->arpcom.ac_if; 2374 2375 if (ifp->if_flags & IFF_RUNNING) { 2376 splx(s); 2377 return; 2378 } 2379 2380 /* Cancel pending I/O and flush buffers. */ 2381 bge_stop(sc); 2382 bge_reset(sc); 2383 bge_chipinit(sc); 2384 2385 /* 2386 * Init the various state machines, ring 2387 * control blocks and firmware. 2388 */ 2389 if (bge_blockinit(sc)) { 2390 printf("bge%d: initialization failure\n", sc->bge_unit); 2391 splx(s); 2392 return; 2393 } 2394 2395 ifp = &sc->arpcom.ac_if; 2396 2397 /* Specify MTU. */ 2398 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2399 ETHER_HDR_LEN + ETHER_CRC_LEN); 2400 2401 /* Load our MAC address. */ 2402 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2403 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2404 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2405 2406 /* Enable or disable promiscuous mode as needed. */ 2407 if (ifp->if_flags & IFF_PROMISC) { 2408 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2409 } else { 2410 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2411 } 2412 2413 /* Program multicast filter. */ 2414 bge_setmulti(sc); 2415 2416 /* Init RX ring. */ 2417 bge_init_rx_ring_std(sc); 2418 2419 /* Init jumbo RX ring. */ 2420 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2421 bge_init_rx_ring_jumbo(sc); 2422 2423 /* Init our RX return ring index */ 2424 sc->bge_rx_saved_considx = 0; 2425 2426 /* Init TX ring. */ 2427 bge_init_tx_ring(sc); 2428 2429 /* Turn on transmitter */ 2430 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2431 2432 /* Turn on receiver */ 2433 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2434 2435 /* Tell firmware we're alive. */ 2436 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2437 2438 /* Enable host interrupts. */ 2439 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2440 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2441 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2442 2443 bge_ifmedia_upd(ifp); 2444 2445 ifp->if_flags |= IFF_RUNNING; 2446 ifp->if_flags &= ~IFF_OACTIVE; 2447 2448 splx(s); 2449 2450 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2451 2452 return; 2453 } 2454 2455 /* 2456 * Set media options. 2457 */ 2458 static int 2459 bge_ifmedia_upd(ifp) 2460 struct ifnet *ifp; 2461 { 2462 struct bge_softc *sc; 2463 struct mii_data *mii; 2464 struct ifmedia *ifm; 2465 2466 sc = ifp->if_softc; 2467 ifm = &sc->bge_ifmedia; 2468 2469 /* If this is a 1000baseX NIC, enable the TBI port. */ 2470 if (sc->bge_tbi) { 2471 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2472 return(EINVAL); 2473 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2474 case IFM_AUTO: 2475 break; 2476 case IFM_1000_SX: 2477 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2478 BGE_CLRBIT(sc, BGE_MAC_MODE, 2479 BGE_MACMODE_HALF_DUPLEX); 2480 } else { 2481 BGE_SETBIT(sc, BGE_MAC_MODE, 2482 BGE_MACMODE_HALF_DUPLEX); 2483 } 2484 break; 2485 default: 2486 return(EINVAL); 2487 } 2488 return(0); 2489 } 2490 2491 mii = device_get_softc(sc->bge_miibus); 2492 sc->bge_link = 0; 2493 if (mii->mii_instance) { 2494 struct mii_softc *miisc; 2495 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2496 miisc = LIST_NEXT(miisc, mii_list)) 2497 mii_phy_reset(miisc); 2498 } 2499 mii_mediachg(mii); 2500 2501 return(0); 2502 } 2503 2504 /* 2505 * Report current media status. 2506 */ 2507 static void 2508 bge_ifmedia_sts(ifp, ifmr) 2509 struct ifnet *ifp; 2510 struct ifmediareq *ifmr; 2511 { 2512 struct bge_softc *sc; 2513 struct mii_data *mii; 2514 2515 sc = ifp->if_softc; 2516 2517 if (sc->bge_tbi) { 2518 ifmr->ifm_status = IFM_AVALID; 2519 ifmr->ifm_active = IFM_ETHER; 2520 if (CSR_READ_4(sc, BGE_MAC_STS) & 2521 BGE_MACSTAT_TBI_PCS_SYNCHED) 2522 ifmr->ifm_status |= IFM_ACTIVE; 2523 ifmr->ifm_active |= IFM_1000_SX; 2524 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2525 ifmr->ifm_active |= IFM_HDX; 2526 else 2527 ifmr->ifm_active |= IFM_FDX; 2528 return; 2529 } 2530 2531 mii = device_get_softc(sc->bge_miibus); 2532 mii_pollstat(mii); 2533 ifmr->ifm_active = mii->mii_media_active; 2534 ifmr->ifm_status = mii->mii_media_status; 2535 2536 return; 2537 } 2538 2539 static int 2540 bge_ioctl(ifp, command, data) 2541 struct ifnet *ifp; 2542 u_long command; 2543 caddr_t data; 2544 { 2545 struct bge_softc *sc = ifp->if_softc; 2546 struct ifreq *ifr = (struct ifreq *) data; 2547 int s, mask, error = 0; 2548 struct mii_data *mii; 2549 2550 s = splimp(); 2551 2552 switch(command) { 2553 case SIOCSIFMTU: 2554 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2555 error = EINVAL; 2556 else { 2557 ifp->if_mtu = ifr->ifr_mtu; 2558 ifp->if_flags &= ~IFF_RUNNING; 2559 bge_init(sc); 2560 } 2561 break; 2562 case SIOCSIFFLAGS: 2563 if (ifp->if_flags & IFF_UP) { 2564 /* 2565 * If only the state of the PROMISC flag changed, 2566 * then just use the 'set promisc mode' command 2567 * instead of reinitializing the entire NIC. Doing 2568 * a full re-init means reloading the firmware and 2569 * waiting for it to start up, which may take a 2570 * second or two. 2571 */ 2572 if (ifp->if_flags & IFF_RUNNING && 2573 ifp->if_flags & IFF_PROMISC && 2574 !(sc->bge_if_flags & IFF_PROMISC)) { 2575 BGE_SETBIT(sc, BGE_RX_MODE, 2576 BGE_RXMODE_RX_PROMISC); 2577 } else if (ifp->if_flags & IFF_RUNNING && 2578 !(ifp->if_flags & IFF_PROMISC) && 2579 sc->bge_if_flags & IFF_PROMISC) { 2580 BGE_CLRBIT(sc, BGE_RX_MODE, 2581 BGE_RXMODE_RX_PROMISC); 2582 } else 2583 bge_init(sc); 2584 } else { 2585 if (ifp->if_flags & IFF_RUNNING) { 2586 bge_stop(sc); 2587 } 2588 } 2589 sc->bge_if_flags = ifp->if_flags; 2590 error = 0; 2591 break; 2592 case SIOCADDMULTI: 2593 case SIOCDELMULTI: 2594 if (ifp->if_flags & IFF_RUNNING) { 2595 bge_setmulti(sc); 2596 error = 0; 2597 } 2598 break; 2599 case SIOCSIFMEDIA: 2600 case SIOCGIFMEDIA: 2601 if (sc->bge_tbi) { 2602 error = ifmedia_ioctl(ifp, ifr, 2603 &sc->bge_ifmedia, command); 2604 } else { 2605 mii = device_get_softc(sc->bge_miibus); 2606 error = ifmedia_ioctl(ifp, ifr, 2607 &mii->mii_media, command); 2608 } 2609 break; 2610 case SIOCSIFCAP: 2611 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2612 if (mask & IFCAP_HWCSUM) { 2613 if (IFCAP_HWCSUM & ifp->if_capenable) 2614 ifp->if_capenable &= ~IFCAP_HWCSUM; 2615 else 2616 ifp->if_capenable |= IFCAP_HWCSUM; 2617 } 2618 error = 0; 2619 break; 2620 default: 2621 error = ether_ioctl(ifp, command, data); 2622 break; 2623 } 2624 2625 (void)splx(s); 2626 2627 return(error); 2628 } 2629 2630 static void 2631 bge_watchdog(ifp) 2632 struct ifnet *ifp; 2633 { 2634 struct bge_softc *sc; 2635 2636 sc = ifp->if_softc; 2637 2638 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2639 2640 ifp->if_flags &= ~IFF_RUNNING; 2641 bge_init(sc); 2642 2643 ifp->if_oerrors++; 2644 2645 return; 2646 } 2647 2648 /* 2649 * Stop the adapter and free any mbufs allocated to the 2650 * RX and TX lists. 2651 */ 2652 static void 2653 bge_stop(sc) 2654 struct bge_softc *sc; 2655 { 2656 struct ifnet *ifp; 2657 struct ifmedia_entry *ifm; 2658 struct mii_data *mii = NULL; 2659 int mtmp, itmp; 2660 2661 ifp = &sc->arpcom.ac_if; 2662 2663 if (!sc->bge_tbi) 2664 mii = device_get_softc(sc->bge_miibus); 2665 2666 untimeout(bge_tick, sc, sc->bge_stat_ch); 2667 2668 /* 2669 * Disable all of the receiver blocks 2670 */ 2671 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2672 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2673 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2674 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2675 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2676 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2677 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2678 2679 /* 2680 * Disable all of the transmit blocks 2681 */ 2682 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2683 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2684 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2685 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2686 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2687 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2688 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2689 2690 /* 2691 * Shut down all of the memory managers and related 2692 * state machines. 2693 */ 2694 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2695 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2696 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2697 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2698 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2699 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2700 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2701 2702 /* Disable host interrupts. */ 2703 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2704 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2705 2706 /* 2707 * Tell firmware we're shutting down. 2708 */ 2709 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2710 2711 /* Free the RX lists. */ 2712 bge_free_rx_ring_std(sc); 2713 2714 /* Free jumbo RX list. */ 2715 bge_free_rx_ring_jumbo(sc); 2716 2717 /* Free TX buffers. */ 2718 bge_free_tx_ring(sc); 2719 2720 /* 2721 * Isolate/power down the PHY, but leave the media selection 2722 * unchanged so that things will be put back to normal when 2723 * we bring the interface back up. 2724 */ 2725 if (!sc->bge_tbi) { 2726 itmp = ifp->if_flags; 2727 ifp->if_flags |= IFF_UP; 2728 ifm = mii->mii_media.ifm_cur; 2729 mtmp = ifm->ifm_media; 2730 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2731 mii_mediachg(mii); 2732 ifm->ifm_media = mtmp; 2733 ifp->if_flags = itmp; 2734 } 2735 2736 sc->bge_link = 0; 2737 2738 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2739 2740 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2741 2742 return; 2743 } 2744 2745 /* 2746 * Stop all chip I/O so that the kernel's probe routines don't 2747 * get confused by errant DMAs when rebooting. 2748 */ 2749 static void 2750 bge_shutdown(dev) 2751 device_t dev; 2752 { 2753 struct bge_softc *sc; 2754 2755 sc = device_get_softc(dev); 2756 2757 bge_stop(sc); 2758 bge_reset(sc); 2759 2760 return; 2761 } 2762