1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_arp.h> 87 #include <net/ethernet.h> 88 #include <net/if_dl.h> 89 #include <net/if_media.h> 90 91 #include <net/bpf.h> 92 93 #include <net/if_types.h> 94 #include <net/if_vlan_var.h> 95 96 #include <netinet/in_systm.h> 97 #include <netinet/in.h> 98 #include <netinet/ip.h> 99 #include <netinet/tcp.h> 100 101 #include <machine/bus.h> 102 #include <machine/resource.h> 103 #include <sys/bus.h> 104 #include <sys/rman.h> 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 #include "miidevs.h" 109 #include <dev/mii/brgphyreg.h> 110 111 #ifdef __sparc64__ 112 #include <dev/ofw/ofw_bus.h> 113 #include <dev/ofw/openfirm.h> 114 #include <machine/ofw_machdep.h> 115 #include <machine/ver.h> 116 #endif 117 118 #include <dev/pci/pcireg.h> 119 #include <dev/pci/pcivar.h> 120 121 #include <dev/bge/if_bgereg.h> 122 123 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 124 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 125 126 MODULE_DEPEND(bge, pci, 1, 1, 1); 127 MODULE_DEPEND(bge, ether, 1, 1, 1); 128 MODULE_DEPEND(bge, miibus, 1, 1, 1); 129 130 /* "device miibus" required. See GENERIC if you get errors here. */ 131 #include "miibus_if.h" 132 133 /* 134 * Various supported device vendors/types and their names. Note: the 135 * spec seems to indicate that the hardware still has Alteon's vendor 136 * ID burned into it, though it will always be overriden by the vendor 137 * ID in the EEPROM. Just to be safe, we cover all possibilities. 138 */ 139 static const struct bge_type { 140 uint16_t bge_vid; 141 uint16_t bge_did; 142 } bge_devs[] = { 143 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 145 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 149 150 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 151 152 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 218 219 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 220 221 { TC_VENDORID, TC_DEVICEID_3C996 }, 222 223 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 224 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 225 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 226 227 { 0, 0 } 228 }; 229 230 static const struct bge_vendor { 231 uint16_t v_id; 232 const char *v_name; 233 } bge_vendors[] = { 234 { ALTEON_VENDORID, "Alteon" }, 235 { ALTIMA_VENDORID, "Altima" }, 236 { APPLE_VENDORID, "Apple" }, 237 { BCOM_VENDORID, "Broadcom" }, 238 { SK_VENDORID, "SysKonnect" }, 239 { TC_VENDORID, "3Com" }, 240 { FJTSU_VENDORID, "Fujitsu" }, 241 242 { 0, NULL } 243 }; 244 245 static const struct bge_revision { 246 uint32_t br_chipid; 247 const char *br_name; 248 } bge_revisions[] = { 249 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 250 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 251 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 252 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 253 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 254 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 255 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 256 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 257 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 258 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 259 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 260 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 261 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 262 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 263 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 264 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 265 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 266 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 267 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 268 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 269 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 270 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 271 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 272 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 273 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 274 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 275 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 276 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 277 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 278 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 279 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 280 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 281 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 282 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 283 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 284 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 285 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 286 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 287 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 288 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 289 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 290 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 291 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 292 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 293 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 294 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 295 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 296 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 297 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 298 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 299 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 300 /* 5754 and 5787 share the same ASIC ID */ 301 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 302 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 303 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 304 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 305 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 306 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 307 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 308 309 { 0, NULL } 310 }; 311 312 /* 313 * Some defaults for major revisions, so that newer steppings 314 * that we don't know about have a shot at working. 315 */ 316 static const struct bge_revision bge_majorrevs[] = { 317 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 318 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 319 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 320 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 321 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 322 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 323 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 324 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 325 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 326 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 327 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 328 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 329 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 330 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 331 /* 5754 and 5787 share the same ASIC ID */ 332 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 333 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 334 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 335 336 { 0, NULL } 337 }; 338 339 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 340 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 341 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 342 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 343 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 344 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 345 346 const struct bge_revision * bge_lookup_rev(uint32_t); 347 const struct bge_vendor * bge_lookup_vendor(uint16_t); 348 349 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 350 351 static int bge_probe(device_t); 352 static int bge_attach(device_t); 353 static int bge_detach(device_t); 354 static int bge_suspend(device_t); 355 static int bge_resume(device_t); 356 static void bge_release_resources(struct bge_softc *); 357 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 358 static int bge_dma_alloc(device_t); 359 static void bge_dma_free(struct bge_softc *); 360 361 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 362 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 363 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 364 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 365 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 366 367 static void bge_txeof(struct bge_softc *, uint16_t); 368 static int bge_rxeof(struct bge_softc *, uint16_t, int); 369 370 static void bge_asf_driver_up (struct bge_softc *); 371 static void bge_tick(void *); 372 static void bge_stats_update(struct bge_softc *); 373 static void bge_stats_update_regs(struct bge_softc *); 374 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 375 uint16_t *); 376 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 377 378 static void bge_intr(void *); 379 static int bge_msi_intr(void *); 380 static void bge_intr_task(void *, int); 381 static void bge_start_locked(struct ifnet *); 382 static void bge_start(struct ifnet *); 383 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 384 static void bge_init_locked(struct bge_softc *); 385 static void bge_init(void *); 386 static void bge_stop(struct bge_softc *); 387 static void bge_watchdog(struct bge_softc *); 388 static int bge_shutdown(device_t); 389 static int bge_ifmedia_upd_locked(struct ifnet *); 390 static int bge_ifmedia_upd(struct ifnet *); 391 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 392 393 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 394 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 395 396 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 397 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 398 399 static void bge_setpromisc(struct bge_softc *); 400 static void bge_setmulti(struct bge_softc *); 401 static void bge_setvlan(struct bge_softc *); 402 403 static __inline void bge_rxreuse_std(struct bge_softc *, int); 404 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 405 static int bge_newbuf_std(struct bge_softc *, int); 406 static int bge_newbuf_jumbo(struct bge_softc *, int); 407 static int bge_init_rx_ring_std(struct bge_softc *); 408 static void bge_free_rx_ring_std(struct bge_softc *); 409 static int bge_init_rx_ring_jumbo(struct bge_softc *); 410 static void bge_free_rx_ring_jumbo(struct bge_softc *); 411 static void bge_free_tx_ring(struct bge_softc *); 412 static int bge_init_tx_ring(struct bge_softc *); 413 414 static int bge_chipinit(struct bge_softc *); 415 static int bge_blockinit(struct bge_softc *); 416 417 static int bge_has_eaddr(struct bge_softc *); 418 static uint32_t bge_readmem_ind(struct bge_softc *, int); 419 static void bge_writemem_ind(struct bge_softc *, int, int); 420 static void bge_writembx(struct bge_softc *, int, int); 421 #ifdef notdef 422 static uint32_t bge_readreg_ind(struct bge_softc *, int); 423 #endif 424 static void bge_writemem_direct(struct bge_softc *, int, int); 425 static void bge_writereg_ind(struct bge_softc *, int, int); 426 427 static int bge_miibus_readreg(device_t, int, int); 428 static int bge_miibus_writereg(device_t, int, int, int); 429 static void bge_miibus_statchg(device_t); 430 #ifdef DEVICE_POLLING 431 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 432 #endif 433 434 #define BGE_RESET_START 1 435 #define BGE_RESET_STOP 2 436 static void bge_sig_post_reset(struct bge_softc *, int); 437 static void bge_sig_legacy(struct bge_softc *, int); 438 static void bge_sig_pre_reset(struct bge_softc *, int); 439 static void bge_stop_fw(struct bge_softc *); 440 static int bge_reset(struct bge_softc *); 441 static void bge_link_upd(struct bge_softc *); 442 443 /* 444 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 445 * leak information to untrusted users. It is also known to cause alignment 446 * traps on certain architectures. 447 */ 448 #ifdef BGE_REGISTER_DEBUG 449 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 450 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 451 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 452 #endif 453 static void bge_add_sysctls(struct bge_softc *); 454 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 455 456 static device_method_t bge_methods[] = { 457 /* Device interface */ 458 DEVMETHOD(device_probe, bge_probe), 459 DEVMETHOD(device_attach, bge_attach), 460 DEVMETHOD(device_detach, bge_detach), 461 DEVMETHOD(device_shutdown, bge_shutdown), 462 DEVMETHOD(device_suspend, bge_suspend), 463 DEVMETHOD(device_resume, bge_resume), 464 465 /* bus interface */ 466 DEVMETHOD(bus_print_child, bus_generic_print_child), 467 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 468 469 /* MII interface */ 470 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 471 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 472 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 473 474 { 0, 0 } 475 }; 476 477 static driver_t bge_driver = { 478 "bge", 479 bge_methods, 480 sizeof(struct bge_softc) 481 }; 482 483 static devclass_t bge_devclass; 484 485 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 486 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 487 488 static int bge_allow_asf = 1; 489 490 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 491 492 SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 493 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 494 "Allow ASF mode if available"); 495 496 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 497 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 498 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 499 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 500 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 501 502 static int 503 bge_has_eaddr(struct bge_softc *sc) 504 { 505 #ifdef __sparc64__ 506 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 507 device_t dev; 508 uint32_t subvendor; 509 510 dev = sc->bge_dev; 511 512 /* 513 * The on-board BGEs found in sun4u machines aren't fitted with 514 * an EEPROM which means that we have to obtain the MAC address 515 * via OFW and that some tests will always fail. We distinguish 516 * such BGEs by the subvendor ID, which also has to be obtained 517 * from OFW instead of the PCI configuration space as the latter 518 * indicates Broadcom as the subvendor of the netboot interface. 519 * For early Blade 1500 and 2500 we even have to check the OFW 520 * device path as the subvendor ID always defaults to Broadcom 521 * there. 522 */ 523 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 524 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 525 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 526 return (0); 527 memset(buf, 0, sizeof(buf)); 528 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 529 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 530 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 531 return (0); 532 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 533 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 534 return (0); 535 } 536 #endif 537 return (1); 538 } 539 540 static uint32_t 541 bge_readmem_ind(struct bge_softc *sc, int off) 542 { 543 device_t dev; 544 uint32_t val; 545 546 dev = sc->bge_dev; 547 548 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 549 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 550 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 551 return (val); 552 } 553 554 static void 555 bge_writemem_ind(struct bge_softc *sc, int off, int val) 556 { 557 device_t dev; 558 559 dev = sc->bge_dev; 560 561 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 562 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 563 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 564 } 565 566 #ifdef notdef 567 static uint32_t 568 bge_readreg_ind(struct bge_softc *sc, int off) 569 { 570 device_t dev; 571 572 dev = sc->bge_dev; 573 574 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 575 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 576 } 577 #endif 578 579 static void 580 bge_writereg_ind(struct bge_softc *sc, int off, int val) 581 { 582 device_t dev; 583 584 dev = sc->bge_dev; 585 586 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 587 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 588 } 589 590 static void 591 bge_writemem_direct(struct bge_softc *sc, int off, int val) 592 { 593 CSR_WRITE_4(sc, off, val); 594 } 595 596 static void 597 bge_writembx(struct bge_softc *sc, int off, int val) 598 { 599 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 600 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 601 602 CSR_WRITE_4(sc, off, val); 603 } 604 605 /* 606 * Map a single buffer address. 607 */ 608 609 static void 610 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 611 { 612 struct bge_dmamap_arg *ctx; 613 614 if (error) 615 return; 616 617 ctx = arg; 618 619 if (nseg > ctx->bge_maxsegs) { 620 ctx->bge_maxsegs = 0; 621 return; 622 } 623 624 ctx->bge_busaddr = segs->ds_addr; 625 } 626 627 static uint8_t 628 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 629 { 630 uint32_t access, byte = 0; 631 int i; 632 633 /* Lock. */ 634 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 635 for (i = 0; i < 8000; i++) { 636 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 637 break; 638 DELAY(20); 639 } 640 if (i == 8000) 641 return (1); 642 643 /* Enable access. */ 644 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 645 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 646 647 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 648 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 649 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 650 DELAY(10); 651 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 652 DELAY(10); 653 break; 654 } 655 } 656 657 if (i == BGE_TIMEOUT * 10) { 658 if_printf(sc->bge_ifp, "nvram read timed out\n"); 659 return (1); 660 } 661 662 /* Get result. */ 663 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 664 665 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 666 667 /* Disable access. */ 668 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 669 670 /* Unlock. */ 671 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 672 CSR_READ_4(sc, BGE_NVRAM_SWARB); 673 674 return (0); 675 } 676 677 /* 678 * Read a sequence of bytes from NVRAM. 679 */ 680 static int 681 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 682 { 683 int err = 0, i; 684 uint8_t byte = 0; 685 686 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 687 return (1); 688 689 for (i = 0; i < cnt; i++) { 690 err = bge_nvram_getbyte(sc, off + i, &byte); 691 if (err) 692 break; 693 *(dest + i) = byte; 694 } 695 696 return (err ? 1 : 0); 697 } 698 699 /* 700 * Read a byte of data stored in the EEPROM at address 'addr.' The 701 * BCM570x supports both the traditional bitbang interface and an 702 * auto access interface for reading the EEPROM. We use the auto 703 * access method. 704 */ 705 static uint8_t 706 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 707 { 708 int i; 709 uint32_t byte = 0; 710 711 /* 712 * Enable use of auto EEPROM access so we can avoid 713 * having to use the bitbang method. 714 */ 715 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 716 717 /* Reset the EEPROM, load the clock period. */ 718 CSR_WRITE_4(sc, BGE_EE_ADDR, 719 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 720 DELAY(20); 721 722 /* Issue the read EEPROM command. */ 723 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 724 725 /* Wait for completion */ 726 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 727 DELAY(10); 728 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 729 break; 730 } 731 732 if (i == BGE_TIMEOUT * 10) { 733 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 734 return (1); 735 } 736 737 /* Get result. */ 738 byte = CSR_READ_4(sc, BGE_EE_DATA); 739 740 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 741 742 return (0); 743 } 744 745 /* 746 * Read a sequence of bytes from the EEPROM. 747 */ 748 static int 749 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 750 { 751 int i, error = 0; 752 uint8_t byte = 0; 753 754 for (i = 0; i < cnt; i++) { 755 error = bge_eeprom_getbyte(sc, off + i, &byte); 756 if (error) 757 break; 758 *(dest + i) = byte; 759 } 760 761 return (error ? 1 : 0); 762 } 763 764 static int 765 bge_miibus_readreg(device_t dev, int phy, int reg) 766 { 767 struct bge_softc *sc; 768 uint32_t val, autopoll; 769 int i; 770 771 sc = device_get_softc(dev); 772 773 /* 774 * Broadcom's own driver always assumes the internal 775 * PHY is at GMII address 1. On some chips, the PHY responds 776 * to accesses at all addresses, which could cause us to 777 * bogusly attach the PHY 32 times at probe type. Always 778 * restricting the lookup to address 1 is simpler than 779 * trying to figure out which chips revisions should be 780 * special-cased. 781 */ 782 if (phy != 1) 783 return (0); 784 785 /* Reading with autopolling on may trigger PCI errors */ 786 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 787 if (autopoll & BGE_MIMODE_AUTOPOLL) { 788 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 789 DELAY(40); 790 } 791 792 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 793 BGE_MIPHY(phy) | BGE_MIREG(reg)); 794 795 for (i = 0; i < BGE_TIMEOUT; i++) { 796 DELAY(10); 797 val = CSR_READ_4(sc, BGE_MI_COMM); 798 if (!(val & BGE_MICOMM_BUSY)) 799 break; 800 } 801 802 if (i == BGE_TIMEOUT) { 803 device_printf(sc->bge_dev, 804 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 805 phy, reg, val); 806 val = 0; 807 goto done; 808 } 809 810 DELAY(5); 811 val = CSR_READ_4(sc, BGE_MI_COMM); 812 813 done: 814 if (autopoll & BGE_MIMODE_AUTOPOLL) { 815 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 816 DELAY(40); 817 } 818 819 if (val & BGE_MICOMM_READFAIL) 820 return (0); 821 822 return (val & 0xFFFF); 823 } 824 825 static int 826 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 827 { 828 struct bge_softc *sc; 829 uint32_t autopoll; 830 int i; 831 832 sc = device_get_softc(dev); 833 834 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 835 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 836 return (0); 837 838 /* Reading with autopolling on may trigger PCI errors */ 839 autopoll = CSR_READ_4(sc, BGE_MI_MODE); 840 if (autopoll & BGE_MIMODE_AUTOPOLL) { 841 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 842 DELAY(40); 843 } 844 845 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 846 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 847 848 for (i = 0; i < BGE_TIMEOUT; i++) { 849 DELAY(10); 850 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 851 DELAY(5); 852 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 853 break; 854 } 855 } 856 857 if (i == BGE_TIMEOUT) { 858 device_printf(sc->bge_dev, 859 "PHY write timed out (phy %d, reg %d, val %d)\n", 860 phy, reg, val); 861 return (0); 862 } 863 864 if (autopoll & BGE_MIMODE_AUTOPOLL) { 865 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 866 DELAY(40); 867 } 868 869 return (0); 870 } 871 872 static void 873 bge_miibus_statchg(device_t dev) 874 { 875 struct bge_softc *sc; 876 struct mii_data *mii; 877 sc = device_get_softc(dev); 878 mii = device_get_softc(sc->bge_miibus); 879 880 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 881 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 882 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 883 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 884 else 885 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 886 887 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 888 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 889 else 890 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 891 } 892 893 /* 894 * Intialize a standard receive ring descriptor. 895 */ 896 static int 897 bge_newbuf_std(struct bge_softc *sc, int i) 898 { 899 struct mbuf *m; 900 struct bge_rx_bd *r; 901 bus_dma_segment_t segs[1]; 902 bus_dmamap_t map; 903 int error, nsegs; 904 905 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 906 if (m == NULL) 907 return (ENOBUFS); 908 m->m_len = m->m_pkthdr.len = MCLBYTES; 909 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 910 m_adj(m, ETHER_ALIGN); 911 912 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 913 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 914 if (error != 0) { 915 m_freem(m); 916 return (error); 917 } 918 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 919 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 920 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 921 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 922 sc->bge_cdata.bge_rx_std_dmamap[i]); 923 } 924 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 925 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 926 sc->bge_cdata.bge_rx_std_sparemap = map; 927 sc->bge_cdata.bge_rx_std_chain[i] = m; 928 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 929 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 930 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 931 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 932 r->bge_flags = BGE_RXBDFLAG_END; 933 r->bge_len = segs[0].ds_len; 934 r->bge_idx = i; 935 936 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 937 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 938 939 return (0); 940 } 941 942 /* 943 * Initialize a jumbo receive ring descriptor. This allocates 944 * a jumbo buffer from the pool managed internally by the driver. 945 */ 946 static int 947 bge_newbuf_jumbo(struct bge_softc *sc, int i) 948 { 949 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 950 bus_dmamap_t map; 951 struct bge_extrx_bd *r; 952 struct mbuf *m; 953 int error, nsegs; 954 955 MGETHDR(m, M_DONTWAIT, MT_DATA); 956 if (m == NULL) 957 return (ENOBUFS); 958 959 m_cljget(m, M_DONTWAIT, MJUM9BYTES); 960 if (!(m->m_flags & M_EXT)) { 961 m_freem(m); 962 return (ENOBUFS); 963 } 964 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 965 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 966 m_adj(m, ETHER_ALIGN); 967 968 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 969 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 970 if (error != 0) { 971 m_freem(m); 972 return (error); 973 } 974 975 if (sc->bge_cdata.bge_rx_jumbo_chain[i] == NULL) { 976 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 977 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 978 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 979 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 980 } 981 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 982 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 983 sc->bge_cdata.bge_rx_jumbo_sparemap; 984 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 985 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 986 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 987 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 988 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 989 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 990 991 /* 992 * Fill in the extended RX buffer descriptor. 993 */ 994 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 995 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 996 r->bge_idx = i; 997 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 998 switch (nsegs) { 999 case 4: 1000 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1001 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1002 r->bge_len3 = segs[3].ds_len; 1003 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1004 case 3: 1005 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1006 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1007 r->bge_len2 = segs[2].ds_len; 1008 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1009 case 2: 1010 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1011 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1012 r->bge_len1 = segs[1].ds_len; 1013 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1014 case 1: 1015 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1016 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1017 r->bge_len0 = segs[0].ds_len; 1018 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1019 break; 1020 default: 1021 panic("%s: %d segments\n", __func__, nsegs); 1022 } 1023 1024 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1025 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1026 1027 return (0); 1028 } 1029 1030 static int 1031 bge_init_rx_ring_std(struct bge_softc *sc) 1032 { 1033 int error, i; 1034 1035 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1036 sc->bge_std = 0; 1037 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1038 if ((error = bge_newbuf_std(sc, i)) != 0) 1039 return (error); 1040 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1041 }; 1042 1043 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1044 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1045 1046 sc->bge_std = 0; 1047 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1048 1049 return (0); 1050 } 1051 1052 static void 1053 bge_free_rx_ring_std(struct bge_softc *sc) 1054 { 1055 int i; 1056 1057 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1058 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1059 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1060 sc->bge_cdata.bge_rx_std_dmamap[i], 1061 BUS_DMASYNC_POSTREAD); 1062 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1063 sc->bge_cdata.bge_rx_std_dmamap[i]); 1064 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1065 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1066 } 1067 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1068 sizeof(struct bge_rx_bd)); 1069 } 1070 } 1071 1072 static int 1073 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1074 { 1075 struct bge_rcb *rcb; 1076 int error, i; 1077 1078 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1079 sc->bge_jumbo = 0; 1080 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1081 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1082 return (error); 1083 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1084 }; 1085 1086 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1087 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1088 1089 sc->bge_jumbo = 0; 1090 1091 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1092 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1093 BGE_RCB_FLAG_USE_EXT_RX_BD); 1094 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1095 1096 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1097 1098 return (0); 1099 } 1100 1101 static void 1102 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1103 { 1104 int i; 1105 1106 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1107 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1108 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1109 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1110 BUS_DMASYNC_POSTREAD); 1111 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1112 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1113 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1114 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1115 } 1116 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1117 sizeof(struct bge_extrx_bd)); 1118 } 1119 } 1120 1121 static void 1122 bge_free_tx_ring(struct bge_softc *sc) 1123 { 1124 int i; 1125 1126 if (sc->bge_ldata.bge_tx_ring == NULL) 1127 return; 1128 1129 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1130 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1131 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1132 sc->bge_cdata.bge_tx_dmamap[i], 1133 BUS_DMASYNC_POSTWRITE); 1134 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1135 sc->bge_cdata.bge_tx_dmamap[i]); 1136 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1137 sc->bge_cdata.bge_tx_chain[i] = NULL; 1138 } 1139 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1140 sizeof(struct bge_tx_bd)); 1141 } 1142 } 1143 1144 static int 1145 bge_init_tx_ring(struct bge_softc *sc) 1146 { 1147 sc->bge_txcnt = 0; 1148 sc->bge_tx_saved_considx = 0; 1149 1150 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1151 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1152 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1153 1154 /* Initialize transmit producer index for host-memory send ring. */ 1155 sc->bge_tx_prodidx = 0; 1156 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1157 1158 /* 5700 b2 errata */ 1159 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1160 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1161 1162 /* NIC-memory send ring not used; initialize to zero. */ 1163 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1164 /* 5700 b2 errata */ 1165 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1166 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1167 1168 return (0); 1169 } 1170 1171 static void 1172 bge_setpromisc(struct bge_softc *sc) 1173 { 1174 struct ifnet *ifp; 1175 1176 BGE_LOCK_ASSERT(sc); 1177 1178 ifp = sc->bge_ifp; 1179 1180 /* Enable or disable promiscuous mode as needed. */ 1181 if (ifp->if_flags & IFF_PROMISC) 1182 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1183 else 1184 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1185 } 1186 1187 static void 1188 bge_setmulti(struct bge_softc *sc) 1189 { 1190 struct ifnet *ifp; 1191 struct ifmultiaddr *ifma; 1192 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1193 int h, i; 1194 1195 BGE_LOCK_ASSERT(sc); 1196 1197 ifp = sc->bge_ifp; 1198 1199 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1200 for (i = 0; i < 4; i++) 1201 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1202 return; 1203 } 1204 1205 /* First, zot all the existing filters. */ 1206 for (i = 0; i < 4; i++) 1207 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1208 1209 /* Now program new ones. */ 1210 if_maddr_rlock(ifp); 1211 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1212 if (ifma->ifma_addr->sa_family != AF_LINK) 1213 continue; 1214 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1215 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1216 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1217 } 1218 if_maddr_runlock(ifp); 1219 1220 for (i = 0; i < 4; i++) 1221 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1222 } 1223 1224 static void 1225 bge_setvlan(struct bge_softc *sc) 1226 { 1227 struct ifnet *ifp; 1228 1229 BGE_LOCK_ASSERT(sc); 1230 1231 ifp = sc->bge_ifp; 1232 1233 /* Enable or disable VLAN tag stripping as needed. */ 1234 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1235 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1236 else 1237 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1238 } 1239 1240 static void 1241 bge_sig_pre_reset(struct bge_softc *sc, int type) 1242 { 1243 1244 /* 1245 * Some chips don't like this so only do this if ASF is enabled 1246 */ 1247 if (sc->bge_asf_mode) 1248 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1249 1250 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1251 switch (type) { 1252 case BGE_RESET_START: 1253 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1254 break; 1255 case BGE_RESET_STOP: 1256 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1257 break; 1258 } 1259 } 1260 } 1261 1262 static void 1263 bge_sig_post_reset(struct bge_softc *sc, int type) 1264 { 1265 1266 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1267 switch (type) { 1268 case BGE_RESET_START: 1269 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000001); 1270 /* START DONE */ 1271 break; 1272 case BGE_RESET_STOP: 1273 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x80000002); 1274 break; 1275 } 1276 } 1277 } 1278 1279 static void 1280 bge_sig_legacy(struct bge_softc *sc, int type) 1281 { 1282 1283 if (sc->bge_asf_mode) { 1284 switch (type) { 1285 case BGE_RESET_START: 1286 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x1); /* START */ 1287 break; 1288 case BGE_RESET_STOP: 1289 bge_writemem_ind(sc, BGE_SDI_STATUS, 0x2); /* UNLOAD */ 1290 break; 1291 } 1292 } 1293 } 1294 1295 static void 1296 bge_stop_fw(struct bge_softc *sc) 1297 { 1298 int i; 1299 1300 if (sc->bge_asf_mode) { 1301 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, BGE_FW_PAUSE); 1302 CSR_WRITE_4(sc, BGE_CPU_EVENT, 1303 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 1304 1305 for (i = 0; i < 100; i++ ) { 1306 if (!(CSR_READ_4(sc, BGE_CPU_EVENT) & (1 << 14))) 1307 break; 1308 DELAY(10); 1309 } 1310 } 1311 } 1312 1313 /* 1314 * Do endian, PCI and DMA initialization. 1315 */ 1316 static int 1317 bge_chipinit(struct bge_softc *sc) 1318 { 1319 uint32_t dma_rw_ctl; 1320 uint16_t val; 1321 int i; 1322 1323 /* Set endianness before we access any non-PCI registers. */ 1324 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4); 1325 1326 /* Clear the MAC control register */ 1327 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1328 1329 /* 1330 * Clear the MAC statistics block in the NIC's 1331 * internal memory. 1332 */ 1333 for (i = BGE_STATS_BLOCK; 1334 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1335 BGE_MEMWIN_WRITE(sc, i, 0); 1336 1337 for (i = BGE_STATUS_BLOCK; 1338 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1339 BGE_MEMWIN_WRITE(sc, i, 0); 1340 1341 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1342 /* 1343 * Fix data corruption caused by non-qword write with WB. 1344 * Fix master abort in PCI mode. 1345 * Fix PCI latency timer. 1346 */ 1347 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1348 val |= (1 << 10) | (1 << 12) | (1 << 13); 1349 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1350 } 1351 1352 /* 1353 * Set up the PCI DMA control register. 1354 */ 1355 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1356 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1357 if (sc->bge_flags & BGE_FLAG_PCIE) { 1358 /* Read watermark not used, 128 bytes for write. */ 1359 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1360 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1361 if (BGE_IS_5714_FAMILY(sc)) { 1362 /* 256 bytes for read and write. */ 1363 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1364 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1365 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1366 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1367 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1368 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1369 /* 1370 * In the BCM5703, the DMA read watermark should 1371 * be set to less than or equal to the maximum 1372 * memory read byte count of the PCI-X command 1373 * register. 1374 */ 1375 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1376 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1377 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1378 /* 1536 bytes for read, 384 bytes for write. */ 1379 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1380 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1381 } else { 1382 /* 384 bytes for read and write. */ 1383 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1384 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1385 0x0F; 1386 } 1387 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1388 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1389 uint32_t tmp; 1390 1391 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1392 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1393 if (tmp == 6 || tmp == 7) 1394 dma_rw_ctl |= 1395 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1396 1397 /* Set PCI-X DMA write workaround. */ 1398 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1399 } 1400 } else { 1401 /* Conventional PCI bus: 256 bytes for read and write. */ 1402 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1403 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1404 1405 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1406 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1407 dma_rw_ctl |= 0x0F; 1408 } 1409 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1410 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1411 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1412 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1413 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1414 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1415 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1416 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1417 1418 /* 1419 * Set up general mode register. 1420 */ 1421 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 1422 BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1423 BGE_MODECTL_TX_NO_PHDR_CSUM); 1424 1425 /* 1426 * BCM5701 B5 have a bug causing data corruption when using 1427 * 64-bit DMA reads, which can be terminated early and then 1428 * completed later as 32-bit accesses, in combination with 1429 * certain bridges. 1430 */ 1431 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1432 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1433 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_FORCE_PCI32); 1434 1435 /* 1436 * Tell the firmware the driver is running 1437 */ 1438 if (sc->bge_asf_mode & ASF_STACKUP) 1439 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 1440 1441 /* 1442 * Disable memory write invalidate. Apparently it is not supported 1443 * properly by these devices. Also ensure that INTx isn't disabled, 1444 * as these chips need it even when using MSI. 1445 */ 1446 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1447 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1448 1449 /* Set the timer prescaler (always 66Mhz) */ 1450 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1451 1452 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1453 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1454 DELAY(40); /* XXX */ 1455 1456 /* Put PHY into ready state */ 1457 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1458 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1459 DELAY(40); 1460 } 1461 1462 return (0); 1463 } 1464 1465 static int 1466 bge_blockinit(struct bge_softc *sc) 1467 { 1468 struct bge_rcb *rcb; 1469 bus_size_t vrcb; 1470 bge_hostaddr taddr; 1471 uint32_t val; 1472 int i; 1473 1474 /* 1475 * Initialize the memory window pointer register so that 1476 * we can access the first 32K of internal NIC RAM. This will 1477 * allow us to set up the TX send ring RCBs and the RX return 1478 * ring RCBs, plus other things which live in NIC memory. 1479 */ 1480 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1481 1482 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1483 1484 if (!(BGE_IS_5705_PLUS(sc))) { 1485 /* Configure mbuf memory pool */ 1486 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1487 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1488 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1489 else 1490 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1491 1492 /* Configure DMA resource pool */ 1493 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1494 BGE_DMA_DESCRIPTORS); 1495 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1496 } 1497 1498 /* Configure mbuf pool watermarks */ 1499 if (!BGE_IS_5705_PLUS(sc)) { 1500 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1501 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1502 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1503 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1504 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1505 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 1506 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 1507 } else { 1508 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1509 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 1510 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1511 } 1512 1513 /* Configure DMA resource watermarks */ 1514 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1515 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1516 1517 /* Enable buffer manager */ 1518 if (!(BGE_IS_5705_PLUS(sc))) { 1519 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1520 BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN); 1521 1522 /* Poll for buffer manager start indication */ 1523 for (i = 0; i < BGE_TIMEOUT; i++) { 1524 DELAY(10); 1525 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1526 break; 1527 } 1528 1529 if (i == BGE_TIMEOUT) { 1530 device_printf(sc->bge_dev, 1531 "buffer manager failed to start\n"); 1532 return (ENXIO); 1533 } 1534 } 1535 1536 /* Enable flow-through queues */ 1537 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1538 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1539 1540 /* Wait until queue initialization is complete */ 1541 for (i = 0; i < BGE_TIMEOUT; i++) { 1542 DELAY(10); 1543 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1544 break; 1545 } 1546 1547 if (i == BGE_TIMEOUT) { 1548 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 1549 return (ENXIO); 1550 } 1551 1552 /* Initialize the standard RX ring control block */ 1553 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 1554 rcb->bge_hostaddr.bge_addr_lo = 1555 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 1556 rcb->bge_hostaddr.bge_addr_hi = 1557 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 1558 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1559 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 1560 if (BGE_IS_5705_PLUS(sc)) 1561 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 1562 else 1563 rcb->bge_maxlen_flags = 1564 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1565 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1566 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1567 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1568 1569 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1570 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1571 1572 /* 1573 * Initialize the jumbo RX ring control block 1574 * We set the 'ring disabled' bit in the flags 1575 * field until we're actually ready to start 1576 * using this ring (i.e. once we set the MTU 1577 * high enough to require it). 1578 */ 1579 if (BGE_IS_JUMBO_CAPABLE(sc)) { 1580 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1581 1582 rcb->bge_hostaddr.bge_addr_lo = 1583 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1584 rcb->bge_hostaddr.bge_addr_hi = 1585 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 1586 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1587 sc->bge_cdata.bge_rx_jumbo_ring_map, 1588 BUS_DMASYNC_PREREAD); 1589 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 1590 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 1591 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1592 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1593 rcb->bge_hostaddr.bge_addr_hi); 1594 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1595 rcb->bge_hostaddr.bge_addr_lo); 1596 1597 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 1598 rcb->bge_maxlen_flags); 1599 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1600 1601 /* Set up dummy disabled mini ring RCB */ 1602 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 1603 rcb->bge_maxlen_flags = 1604 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1605 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 1606 rcb->bge_maxlen_flags); 1607 } 1608 1609 /* 1610 * Set the BD ring replentish thresholds. The recommended 1611 * values are 1/8th the number of descriptors allocated to 1612 * each ring. 1613 * XXX The 5754 requires a lower threshold, so it might be a 1614 * requirement of all 575x family chips. The Linux driver sets 1615 * the lower threshold for all 5705 family chips as well, but there 1616 * are reports that it might not need to be so strict. 1617 * 1618 * XXX Linux does some extra fiddling here for the 5906 parts as 1619 * well. 1620 */ 1621 if (BGE_IS_5705_PLUS(sc)) 1622 val = 8; 1623 else 1624 val = BGE_STD_RX_RING_CNT / 8; 1625 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 1626 if (BGE_IS_JUMBO_CAPABLE(sc)) 1627 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 1628 BGE_JUMBO_RX_RING_CNT/8); 1629 1630 /* 1631 * Disable all unused send rings by setting the 'ring disabled' 1632 * bit in the flags field of all the TX send ring control blocks. 1633 * These are located in NIC memory. 1634 */ 1635 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1636 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1637 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1638 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 1639 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1640 vrcb += sizeof(struct bge_rcb); 1641 } 1642 1643 /* Configure TX RCB 0 (we use only the first ring) */ 1644 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 1645 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 1646 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1647 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1648 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 1649 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 1650 if (!(BGE_IS_5705_PLUS(sc))) 1651 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1652 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 1653 1654 /* Disable all unused RX return rings */ 1655 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1656 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1657 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 1658 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 1659 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1660 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 1661 BGE_RCB_FLAG_RING_DISABLED)); 1662 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 1663 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 1664 (i * (sizeof(uint64_t))), 0); 1665 vrcb += sizeof(struct bge_rcb); 1666 } 1667 1668 /* Initialize RX ring indexes */ 1669 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1670 if (BGE_IS_JUMBO_CAPABLE(sc)) 1671 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1672 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1673 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1674 1675 /* 1676 * Set up RX return ring 0 1677 * Note that the NIC address for RX return rings is 0x00000000. 1678 * The return rings live entirely within the host, so the 1679 * nicaddr field in the RCB isn't used. 1680 */ 1681 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 1682 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 1683 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 1684 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 1685 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000); 1686 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 1687 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 1688 1689 /* Set random backoff seed for TX */ 1690 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1691 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 1692 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 1693 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] + 1694 BGE_TX_BACKOFF_SEED_MASK); 1695 1696 /* Set inter-packet gap */ 1697 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1698 1699 /* 1700 * Specify which ring to use for packets that don't match 1701 * any RX rules. 1702 */ 1703 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1704 1705 /* 1706 * Configure number of RX lists. One interrupt distribution 1707 * list, sixteen active lists, one bad frames class. 1708 */ 1709 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1710 1711 /* Inialize RX list placement stats mask. */ 1712 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1713 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1714 1715 /* Disable host coalescing until we get it set up */ 1716 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1717 1718 /* Poll to make sure it's shut down. */ 1719 for (i = 0; i < BGE_TIMEOUT; i++) { 1720 DELAY(10); 1721 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1722 break; 1723 } 1724 1725 if (i == BGE_TIMEOUT) { 1726 device_printf(sc->bge_dev, 1727 "host coalescing engine failed to idle\n"); 1728 return (ENXIO); 1729 } 1730 1731 /* Set up host coalescing defaults */ 1732 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1733 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1734 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1735 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1736 if (!(BGE_IS_5705_PLUS(sc))) { 1737 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1738 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1739 } 1740 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 1741 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 1742 1743 /* Set up address of statistics block */ 1744 if (!(BGE_IS_5705_PLUS(sc))) { 1745 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 1746 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 1747 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1748 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 1749 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1750 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1751 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1752 } 1753 1754 /* Set up address of status block */ 1755 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 1756 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 1757 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1758 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 1759 1760 /* Set up status block size. */ 1761 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1762 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 1763 val = BGE_STATBLKSZ_FULL; 1764 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 1765 } else { 1766 val = BGE_STATBLKSZ_32BYTE; 1767 bzero(sc->bge_ldata.bge_status_block, 32); 1768 } 1769 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 1770 sc->bge_cdata.bge_status_map, 1771 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1772 1773 /* Turn on host coalescing state machine */ 1774 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 1775 1776 /* Turn on RX BD completion state machine and enable attentions */ 1777 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1778 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 1779 1780 /* Turn on RX list placement state machine */ 1781 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1782 1783 /* Turn on RX list selector state machine. */ 1784 if (!(BGE_IS_5705_PLUS(sc))) 1785 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1786 1787 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 1788 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 1789 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 1790 BGE_MACMODE_FRMHDR_DMA_ENB; 1791 1792 if (sc->bge_flags & BGE_FLAG_TBI) 1793 val |= BGE_PORTMODE_TBI; 1794 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 1795 val |= BGE_PORTMODE_GMII; 1796 else 1797 val |= BGE_PORTMODE_MII; 1798 1799 /* Turn on DMA, clear stats */ 1800 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 1801 1802 /* Set misc. local control, enable interrupts on attentions */ 1803 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1804 1805 #ifdef notdef 1806 /* Assert GPIO pins for PHY reset */ 1807 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 1808 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 1809 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 1810 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 1811 #endif 1812 1813 /* Turn on DMA completion state machine */ 1814 if (!(BGE_IS_5705_PLUS(sc))) 1815 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1816 1817 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 1818 1819 /* Enable host coalescing bug fix. */ 1820 if (BGE_IS_5755_PLUS(sc)) 1821 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 1822 1823 /* Turn on write DMA state machine */ 1824 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 1825 DELAY(40); 1826 1827 /* Turn on read DMA state machine */ 1828 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 1829 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 1830 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1831 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1832 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 1833 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 1834 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 1835 if (sc->bge_flags & BGE_FLAG_PCIE) 1836 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 1837 if (sc->bge_flags & BGE_FLAG_TSO) { 1838 val |= BGE_RDMAMODE_TSO4_ENABLE; 1839 if (sc->bge_asicrev == BGE_ASICREV_BCM5785 || 1840 sc->bge_asicrev == BGE_ASICREV_BCM57780) 1841 val |= BGE_RDMAMODE_TSO6_ENABLE; 1842 } 1843 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 1844 DELAY(40); 1845 1846 /* Turn on RX data completion state machine */ 1847 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1848 1849 /* Turn on RX BD initiator state machine */ 1850 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1851 1852 /* Turn on RX data and RX BD initiator state machine */ 1853 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1854 1855 /* Turn on Mbuf cluster free state machine */ 1856 if (!(BGE_IS_5705_PLUS(sc))) 1857 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1858 1859 /* Turn on send BD completion state machine */ 1860 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1861 1862 /* Turn on send data completion state machine */ 1863 val = BGE_SDCMODE_ENABLE; 1864 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 1865 val |= BGE_SDCMODE_CDELAY; 1866 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 1867 1868 /* Turn on send data initiator state machine */ 1869 if (sc->bge_flags & BGE_FLAG_TSO) 1870 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 0x08); 1871 else 1872 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1873 1874 /* Turn on send BD initiator state machine */ 1875 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1876 1877 /* Turn on send BD selector state machine */ 1878 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1879 1880 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1881 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1882 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 1883 1884 /* ack/clear link change events */ 1885 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1886 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1887 BGE_MACSTAT_LINK_CHANGED); 1888 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1889 1890 /* Enable PHY auto polling (for MII/GMII only) */ 1891 if (sc->bge_flags & BGE_FLAG_TBI) { 1892 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1893 } else { 1894 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL | (10 << 16)); 1895 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 1896 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 1897 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1898 BGE_EVTENB_MI_INTERRUPT); 1899 } 1900 1901 /* 1902 * Clear any pending link state attention. 1903 * Otherwise some link state change events may be lost until attention 1904 * is cleared by bge_intr() -> bge_link_upd() sequence. 1905 * It's not necessary on newer BCM chips - perhaps enabling link 1906 * state change attentions implies clearing pending attention. 1907 */ 1908 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 1909 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 1910 BGE_MACSTAT_LINK_CHANGED); 1911 1912 /* Enable link state change attentions. */ 1913 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1914 1915 return (0); 1916 } 1917 1918 const struct bge_revision * 1919 bge_lookup_rev(uint32_t chipid) 1920 { 1921 const struct bge_revision *br; 1922 1923 for (br = bge_revisions; br->br_name != NULL; br++) { 1924 if (br->br_chipid == chipid) 1925 return (br); 1926 } 1927 1928 for (br = bge_majorrevs; br->br_name != NULL; br++) { 1929 if (br->br_chipid == BGE_ASICREV(chipid)) 1930 return (br); 1931 } 1932 1933 return (NULL); 1934 } 1935 1936 const struct bge_vendor * 1937 bge_lookup_vendor(uint16_t vid) 1938 { 1939 const struct bge_vendor *v; 1940 1941 for (v = bge_vendors; v->v_name != NULL; v++) 1942 if (v->v_id == vid) 1943 return (v); 1944 1945 panic("%s: unknown vendor %d", __func__, vid); 1946 return (NULL); 1947 } 1948 1949 /* 1950 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1951 * against our list and return its name if we find a match. 1952 * 1953 * Note that since the Broadcom controller contains VPD support, we 1954 * try to get the device name string from the controller itself instead 1955 * of the compiled-in string. It guarantees we'll always announce the 1956 * right product name. We fall back to the compiled-in string when 1957 * VPD is unavailable or corrupt. 1958 */ 1959 static int 1960 bge_probe(device_t dev) 1961 { 1962 const struct bge_type *t = bge_devs; 1963 struct bge_softc *sc = device_get_softc(dev); 1964 uint16_t vid, did; 1965 1966 sc->bge_dev = dev; 1967 vid = pci_get_vendor(dev); 1968 did = pci_get_device(dev); 1969 while(t->bge_vid != 0) { 1970 if ((vid == t->bge_vid) && (did == t->bge_did)) { 1971 char model[64], buf[96]; 1972 const struct bge_revision *br; 1973 const struct bge_vendor *v; 1974 uint32_t id; 1975 1976 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 1977 BGE_PCIMISCCTL_ASICREV_SHIFT; 1978 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) 1979 id = pci_read_config(dev, 1980 BGE_PCI_PRODID_ASICREV, 4); 1981 br = bge_lookup_rev(id); 1982 v = bge_lookup_vendor(vid); 1983 { 1984 #if __FreeBSD_version > 700024 1985 const char *pname; 1986 1987 if (bge_has_eaddr(sc) && 1988 pci_get_vpd_ident(dev, &pname) == 0) 1989 snprintf(model, 64, "%s", pname); 1990 else 1991 #endif 1992 snprintf(model, 64, "%s %s", 1993 v->v_name, 1994 br != NULL ? br->br_name : 1995 "NetXtreme Ethernet Controller"); 1996 } 1997 snprintf(buf, 96, "%s, %sASIC rev. %#08x", model, 1998 br != NULL ? "" : "unknown ", id); 1999 device_set_desc_copy(dev, buf); 2000 return (0); 2001 } 2002 t++; 2003 } 2004 2005 return (ENXIO); 2006 } 2007 2008 static void 2009 bge_dma_free(struct bge_softc *sc) 2010 { 2011 int i; 2012 2013 /* Destroy DMA maps for RX buffers. */ 2014 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2015 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2016 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2017 sc->bge_cdata.bge_rx_std_dmamap[i]); 2018 } 2019 if (sc->bge_cdata.bge_rx_std_sparemap) 2020 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2021 sc->bge_cdata.bge_rx_std_sparemap); 2022 2023 /* Destroy DMA maps for jumbo RX buffers. */ 2024 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2025 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2026 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2027 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2028 } 2029 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2030 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2031 sc->bge_cdata.bge_rx_jumbo_sparemap); 2032 2033 /* Destroy DMA maps for TX buffers. */ 2034 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2035 if (sc->bge_cdata.bge_tx_dmamap[i]) 2036 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2037 sc->bge_cdata.bge_tx_dmamap[i]); 2038 } 2039 2040 if (sc->bge_cdata.bge_rx_mtag) 2041 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2042 if (sc->bge_cdata.bge_tx_mtag) 2043 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2044 2045 2046 /* Destroy standard RX ring. */ 2047 if (sc->bge_cdata.bge_rx_std_ring_map) 2048 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2049 sc->bge_cdata.bge_rx_std_ring_map); 2050 if (sc->bge_cdata.bge_rx_std_ring_map && sc->bge_ldata.bge_rx_std_ring) 2051 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2052 sc->bge_ldata.bge_rx_std_ring, 2053 sc->bge_cdata.bge_rx_std_ring_map); 2054 2055 if (sc->bge_cdata.bge_rx_std_ring_tag) 2056 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2057 2058 /* Destroy jumbo RX ring. */ 2059 if (sc->bge_cdata.bge_rx_jumbo_ring_map) 2060 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2061 sc->bge_cdata.bge_rx_jumbo_ring_map); 2062 2063 if (sc->bge_cdata.bge_rx_jumbo_ring_map && 2064 sc->bge_ldata.bge_rx_jumbo_ring) 2065 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2066 sc->bge_ldata.bge_rx_jumbo_ring, 2067 sc->bge_cdata.bge_rx_jumbo_ring_map); 2068 2069 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2070 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2071 2072 /* Destroy RX return ring. */ 2073 if (sc->bge_cdata.bge_rx_return_ring_map) 2074 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2075 sc->bge_cdata.bge_rx_return_ring_map); 2076 2077 if (sc->bge_cdata.bge_rx_return_ring_map && 2078 sc->bge_ldata.bge_rx_return_ring) 2079 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2080 sc->bge_ldata.bge_rx_return_ring, 2081 sc->bge_cdata.bge_rx_return_ring_map); 2082 2083 if (sc->bge_cdata.bge_rx_return_ring_tag) 2084 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2085 2086 /* Destroy TX ring. */ 2087 if (sc->bge_cdata.bge_tx_ring_map) 2088 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2089 sc->bge_cdata.bge_tx_ring_map); 2090 2091 if (sc->bge_cdata.bge_tx_ring_map && sc->bge_ldata.bge_tx_ring) 2092 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2093 sc->bge_ldata.bge_tx_ring, 2094 sc->bge_cdata.bge_tx_ring_map); 2095 2096 if (sc->bge_cdata.bge_tx_ring_tag) 2097 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2098 2099 /* Destroy status block. */ 2100 if (sc->bge_cdata.bge_status_map) 2101 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2102 sc->bge_cdata.bge_status_map); 2103 2104 if (sc->bge_cdata.bge_status_map && sc->bge_ldata.bge_status_block) 2105 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2106 sc->bge_ldata.bge_status_block, 2107 sc->bge_cdata.bge_status_map); 2108 2109 if (sc->bge_cdata.bge_status_tag) 2110 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2111 2112 /* Destroy statistics block. */ 2113 if (sc->bge_cdata.bge_stats_map) 2114 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2115 sc->bge_cdata.bge_stats_map); 2116 2117 if (sc->bge_cdata.bge_stats_map && sc->bge_ldata.bge_stats) 2118 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2119 sc->bge_ldata.bge_stats, 2120 sc->bge_cdata.bge_stats_map); 2121 2122 if (sc->bge_cdata.bge_stats_tag) 2123 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2124 2125 /* Destroy the parent tag. */ 2126 if (sc->bge_cdata.bge_parent_tag) 2127 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2128 } 2129 2130 static int 2131 bge_dma_alloc(device_t dev) 2132 { 2133 struct bge_dmamap_arg ctx; 2134 struct bge_softc *sc; 2135 bus_addr_t lowaddr; 2136 bus_size_t sbsz, txsegsz, txmaxsegsz; 2137 int i, error; 2138 2139 sc = device_get_softc(dev); 2140 2141 lowaddr = BUS_SPACE_MAXADDR; 2142 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2143 lowaddr = BGE_DMA_MAXADDR; 2144 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) 2145 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2146 /* 2147 * Allocate the parent bus DMA tag appropriate for PCI. 2148 */ 2149 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2150 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2151 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2152 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2153 2154 if (error != 0) { 2155 device_printf(sc->bge_dev, 2156 "could not allocate parent dma tag\n"); 2157 return (ENOMEM); 2158 } 2159 2160 /* 2161 * Create tag for Tx mbufs. 2162 */ 2163 if (sc->bge_flags & BGE_FLAG_TSO) { 2164 txsegsz = BGE_TSOSEG_SZ; 2165 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 2166 } else { 2167 txsegsz = MCLBYTES; 2168 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 2169 } 2170 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 2171 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 2172 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 2173 &sc->bge_cdata.bge_tx_mtag); 2174 2175 if (error) { 2176 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 2177 return (ENOMEM); 2178 } 2179 2180 /* 2181 * Create tag for Rx mbufs. 2182 */ 2183 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 1, 0, 2184 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 1, 2185 MCLBYTES, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 2186 2187 if (error) { 2188 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 2189 return (ENOMEM); 2190 } 2191 2192 /* Create DMA maps for RX buffers. */ 2193 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2194 &sc->bge_cdata.bge_rx_std_sparemap); 2195 if (error) { 2196 device_printf(sc->bge_dev, 2197 "can't create spare DMA map for RX\n"); 2198 return (ENOMEM); 2199 } 2200 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2201 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 2202 &sc->bge_cdata.bge_rx_std_dmamap[i]); 2203 if (error) { 2204 device_printf(sc->bge_dev, 2205 "can't create DMA map for RX\n"); 2206 return (ENOMEM); 2207 } 2208 } 2209 2210 /* Create DMA maps for TX buffers. */ 2211 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2212 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 2213 &sc->bge_cdata.bge_tx_dmamap[i]); 2214 if (error) { 2215 device_printf(sc->bge_dev, 2216 "can't create DMA map for TX\n"); 2217 return (ENOMEM); 2218 } 2219 } 2220 2221 /* Create tag for standard RX ring. */ 2222 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2223 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2224 NULL, BGE_STD_RX_RING_SZ, 1, BGE_STD_RX_RING_SZ, 0, 2225 NULL, NULL, &sc->bge_cdata.bge_rx_std_ring_tag); 2226 2227 if (error) { 2228 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2229 return (ENOMEM); 2230 } 2231 2232 /* Allocate DMA'able memory for standard RX ring. */ 2233 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_std_ring_tag, 2234 (void **)&sc->bge_ldata.bge_rx_std_ring, BUS_DMA_NOWAIT, 2235 &sc->bge_cdata.bge_rx_std_ring_map); 2236 if (error) 2237 return (ENOMEM); 2238 2239 bzero((char *)sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 2240 2241 /* Load the address of the standard RX ring. */ 2242 ctx.bge_maxsegs = 1; 2243 ctx.sc = sc; 2244 2245 error = bus_dmamap_load(sc->bge_cdata.bge_rx_std_ring_tag, 2246 sc->bge_cdata.bge_rx_std_ring_map, sc->bge_ldata.bge_rx_std_ring, 2247 BGE_STD_RX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2248 2249 if (error) 2250 return (ENOMEM); 2251 2252 sc->bge_ldata.bge_rx_std_ring_paddr = ctx.bge_busaddr; 2253 2254 /* Create tags for jumbo mbufs. */ 2255 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2256 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2257 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2258 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 2259 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 2260 if (error) { 2261 device_printf(sc->bge_dev, 2262 "could not allocate jumbo dma tag\n"); 2263 return (ENOMEM); 2264 } 2265 2266 /* Create tag for jumbo RX ring. */ 2267 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2268 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2269 NULL, BGE_JUMBO_RX_RING_SZ, 1, BGE_JUMBO_RX_RING_SZ, 0, 2270 NULL, NULL, &sc->bge_cdata.bge_rx_jumbo_ring_tag); 2271 2272 if (error) { 2273 device_printf(sc->bge_dev, 2274 "could not allocate jumbo ring dma tag\n"); 2275 return (ENOMEM); 2276 } 2277 2278 /* Allocate DMA'able memory for jumbo RX ring. */ 2279 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2280 (void **)&sc->bge_ldata.bge_rx_jumbo_ring, 2281 BUS_DMA_NOWAIT | BUS_DMA_ZERO, 2282 &sc->bge_cdata.bge_rx_jumbo_ring_map); 2283 if (error) 2284 return (ENOMEM); 2285 2286 /* Load the address of the jumbo RX ring. */ 2287 ctx.bge_maxsegs = 1; 2288 ctx.sc = sc; 2289 2290 error = bus_dmamap_load(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2291 sc->bge_cdata.bge_rx_jumbo_ring_map, 2292 sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ, 2293 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2294 2295 if (error) 2296 return (ENOMEM); 2297 2298 sc->bge_ldata.bge_rx_jumbo_ring_paddr = ctx.bge_busaddr; 2299 2300 /* Create DMA maps for jumbo RX buffers. */ 2301 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2302 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 2303 if (error) { 2304 device_printf(sc->bge_dev, 2305 "can't create spare DMA map for jumbo RX\n"); 2306 return (ENOMEM); 2307 } 2308 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2309 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 2310 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2311 if (error) { 2312 device_printf(sc->bge_dev, 2313 "can't create DMA map for jumbo RX\n"); 2314 return (ENOMEM); 2315 } 2316 } 2317 2318 } 2319 2320 /* Create tag for RX return ring. */ 2321 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2322 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2323 NULL, BGE_RX_RTN_RING_SZ(sc), 1, BGE_RX_RTN_RING_SZ(sc), 0, 2324 NULL, NULL, &sc->bge_cdata.bge_rx_return_ring_tag); 2325 2326 if (error) { 2327 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2328 return (ENOMEM); 2329 } 2330 2331 /* Allocate DMA'able memory for RX return ring. */ 2332 error = bus_dmamem_alloc(sc->bge_cdata.bge_rx_return_ring_tag, 2333 (void **)&sc->bge_ldata.bge_rx_return_ring, BUS_DMA_NOWAIT, 2334 &sc->bge_cdata.bge_rx_return_ring_map); 2335 if (error) 2336 return (ENOMEM); 2337 2338 bzero((char *)sc->bge_ldata.bge_rx_return_ring, 2339 BGE_RX_RTN_RING_SZ(sc)); 2340 2341 /* Load the address of the RX return ring. */ 2342 ctx.bge_maxsegs = 1; 2343 ctx.sc = sc; 2344 2345 error = bus_dmamap_load(sc->bge_cdata.bge_rx_return_ring_tag, 2346 sc->bge_cdata.bge_rx_return_ring_map, 2347 sc->bge_ldata.bge_rx_return_ring, BGE_RX_RTN_RING_SZ(sc), 2348 bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2349 2350 if (error) 2351 return (ENOMEM); 2352 2353 sc->bge_ldata.bge_rx_return_ring_paddr = ctx.bge_busaddr; 2354 2355 /* Create tag for TX ring. */ 2356 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2357 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2358 NULL, BGE_TX_RING_SZ, 1, BGE_TX_RING_SZ, 0, NULL, NULL, 2359 &sc->bge_cdata.bge_tx_ring_tag); 2360 2361 if (error) { 2362 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2363 return (ENOMEM); 2364 } 2365 2366 /* Allocate DMA'able memory for TX ring. */ 2367 error = bus_dmamem_alloc(sc->bge_cdata.bge_tx_ring_tag, 2368 (void **)&sc->bge_ldata.bge_tx_ring, BUS_DMA_NOWAIT, 2369 &sc->bge_cdata.bge_tx_ring_map); 2370 if (error) 2371 return (ENOMEM); 2372 2373 bzero((char *)sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 2374 2375 /* Load the address of the TX ring. */ 2376 ctx.bge_maxsegs = 1; 2377 ctx.sc = sc; 2378 2379 error = bus_dmamap_load(sc->bge_cdata.bge_tx_ring_tag, 2380 sc->bge_cdata.bge_tx_ring_map, sc->bge_ldata.bge_tx_ring, 2381 BGE_TX_RING_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2382 2383 if (error) 2384 return (ENOMEM); 2385 2386 sc->bge_ldata.bge_tx_ring_paddr = ctx.bge_busaddr; 2387 2388 /* 2389 * Create tag for status block. 2390 * Because we only use single Tx/Rx/Rx return ring, use 2391 * minimum status block size except BCM5700 AX/BX which 2392 * seems to want to see full status block size regardless 2393 * of configured number of ring. 2394 */ 2395 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2396 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 2397 sbsz = BGE_STATUS_BLK_SZ; 2398 else 2399 sbsz = 32; 2400 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2401 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2402 NULL, sbsz, 1, sbsz, 0, NULL, NULL, &sc->bge_cdata.bge_status_tag); 2403 2404 if (error) { 2405 device_printf(sc->bge_dev, 2406 "could not allocate status dma tag\n"); 2407 return (ENOMEM); 2408 } 2409 2410 /* Allocate DMA'able memory for status block. */ 2411 error = bus_dmamem_alloc(sc->bge_cdata.bge_status_tag, 2412 (void **)&sc->bge_ldata.bge_status_block, BUS_DMA_NOWAIT, 2413 &sc->bge_cdata.bge_status_map); 2414 if (error) 2415 return (ENOMEM); 2416 2417 bzero((char *)sc->bge_ldata.bge_status_block, sbsz); 2418 2419 /* Load the address of the status block. */ 2420 ctx.sc = sc; 2421 ctx.bge_maxsegs = 1; 2422 2423 error = bus_dmamap_load(sc->bge_cdata.bge_status_tag, 2424 sc->bge_cdata.bge_status_map, sc->bge_ldata.bge_status_block, 2425 sbsz, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2426 2427 if (error) 2428 return (ENOMEM); 2429 2430 sc->bge_ldata.bge_status_block_paddr = ctx.bge_busaddr; 2431 2432 /* Create tag for statistics block. */ 2433 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2434 PAGE_SIZE, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2435 NULL, BGE_STATS_SZ, 1, BGE_STATS_SZ, 0, NULL, NULL, 2436 &sc->bge_cdata.bge_stats_tag); 2437 2438 if (error) { 2439 device_printf(sc->bge_dev, "could not allocate dma tag\n"); 2440 return (ENOMEM); 2441 } 2442 2443 /* Allocate DMA'able memory for statistics block. */ 2444 error = bus_dmamem_alloc(sc->bge_cdata.bge_stats_tag, 2445 (void **)&sc->bge_ldata.bge_stats, BUS_DMA_NOWAIT, 2446 &sc->bge_cdata.bge_stats_map); 2447 if (error) 2448 return (ENOMEM); 2449 2450 bzero((char *)sc->bge_ldata.bge_stats, BGE_STATS_SZ); 2451 2452 /* Load the address of the statstics block. */ 2453 ctx.sc = sc; 2454 ctx.bge_maxsegs = 1; 2455 2456 error = bus_dmamap_load(sc->bge_cdata.bge_stats_tag, 2457 sc->bge_cdata.bge_stats_map, sc->bge_ldata.bge_stats, 2458 BGE_STATS_SZ, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT); 2459 2460 if (error) 2461 return (ENOMEM); 2462 2463 sc->bge_ldata.bge_stats_paddr = ctx.bge_busaddr; 2464 2465 return (0); 2466 } 2467 2468 /* 2469 * Return true if this device has more than one port. 2470 */ 2471 static int 2472 bge_has_multiple_ports(struct bge_softc *sc) 2473 { 2474 device_t dev = sc->bge_dev; 2475 u_int b, d, f, fscan, s; 2476 2477 d = pci_get_domain(dev); 2478 b = pci_get_bus(dev); 2479 s = pci_get_slot(dev); 2480 f = pci_get_function(dev); 2481 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 2482 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 2483 return (1); 2484 return (0); 2485 } 2486 2487 /* 2488 * Return true if MSI can be used with this device. 2489 */ 2490 static int 2491 bge_can_use_msi(struct bge_softc *sc) 2492 { 2493 int can_use_msi = 0; 2494 2495 switch (sc->bge_asicrev) { 2496 case BGE_ASICREV_BCM5714_A0: 2497 case BGE_ASICREV_BCM5714: 2498 /* 2499 * Apparently, MSI doesn't work when these chips are 2500 * configured in single-port mode. 2501 */ 2502 if (bge_has_multiple_ports(sc)) 2503 can_use_msi = 1; 2504 break; 2505 case BGE_ASICREV_BCM5750: 2506 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 2507 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 2508 can_use_msi = 1; 2509 break; 2510 default: 2511 if (BGE_IS_575X_PLUS(sc)) 2512 can_use_msi = 1; 2513 } 2514 return (can_use_msi); 2515 } 2516 2517 static int 2518 bge_attach(device_t dev) 2519 { 2520 struct ifnet *ifp; 2521 struct bge_softc *sc; 2522 uint32_t hwcfg = 0, misccfg; 2523 u_char eaddr[ETHER_ADDR_LEN]; 2524 int error, msicount, reg, rid, trys; 2525 2526 sc = device_get_softc(dev); 2527 sc->bge_dev = dev; 2528 2529 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 2530 2531 /* 2532 * Map control/status registers. 2533 */ 2534 pci_enable_busmaster(dev); 2535 2536 rid = PCIR_BAR(0); 2537 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 2538 RF_ACTIVE); 2539 2540 if (sc->bge_res == NULL) { 2541 device_printf (sc->bge_dev, "couldn't map memory\n"); 2542 error = ENXIO; 2543 goto fail; 2544 } 2545 2546 /* Save various chip information. */ 2547 sc->bge_chipid = 2548 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2549 BGE_PCIMISCCTL_ASICREV_SHIFT; 2550 if (BGE_ASICREV(sc->bge_chipid) == BGE_ASICREV_USE_PRODID_REG) 2551 sc->bge_chipid = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 2552 4); 2553 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 2554 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 2555 2556 /* 2557 * Don't enable Ethernet@WireSpeed for the 5700, 5906, or the 2558 * 5705 A0 and A1 chips. 2559 */ 2560 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 2561 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 2562 sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 2563 sc->bge_chipid != BGE_CHIPID_BCM5705_A1) 2564 sc->bge_flags |= BGE_FLAG_WIRESPEED; 2565 2566 if (bge_has_eaddr(sc)) 2567 sc->bge_flags |= BGE_FLAG_EADDR; 2568 2569 /* Save chipset family. */ 2570 switch (sc->bge_asicrev) { 2571 case BGE_ASICREV_BCM5755: 2572 case BGE_ASICREV_BCM5761: 2573 case BGE_ASICREV_BCM5784: 2574 case BGE_ASICREV_BCM5785: 2575 case BGE_ASICREV_BCM5787: 2576 case BGE_ASICREV_BCM57780: 2577 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 2578 BGE_FLAG_5705_PLUS; 2579 break; 2580 case BGE_ASICREV_BCM5700: 2581 case BGE_ASICREV_BCM5701: 2582 case BGE_ASICREV_BCM5703: 2583 case BGE_ASICREV_BCM5704: 2584 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 2585 break; 2586 case BGE_ASICREV_BCM5714_A0: 2587 case BGE_ASICREV_BCM5780: 2588 case BGE_ASICREV_BCM5714: 2589 sc->bge_flags |= BGE_FLAG_5714_FAMILY /* | BGE_FLAG_JUMBO */; 2590 /* FALLTHROUGH */ 2591 case BGE_ASICREV_BCM5750: 2592 case BGE_ASICREV_BCM5752: 2593 case BGE_ASICREV_BCM5906: 2594 sc->bge_flags |= BGE_FLAG_575X_PLUS; 2595 /* FALLTHROUGH */ 2596 case BGE_ASICREV_BCM5705: 2597 sc->bge_flags |= BGE_FLAG_5705_PLUS; 2598 break; 2599 } 2600 2601 /* Set various bug flags. */ 2602 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 2603 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 2604 sc->bge_flags |= BGE_FLAG_CRC_BUG; 2605 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 2606 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 2607 sc->bge_flags |= BGE_FLAG_ADC_BUG; 2608 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 2609 sc->bge_flags |= BGE_FLAG_5704_A0_BUG; 2610 if (pci_get_subvendor(dev) == DELL_VENDORID) 2611 sc->bge_flags |= BGE_FLAG_NO_3LED; 2612 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 2613 sc->bge_flags |= BGE_FLAG_ADJUST_TRIM; 2614 if (BGE_IS_5705_PLUS(sc) && 2615 !(sc->bge_flags & BGE_FLAG_ADJUST_TRIM)) { 2616 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2617 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2618 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2619 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 2620 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 2621 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 2622 sc->bge_flags |= BGE_FLAG_JITTER_BUG; 2623 } else if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 2624 sc->bge_flags |= BGE_FLAG_BER_BUG; 2625 } 2626 2627 /* 2628 * All controllers that are not 5755 or higher have 4GB 2629 * boundary DMA bug. 2630 * Whenever an address crosses a multiple of the 4GB boundary 2631 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 2632 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 2633 * state machine will lockup and cause the device to hang. 2634 */ 2635 if (BGE_IS_5755_PLUS(sc) == 0) 2636 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 2637 2638 /* 2639 * We could possibly check for BCOM_DEVICEID_BCM5788 in bge_probe() 2640 * but I do not know the DEVICEID for the 5788M. 2641 */ 2642 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID; 2643 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 2644 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 2645 sc->bge_flags |= BGE_FLAG_5788; 2646 2647 /* 2648 * Some controllers seem to require a special firmware to use 2649 * TSO. But the firmware is not available to FreeBSD and Linux 2650 * claims that the TSO performed by the firmware is slower than 2651 * hardware based TSO. Moreover the firmware based TSO has one 2652 * known bug which can't handle TSO if ethernet header + IP/TCP 2653 * header is greater than 80 bytes. The workaround for the TSO 2654 * bug exist but it seems it's too expensive than not using 2655 * TSO at all. Some hardwares also have the TSO bug so limit 2656 * the TSO to the controllers that are not affected TSO issues 2657 * (e.g. 5755 or higher). 2658 */ 2659 if (BGE_IS_5755_PLUS(sc)) { 2660 /* 2661 * BCM5754 and BCM5787 shares the same ASIC id so 2662 * explicit device id check is required. 2663 * Due to unknown reason TSO does not work on BCM5755M. 2664 */ 2665 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 2666 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 2667 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 2668 sc->bge_flags |= BGE_FLAG_TSO; 2669 } 2670 2671 /* 2672 * Check if this is a PCI-X or PCI Express device. 2673 */ 2674 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) { 2675 /* 2676 * Found a PCI Express capabilities register, this 2677 * must be a PCI Express device. 2678 */ 2679 sc->bge_flags |= BGE_FLAG_PCIE; 2680 sc->bge_expcap = reg; 2681 if (pci_get_max_read_req(dev) != 4096) 2682 pci_set_max_read_req(dev, 4096); 2683 } else { 2684 /* 2685 * Check if the device is in PCI-X Mode. 2686 * (This bit is not valid on PCI Express controllers.) 2687 */ 2688 if (pci_find_extcap(dev, PCIY_PCIX, ®) == 0) 2689 sc->bge_pcixcap = reg; 2690 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 2691 BGE_PCISTATE_PCI_BUSMODE) == 0) 2692 sc->bge_flags |= BGE_FLAG_PCIX; 2693 } 2694 2695 /* 2696 * The 40bit DMA bug applies to the 5714/5715 controllers and is 2697 * not actually a MAC controller bug but an issue with the embedded 2698 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 2699 */ 2700 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 2701 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 2702 /* 2703 * Allocate the interrupt, using MSI if possible. These devices 2704 * support 8 MSI messages, but only the first one is used in 2705 * normal operation. 2706 */ 2707 rid = 0; 2708 if (pci_find_extcap(sc->bge_dev, PCIY_MSI, ®) == 0) { 2709 sc->bge_msicap = reg; 2710 if (bge_can_use_msi(sc)) { 2711 msicount = pci_msi_count(dev); 2712 if (msicount > 1) 2713 msicount = 1; 2714 } else 2715 msicount = 0; 2716 if (msicount == 1 && pci_alloc_msi(dev, &msicount) == 0) { 2717 rid = 1; 2718 sc->bge_flags |= BGE_FLAG_MSI; 2719 } 2720 } 2721 2722 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 2723 RF_SHAREABLE | RF_ACTIVE); 2724 2725 if (sc->bge_irq == NULL) { 2726 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 2727 error = ENXIO; 2728 goto fail; 2729 } 2730 2731 if (bootverbose) 2732 device_printf(dev, 2733 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n", 2734 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev, 2735 (sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" : 2736 ((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI")); 2737 2738 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 2739 2740 /* Try to reset the chip. */ 2741 if (bge_reset(sc)) { 2742 device_printf(sc->bge_dev, "chip reset failed\n"); 2743 error = ENXIO; 2744 goto fail; 2745 } 2746 2747 sc->bge_asf_mode = 0; 2748 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) 2749 == BGE_MAGIC_NUMBER)) { 2750 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG) 2751 & BGE_HWCFG_ASF) { 2752 sc->bge_asf_mode |= ASF_ENABLE; 2753 sc->bge_asf_mode |= ASF_STACKUP; 2754 if (BGE_IS_575X_PLUS(sc)) 2755 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 2756 } 2757 } 2758 2759 /* Try to reset the chip again the nice way. */ 2760 bge_stop_fw(sc); 2761 bge_sig_pre_reset(sc, BGE_RESET_STOP); 2762 if (bge_reset(sc)) { 2763 device_printf(sc->bge_dev, "chip reset failed\n"); 2764 error = ENXIO; 2765 goto fail; 2766 } 2767 2768 bge_sig_legacy(sc, BGE_RESET_STOP); 2769 bge_sig_post_reset(sc, BGE_RESET_STOP); 2770 2771 if (bge_chipinit(sc)) { 2772 device_printf(sc->bge_dev, "chip initialization failed\n"); 2773 error = ENXIO; 2774 goto fail; 2775 } 2776 2777 error = bge_get_eaddr(sc, eaddr); 2778 if (error) { 2779 device_printf(sc->bge_dev, 2780 "failed to read station address\n"); 2781 error = ENXIO; 2782 goto fail; 2783 } 2784 2785 /* 5705 limits RX return ring to 512 entries. */ 2786 if (BGE_IS_5705_PLUS(sc)) 2787 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 2788 else 2789 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 2790 2791 if (bge_dma_alloc(dev)) { 2792 device_printf(sc->bge_dev, 2793 "failed to allocate DMA resources\n"); 2794 error = ENXIO; 2795 goto fail; 2796 } 2797 2798 /* Set default tuneable values. */ 2799 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 2800 sc->bge_rx_coal_ticks = 150; 2801 sc->bge_tx_coal_ticks = 150; 2802 sc->bge_rx_max_coal_bds = 10; 2803 sc->bge_tx_max_coal_bds = 10; 2804 2805 /* Set up ifnet structure */ 2806 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 2807 if (ifp == NULL) { 2808 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 2809 error = ENXIO; 2810 goto fail; 2811 } 2812 ifp->if_softc = sc; 2813 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 2814 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 2815 ifp->if_ioctl = bge_ioctl; 2816 ifp->if_start = bge_start; 2817 ifp->if_init = bge_init; 2818 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 2819 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 2820 IFQ_SET_READY(&ifp->if_snd); 2821 ifp->if_hwassist = BGE_CSUM_FEATURES; 2822 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 2823 IFCAP_VLAN_MTU; 2824 if ((sc->bge_flags & BGE_FLAG_TSO) != 0) { 2825 ifp->if_hwassist |= CSUM_TSO; 2826 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 2827 } 2828 #ifdef IFCAP_VLAN_HWCSUM 2829 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 2830 #endif 2831 ifp->if_capenable = ifp->if_capabilities; 2832 #ifdef DEVICE_POLLING 2833 ifp->if_capabilities |= IFCAP_POLLING; 2834 #endif 2835 2836 /* 2837 * 5700 B0 chips do not support checksumming correctly due 2838 * to hardware bugs. 2839 */ 2840 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 2841 ifp->if_capabilities &= ~IFCAP_HWCSUM; 2842 ifp->if_capenable &= ~IFCAP_HWCSUM; 2843 ifp->if_hwassist = 0; 2844 } 2845 2846 /* 2847 * Figure out what sort of media we have by checking the 2848 * hardware config word in the first 32k of NIC internal memory, 2849 * or fall back to examining the EEPROM if necessary. 2850 * Note: on some BCM5700 cards, this value appears to be unset. 2851 * If that's the case, we have to rely on identifying the NIC 2852 * by its PCI subsystem ID, as we do below for the SysKonnect 2853 * SK-9D41. 2854 */ 2855 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 2856 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 2857 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 2858 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 2859 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 2860 sizeof(hwcfg))) { 2861 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 2862 error = ENXIO; 2863 goto fail; 2864 } 2865 hwcfg = ntohl(hwcfg); 2866 } 2867 2868 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 2869 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 2870 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 2871 if (BGE_IS_5714_FAMILY(sc)) 2872 sc->bge_flags |= BGE_FLAG_MII_SERDES; 2873 else 2874 sc->bge_flags |= BGE_FLAG_TBI; 2875 } 2876 2877 if (sc->bge_flags & BGE_FLAG_TBI) { 2878 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 2879 bge_ifmedia_sts); 2880 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 2881 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 2882 0, NULL); 2883 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 2884 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 2885 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 2886 } else { 2887 /* 2888 * Do transceiver setup and tell the firmware the 2889 * driver is down so we can try to get access the 2890 * probe if ASF is running. Retry a couple of times 2891 * if we get a conflict with the ASF firmware accessing 2892 * the PHY. 2893 */ 2894 trys = 0; 2895 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2896 again: 2897 bge_asf_driver_up(sc); 2898 2899 if (mii_phy_probe(dev, &sc->bge_miibus, 2900 bge_ifmedia_upd, bge_ifmedia_sts)) { 2901 if (trys++ < 4) { 2902 device_printf(sc->bge_dev, "Try again\n"); 2903 bge_miibus_writereg(sc->bge_dev, 1, MII_BMCR, 2904 BMCR_RESET); 2905 goto again; 2906 } 2907 2908 device_printf(sc->bge_dev, "MII without any PHY!\n"); 2909 error = ENXIO; 2910 goto fail; 2911 } 2912 2913 /* 2914 * Now tell the firmware we are going up after probing the PHY 2915 */ 2916 if (sc->bge_asf_mode & ASF_STACKUP) 2917 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2918 } 2919 2920 /* 2921 * When using the BCM5701 in PCI-X mode, data corruption has 2922 * been observed in the first few bytes of some received packets. 2923 * Aligning the packet buffer in memory eliminates the corruption. 2924 * Unfortunately, this misaligns the packet payloads. On platforms 2925 * which do not support unaligned accesses, we will realign the 2926 * payloads by copying the received packets. 2927 */ 2928 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 2929 sc->bge_flags & BGE_FLAG_PCIX) 2930 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 2931 2932 /* 2933 * Call MI attach routine. 2934 */ 2935 ether_ifattach(ifp, eaddr); 2936 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 2937 2938 /* Tell upper layer we support long frames. */ 2939 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 2940 2941 /* 2942 * Hookup IRQ last. 2943 */ 2944 #if __FreeBSD_version > 700030 2945 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 2946 /* Take advantage of single-shot MSI. */ 2947 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 2948 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 2949 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 2950 taskqueue_thread_enqueue, &sc->bge_tq); 2951 if (sc->bge_tq == NULL) { 2952 device_printf(dev, "could not create taskqueue.\n"); 2953 ether_ifdetach(ifp); 2954 error = ENXIO; 2955 goto fail; 2956 } 2957 taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, "%s taskq", 2958 device_get_nameunit(sc->bge_dev)); 2959 error = bus_setup_intr(dev, sc->bge_irq, 2960 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 2961 &sc->bge_intrhand); 2962 if (error) 2963 ether_ifdetach(ifp); 2964 } else 2965 error = bus_setup_intr(dev, sc->bge_irq, 2966 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 2967 &sc->bge_intrhand); 2968 #else 2969 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET | INTR_MPSAFE, 2970 bge_intr, sc, &sc->bge_intrhand); 2971 #endif 2972 2973 if (error) { 2974 bge_detach(dev); 2975 device_printf(sc->bge_dev, "couldn't set up irq\n"); 2976 } 2977 2978 bge_add_sysctls(sc); 2979 2980 return (0); 2981 2982 fail: 2983 bge_release_resources(sc); 2984 2985 return (error); 2986 } 2987 2988 static int 2989 bge_detach(device_t dev) 2990 { 2991 struct bge_softc *sc; 2992 struct ifnet *ifp; 2993 2994 sc = device_get_softc(dev); 2995 ifp = sc->bge_ifp; 2996 2997 #ifdef DEVICE_POLLING 2998 if (ifp->if_capenable & IFCAP_POLLING) 2999 ether_poll_deregister(ifp); 3000 #endif 3001 3002 BGE_LOCK(sc); 3003 bge_stop(sc); 3004 bge_reset(sc); 3005 BGE_UNLOCK(sc); 3006 3007 callout_drain(&sc->bge_stat_ch); 3008 3009 if (sc->bge_tq) 3010 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3011 ether_ifdetach(ifp); 3012 3013 if (sc->bge_flags & BGE_FLAG_TBI) { 3014 ifmedia_removeall(&sc->bge_ifmedia); 3015 } else { 3016 bus_generic_detach(dev); 3017 device_delete_child(dev, sc->bge_miibus); 3018 } 3019 3020 bge_release_resources(sc); 3021 3022 return (0); 3023 } 3024 3025 static void 3026 bge_release_resources(struct bge_softc *sc) 3027 { 3028 device_t dev; 3029 3030 dev = sc->bge_dev; 3031 3032 if (sc->bge_tq != NULL) 3033 taskqueue_free(sc->bge_tq); 3034 3035 if (sc->bge_intrhand != NULL) 3036 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3037 3038 if (sc->bge_irq != NULL) 3039 bus_release_resource(dev, SYS_RES_IRQ, 3040 sc->bge_flags & BGE_FLAG_MSI ? 1 : 0, sc->bge_irq); 3041 3042 if (sc->bge_flags & BGE_FLAG_MSI) 3043 pci_release_msi(dev); 3044 3045 if (sc->bge_res != NULL) 3046 bus_release_resource(dev, SYS_RES_MEMORY, 3047 PCIR_BAR(0), sc->bge_res); 3048 3049 if (sc->bge_ifp != NULL) 3050 if_free(sc->bge_ifp); 3051 3052 bge_dma_free(sc); 3053 3054 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 3055 BGE_LOCK_DESTROY(sc); 3056 } 3057 3058 static int 3059 bge_reset(struct bge_softc *sc) 3060 { 3061 device_t dev; 3062 uint32_t cachesize, command, pcistate, reset, val; 3063 void (*write_op)(struct bge_softc *, int, int); 3064 uint16_t devctl; 3065 int i; 3066 3067 dev = sc->bge_dev; 3068 3069 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 3070 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3071 if (sc->bge_flags & BGE_FLAG_PCIE) 3072 write_op = bge_writemem_direct; 3073 else 3074 write_op = bge_writemem_ind; 3075 } else 3076 write_op = bge_writereg_ind; 3077 3078 /* Save some important PCI state. */ 3079 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 3080 command = pci_read_config(dev, BGE_PCI_CMD, 4); 3081 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3082 3083 pci_write_config(dev, BGE_PCI_MISC_CTL, 3084 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3085 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3086 3087 /* Disable fastboot on controllers that support it. */ 3088 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 3089 BGE_IS_5755_PLUS(sc)) { 3090 if (bootverbose) 3091 device_printf(dev, "Disabling fastboot\n"); 3092 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 3093 } 3094 3095 /* 3096 * Write the magic number to SRAM at offset 0xB50. 3097 * When firmware finishes its initialization it will 3098 * write ~BGE_MAGIC_NUMBER to the same location. 3099 */ 3100 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 3101 3102 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 3103 3104 /* XXX: Broadcom Linux driver. */ 3105 if (sc->bge_flags & BGE_FLAG_PCIE) { 3106 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 3107 CSR_WRITE_4(sc, 0x7E2C, 0x20); 3108 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 3109 /* Prevent PCIE link training during global reset */ 3110 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 3111 reset |= 1 << 29; 3112 } 3113 } 3114 3115 /* 3116 * Set GPHY Power Down Override to leave GPHY 3117 * powered up in D0 uninitialized. 3118 */ 3119 if (BGE_IS_5705_PLUS(sc)) 3120 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 3121 3122 /* Issue global reset */ 3123 write_op(sc, BGE_MISC_CFG, reset); 3124 3125 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3126 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3127 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 3128 val | BGE_VCPU_STATUS_DRV_RESET); 3129 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 3130 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 3131 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 3132 } 3133 3134 DELAY(1000); 3135 3136 /* XXX: Broadcom Linux driver. */ 3137 if (sc->bge_flags & BGE_FLAG_PCIE) { 3138 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 3139 DELAY(500000); /* wait for link training to complete */ 3140 val = pci_read_config(dev, 0xC4, 4); 3141 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 3142 } 3143 devctl = pci_read_config(dev, 3144 sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 2); 3145 /* Clear enable no snoop and disable relaxed ordering. */ 3146 devctl &= ~(PCIM_EXP_CTL_RELAXED_ORD_ENABLE | 3147 PCIM_EXP_CTL_NOSNOOP_ENABLE); 3148 /* Set PCIE max payload size to 128. */ 3149 devctl &= ~PCIM_EXP_CTL_MAX_PAYLOAD; 3150 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_CTL, 3151 devctl, 2); 3152 /* Clear error status. */ 3153 pci_write_config(dev, sc->bge_expcap + PCIR_EXPRESS_DEVICE_STA, 3154 PCIM_EXP_STA_CORRECTABLE_ERROR | 3155 PCIM_EXP_STA_NON_FATAL_ERROR | PCIM_EXP_STA_FATAL_ERROR | 3156 PCIM_EXP_STA_UNSUPPORTED_REQ, 2); 3157 } 3158 3159 /* Reset some of the PCI state that got zapped by reset. */ 3160 pci_write_config(dev, BGE_PCI_MISC_CTL, 3161 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 3162 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 3163 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 3164 pci_write_config(dev, BGE_PCI_CMD, command, 4); 3165 write_op(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 3166 /* 3167 * Disable PCI-X relaxed ordering to ensure status block update 3168 * comes first then packet buffer DMA. Otherwise driver may 3169 * read stale status block. 3170 */ 3171 if (sc->bge_flags & BGE_FLAG_PCIX) { 3172 devctl = pci_read_config(dev, 3173 sc->bge_pcixcap + PCIXR_COMMAND, 2); 3174 devctl &= ~PCIXM_COMMAND_ERO; 3175 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 3176 devctl &= ~PCIXM_COMMAND_MAX_READ; 3177 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3178 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 3179 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 3180 PCIXM_COMMAND_MAX_READ); 3181 devctl |= PCIXM_COMMAND_MAX_READ_2048; 3182 } 3183 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 3184 devctl, 2); 3185 } 3186 /* Re-enable MSI, if neccesary, and enable the memory arbiter. */ 3187 if (BGE_IS_5714_FAMILY(sc)) { 3188 /* This chip disables MSI on reset. */ 3189 if (sc->bge_flags & BGE_FLAG_MSI) { 3190 val = pci_read_config(dev, 3191 sc->bge_msicap + PCIR_MSI_CTRL, 2); 3192 pci_write_config(dev, 3193 sc->bge_msicap + PCIR_MSI_CTRL, 3194 val | PCIM_MSICTRL_MSI_ENABLE, 2); 3195 val = CSR_READ_4(sc, BGE_MSI_MODE); 3196 CSR_WRITE_4(sc, BGE_MSI_MODE, 3197 val | BGE_MSIMODE_ENABLE); 3198 } 3199 val = CSR_READ_4(sc, BGE_MARB_MODE); 3200 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 3201 } else 3202 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 3203 3204 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3205 for (i = 0; i < BGE_TIMEOUT; i++) { 3206 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 3207 if (val & BGE_VCPU_STATUS_INIT_DONE) 3208 break; 3209 DELAY(100); 3210 } 3211 if (i == BGE_TIMEOUT) { 3212 device_printf(dev, "reset timed out\n"); 3213 return (1); 3214 } 3215 } else { 3216 /* 3217 * Poll until we see the 1's complement of the magic number. 3218 * This indicates that the firmware initialization is complete. 3219 * We expect this to fail if no chip containing the Ethernet 3220 * address is fitted though. 3221 */ 3222 for (i = 0; i < BGE_TIMEOUT; i++) { 3223 DELAY(10); 3224 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 3225 if (val == ~BGE_MAGIC_NUMBER) 3226 break; 3227 } 3228 3229 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 3230 device_printf(dev, 3231 "firmware handshake timed out, found 0x%08x\n", 3232 val); 3233 } 3234 3235 /* 3236 * XXX Wait for the value of the PCISTATE register to 3237 * return to its original pre-reset state. This is a 3238 * fairly good indicator of reset completion. If we don't 3239 * wait for the reset to fully complete, trying to read 3240 * from the device's non-PCI registers may yield garbage 3241 * results. 3242 */ 3243 for (i = 0; i < BGE_TIMEOUT; i++) { 3244 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 3245 break; 3246 DELAY(10); 3247 } 3248 3249 /* Fix up byte swapping. */ 3250 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS | 3251 BGE_MODECTL_BYTESWAP_DATA); 3252 3253 /* Tell the ASF firmware we are up */ 3254 if (sc->bge_asf_mode & ASF_STACKUP) 3255 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3256 3257 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 3258 3259 /* 3260 * The 5704 in TBI mode apparently needs some special 3261 * adjustment to insure the SERDES drive level is set 3262 * to 1.2V. 3263 */ 3264 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 3265 sc->bge_flags & BGE_FLAG_TBI) { 3266 val = CSR_READ_4(sc, BGE_SERDES_CFG); 3267 val = (val & ~0xFFF) | 0x880; 3268 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 3269 } 3270 3271 /* XXX: Broadcom Linux driver. */ 3272 if (sc->bge_flags & BGE_FLAG_PCIE && 3273 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 3274 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 3275 /* Enable Data FIFO protection. */ 3276 val = CSR_READ_4(sc, 0x7C00); 3277 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 3278 } 3279 DELAY(10000); 3280 3281 return (0); 3282 } 3283 3284 static __inline void 3285 bge_rxreuse_std(struct bge_softc *sc, int i) 3286 { 3287 struct bge_rx_bd *r; 3288 3289 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 3290 r->bge_flags = BGE_RXBDFLAG_END; 3291 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 3292 r->bge_idx = i; 3293 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3294 } 3295 3296 static __inline void 3297 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 3298 { 3299 struct bge_extrx_bd *r; 3300 3301 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 3302 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 3303 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 3304 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 3305 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 3306 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 3307 r->bge_idx = i; 3308 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3309 } 3310 3311 /* 3312 * Frame reception handling. This is called if there's a frame 3313 * on the receive return list. 3314 * 3315 * Note: we have to be able to handle two possibilities here: 3316 * 1) the frame is from the jumbo receive ring 3317 * 2) the frame is from the standard receive ring 3318 */ 3319 3320 static int 3321 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 3322 { 3323 struct ifnet *ifp; 3324 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 3325 uint16_t rx_cons; 3326 3327 rx_cons = sc->bge_rx_saved_considx; 3328 3329 /* Nothing to do. */ 3330 if (rx_cons == rx_prod) 3331 return (rx_npkts); 3332 3333 ifp = sc->bge_ifp; 3334 3335 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3336 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 3337 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3338 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 3339 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 3340 (MCLBYTES - ETHER_ALIGN)) 3341 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3342 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 3343 3344 while (rx_cons != rx_prod) { 3345 struct bge_rx_bd *cur_rx; 3346 uint32_t rxidx; 3347 struct mbuf *m = NULL; 3348 uint16_t vlan_tag = 0; 3349 int have_tag = 0; 3350 3351 #ifdef DEVICE_POLLING 3352 if (ifp->if_capenable & IFCAP_POLLING) { 3353 if (sc->rxcycles <= 0) 3354 break; 3355 sc->rxcycles--; 3356 } 3357 #endif 3358 3359 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 3360 3361 rxidx = cur_rx->bge_idx; 3362 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 3363 3364 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 3365 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 3366 have_tag = 1; 3367 vlan_tag = cur_rx->bge_vlan_tag; 3368 } 3369 3370 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 3371 jumbocnt++; 3372 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 3373 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3374 bge_rxreuse_jumbo(sc, rxidx); 3375 continue; 3376 } 3377 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 3378 bge_rxreuse_jumbo(sc, rxidx); 3379 ifp->if_iqdrops++; 3380 continue; 3381 } 3382 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 3383 } else { 3384 stdcnt++; 3385 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 3386 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 3387 bge_rxreuse_std(sc, rxidx); 3388 continue; 3389 } 3390 if (bge_newbuf_std(sc, rxidx) != 0) { 3391 bge_rxreuse_std(sc, rxidx); 3392 ifp->if_iqdrops++; 3393 continue; 3394 } 3395 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 3396 } 3397 3398 ifp->if_ipackets++; 3399 #ifndef __NO_STRICT_ALIGNMENT 3400 /* 3401 * For architectures with strict alignment we must make sure 3402 * the payload is aligned. 3403 */ 3404 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 3405 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 3406 cur_rx->bge_len); 3407 m->m_data += ETHER_ALIGN; 3408 } 3409 #endif 3410 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 3411 m->m_pkthdr.rcvif = ifp; 3412 3413 if (ifp->if_capenable & IFCAP_RXCSUM) { 3414 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 3415 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3416 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 3417 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3418 } 3419 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 3420 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 3421 m->m_pkthdr.csum_data = 3422 cur_rx->bge_tcp_udp_csum; 3423 m->m_pkthdr.csum_flags |= 3424 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 3425 } 3426 } 3427 3428 /* 3429 * If we received a packet with a vlan tag, 3430 * attach that information to the packet. 3431 */ 3432 if (have_tag) { 3433 #if __FreeBSD_version > 700022 3434 m->m_pkthdr.ether_vtag = vlan_tag; 3435 m->m_flags |= M_VLANTAG; 3436 #else 3437 VLAN_INPUT_TAG_NEW(ifp, m, vlan_tag); 3438 if (m == NULL) 3439 continue; 3440 #endif 3441 } 3442 3443 if (holdlck != 0) { 3444 BGE_UNLOCK(sc); 3445 (*ifp->if_input)(ifp, m); 3446 BGE_LOCK(sc); 3447 } else 3448 (*ifp->if_input)(ifp, m); 3449 rx_npkts++; 3450 3451 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 3452 return (rx_npkts); 3453 } 3454 3455 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 3456 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 3457 if (stdcnt > 0) 3458 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 3459 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 3460 3461 if (jumbocnt > 0) 3462 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 3463 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 3464 3465 sc->bge_rx_saved_considx = rx_cons; 3466 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 3467 if (stdcnt) 3468 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 3469 if (jumbocnt) 3470 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 3471 #ifdef notyet 3472 /* 3473 * This register wraps very quickly under heavy packet drops. 3474 * If you need correct statistics, you can enable this check. 3475 */ 3476 if (BGE_IS_5705_PLUS(sc)) 3477 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3478 #endif 3479 return (rx_npkts); 3480 } 3481 3482 static void 3483 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 3484 { 3485 struct bge_tx_bd *cur_tx = NULL; 3486 struct ifnet *ifp; 3487 3488 BGE_LOCK_ASSERT(sc); 3489 3490 /* Nothing to do. */ 3491 if (sc->bge_tx_saved_considx == tx_cons) 3492 return; 3493 3494 ifp = sc->bge_ifp; 3495 3496 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 3497 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3498 /* 3499 * Go through our tx ring and free mbufs for those 3500 * frames that have been sent. 3501 */ 3502 while (sc->bge_tx_saved_considx != tx_cons) { 3503 uint32_t idx = 0; 3504 3505 idx = sc->bge_tx_saved_considx; 3506 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 3507 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 3508 ifp->if_opackets++; 3509 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 3510 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 3511 sc->bge_cdata.bge_tx_dmamap[idx], 3512 BUS_DMASYNC_POSTWRITE); 3513 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 3514 sc->bge_cdata.bge_tx_dmamap[idx]); 3515 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 3516 sc->bge_cdata.bge_tx_chain[idx] = NULL; 3517 } 3518 sc->bge_txcnt--; 3519 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 3520 } 3521 3522 if (cur_tx != NULL) 3523 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3524 if (sc->bge_txcnt == 0) 3525 sc->bge_timer = 0; 3526 } 3527 3528 #ifdef DEVICE_POLLING 3529 static int 3530 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 3531 { 3532 struct bge_softc *sc = ifp->if_softc; 3533 uint16_t rx_prod, tx_cons; 3534 uint32_t statusword; 3535 int rx_npkts = 0; 3536 3537 BGE_LOCK(sc); 3538 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3539 BGE_UNLOCK(sc); 3540 return (rx_npkts); 3541 } 3542 3543 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3544 sc->bge_cdata.bge_status_map, 3545 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3546 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3547 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3548 3549 statusword = atomic_readandclear_32( 3550 &sc->bge_ldata.bge_status_block->bge_status); 3551 3552 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3553 sc->bge_cdata.bge_status_map, 3554 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3555 3556 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 3557 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 3558 sc->bge_link_evt++; 3559 3560 if (cmd == POLL_AND_CHECK_STATUS) 3561 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3562 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3563 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 3564 bge_link_upd(sc); 3565 3566 sc->rxcycles = count; 3567 rx_npkts = bge_rxeof(sc, rx_prod, 1); 3568 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 3569 BGE_UNLOCK(sc); 3570 return (rx_npkts); 3571 } 3572 bge_txeof(sc, tx_cons); 3573 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3574 bge_start_locked(ifp); 3575 3576 BGE_UNLOCK(sc); 3577 return (rx_npkts); 3578 } 3579 #endif /* DEVICE_POLLING */ 3580 3581 static int 3582 bge_msi_intr(void *arg) 3583 { 3584 struct bge_softc *sc; 3585 3586 sc = (struct bge_softc *)arg; 3587 /* 3588 * This interrupt is not shared and controller already 3589 * disabled further interrupt. 3590 */ 3591 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 3592 return (FILTER_HANDLED); 3593 } 3594 3595 static void 3596 bge_intr_task(void *arg, int pending) 3597 { 3598 struct bge_softc *sc; 3599 struct ifnet *ifp; 3600 uint32_t status; 3601 uint16_t rx_prod, tx_cons; 3602 3603 sc = (struct bge_softc *)arg; 3604 ifp = sc->bge_ifp; 3605 3606 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3607 return; 3608 3609 /* Get updated status block. */ 3610 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3611 sc->bge_cdata.bge_status_map, 3612 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3613 3614 /* Save producer/consumer indexess. */ 3615 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3616 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3617 status = sc->bge_ldata.bge_status_block->bge_status; 3618 sc->bge_ldata.bge_status_block->bge_status = 0; 3619 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3620 sc->bge_cdata.bge_status_map, 3621 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3622 /* Let controller work. */ 3623 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3624 3625 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) { 3626 BGE_LOCK(sc); 3627 bge_link_upd(sc); 3628 BGE_UNLOCK(sc); 3629 } 3630 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3631 /* Check RX return ring producer/consumer. */ 3632 bge_rxeof(sc, rx_prod, 0); 3633 } 3634 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3635 BGE_LOCK(sc); 3636 /* Check TX ring producer/consumer. */ 3637 bge_txeof(sc, tx_cons); 3638 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3639 bge_start_locked(ifp); 3640 BGE_UNLOCK(sc); 3641 } 3642 } 3643 3644 static void 3645 bge_intr(void *xsc) 3646 { 3647 struct bge_softc *sc; 3648 struct ifnet *ifp; 3649 uint32_t statusword; 3650 uint16_t rx_prod, tx_cons; 3651 3652 sc = xsc; 3653 3654 BGE_LOCK(sc); 3655 3656 ifp = sc->bge_ifp; 3657 3658 #ifdef DEVICE_POLLING 3659 if (ifp->if_capenable & IFCAP_POLLING) { 3660 BGE_UNLOCK(sc); 3661 return; 3662 } 3663 #endif 3664 3665 /* 3666 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 3667 * disable interrupts by writing nonzero like we used to, since with 3668 * our current organization this just gives complications and 3669 * pessimizations for re-enabling interrupts. We used to have races 3670 * instead of the necessary complications. Disabling interrupts 3671 * would just reduce the chance of a status update while we are 3672 * running (by switching to the interrupt-mode coalescence 3673 * parameters), but this chance is already very low so it is more 3674 * efficient to get another interrupt than prevent it. 3675 * 3676 * We do the ack first to ensure another interrupt if there is a 3677 * status update after the ack. We don't check for the status 3678 * changing later because it is more efficient to get another 3679 * interrupt than prevent it, not quite as above (not checking is 3680 * a smaller optimization than not toggling the interrupt enable, 3681 * since checking doesn't involve PCI accesses and toggling require 3682 * the status check). So toggling would probably be a pessimization 3683 * even with MSI. It would only be needed for using a task queue. 3684 */ 3685 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 3686 3687 /* 3688 * Do the mandatory PCI flush as well as get the link status. 3689 */ 3690 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 3691 3692 /* Make sure the descriptor ring indexes are coherent. */ 3693 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3694 sc->bge_cdata.bge_status_map, 3695 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3696 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 3697 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 3698 sc->bge_ldata.bge_status_block->bge_status = 0; 3699 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 3700 sc->bge_cdata.bge_status_map, 3701 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3702 3703 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 3704 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 3705 statusword || sc->bge_link_evt) 3706 bge_link_upd(sc); 3707 3708 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3709 /* Check RX return ring producer/consumer. */ 3710 bge_rxeof(sc, rx_prod, 1); 3711 } 3712 3713 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3714 /* Check TX ring producer/consumer. */ 3715 bge_txeof(sc, tx_cons); 3716 } 3717 3718 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 3719 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3720 bge_start_locked(ifp); 3721 3722 BGE_UNLOCK(sc); 3723 } 3724 3725 static void 3726 bge_asf_driver_up(struct bge_softc *sc) 3727 { 3728 if (sc->bge_asf_mode & ASF_STACKUP) { 3729 /* Send ASF heartbeat aprox. every 2s */ 3730 if (sc->bge_asf_count) 3731 sc->bge_asf_count --; 3732 else { 3733 sc->bge_asf_count = 2; 3734 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM_FW, 3735 BGE_FW_DRV_ALIVE); 3736 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_LEN, 4); 3737 bge_writemem_ind(sc, BGE_SOFTWARE_GENNCOMM_FW_DATA, 3); 3738 CSR_WRITE_4(sc, BGE_CPU_EVENT, 3739 CSR_READ_4(sc, BGE_CPU_EVENT) | (1 << 14)); 3740 } 3741 } 3742 } 3743 3744 static void 3745 bge_tick(void *xsc) 3746 { 3747 struct bge_softc *sc = xsc; 3748 struct mii_data *mii = NULL; 3749 3750 BGE_LOCK_ASSERT(sc); 3751 3752 /* Synchronize with possible callout reset/stop. */ 3753 if (callout_pending(&sc->bge_stat_ch) || 3754 !callout_active(&sc->bge_stat_ch)) 3755 return; 3756 3757 if (BGE_IS_5705_PLUS(sc)) 3758 bge_stats_update_regs(sc); 3759 else 3760 bge_stats_update(sc); 3761 3762 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 3763 mii = device_get_softc(sc->bge_miibus); 3764 /* 3765 * Do not touch PHY if we have link up. This could break 3766 * IPMI/ASF mode or produce extra input errors 3767 * (extra errors was reported for bcm5701 & bcm5704). 3768 */ 3769 if (!sc->bge_link) 3770 mii_tick(mii); 3771 } else { 3772 /* 3773 * Since in TBI mode auto-polling can't be used we should poll 3774 * link status manually. Here we register pending link event 3775 * and trigger interrupt. 3776 */ 3777 #ifdef DEVICE_POLLING 3778 /* In polling mode we poll link state in bge_poll(). */ 3779 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 3780 #endif 3781 { 3782 sc->bge_link_evt++; 3783 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3784 sc->bge_flags & BGE_FLAG_5788) 3785 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 3786 else 3787 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 3788 } 3789 } 3790 3791 bge_asf_driver_up(sc); 3792 bge_watchdog(sc); 3793 3794 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 3795 } 3796 3797 static void 3798 bge_stats_update_regs(struct bge_softc *sc) 3799 { 3800 struct ifnet *ifp; 3801 3802 ifp = sc->bge_ifp; 3803 3804 ifp->if_collisions += CSR_READ_4(sc, BGE_MAC_STATS + 3805 offsetof(struct bge_mac_stats_regs, etherStatsCollisions)); 3806 3807 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 3808 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 3809 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 3810 } 3811 3812 static void 3813 bge_stats_update(struct bge_softc *sc) 3814 { 3815 struct ifnet *ifp; 3816 bus_size_t stats; 3817 uint32_t cnt; /* current register value */ 3818 3819 ifp = sc->bge_ifp; 3820 3821 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 3822 3823 #define READ_STAT(sc, stats, stat) \ 3824 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 3825 3826 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 3827 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 3828 sc->bge_tx_collisions = cnt; 3829 3830 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 3831 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 3832 sc->bge_rx_discards = cnt; 3833 3834 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 3835 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 3836 sc->bge_tx_discards = cnt; 3837 3838 #undef READ_STAT 3839 } 3840 3841 /* 3842 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 3843 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 3844 * but when such padded frames employ the bge IP/TCP checksum offload, 3845 * the hardware checksum assist gives incorrect results (possibly 3846 * from incorporating its own padding into the UDP/TCP checksum; who knows). 3847 * If we pad such runts with zeros, the onboard checksum comes out correct. 3848 */ 3849 static __inline int 3850 bge_cksum_pad(struct mbuf *m) 3851 { 3852 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 3853 struct mbuf *last; 3854 3855 /* If there's only the packet-header and we can pad there, use it. */ 3856 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 3857 M_TRAILINGSPACE(m) >= padlen) { 3858 last = m; 3859 } else { 3860 /* 3861 * Walk packet chain to find last mbuf. We will either 3862 * pad there, or append a new mbuf and pad it. 3863 */ 3864 for (last = m; last->m_next != NULL; last = last->m_next); 3865 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 3866 /* Allocate new empty mbuf, pad it. Compact later. */ 3867 struct mbuf *n; 3868 3869 MGET(n, M_DONTWAIT, MT_DATA); 3870 if (n == NULL) 3871 return (ENOBUFS); 3872 n->m_len = 0; 3873 last->m_next = n; 3874 last = n; 3875 } 3876 } 3877 3878 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 3879 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 3880 last->m_len += padlen; 3881 m->m_pkthdr.len += padlen; 3882 3883 return (0); 3884 } 3885 3886 static struct mbuf * 3887 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss) 3888 { 3889 struct ip *ip; 3890 struct tcphdr *tcp; 3891 struct mbuf *n; 3892 uint16_t hlen; 3893 uint32_t poff; 3894 3895 if (M_WRITABLE(m) == 0) { 3896 /* Get a writable copy. */ 3897 n = m_dup(m, M_DONTWAIT); 3898 m_freem(m); 3899 if (n == NULL) 3900 return (NULL); 3901 m = n; 3902 } 3903 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 3904 if (m == NULL) 3905 return (NULL); 3906 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 3907 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 3908 m = m_pullup(m, poff + sizeof(struct tcphdr)); 3909 if (m == NULL) 3910 return (NULL); 3911 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 3912 m = m_pullup(m, poff + (tcp->th_off << 2)); 3913 if (m == NULL) 3914 return (NULL); 3915 /* 3916 * It seems controller doesn't modify IP length and TCP pseudo 3917 * checksum. These checksum computed by upper stack should be 0. 3918 */ 3919 *mss = m->m_pkthdr.tso_segsz; 3920 ip->ip_sum = 0; 3921 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 3922 /* Clear pseudo checksum computed by TCP stack. */ 3923 tcp->th_sum = 0; 3924 /* 3925 * Broadcom controllers uses different descriptor format for 3926 * TSO depending on ASIC revision. Due to TSO-capable firmware 3927 * license issue and lower performance of firmware based TSO 3928 * we only support hardware based TSO which is applicable for 3929 * BCM5755 or newer controllers. Hardware based TSO uses 11 3930 * bits to store MSS and upper 5 bits are used to store IP/TCP 3931 * header length(including IP/TCP options). The header length 3932 * is expressed as 32 bits unit. 3933 */ 3934 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 3935 *mss |= (hlen << 11); 3936 return (m); 3937 } 3938 3939 /* 3940 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 3941 * pointers to descriptors. 3942 */ 3943 static int 3944 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 3945 { 3946 bus_dma_segment_t segs[BGE_NSEG_NEW]; 3947 bus_dmamap_t map; 3948 struct bge_tx_bd *d; 3949 struct mbuf *m = *m_head; 3950 uint32_t idx = *txidx; 3951 uint16_t csum_flags, mss, vlan_tag; 3952 int nsegs, i, error; 3953 3954 csum_flags = 0; 3955 mss = 0; 3956 vlan_tag = 0; 3957 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 3958 *m_head = m = bge_setup_tso(sc, m, &mss); 3959 if (*m_head == NULL) 3960 return (ENOBUFS); 3961 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 3962 BGE_TXBDFLAG_CPU_POST_DMA; 3963 } else if ((m->m_pkthdr.csum_flags & BGE_CSUM_FEATURES) != 0) { 3964 if (m->m_pkthdr.csum_flags & CSUM_IP) 3965 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 3966 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 3967 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 3968 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 3969 (error = bge_cksum_pad(m)) != 0) { 3970 m_freem(m); 3971 *m_head = NULL; 3972 return (error); 3973 } 3974 } 3975 if (m->m_flags & M_LASTFRAG) 3976 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 3977 else if (m->m_flags & M_FRAG) 3978 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 3979 } 3980 3981 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0 && 3982 sc->bge_forced_collapse > 0 && 3983 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 3984 /* 3985 * Forcedly collapse mbuf chains to overcome hardware 3986 * limitation which only support a single outstanding 3987 * DMA read operation. 3988 */ 3989 if (sc->bge_forced_collapse == 1) 3990 m = m_defrag(m, M_DONTWAIT); 3991 else 3992 m = m_collapse(m, M_DONTWAIT, sc->bge_forced_collapse); 3993 if (m == NULL) 3994 m = *m_head; 3995 *m_head = m; 3996 } 3997 3998 map = sc->bge_cdata.bge_tx_dmamap[idx]; 3999 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 4000 &nsegs, BUS_DMA_NOWAIT); 4001 if (error == EFBIG) { 4002 m = m_collapse(m, M_DONTWAIT, BGE_NSEG_NEW); 4003 if (m == NULL) { 4004 m_freem(*m_head); 4005 *m_head = NULL; 4006 return (ENOBUFS); 4007 } 4008 *m_head = m; 4009 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 4010 m, segs, &nsegs, BUS_DMA_NOWAIT); 4011 if (error) { 4012 m_freem(m); 4013 *m_head = NULL; 4014 return (error); 4015 } 4016 } else if (error != 0) 4017 return (error); 4018 4019 /* Check if we have enough free send BDs. */ 4020 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 4021 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 4022 return (ENOBUFS); 4023 } 4024 4025 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 4026 4027 #if __FreeBSD_version > 700022 4028 if (m->m_flags & M_VLANTAG) { 4029 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4030 vlan_tag = m->m_pkthdr.ether_vtag; 4031 } 4032 #else 4033 { 4034 struct m_tag *mtag; 4035 4036 if ((mtag = VLAN_OUTPUT_TAG(sc->bge_ifp, m)) != NULL) { 4037 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 4038 vlan_tag = VLAN_TAG_VALUE(mtag); 4039 } 4040 } 4041 #endif 4042 for (i = 0; ; i++) { 4043 d = &sc->bge_ldata.bge_tx_ring[idx]; 4044 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 4045 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 4046 d->bge_len = segs[i].ds_len; 4047 d->bge_flags = csum_flags; 4048 d->bge_vlan_tag = vlan_tag; 4049 d->bge_mss = mss; 4050 if (i == nsegs - 1) 4051 break; 4052 BGE_INC(idx, BGE_TX_RING_CNT); 4053 } 4054 4055 /* Mark the last segment as end of packet... */ 4056 d->bge_flags |= BGE_TXBDFLAG_END; 4057 4058 /* 4059 * Insure that the map for this transmission 4060 * is placed at the array index of the last descriptor 4061 * in this chain. 4062 */ 4063 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 4064 sc->bge_cdata.bge_tx_dmamap[idx] = map; 4065 sc->bge_cdata.bge_tx_chain[idx] = m; 4066 sc->bge_txcnt += nsegs; 4067 4068 BGE_INC(idx, BGE_TX_RING_CNT); 4069 *txidx = idx; 4070 4071 return (0); 4072 } 4073 4074 /* 4075 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4076 * to the mbuf data regions directly in the transmit descriptors. 4077 */ 4078 static void 4079 bge_start_locked(struct ifnet *ifp) 4080 { 4081 struct bge_softc *sc; 4082 struct mbuf *m_head; 4083 uint32_t prodidx; 4084 int count; 4085 4086 sc = ifp->if_softc; 4087 BGE_LOCK_ASSERT(sc); 4088 4089 if (!sc->bge_link || 4090 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4091 IFF_DRV_RUNNING) 4092 return; 4093 4094 prodidx = sc->bge_tx_prodidx; 4095 4096 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 4097 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 4098 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4099 break; 4100 } 4101 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 4102 if (m_head == NULL) 4103 break; 4104 4105 /* 4106 * XXX 4107 * The code inside the if() block is never reached since we 4108 * must mark CSUM_IP_FRAGS in our if_hwassist to start getting 4109 * requests to checksum TCP/UDP in a fragmented packet. 4110 * 4111 * XXX 4112 * safety overkill. If this is a fragmented packet chain 4113 * with delayed TCP/UDP checksums, then only encapsulate 4114 * it if we have enough descriptors to handle the entire 4115 * chain at once. 4116 * (paranoia -- may not actually be needed) 4117 */ 4118 if (m_head->m_flags & M_FIRSTFRAG && 4119 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 4120 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 4121 m_head->m_pkthdr.csum_data + 16) { 4122 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4123 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4124 break; 4125 } 4126 } 4127 4128 /* 4129 * Pack the data into the transmit ring. If we 4130 * don't have room, set the OACTIVE flag and wait 4131 * for the NIC to drain the ring. 4132 */ 4133 if (bge_encap(sc, &m_head, &prodidx)) { 4134 if (m_head == NULL) 4135 break; 4136 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 4137 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 4138 break; 4139 } 4140 ++count; 4141 4142 /* 4143 * If there's a BPF listener, bounce a copy of this frame 4144 * to him. 4145 */ 4146 #ifdef ETHER_BPF_MTAP 4147 ETHER_BPF_MTAP(ifp, m_head); 4148 #else 4149 BPF_MTAP(ifp, m_head); 4150 #endif 4151 } 4152 4153 if (count > 0) { 4154 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4155 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 4156 /* Transmit. */ 4157 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4158 /* 5700 b2 errata */ 4159 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 4160 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 4161 4162 sc->bge_tx_prodidx = prodidx; 4163 4164 /* 4165 * Set a timeout in case the chip goes out to lunch. 4166 */ 4167 sc->bge_timer = 5; 4168 } 4169 } 4170 4171 /* 4172 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 4173 * to the mbuf data regions directly in the transmit descriptors. 4174 */ 4175 static void 4176 bge_start(struct ifnet *ifp) 4177 { 4178 struct bge_softc *sc; 4179 4180 sc = ifp->if_softc; 4181 BGE_LOCK(sc); 4182 bge_start_locked(ifp); 4183 BGE_UNLOCK(sc); 4184 } 4185 4186 static void 4187 bge_init_locked(struct bge_softc *sc) 4188 { 4189 struct ifnet *ifp; 4190 uint16_t *m; 4191 4192 BGE_LOCK_ASSERT(sc); 4193 4194 ifp = sc->bge_ifp; 4195 4196 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4197 return; 4198 4199 /* Cancel pending I/O and flush buffers. */ 4200 bge_stop(sc); 4201 4202 bge_stop_fw(sc); 4203 bge_sig_pre_reset(sc, BGE_RESET_START); 4204 bge_reset(sc); 4205 bge_sig_legacy(sc, BGE_RESET_START); 4206 bge_sig_post_reset(sc, BGE_RESET_START); 4207 4208 bge_chipinit(sc); 4209 4210 /* 4211 * Init the various state machines, ring 4212 * control blocks and firmware. 4213 */ 4214 if (bge_blockinit(sc)) { 4215 device_printf(sc->bge_dev, "initialization failure\n"); 4216 return; 4217 } 4218 4219 ifp = sc->bge_ifp; 4220 4221 /* Specify MTU. */ 4222 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 4223 ETHER_HDR_LEN + ETHER_CRC_LEN + 4224 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 4225 4226 /* Load our MAC address. */ 4227 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 4228 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 4229 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 4230 4231 /* Program promiscuous mode. */ 4232 bge_setpromisc(sc); 4233 4234 /* Program multicast filter. */ 4235 bge_setmulti(sc); 4236 4237 /* Program VLAN tag stripping. */ 4238 bge_setvlan(sc); 4239 4240 /* Init RX ring. */ 4241 if (bge_init_rx_ring_std(sc) != 0) { 4242 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 4243 bge_stop(sc); 4244 return; 4245 } 4246 4247 /* 4248 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 4249 * memory to insure that the chip has in fact read the first 4250 * entry of the ring. 4251 */ 4252 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 4253 uint32_t v, i; 4254 for (i = 0; i < 10; i++) { 4255 DELAY(20); 4256 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 4257 if (v == (MCLBYTES - ETHER_ALIGN)) 4258 break; 4259 } 4260 if (i == 10) 4261 device_printf (sc->bge_dev, 4262 "5705 A0 chip failed to load RX ring\n"); 4263 } 4264 4265 /* Init jumbo RX ring. */ 4266 if (ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4267 (MCLBYTES - ETHER_ALIGN)) { 4268 if (bge_init_rx_ring_jumbo(sc) != 0) { 4269 device_printf(sc->bge_dev, 4270 "no memory for jumbo Rx buffers.\n"); 4271 bge_stop(sc); 4272 return; 4273 } 4274 } 4275 4276 /* Init our RX return ring index. */ 4277 sc->bge_rx_saved_considx = 0; 4278 4279 /* Init our RX/TX stat counters. */ 4280 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 4281 4282 /* Init TX ring. */ 4283 bge_init_tx_ring(sc); 4284 4285 /* Turn on transmitter. */ 4286 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 4287 4288 /* Turn on receiver. */ 4289 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4290 4291 /* Tell firmware we're alive. */ 4292 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4293 4294 #ifdef DEVICE_POLLING 4295 /* Disable interrupts if we are polling. */ 4296 if (ifp->if_capenable & IFCAP_POLLING) { 4297 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4298 BGE_PCIMISCCTL_MASK_PCI_INTR); 4299 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4300 } else 4301 #endif 4302 4303 /* Enable host interrupts. */ 4304 { 4305 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 4306 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4307 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4308 } 4309 4310 bge_ifmedia_upd_locked(ifp); 4311 4312 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4313 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4314 4315 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4316 } 4317 4318 static void 4319 bge_init(void *xsc) 4320 { 4321 struct bge_softc *sc = xsc; 4322 4323 BGE_LOCK(sc); 4324 bge_init_locked(sc); 4325 BGE_UNLOCK(sc); 4326 } 4327 4328 /* 4329 * Set media options. 4330 */ 4331 static int 4332 bge_ifmedia_upd(struct ifnet *ifp) 4333 { 4334 struct bge_softc *sc = ifp->if_softc; 4335 int res; 4336 4337 BGE_LOCK(sc); 4338 res = bge_ifmedia_upd_locked(ifp); 4339 BGE_UNLOCK(sc); 4340 4341 return (res); 4342 } 4343 4344 static int 4345 bge_ifmedia_upd_locked(struct ifnet *ifp) 4346 { 4347 struct bge_softc *sc = ifp->if_softc; 4348 struct mii_data *mii; 4349 struct mii_softc *miisc; 4350 struct ifmedia *ifm; 4351 4352 BGE_LOCK_ASSERT(sc); 4353 4354 ifm = &sc->bge_ifmedia; 4355 4356 /* If this is a 1000baseX NIC, enable the TBI port. */ 4357 if (sc->bge_flags & BGE_FLAG_TBI) { 4358 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 4359 return (EINVAL); 4360 switch(IFM_SUBTYPE(ifm->ifm_media)) { 4361 case IFM_AUTO: 4362 /* 4363 * The BCM5704 ASIC appears to have a special 4364 * mechanism for programming the autoneg 4365 * advertisement registers in TBI mode. 4366 */ 4367 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4368 uint32_t sgdig; 4369 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 4370 if (sgdig & BGE_SGDIGSTS_DONE) { 4371 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 4372 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 4373 sgdig |= BGE_SGDIGCFG_AUTO | 4374 BGE_SGDIGCFG_PAUSE_CAP | 4375 BGE_SGDIGCFG_ASYM_PAUSE; 4376 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 4377 sgdig | BGE_SGDIGCFG_SEND); 4378 DELAY(5); 4379 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 4380 } 4381 } 4382 break; 4383 case IFM_1000_SX: 4384 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 4385 BGE_CLRBIT(sc, BGE_MAC_MODE, 4386 BGE_MACMODE_HALF_DUPLEX); 4387 } else { 4388 BGE_SETBIT(sc, BGE_MAC_MODE, 4389 BGE_MACMODE_HALF_DUPLEX); 4390 } 4391 break; 4392 default: 4393 return (EINVAL); 4394 } 4395 return (0); 4396 } 4397 4398 sc->bge_link_evt++; 4399 mii = device_get_softc(sc->bge_miibus); 4400 if (mii->mii_instance) 4401 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 4402 mii_phy_reset(miisc); 4403 mii_mediachg(mii); 4404 4405 /* 4406 * Force an interrupt so that we will call bge_link_upd 4407 * if needed and clear any pending link state attention. 4408 * Without this we are not getting any further interrupts 4409 * for link state changes and thus will not UP the link and 4410 * not be able to send in bge_start_locked. The only 4411 * way to get things working was to receive a packet and 4412 * get an RX intr. 4413 * bge_tick should help for fiber cards and we might not 4414 * need to do this here if BGE_FLAG_TBI is set but as 4415 * we poll for fiber anyway it should not harm. 4416 */ 4417 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4418 sc->bge_flags & BGE_FLAG_5788) 4419 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4420 else 4421 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4422 4423 return (0); 4424 } 4425 4426 /* 4427 * Report current media status. 4428 */ 4429 static void 4430 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 4431 { 4432 struct bge_softc *sc = ifp->if_softc; 4433 struct mii_data *mii; 4434 4435 BGE_LOCK(sc); 4436 4437 if (sc->bge_flags & BGE_FLAG_TBI) { 4438 ifmr->ifm_status = IFM_AVALID; 4439 ifmr->ifm_active = IFM_ETHER; 4440 if (CSR_READ_4(sc, BGE_MAC_STS) & 4441 BGE_MACSTAT_TBI_PCS_SYNCHED) 4442 ifmr->ifm_status |= IFM_ACTIVE; 4443 else { 4444 ifmr->ifm_active |= IFM_NONE; 4445 BGE_UNLOCK(sc); 4446 return; 4447 } 4448 ifmr->ifm_active |= IFM_1000_SX; 4449 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 4450 ifmr->ifm_active |= IFM_HDX; 4451 else 4452 ifmr->ifm_active |= IFM_FDX; 4453 BGE_UNLOCK(sc); 4454 return; 4455 } 4456 4457 mii = device_get_softc(sc->bge_miibus); 4458 mii_pollstat(mii); 4459 ifmr->ifm_active = mii->mii_media_active; 4460 ifmr->ifm_status = mii->mii_media_status; 4461 4462 BGE_UNLOCK(sc); 4463 } 4464 4465 static int 4466 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 4467 { 4468 struct bge_softc *sc = ifp->if_softc; 4469 struct ifreq *ifr = (struct ifreq *) data; 4470 struct mii_data *mii; 4471 int flags, mask, error = 0; 4472 4473 switch (command) { 4474 case SIOCSIFMTU: 4475 if (ifr->ifr_mtu < ETHERMIN || 4476 ((BGE_IS_JUMBO_CAPABLE(sc)) && 4477 ifr->ifr_mtu > BGE_JUMBO_MTU) || 4478 ((!BGE_IS_JUMBO_CAPABLE(sc)) && 4479 ifr->ifr_mtu > ETHERMTU)) 4480 error = EINVAL; 4481 else if (ifp->if_mtu != ifr->ifr_mtu) { 4482 ifp->if_mtu = ifr->ifr_mtu; 4483 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4484 bge_init(sc); 4485 } 4486 break; 4487 case SIOCSIFFLAGS: 4488 BGE_LOCK(sc); 4489 if (ifp->if_flags & IFF_UP) { 4490 /* 4491 * If only the state of the PROMISC flag changed, 4492 * then just use the 'set promisc mode' command 4493 * instead of reinitializing the entire NIC. Doing 4494 * a full re-init means reloading the firmware and 4495 * waiting for it to start up, which may take a 4496 * second or two. Similarly for ALLMULTI. 4497 */ 4498 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4499 flags = ifp->if_flags ^ sc->bge_if_flags; 4500 if (flags & IFF_PROMISC) 4501 bge_setpromisc(sc); 4502 if (flags & IFF_ALLMULTI) 4503 bge_setmulti(sc); 4504 } else 4505 bge_init_locked(sc); 4506 } else { 4507 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4508 bge_stop(sc); 4509 } 4510 } 4511 sc->bge_if_flags = ifp->if_flags; 4512 BGE_UNLOCK(sc); 4513 error = 0; 4514 break; 4515 case SIOCADDMULTI: 4516 case SIOCDELMULTI: 4517 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4518 BGE_LOCK(sc); 4519 bge_setmulti(sc); 4520 BGE_UNLOCK(sc); 4521 error = 0; 4522 } 4523 break; 4524 case SIOCSIFMEDIA: 4525 case SIOCGIFMEDIA: 4526 if (sc->bge_flags & BGE_FLAG_TBI) { 4527 error = ifmedia_ioctl(ifp, ifr, 4528 &sc->bge_ifmedia, command); 4529 } else { 4530 mii = device_get_softc(sc->bge_miibus); 4531 error = ifmedia_ioctl(ifp, ifr, 4532 &mii->mii_media, command); 4533 } 4534 break; 4535 case SIOCSIFCAP: 4536 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 4537 #ifdef DEVICE_POLLING 4538 if (mask & IFCAP_POLLING) { 4539 if (ifr->ifr_reqcap & IFCAP_POLLING) { 4540 error = ether_poll_register(bge_poll, ifp); 4541 if (error) 4542 return (error); 4543 BGE_LOCK(sc); 4544 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 4545 BGE_PCIMISCCTL_MASK_PCI_INTR); 4546 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4547 ifp->if_capenable |= IFCAP_POLLING; 4548 BGE_UNLOCK(sc); 4549 } else { 4550 error = ether_poll_deregister(ifp); 4551 /* Enable interrupt even in error case */ 4552 BGE_LOCK(sc); 4553 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 4554 BGE_PCIMISCCTL_MASK_PCI_INTR); 4555 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4556 ifp->if_capenable &= ~IFCAP_POLLING; 4557 BGE_UNLOCK(sc); 4558 } 4559 } 4560 #endif 4561 if (mask & IFCAP_HWCSUM) { 4562 ifp->if_capenable ^= IFCAP_HWCSUM; 4563 if (IFCAP_HWCSUM & ifp->if_capenable && 4564 IFCAP_HWCSUM & ifp->if_capabilities) 4565 ifp->if_hwassist |= BGE_CSUM_FEATURES; 4566 else 4567 ifp->if_hwassist &= ~BGE_CSUM_FEATURES; 4568 } 4569 4570 if ((mask & IFCAP_TSO4) != 0 && 4571 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 4572 ifp->if_capenable ^= IFCAP_TSO4; 4573 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 4574 ifp->if_hwassist |= CSUM_TSO; 4575 else 4576 ifp->if_hwassist &= ~CSUM_TSO; 4577 } 4578 4579 if (mask & IFCAP_VLAN_MTU) { 4580 ifp->if_capenable ^= IFCAP_VLAN_MTU; 4581 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4582 bge_init(sc); 4583 } 4584 4585 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 4586 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 4587 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 4588 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 4589 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 4590 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 4591 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 4592 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 4593 BGE_LOCK(sc); 4594 bge_setvlan(sc); 4595 BGE_UNLOCK(sc); 4596 } 4597 #ifdef VLAN_CAPABILITIES 4598 VLAN_CAPABILITIES(ifp); 4599 #endif 4600 break; 4601 default: 4602 error = ether_ioctl(ifp, command, data); 4603 break; 4604 } 4605 4606 return (error); 4607 } 4608 4609 static void 4610 bge_watchdog(struct bge_softc *sc) 4611 { 4612 struct ifnet *ifp; 4613 4614 BGE_LOCK_ASSERT(sc); 4615 4616 if (sc->bge_timer == 0 || --sc->bge_timer) 4617 return; 4618 4619 ifp = sc->bge_ifp; 4620 4621 if_printf(ifp, "watchdog timeout -- resetting\n"); 4622 4623 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 4624 bge_init_locked(sc); 4625 4626 ifp->if_oerrors++; 4627 } 4628 4629 /* 4630 * Stop the adapter and free any mbufs allocated to the 4631 * RX and TX lists. 4632 */ 4633 static void 4634 bge_stop(struct bge_softc *sc) 4635 { 4636 struct ifnet *ifp; 4637 4638 BGE_LOCK_ASSERT(sc); 4639 4640 ifp = sc->bge_ifp; 4641 4642 callout_stop(&sc->bge_stat_ch); 4643 4644 /* Disable host interrupts. */ 4645 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 4646 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 4647 4648 /* 4649 * Tell firmware we're shutting down. 4650 */ 4651 bge_stop_fw(sc); 4652 bge_sig_pre_reset(sc, BGE_RESET_STOP); 4653 4654 /* 4655 * Disable all of the receiver blocks. 4656 */ 4657 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 4658 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 4659 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 4660 if (!(BGE_IS_5705_PLUS(sc))) 4661 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 4662 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 4663 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 4664 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 4665 4666 /* 4667 * Disable all of the transmit blocks. 4668 */ 4669 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 4670 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 4671 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 4672 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 4673 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 4674 if (!(BGE_IS_5705_PLUS(sc))) 4675 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 4676 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 4677 4678 /* 4679 * Shut down all of the memory managers and related 4680 * state machines. 4681 */ 4682 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 4683 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 4684 if (!(BGE_IS_5705_PLUS(sc))) 4685 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 4686 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 4687 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 4688 if (!(BGE_IS_5705_PLUS(sc))) { 4689 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 4690 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4691 } 4692 4693 bge_reset(sc); 4694 bge_sig_legacy(sc, BGE_RESET_STOP); 4695 bge_sig_post_reset(sc, BGE_RESET_STOP); 4696 4697 /* 4698 * Keep the ASF firmware running if up. 4699 */ 4700 if (sc->bge_asf_mode & ASF_STACKUP) 4701 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4702 else 4703 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 4704 4705 /* Free the RX lists. */ 4706 bge_free_rx_ring_std(sc); 4707 4708 /* Free jumbo RX list. */ 4709 if (BGE_IS_JUMBO_CAPABLE(sc)) 4710 bge_free_rx_ring_jumbo(sc); 4711 4712 /* Free TX buffers. */ 4713 bge_free_tx_ring(sc); 4714 4715 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 4716 4717 /* Clear MAC's link state (PHY may still have link UP). */ 4718 if (bootverbose && sc->bge_link) 4719 if_printf(sc->bge_ifp, "link DOWN\n"); 4720 sc->bge_link = 0; 4721 4722 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4723 } 4724 4725 /* 4726 * Stop all chip I/O so that the kernel's probe routines don't 4727 * get confused by errant DMAs when rebooting. 4728 */ 4729 static int 4730 bge_shutdown(device_t dev) 4731 { 4732 struct bge_softc *sc; 4733 4734 sc = device_get_softc(dev); 4735 BGE_LOCK(sc); 4736 bge_stop(sc); 4737 bge_reset(sc); 4738 BGE_UNLOCK(sc); 4739 4740 return (0); 4741 } 4742 4743 static int 4744 bge_suspend(device_t dev) 4745 { 4746 struct bge_softc *sc; 4747 4748 sc = device_get_softc(dev); 4749 BGE_LOCK(sc); 4750 bge_stop(sc); 4751 BGE_UNLOCK(sc); 4752 4753 return (0); 4754 } 4755 4756 static int 4757 bge_resume(device_t dev) 4758 { 4759 struct bge_softc *sc; 4760 struct ifnet *ifp; 4761 4762 sc = device_get_softc(dev); 4763 BGE_LOCK(sc); 4764 ifp = sc->bge_ifp; 4765 if (ifp->if_flags & IFF_UP) { 4766 bge_init_locked(sc); 4767 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 4768 bge_start_locked(ifp); 4769 } 4770 BGE_UNLOCK(sc); 4771 4772 return (0); 4773 } 4774 4775 static void 4776 bge_link_upd(struct bge_softc *sc) 4777 { 4778 struct mii_data *mii; 4779 uint32_t link, status; 4780 4781 BGE_LOCK_ASSERT(sc); 4782 4783 /* Clear 'pending link event' flag. */ 4784 sc->bge_link_evt = 0; 4785 4786 /* 4787 * Process link state changes. 4788 * Grrr. The link status word in the status block does 4789 * not work correctly on the BCM5700 rev AX and BX chips, 4790 * according to all available information. Hence, we have 4791 * to enable MII interrupts in order to properly obtain 4792 * async link changes. Unfortunately, this also means that 4793 * we have to read the MAC status register to detect link 4794 * changes, thereby adding an additional register access to 4795 * the interrupt handler. 4796 * 4797 * XXX: perhaps link state detection procedure used for 4798 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 4799 */ 4800 4801 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4802 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 4803 status = CSR_READ_4(sc, BGE_MAC_STS); 4804 if (status & BGE_MACSTAT_MI_INTERRUPT) { 4805 mii = device_get_softc(sc->bge_miibus); 4806 mii_pollstat(mii); 4807 if (!sc->bge_link && 4808 mii->mii_media_status & IFM_ACTIVE && 4809 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4810 sc->bge_link++; 4811 if (bootverbose) 4812 if_printf(sc->bge_ifp, "link UP\n"); 4813 } else if (sc->bge_link && 4814 (!(mii->mii_media_status & IFM_ACTIVE) || 4815 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4816 sc->bge_link = 0; 4817 if (bootverbose) 4818 if_printf(sc->bge_ifp, "link DOWN\n"); 4819 } 4820 4821 /* Clear the interrupt. */ 4822 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 4823 BGE_EVTENB_MI_INTERRUPT); 4824 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 4825 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 4826 BRGPHY_INTRS); 4827 } 4828 return; 4829 } 4830 4831 if (sc->bge_flags & BGE_FLAG_TBI) { 4832 status = CSR_READ_4(sc, BGE_MAC_STS); 4833 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 4834 if (!sc->bge_link) { 4835 sc->bge_link++; 4836 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 4837 BGE_CLRBIT(sc, BGE_MAC_MODE, 4838 BGE_MACMODE_TBI_SEND_CFGS); 4839 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 4840 if (bootverbose) 4841 if_printf(sc->bge_ifp, "link UP\n"); 4842 if_link_state_change(sc->bge_ifp, 4843 LINK_STATE_UP); 4844 } 4845 } else if (sc->bge_link) { 4846 sc->bge_link = 0; 4847 if (bootverbose) 4848 if_printf(sc->bge_ifp, "link DOWN\n"); 4849 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 4850 } 4851 } else if (CSR_READ_4(sc, BGE_MI_MODE) & BGE_MIMODE_AUTOPOLL) { 4852 /* 4853 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 4854 * in status word always set. Workaround this bug by reading 4855 * PHY link status directly. 4856 */ 4857 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 4858 4859 if (link != sc->bge_link || 4860 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 4861 mii = device_get_softc(sc->bge_miibus); 4862 mii_pollstat(mii); 4863 if (!sc->bge_link && 4864 mii->mii_media_status & IFM_ACTIVE && 4865 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 4866 sc->bge_link++; 4867 if (bootverbose) 4868 if_printf(sc->bge_ifp, "link UP\n"); 4869 } else if (sc->bge_link && 4870 (!(mii->mii_media_status & IFM_ACTIVE) || 4871 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 4872 sc->bge_link = 0; 4873 if (bootverbose) 4874 if_printf(sc->bge_ifp, "link DOWN\n"); 4875 } 4876 } 4877 } else { 4878 /* 4879 * Discard link events for MII/GMII controllers 4880 * if MI auto-polling is disabled. 4881 */ 4882 } 4883 4884 /* Clear the attention. */ 4885 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 4886 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 4887 BGE_MACSTAT_LINK_CHANGED); 4888 } 4889 4890 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 4891 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 4892 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 4893 desc) 4894 4895 static void 4896 bge_add_sysctls(struct bge_softc *sc) 4897 { 4898 struct sysctl_ctx_list *ctx; 4899 struct sysctl_oid_list *children, *schildren; 4900 struct sysctl_oid *tree; 4901 4902 ctx = device_get_sysctl_ctx(sc->bge_dev); 4903 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 4904 4905 #ifdef BGE_REGISTER_DEBUG 4906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 4907 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 4908 "Debug Information"); 4909 4910 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 4911 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 4912 "Register Read"); 4913 4914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 4915 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 4916 "Memory Read"); 4917 4918 #endif 4919 4920 /* 4921 * A common design characteristic for many Broadcom client controllers 4922 * is that they only support a single outstanding DMA read operation 4923 * on the PCIe bus. This means that it will take twice as long to fetch 4924 * a TX frame that is split into header and payload buffers as it does 4925 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 4926 * these controllers, coalescing buffers to reduce the number of memory 4927 * reads is effective way to get maximum performance(about 940Mbps). 4928 * Without collapsing TX buffers the maximum TCP bulk transfer 4929 * performance is about 850Mbps. However forcing coalescing mbufs 4930 * consumes a lot of CPU cycles, so leave it off by default. 4931 */ 4932 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 4933 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 4934 "Number of fragmented TX buffers of a frame allowed before " 4935 "forced collapsing"); 4936 resource_int_value(device_get_name(sc->bge_dev), 4937 device_get_unit(sc->bge_dev), "forced_collapse", 4938 &sc->bge_forced_collapse); 4939 4940 if (BGE_IS_5705_PLUS(sc)) 4941 return; 4942 4943 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD, 4944 NULL, "BGE Statistics"); 4945 schildren = children = SYSCTL_CHILDREN(tree); 4946 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 4947 children, COSFramesDroppedDueToFilters, 4948 "FramesDroppedDueToFilters"); 4949 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 4950 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 4951 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 4952 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 4953 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 4954 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 4955 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 4956 children, ifInDiscards, "InputDiscards"); 4957 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 4958 children, ifInErrors, "InputErrors"); 4959 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 4960 children, nicRecvThresholdHit, "RecvThresholdHit"); 4961 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 4962 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 4963 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 4964 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 4965 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 4966 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 4967 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 4968 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 4969 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 4970 children, nicRingStatusUpdate, "RingStatusUpdate"); 4971 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 4972 children, nicInterrupts, "Interrupts"); 4973 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 4974 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 4975 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 4976 children, nicSendThresholdHit, "SendThresholdHit"); 4977 4978 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 4979 NULL, "BGE RX Statistics"); 4980 children = SYSCTL_CHILDREN(tree); 4981 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 4982 children, rxstats.ifHCInOctets, "Octets"); 4983 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 4984 children, rxstats.etherStatsFragments, "Fragments"); 4985 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 4986 children, rxstats.ifHCInUcastPkts, "UcastPkts"); 4987 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 4988 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 4989 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 4990 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 4991 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 4992 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 4993 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 4994 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 4995 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 4996 children, rxstats.xoffPauseFramesReceived, 4997 "xoffPauseFramesReceived"); 4998 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 4999 children, rxstats.macControlFramesReceived, 5000 "ControlFramesReceived"); 5001 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 5002 children, rxstats.xoffStateEntered, "xoffStateEntered"); 5003 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 5004 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 5005 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 5006 children, rxstats.etherStatsJabbers, "Jabbers"); 5007 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 5008 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 5009 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 5010 children, rxstats.inRangeLengthError, "inRangeLengthError"); 5011 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 5012 children, rxstats.outRangeLengthError, "outRangeLengthError"); 5013 5014 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 5015 NULL, "BGE TX Statistics"); 5016 children = SYSCTL_CHILDREN(tree); 5017 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 5018 children, txstats.ifHCOutOctets, "Octets"); 5019 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 5020 children, txstats.etherStatsCollisions, "Collisions"); 5021 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 5022 children, txstats.outXonSent, "XonSent"); 5023 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 5024 children, txstats.outXoffSent, "XoffSent"); 5025 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 5026 children, txstats.flowControlDone, "flowControlDone"); 5027 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 5028 children, txstats.dot3StatsInternalMacTransmitErrors, 5029 "InternalMacTransmitErrors"); 5030 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 5031 children, txstats.dot3StatsSingleCollisionFrames, 5032 "SingleCollisionFrames"); 5033 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 5034 children, txstats.dot3StatsMultipleCollisionFrames, 5035 "MultipleCollisionFrames"); 5036 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 5037 children, txstats.dot3StatsDeferredTransmissions, 5038 "DeferredTransmissions"); 5039 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 5040 children, txstats.dot3StatsExcessiveCollisions, 5041 "ExcessiveCollisions"); 5042 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 5043 children, txstats.dot3StatsLateCollisions, 5044 "LateCollisions"); 5045 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 5046 children, txstats.ifHCOutUcastPkts, "UcastPkts"); 5047 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 5048 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 5049 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 5050 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 5051 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 5052 children, txstats.dot3StatsCarrierSenseErrors, 5053 "CarrierSenseErrors"); 5054 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 5055 children, txstats.ifOutDiscards, "Discards"); 5056 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 5057 children, txstats.ifOutErrors, "Errors"); 5058 } 5059 5060 static int 5061 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 5062 { 5063 struct bge_softc *sc; 5064 uint32_t result; 5065 int offset; 5066 5067 sc = (struct bge_softc *)arg1; 5068 offset = arg2; 5069 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 5070 offsetof(bge_hostaddr, bge_addr_lo)); 5071 return (sysctl_handle_int(oidp, &result, 0, req)); 5072 } 5073 5074 #ifdef BGE_REGISTER_DEBUG 5075 static int 5076 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 5077 { 5078 struct bge_softc *sc; 5079 uint16_t *sbdata; 5080 int error; 5081 int result; 5082 int i, j; 5083 5084 result = -1; 5085 error = sysctl_handle_int(oidp, &result, 0, req); 5086 if (error || (req->newptr == NULL)) 5087 return (error); 5088 5089 if (result == 1) { 5090 sc = (struct bge_softc *)arg1; 5091 5092 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 5093 printf("Status Block:\n"); 5094 for (i = 0x0; i < (BGE_STATUS_BLK_SZ / 4); ) { 5095 printf("%06x:", i); 5096 for (j = 0; j < 8; j++) { 5097 printf(" %04x", sbdata[i]); 5098 i += 4; 5099 } 5100 printf("\n"); 5101 } 5102 5103 printf("Registers:\n"); 5104 for (i = 0x800; i < 0xA00; ) { 5105 printf("%06x:", i); 5106 for (j = 0; j < 8; j++) { 5107 printf(" %08x", CSR_READ_4(sc, i)); 5108 i += 4; 5109 } 5110 printf("\n"); 5111 } 5112 5113 printf("Hardware Flags:\n"); 5114 if (BGE_IS_5755_PLUS(sc)) 5115 printf(" - 5755 Plus\n"); 5116 if (BGE_IS_575X_PLUS(sc)) 5117 printf(" - 575X Plus\n"); 5118 if (BGE_IS_5705_PLUS(sc)) 5119 printf(" - 5705 Plus\n"); 5120 if (BGE_IS_5714_FAMILY(sc)) 5121 printf(" - 5714 Family\n"); 5122 if (BGE_IS_5700_FAMILY(sc)) 5123 printf(" - 5700 Family\n"); 5124 if (sc->bge_flags & BGE_FLAG_JUMBO) 5125 printf(" - Supports Jumbo Frames\n"); 5126 if (sc->bge_flags & BGE_FLAG_PCIX) 5127 printf(" - PCI-X Bus\n"); 5128 if (sc->bge_flags & BGE_FLAG_PCIE) 5129 printf(" - PCI Express Bus\n"); 5130 if (sc->bge_flags & BGE_FLAG_NO_3LED) 5131 printf(" - No 3 LEDs\n"); 5132 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 5133 printf(" - RX Alignment Bug\n"); 5134 } 5135 5136 return (error); 5137 } 5138 5139 static int 5140 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 5141 { 5142 struct bge_softc *sc; 5143 int error; 5144 uint16_t result; 5145 uint32_t val; 5146 5147 result = -1; 5148 error = sysctl_handle_int(oidp, &result, 0, req); 5149 if (error || (req->newptr == NULL)) 5150 return (error); 5151 5152 if (result < 0x8000) { 5153 sc = (struct bge_softc *)arg1; 5154 val = CSR_READ_4(sc, result); 5155 printf("reg 0x%06X = 0x%08X\n", result, val); 5156 } 5157 5158 return (error); 5159 } 5160 5161 static int 5162 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 5163 { 5164 struct bge_softc *sc; 5165 int error; 5166 uint16_t result; 5167 uint32_t val; 5168 5169 result = -1; 5170 error = sysctl_handle_int(oidp, &result, 0, req); 5171 if (error || (req->newptr == NULL)) 5172 return (error); 5173 5174 if (result < 0x8000) { 5175 sc = (struct bge_softc *)arg1; 5176 val = bge_readmem_ind(sc, result); 5177 printf("mem 0x%06X = 0x%08X\n", result, val); 5178 } 5179 5180 return (error); 5181 } 5182 #endif 5183 5184 static int 5185 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 5186 { 5187 5188 if (sc->bge_flags & BGE_FLAG_EADDR) 5189 return (1); 5190 5191 #ifdef __sparc64__ 5192 OF_getetheraddr(sc->bge_dev, ether_addr); 5193 return (0); 5194 #endif 5195 return (1); 5196 } 5197 5198 static int 5199 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 5200 { 5201 uint32_t mac_addr; 5202 5203 mac_addr = bge_readmem_ind(sc, 0x0c14); 5204 if ((mac_addr >> 16) == 0x484b) { 5205 ether_addr[0] = (uint8_t)(mac_addr >> 8); 5206 ether_addr[1] = (uint8_t)mac_addr; 5207 mac_addr = bge_readmem_ind(sc, 0x0c18); 5208 ether_addr[2] = (uint8_t)(mac_addr >> 24); 5209 ether_addr[3] = (uint8_t)(mac_addr >> 16); 5210 ether_addr[4] = (uint8_t)(mac_addr >> 8); 5211 ether_addr[5] = (uint8_t)mac_addr; 5212 return (0); 5213 } 5214 return (1); 5215 } 5216 5217 static int 5218 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 5219 { 5220 int mac_offset = BGE_EE_MAC_OFFSET; 5221 5222 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5223 mac_offset = BGE_EE_MAC_OFFSET_5906; 5224 5225 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 5226 ETHER_ADDR_LEN)); 5227 } 5228 5229 static int 5230 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 5231 { 5232 5233 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 5234 return (1); 5235 5236 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 5237 ETHER_ADDR_LEN)); 5238 } 5239 5240 static int 5241 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 5242 { 5243 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 5244 /* NOTE: Order is critical */ 5245 bge_get_eaddr_fw, 5246 bge_get_eaddr_mem, 5247 bge_get_eaddr_nvram, 5248 bge_get_eaddr_eeprom, 5249 NULL 5250 }; 5251 const bge_eaddr_fcn_t *func; 5252 5253 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 5254 if ((*func)(sc, eaddr) == 0) 5255 break; 5256 } 5257 return (*func == NULL ? ENXIO : 0); 5258 } 5259