1 /*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * Broadcom BCM57xx(x)/BCM590x NetXtreme and NetLink family Ethernet driver 39 * 40 * The Broadcom BCM5700 is based on technology originally developed by 41 * Alteon Networks as part of the Tigon I and Tigon II Gigabit Ethernet 42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has 43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 44 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 45 * frames, highly configurable RX filtering, and 16 RX and TX queues 46 * (which, along with RX filter rules, can be used for QOS applications). 47 * Other features, such as TCP segmentation, may be available as part 48 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 49 * firmware images can be stored in hardware and need not be compiled 50 * into the driver. 51 * 52 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 53 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 54 * 55 * The BCM5701 is a single-chip solution incorporating both the BCM5700 56 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 57 * does not support external SSRAM. 58 * 59 * Broadcom also produces a variation of the BCM5700 under the "Altima" 60 * brand name, which is functionally similar but lacks PCI-X support. 61 * 62 * Without external SSRAM, you can only have at most 4 TX rings, 63 * and the use of the mini RX ring is disabled. This seems to imply 64 * that these features are simply not available on the BCM5701. As a 65 * result, this driver does not implement any support for the mini RX 66 * ring. 67 */ 68 69 #ifdef HAVE_KERNEL_OPTION_HEADERS 70 #include "opt_device_polling.h" 71 #endif 72 73 #include <sys/param.h> 74 #include <sys/endian.h> 75 #include <sys/systm.h> 76 #include <sys/sockio.h> 77 #include <sys/mbuf.h> 78 #include <sys/malloc.h> 79 #include <sys/kernel.h> 80 #include <sys/module.h> 81 #include <sys/socket.h> 82 #include <sys/sysctl.h> 83 #include <sys/taskqueue.h> 84 85 #include <net/if.h> 86 #include <net/if_var.h> 87 #include <net/if_arp.h> 88 #include <net/ethernet.h> 89 #include <net/if_dl.h> 90 #include <net/if_media.h> 91 92 #include <net/bpf.h> 93 94 #include <net/if_types.h> 95 #include <net/if_vlan_var.h> 96 97 #include <netinet/in_systm.h> 98 #include <netinet/in.h> 99 #include <netinet/ip.h> 100 #include <netinet/tcp.h> 101 102 #include <machine/bus.h> 103 #include <machine/resource.h> 104 #include <sys/bus.h> 105 #include <sys/rman.h> 106 107 #include <dev/mii/mii.h> 108 #include <dev/mii/miivar.h> 109 #include "miidevs.h" 110 #include <dev/mii/brgphyreg.h> 111 112 #ifdef __sparc64__ 113 #include <dev/ofw/ofw_bus.h> 114 #include <dev/ofw/openfirm.h> 115 #include <machine/ofw_machdep.h> 116 #include <machine/ver.h> 117 #endif 118 119 #include <dev/pci/pcireg.h> 120 #include <dev/pci/pcivar.h> 121 122 #include <dev/bge/if_bgereg.h> 123 124 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP) 125 #define ETHER_MIN_NOPAD (ETHER_MIN_LEN - ETHER_CRC_LEN) /* i.e., 60 */ 126 127 MODULE_DEPEND(bge, pci, 1, 1, 1); 128 MODULE_DEPEND(bge, ether, 1, 1, 1); 129 MODULE_DEPEND(bge, miibus, 1, 1, 1); 130 131 /* "device miibus" required. See GENERIC if you get errors here. */ 132 #include "miibus_if.h" 133 134 /* 135 * Various supported device vendors/types and their names. Note: the 136 * spec seems to indicate that the hardware still has Alteon's vendor 137 * ID burned into it, though it will always be overriden by the vendor 138 * ID in the EEPROM. Just to be safe, we cover all possibilities. 139 */ 140 static const struct bge_type { 141 uint16_t bge_vid; 142 uint16_t bge_did; 143 } bge_devs[] = { 144 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5700 }, 145 { ALTEON_VENDORID, ALTEON_DEVICEID_BCM5701 }, 146 147 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000 }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1002 }, 149 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100 }, 150 151 { APPLE_VENDORID, APPLE_DEVICE_BCM5701 }, 152 153 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700 }, 154 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701 }, 155 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702 }, 156 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702_ALT }, 157 { BCOM_VENDORID, BCOM_DEVICEID_BCM5702X }, 158 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703 }, 159 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703_ALT }, 160 { BCOM_VENDORID, BCOM_DEVICEID_BCM5703X }, 161 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704C }, 162 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S }, 163 { BCOM_VENDORID, BCOM_DEVICEID_BCM5704S_ALT }, 164 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705 }, 165 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705F }, 166 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705K }, 167 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M }, 168 { BCOM_VENDORID, BCOM_DEVICEID_BCM5705M_ALT }, 169 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714C }, 170 { BCOM_VENDORID, BCOM_DEVICEID_BCM5714S }, 171 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715 }, 172 { BCOM_VENDORID, BCOM_DEVICEID_BCM5715S }, 173 { BCOM_VENDORID, BCOM_DEVICEID_BCM5717 }, 174 { BCOM_VENDORID, BCOM_DEVICEID_BCM5718 }, 175 { BCOM_VENDORID, BCOM_DEVICEID_BCM5719 }, 176 { BCOM_VENDORID, BCOM_DEVICEID_BCM5720 }, 177 { BCOM_VENDORID, BCOM_DEVICEID_BCM5721 }, 178 { BCOM_VENDORID, BCOM_DEVICEID_BCM5722 }, 179 { BCOM_VENDORID, BCOM_DEVICEID_BCM5723 }, 180 { BCOM_VENDORID, BCOM_DEVICEID_BCM5725 }, 181 { BCOM_VENDORID, BCOM_DEVICEID_BCM5727 }, 182 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750 }, 183 { BCOM_VENDORID, BCOM_DEVICEID_BCM5750M }, 184 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751 }, 185 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751F }, 186 { BCOM_VENDORID, BCOM_DEVICEID_BCM5751M }, 187 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752 }, 188 { BCOM_VENDORID, BCOM_DEVICEID_BCM5752M }, 189 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753 }, 190 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753F }, 191 { BCOM_VENDORID, BCOM_DEVICEID_BCM5753M }, 192 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754 }, 193 { BCOM_VENDORID, BCOM_DEVICEID_BCM5754M }, 194 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755 }, 195 { BCOM_VENDORID, BCOM_DEVICEID_BCM5755M }, 196 { BCOM_VENDORID, BCOM_DEVICEID_BCM5756 }, 197 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761 }, 198 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761E }, 199 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761S }, 200 { BCOM_VENDORID, BCOM_DEVICEID_BCM5761SE }, 201 { BCOM_VENDORID, BCOM_DEVICEID_BCM5762 }, 202 { BCOM_VENDORID, BCOM_DEVICEID_BCM5764 }, 203 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780 }, 204 { BCOM_VENDORID, BCOM_DEVICEID_BCM5780S }, 205 { BCOM_VENDORID, BCOM_DEVICEID_BCM5781 }, 206 { BCOM_VENDORID, BCOM_DEVICEID_BCM5782 }, 207 { BCOM_VENDORID, BCOM_DEVICEID_BCM5784 }, 208 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785F }, 209 { BCOM_VENDORID, BCOM_DEVICEID_BCM5785G }, 210 { BCOM_VENDORID, BCOM_DEVICEID_BCM5786 }, 211 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787 }, 212 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787F }, 213 { BCOM_VENDORID, BCOM_DEVICEID_BCM5787M }, 214 { BCOM_VENDORID, BCOM_DEVICEID_BCM5788 }, 215 { BCOM_VENDORID, BCOM_DEVICEID_BCM5789 }, 216 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901 }, 217 { BCOM_VENDORID, BCOM_DEVICEID_BCM5901A2 }, 218 { BCOM_VENDORID, BCOM_DEVICEID_BCM5903M }, 219 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906 }, 220 { BCOM_VENDORID, BCOM_DEVICEID_BCM5906M }, 221 { BCOM_VENDORID, BCOM_DEVICEID_BCM57760 }, 222 { BCOM_VENDORID, BCOM_DEVICEID_BCM57761 }, 223 { BCOM_VENDORID, BCOM_DEVICEID_BCM57762 }, 224 { BCOM_VENDORID, BCOM_DEVICEID_BCM57764 }, 225 { BCOM_VENDORID, BCOM_DEVICEID_BCM57765 }, 226 { BCOM_VENDORID, BCOM_DEVICEID_BCM57766 }, 227 { BCOM_VENDORID, BCOM_DEVICEID_BCM57767 }, 228 { BCOM_VENDORID, BCOM_DEVICEID_BCM57780 }, 229 { BCOM_VENDORID, BCOM_DEVICEID_BCM57781 }, 230 { BCOM_VENDORID, BCOM_DEVICEID_BCM57782 }, 231 { BCOM_VENDORID, BCOM_DEVICEID_BCM57785 }, 232 { BCOM_VENDORID, BCOM_DEVICEID_BCM57786 }, 233 { BCOM_VENDORID, BCOM_DEVICEID_BCM57787 }, 234 { BCOM_VENDORID, BCOM_DEVICEID_BCM57788 }, 235 { BCOM_VENDORID, BCOM_DEVICEID_BCM57790 }, 236 { BCOM_VENDORID, BCOM_DEVICEID_BCM57791 }, 237 { BCOM_VENDORID, BCOM_DEVICEID_BCM57795 }, 238 239 { SK_VENDORID, SK_DEVICEID_ALTIMA }, 240 241 { TC_VENDORID, TC_DEVICEID_3C996 }, 242 243 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE4 }, 244 { FJTSU_VENDORID, FJTSU_DEVICEID_PW008GE5 }, 245 { FJTSU_VENDORID, FJTSU_DEVICEID_PP250450 }, 246 247 { 0, 0 } 248 }; 249 250 static const struct bge_vendor { 251 uint16_t v_id; 252 const char *v_name; 253 } bge_vendors[] = { 254 { ALTEON_VENDORID, "Alteon" }, 255 { ALTIMA_VENDORID, "Altima" }, 256 { APPLE_VENDORID, "Apple" }, 257 { BCOM_VENDORID, "Broadcom" }, 258 { SK_VENDORID, "SysKonnect" }, 259 { TC_VENDORID, "3Com" }, 260 { FJTSU_VENDORID, "Fujitsu" }, 261 262 { 0, NULL } 263 }; 264 265 static const struct bge_revision { 266 uint32_t br_chipid; 267 const char *br_name; 268 } bge_revisions[] = { 269 { BGE_CHIPID_BCM5700_A0, "BCM5700 A0" }, 270 { BGE_CHIPID_BCM5700_A1, "BCM5700 A1" }, 271 { BGE_CHIPID_BCM5700_B0, "BCM5700 B0" }, 272 { BGE_CHIPID_BCM5700_B1, "BCM5700 B1" }, 273 { BGE_CHIPID_BCM5700_B2, "BCM5700 B2" }, 274 { BGE_CHIPID_BCM5700_B3, "BCM5700 B3" }, 275 { BGE_CHIPID_BCM5700_ALTIMA, "BCM5700 Altima" }, 276 { BGE_CHIPID_BCM5700_C0, "BCM5700 C0" }, 277 { BGE_CHIPID_BCM5701_A0, "BCM5701 A0" }, 278 { BGE_CHIPID_BCM5701_B0, "BCM5701 B0" }, 279 { BGE_CHIPID_BCM5701_B2, "BCM5701 B2" }, 280 { BGE_CHIPID_BCM5701_B5, "BCM5701 B5" }, 281 { BGE_CHIPID_BCM5703_A0, "BCM5703 A0" }, 282 { BGE_CHIPID_BCM5703_A1, "BCM5703 A1" }, 283 { BGE_CHIPID_BCM5703_A2, "BCM5703 A2" }, 284 { BGE_CHIPID_BCM5703_A3, "BCM5703 A3" }, 285 { BGE_CHIPID_BCM5703_B0, "BCM5703 B0" }, 286 { BGE_CHIPID_BCM5704_A0, "BCM5704 A0" }, 287 { BGE_CHIPID_BCM5704_A1, "BCM5704 A1" }, 288 { BGE_CHIPID_BCM5704_A2, "BCM5704 A2" }, 289 { BGE_CHIPID_BCM5704_A3, "BCM5704 A3" }, 290 { BGE_CHIPID_BCM5704_B0, "BCM5704 B0" }, 291 { BGE_CHIPID_BCM5705_A0, "BCM5705 A0" }, 292 { BGE_CHIPID_BCM5705_A1, "BCM5705 A1" }, 293 { BGE_CHIPID_BCM5705_A2, "BCM5705 A2" }, 294 { BGE_CHIPID_BCM5705_A3, "BCM5705 A3" }, 295 { BGE_CHIPID_BCM5750_A0, "BCM5750 A0" }, 296 { BGE_CHIPID_BCM5750_A1, "BCM5750 A1" }, 297 { BGE_CHIPID_BCM5750_A3, "BCM5750 A3" }, 298 { BGE_CHIPID_BCM5750_B0, "BCM5750 B0" }, 299 { BGE_CHIPID_BCM5750_B1, "BCM5750 B1" }, 300 { BGE_CHIPID_BCM5750_C0, "BCM5750 C0" }, 301 { BGE_CHIPID_BCM5750_C1, "BCM5750 C1" }, 302 { BGE_CHIPID_BCM5750_C2, "BCM5750 C2" }, 303 { BGE_CHIPID_BCM5714_A0, "BCM5714 A0" }, 304 { BGE_CHIPID_BCM5752_A0, "BCM5752 A0" }, 305 { BGE_CHIPID_BCM5752_A1, "BCM5752 A1" }, 306 { BGE_CHIPID_BCM5752_A2, "BCM5752 A2" }, 307 { BGE_CHIPID_BCM5714_B0, "BCM5714 B0" }, 308 { BGE_CHIPID_BCM5714_B3, "BCM5714 B3" }, 309 { BGE_CHIPID_BCM5715_A0, "BCM5715 A0" }, 310 { BGE_CHIPID_BCM5715_A1, "BCM5715 A1" }, 311 { BGE_CHIPID_BCM5715_A3, "BCM5715 A3" }, 312 { BGE_CHIPID_BCM5717_A0, "BCM5717 A0" }, 313 { BGE_CHIPID_BCM5717_B0, "BCM5717 B0" }, 314 { BGE_CHIPID_BCM5719_A0, "BCM5719 A0" }, 315 { BGE_CHIPID_BCM5720_A0, "BCM5720 A0" }, 316 { BGE_CHIPID_BCM5755_A0, "BCM5755 A0" }, 317 { BGE_CHIPID_BCM5755_A1, "BCM5755 A1" }, 318 { BGE_CHIPID_BCM5755_A2, "BCM5755 A2" }, 319 { BGE_CHIPID_BCM5722_A0, "BCM5722 A0" }, 320 { BGE_CHIPID_BCM5761_A0, "BCM5761 A0" }, 321 { BGE_CHIPID_BCM5761_A1, "BCM5761 A1" }, 322 { BGE_CHIPID_BCM5762_A0, "BCM5762 A0" }, 323 { BGE_CHIPID_BCM5784_A0, "BCM5784 A0" }, 324 { BGE_CHIPID_BCM5784_A1, "BCM5784 A1" }, 325 /* 5754 and 5787 share the same ASIC ID */ 326 { BGE_CHIPID_BCM5787_A0, "BCM5754/5787 A0" }, 327 { BGE_CHIPID_BCM5787_A1, "BCM5754/5787 A1" }, 328 { BGE_CHIPID_BCM5787_A2, "BCM5754/5787 A2" }, 329 { BGE_CHIPID_BCM5906_A1, "BCM5906 A1" }, 330 { BGE_CHIPID_BCM5906_A2, "BCM5906 A2" }, 331 { BGE_CHIPID_BCM57765_A0, "BCM57765 A0" }, 332 { BGE_CHIPID_BCM57765_B0, "BCM57765 B0" }, 333 { BGE_CHIPID_BCM57780_A0, "BCM57780 A0" }, 334 { BGE_CHIPID_BCM57780_A1, "BCM57780 A1" }, 335 336 { 0, NULL } 337 }; 338 339 /* 340 * Some defaults for major revisions, so that newer steppings 341 * that we don't know about have a shot at working. 342 */ 343 static const struct bge_revision bge_majorrevs[] = { 344 { BGE_ASICREV_BCM5700, "unknown BCM5700" }, 345 { BGE_ASICREV_BCM5701, "unknown BCM5701" }, 346 { BGE_ASICREV_BCM5703, "unknown BCM5703" }, 347 { BGE_ASICREV_BCM5704, "unknown BCM5704" }, 348 { BGE_ASICREV_BCM5705, "unknown BCM5705" }, 349 { BGE_ASICREV_BCM5750, "unknown BCM5750" }, 350 { BGE_ASICREV_BCM5714_A0, "unknown BCM5714" }, 351 { BGE_ASICREV_BCM5752, "unknown BCM5752" }, 352 { BGE_ASICREV_BCM5780, "unknown BCM5780" }, 353 { BGE_ASICREV_BCM5714, "unknown BCM5714" }, 354 { BGE_ASICREV_BCM5755, "unknown BCM5755" }, 355 { BGE_ASICREV_BCM5761, "unknown BCM5761" }, 356 { BGE_ASICREV_BCM5784, "unknown BCM5784" }, 357 { BGE_ASICREV_BCM5785, "unknown BCM5785" }, 358 /* 5754 and 5787 share the same ASIC ID */ 359 { BGE_ASICREV_BCM5787, "unknown BCM5754/5787" }, 360 { BGE_ASICREV_BCM5906, "unknown BCM5906" }, 361 { BGE_ASICREV_BCM57765, "unknown BCM57765" }, 362 { BGE_ASICREV_BCM57766, "unknown BCM57766" }, 363 { BGE_ASICREV_BCM57780, "unknown BCM57780" }, 364 { BGE_ASICREV_BCM5717, "unknown BCM5717" }, 365 { BGE_ASICREV_BCM5719, "unknown BCM5719" }, 366 { BGE_ASICREV_BCM5720, "unknown BCM5720" }, 367 { BGE_ASICREV_BCM5762, "unknown BCM5762" }, 368 369 { 0, NULL } 370 }; 371 372 #define BGE_IS_JUMBO_CAPABLE(sc) ((sc)->bge_flags & BGE_FLAG_JUMBO) 373 #define BGE_IS_5700_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5700_FAMILY) 374 #define BGE_IS_5705_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5705_PLUS) 375 #define BGE_IS_5714_FAMILY(sc) ((sc)->bge_flags & BGE_FLAG_5714_FAMILY) 376 #define BGE_IS_575X_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_575X_PLUS) 377 #define BGE_IS_5755_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5755_PLUS) 378 #define BGE_IS_5717_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_5717_PLUS) 379 #define BGE_IS_57765_PLUS(sc) ((sc)->bge_flags & BGE_FLAG_57765_PLUS) 380 381 static uint32_t bge_chipid(device_t); 382 static const struct bge_vendor * bge_lookup_vendor(uint16_t); 383 static const struct bge_revision * bge_lookup_rev(uint32_t); 384 385 typedef int (*bge_eaddr_fcn_t)(struct bge_softc *, uint8_t[]); 386 387 static int bge_probe(device_t); 388 static int bge_attach(device_t); 389 static int bge_detach(device_t); 390 static int bge_suspend(device_t); 391 static int bge_resume(device_t); 392 static void bge_release_resources(struct bge_softc *); 393 static void bge_dma_map_addr(void *, bus_dma_segment_t *, int, int); 394 static int bge_dma_alloc(struct bge_softc *); 395 static void bge_dma_free(struct bge_softc *); 396 static int bge_dma_ring_alloc(struct bge_softc *, bus_size_t, bus_size_t, 397 bus_dma_tag_t *, uint8_t **, bus_dmamap_t *, bus_addr_t *, const char *); 398 399 static void bge_devinfo(struct bge_softc *); 400 static int bge_mbox_reorder(struct bge_softc *); 401 402 static int bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]); 403 static int bge_get_eaddr_mem(struct bge_softc *, uint8_t[]); 404 static int bge_get_eaddr_nvram(struct bge_softc *, uint8_t[]); 405 static int bge_get_eaddr_eeprom(struct bge_softc *, uint8_t[]); 406 static int bge_get_eaddr(struct bge_softc *, uint8_t[]); 407 408 static void bge_txeof(struct bge_softc *, uint16_t); 409 static void bge_rxcsum(struct bge_softc *, struct bge_rx_bd *, struct mbuf *); 410 static int bge_rxeof(struct bge_softc *, uint16_t, int); 411 412 static void bge_asf_driver_up (struct bge_softc *); 413 static void bge_tick(void *); 414 static void bge_stats_clear_regs(struct bge_softc *); 415 static void bge_stats_update(struct bge_softc *); 416 static void bge_stats_update_regs(struct bge_softc *); 417 static struct mbuf *bge_check_short_dma(struct mbuf *); 418 static struct mbuf *bge_setup_tso(struct bge_softc *, struct mbuf *, 419 uint16_t *, uint16_t *); 420 static int bge_encap(struct bge_softc *, struct mbuf **, uint32_t *); 421 422 static void bge_intr(void *); 423 static int bge_msi_intr(void *); 424 static void bge_intr_task(void *, int); 425 static void bge_start_locked(struct ifnet *); 426 static void bge_start(struct ifnet *); 427 static int bge_ioctl(struct ifnet *, u_long, caddr_t); 428 static void bge_init_locked(struct bge_softc *); 429 static void bge_init(void *); 430 static void bge_stop_block(struct bge_softc *, bus_size_t, uint32_t); 431 static void bge_stop(struct bge_softc *); 432 static void bge_watchdog(struct bge_softc *); 433 static int bge_shutdown(device_t); 434 static int bge_ifmedia_upd_locked(struct ifnet *); 435 static int bge_ifmedia_upd(struct ifnet *); 436 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 437 438 static uint8_t bge_nvram_getbyte(struct bge_softc *, int, uint8_t *); 439 static int bge_read_nvram(struct bge_softc *, caddr_t, int, int); 440 441 static uint8_t bge_eeprom_getbyte(struct bge_softc *, int, uint8_t *); 442 static int bge_read_eeprom(struct bge_softc *, caddr_t, int, int); 443 444 static void bge_setpromisc(struct bge_softc *); 445 static void bge_setmulti(struct bge_softc *); 446 static void bge_setvlan(struct bge_softc *); 447 448 static __inline void bge_rxreuse_std(struct bge_softc *, int); 449 static __inline void bge_rxreuse_jumbo(struct bge_softc *, int); 450 static int bge_newbuf_std(struct bge_softc *, int); 451 static int bge_newbuf_jumbo(struct bge_softc *, int); 452 static int bge_init_rx_ring_std(struct bge_softc *); 453 static void bge_free_rx_ring_std(struct bge_softc *); 454 static int bge_init_rx_ring_jumbo(struct bge_softc *); 455 static void bge_free_rx_ring_jumbo(struct bge_softc *); 456 static void bge_free_tx_ring(struct bge_softc *); 457 static int bge_init_tx_ring(struct bge_softc *); 458 459 static int bge_chipinit(struct bge_softc *); 460 static int bge_blockinit(struct bge_softc *); 461 static uint32_t bge_dma_swap_options(struct bge_softc *); 462 463 static int bge_has_eaddr(struct bge_softc *); 464 static uint32_t bge_readmem_ind(struct bge_softc *, int); 465 static void bge_writemem_ind(struct bge_softc *, int, int); 466 static void bge_writembx(struct bge_softc *, int, int); 467 #ifdef notdef 468 static uint32_t bge_readreg_ind(struct bge_softc *, int); 469 #endif 470 static void bge_writemem_direct(struct bge_softc *, int, int); 471 static void bge_writereg_ind(struct bge_softc *, int, int); 472 473 static int bge_miibus_readreg(device_t, int, int); 474 static int bge_miibus_writereg(device_t, int, int, int); 475 static void bge_miibus_statchg(device_t); 476 #ifdef DEVICE_POLLING 477 static int bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count); 478 #endif 479 480 #define BGE_RESET_SHUTDOWN 0 481 #define BGE_RESET_START 1 482 #define BGE_RESET_SUSPEND 2 483 static void bge_sig_post_reset(struct bge_softc *, int); 484 static void bge_sig_legacy(struct bge_softc *, int); 485 static void bge_sig_pre_reset(struct bge_softc *, int); 486 static void bge_stop_fw(struct bge_softc *); 487 static int bge_reset(struct bge_softc *); 488 static void bge_link_upd(struct bge_softc *); 489 490 static void bge_ape_lock_init(struct bge_softc *); 491 static void bge_ape_read_fw_ver(struct bge_softc *); 492 static int bge_ape_lock(struct bge_softc *, int); 493 static void bge_ape_unlock(struct bge_softc *, int); 494 static void bge_ape_send_event(struct bge_softc *, uint32_t); 495 static void bge_ape_driver_state_change(struct bge_softc *, int); 496 497 /* 498 * The BGE_REGISTER_DEBUG option is only for low-level debugging. It may 499 * leak information to untrusted users. It is also known to cause alignment 500 * traps on certain architectures. 501 */ 502 #ifdef BGE_REGISTER_DEBUG 503 static int bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS); 504 static int bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS); 505 static int bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS); 506 static int bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS); 507 #endif 508 static void bge_add_sysctls(struct bge_softc *); 509 static void bge_add_sysctl_stats_regs(struct bge_softc *, 510 struct sysctl_ctx_list *, struct sysctl_oid_list *); 511 static void bge_add_sysctl_stats(struct bge_softc *, struct sysctl_ctx_list *, 512 struct sysctl_oid_list *); 513 static int bge_sysctl_stats(SYSCTL_HANDLER_ARGS); 514 515 static device_method_t bge_methods[] = { 516 /* Device interface */ 517 DEVMETHOD(device_probe, bge_probe), 518 DEVMETHOD(device_attach, bge_attach), 519 DEVMETHOD(device_detach, bge_detach), 520 DEVMETHOD(device_shutdown, bge_shutdown), 521 DEVMETHOD(device_suspend, bge_suspend), 522 DEVMETHOD(device_resume, bge_resume), 523 524 /* MII interface */ 525 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 526 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 527 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 528 529 DEVMETHOD_END 530 }; 531 532 static driver_t bge_driver = { 533 "bge", 534 bge_methods, 535 sizeof(struct bge_softc) 536 }; 537 538 static devclass_t bge_devclass; 539 540 DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 541 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 542 543 static int bge_allow_asf = 1; 544 545 TUNABLE_INT("hw.bge.allow_asf", &bge_allow_asf); 546 547 static SYSCTL_NODE(_hw, OID_AUTO, bge, CTLFLAG_RD, 0, "BGE driver parameters"); 548 SYSCTL_INT(_hw_bge, OID_AUTO, allow_asf, CTLFLAG_RD, &bge_allow_asf, 0, 549 "Allow ASF mode if available"); 550 551 #define SPARC64_BLADE_1500_MODEL "SUNW,Sun-Blade-1500" 552 #define SPARC64_BLADE_1500_PATH_BGE "/pci@1f,700000/network@2" 553 #define SPARC64_BLADE_2500_MODEL "SUNW,Sun-Blade-2500" 554 #define SPARC64_BLADE_2500_PATH_BGE "/pci@1c,600000/network@3" 555 #define SPARC64_OFW_SUBVENDOR "subsystem-vendor-id" 556 557 static int 558 bge_has_eaddr(struct bge_softc *sc) 559 { 560 #ifdef __sparc64__ 561 char buf[sizeof(SPARC64_BLADE_1500_PATH_BGE)]; 562 device_t dev; 563 uint32_t subvendor; 564 565 dev = sc->bge_dev; 566 567 /* 568 * The on-board BGEs found in sun4u machines aren't fitted with 569 * an EEPROM which means that we have to obtain the MAC address 570 * via OFW and that some tests will always fail. We distinguish 571 * such BGEs by the subvendor ID, which also has to be obtained 572 * from OFW instead of the PCI configuration space as the latter 573 * indicates Broadcom as the subvendor of the netboot interface. 574 * For early Blade 1500 and 2500 we even have to check the OFW 575 * device path as the subvendor ID always defaults to Broadcom 576 * there. 577 */ 578 if (OF_getprop(ofw_bus_get_node(dev), SPARC64_OFW_SUBVENDOR, 579 &subvendor, sizeof(subvendor)) == sizeof(subvendor) && 580 (subvendor == FJTSU_VENDORID || subvendor == SUN_VENDORID)) 581 return (0); 582 memset(buf, 0, sizeof(buf)); 583 if (OF_package_to_path(ofw_bus_get_node(dev), buf, sizeof(buf)) > 0) { 584 if (strcmp(sparc64_model, SPARC64_BLADE_1500_MODEL) == 0 && 585 strcmp(buf, SPARC64_BLADE_1500_PATH_BGE) == 0) 586 return (0); 587 if (strcmp(sparc64_model, SPARC64_BLADE_2500_MODEL) == 0 && 588 strcmp(buf, SPARC64_BLADE_2500_PATH_BGE) == 0) 589 return (0); 590 } 591 #endif 592 return (1); 593 } 594 595 static uint32_t 596 bge_readmem_ind(struct bge_softc *sc, int off) 597 { 598 device_t dev; 599 uint32_t val; 600 601 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 602 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 603 return (0); 604 605 dev = sc->bge_dev; 606 607 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 608 val = pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4); 609 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 610 return (val); 611 } 612 613 static void 614 bge_writemem_ind(struct bge_softc *sc, int off, int val) 615 { 616 device_t dev; 617 618 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 619 off >= BGE_STATS_BLOCK && off < BGE_SEND_RING_1_TO_4) 620 return; 621 622 dev = sc->bge_dev; 623 624 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 625 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 626 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4); 627 } 628 629 #ifdef notdef 630 static uint32_t 631 bge_readreg_ind(struct bge_softc *sc, int off) 632 { 633 device_t dev; 634 635 dev = sc->bge_dev; 636 637 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 638 return (pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 639 } 640 #endif 641 642 static void 643 bge_writereg_ind(struct bge_softc *sc, int off, int val) 644 { 645 device_t dev; 646 647 dev = sc->bge_dev; 648 649 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 650 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 651 } 652 653 static void 654 bge_writemem_direct(struct bge_softc *sc, int off, int val) 655 { 656 CSR_WRITE_4(sc, off, val); 657 } 658 659 static void 660 bge_writembx(struct bge_softc *sc, int off, int val) 661 { 662 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 663 off += BGE_LPMBX_IRQ0_HI - BGE_MBX_IRQ0_HI; 664 665 CSR_WRITE_4(sc, off, val); 666 if ((sc->bge_flags & BGE_FLAG_MBOX_REORDER) != 0) 667 CSR_READ_4(sc, off); 668 } 669 670 /* 671 * Clear all stale locks and select the lock for this driver instance. 672 */ 673 static void 674 bge_ape_lock_init(struct bge_softc *sc) 675 { 676 uint32_t bit, regbase; 677 int i; 678 679 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 680 regbase = BGE_APE_LOCK_GRANT; 681 else 682 regbase = BGE_APE_PER_LOCK_GRANT; 683 684 /* Clear any stale locks. */ 685 for (i = BGE_APE_LOCK_PHY0; i <= BGE_APE_LOCK_GPIO; i++) { 686 switch (i) { 687 case BGE_APE_LOCK_PHY0: 688 case BGE_APE_LOCK_PHY1: 689 case BGE_APE_LOCK_PHY2: 690 case BGE_APE_LOCK_PHY3: 691 bit = BGE_APE_LOCK_GRANT_DRIVER0; 692 break; 693 default: 694 if (sc->bge_func_addr == 0) 695 bit = BGE_APE_LOCK_GRANT_DRIVER0; 696 else 697 bit = (1 << sc->bge_func_addr); 698 } 699 APE_WRITE_4(sc, regbase + 4 * i, bit); 700 } 701 702 /* Select the PHY lock based on the device's function number. */ 703 switch (sc->bge_func_addr) { 704 case 0: 705 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY0; 706 break; 707 case 1: 708 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY1; 709 break; 710 case 2: 711 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY2; 712 break; 713 case 3: 714 sc->bge_phy_ape_lock = BGE_APE_LOCK_PHY3; 715 break; 716 default: 717 device_printf(sc->bge_dev, 718 "PHY lock not supported on this function\n"); 719 } 720 } 721 722 /* 723 * Check for APE firmware, set flags, and print version info. 724 */ 725 static void 726 bge_ape_read_fw_ver(struct bge_softc *sc) 727 { 728 const char *fwtype; 729 uint32_t apedata, features; 730 731 /* Check for a valid APE signature in shared memory. */ 732 apedata = APE_READ_4(sc, BGE_APE_SEG_SIG); 733 if (apedata != BGE_APE_SEG_SIG_MAGIC) { 734 sc->bge_mfw_flags &= ~ BGE_MFW_ON_APE; 735 return; 736 } 737 738 /* Check if APE firmware is running. */ 739 apedata = APE_READ_4(sc, BGE_APE_FW_STATUS); 740 if ((apedata & BGE_APE_FW_STATUS_READY) == 0) { 741 device_printf(sc->bge_dev, "APE signature found " 742 "but FW status not ready! 0x%08x\n", apedata); 743 return; 744 } 745 746 sc->bge_mfw_flags |= BGE_MFW_ON_APE; 747 748 /* Fetch the APE firwmare type and version. */ 749 apedata = APE_READ_4(sc, BGE_APE_FW_VERSION); 750 features = APE_READ_4(sc, BGE_APE_FW_FEATURES); 751 if ((features & BGE_APE_FW_FEATURE_NCSI) != 0) { 752 sc->bge_mfw_flags |= BGE_MFW_TYPE_NCSI; 753 fwtype = "NCSI"; 754 } else if ((features & BGE_APE_FW_FEATURE_DASH) != 0) { 755 sc->bge_mfw_flags |= BGE_MFW_TYPE_DASH; 756 fwtype = "DASH"; 757 } else 758 fwtype = "UNKN"; 759 760 /* Print the APE firmware version. */ 761 device_printf(sc->bge_dev, "APE FW version: %s v%d.%d.%d.%d\n", 762 fwtype, 763 (apedata & BGE_APE_FW_VERSION_MAJMSK) >> BGE_APE_FW_VERSION_MAJSFT, 764 (apedata & BGE_APE_FW_VERSION_MINMSK) >> BGE_APE_FW_VERSION_MINSFT, 765 (apedata & BGE_APE_FW_VERSION_REVMSK) >> BGE_APE_FW_VERSION_REVSFT, 766 (apedata & BGE_APE_FW_VERSION_BLDMSK)); 767 } 768 769 static int 770 bge_ape_lock(struct bge_softc *sc, int locknum) 771 { 772 uint32_t bit, gnt, req, status; 773 int i, off; 774 775 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 776 return (0); 777 778 /* Lock request/grant registers have different bases. */ 779 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) { 780 req = BGE_APE_LOCK_REQ; 781 gnt = BGE_APE_LOCK_GRANT; 782 } else { 783 req = BGE_APE_PER_LOCK_REQ; 784 gnt = BGE_APE_PER_LOCK_GRANT; 785 } 786 787 off = 4 * locknum; 788 789 switch (locknum) { 790 case BGE_APE_LOCK_GPIO: 791 /* Lock required when using GPIO. */ 792 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 793 return (0); 794 if (sc->bge_func_addr == 0) 795 bit = BGE_APE_LOCK_REQ_DRIVER0; 796 else 797 bit = (1 << sc->bge_func_addr); 798 break; 799 case BGE_APE_LOCK_GRC: 800 /* Lock required to reset the device. */ 801 if (sc->bge_func_addr == 0) 802 bit = BGE_APE_LOCK_REQ_DRIVER0; 803 else 804 bit = (1 << sc->bge_func_addr); 805 break; 806 case BGE_APE_LOCK_MEM: 807 /* Lock required when accessing certain APE memory. */ 808 if (sc->bge_func_addr == 0) 809 bit = BGE_APE_LOCK_REQ_DRIVER0; 810 else 811 bit = (1 << sc->bge_func_addr); 812 break; 813 case BGE_APE_LOCK_PHY0: 814 case BGE_APE_LOCK_PHY1: 815 case BGE_APE_LOCK_PHY2: 816 case BGE_APE_LOCK_PHY3: 817 /* Lock required when accessing PHYs. */ 818 bit = BGE_APE_LOCK_REQ_DRIVER0; 819 break; 820 default: 821 return (EINVAL); 822 } 823 824 /* Request a lock. */ 825 APE_WRITE_4(sc, req + off, bit); 826 827 /* Wait up to 1 second to acquire lock. */ 828 for (i = 0; i < 20000; i++) { 829 status = APE_READ_4(sc, gnt + off); 830 if (status == bit) 831 break; 832 DELAY(50); 833 } 834 835 /* Handle any errors. */ 836 if (status != bit) { 837 device_printf(sc->bge_dev, "APE lock %d request failed! " 838 "request = 0x%04x[0x%04x], status = 0x%04x[0x%04x]\n", 839 locknum, req + off, bit & 0xFFFF, gnt + off, 840 status & 0xFFFF); 841 /* Revoke the lock request. */ 842 APE_WRITE_4(sc, gnt + off, bit); 843 return (EBUSY); 844 } 845 846 return (0); 847 } 848 849 static void 850 bge_ape_unlock(struct bge_softc *sc, int locknum) 851 { 852 uint32_t bit, gnt; 853 int off; 854 855 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 856 return; 857 858 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 859 gnt = BGE_APE_LOCK_GRANT; 860 else 861 gnt = BGE_APE_PER_LOCK_GRANT; 862 863 off = 4 * locknum; 864 865 switch (locknum) { 866 case BGE_APE_LOCK_GPIO: 867 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 868 return; 869 if (sc->bge_func_addr == 0) 870 bit = BGE_APE_LOCK_GRANT_DRIVER0; 871 else 872 bit = (1 << sc->bge_func_addr); 873 break; 874 case BGE_APE_LOCK_GRC: 875 if (sc->bge_func_addr == 0) 876 bit = BGE_APE_LOCK_GRANT_DRIVER0; 877 else 878 bit = (1 << sc->bge_func_addr); 879 break; 880 case BGE_APE_LOCK_MEM: 881 if (sc->bge_func_addr == 0) 882 bit = BGE_APE_LOCK_GRANT_DRIVER0; 883 else 884 bit = (1 << sc->bge_func_addr); 885 break; 886 case BGE_APE_LOCK_PHY0: 887 case BGE_APE_LOCK_PHY1: 888 case BGE_APE_LOCK_PHY2: 889 case BGE_APE_LOCK_PHY3: 890 bit = BGE_APE_LOCK_GRANT_DRIVER0; 891 break; 892 default: 893 return; 894 } 895 896 APE_WRITE_4(sc, gnt + off, bit); 897 } 898 899 /* 900 * Send an event to the APE firmware. 901 */ 902 static void 903 bge_ape_send_event(struct bge_softc *sc, uint32_t event) 904 { 905 uint32_t apedata; 906 int i; 907 908 /* NCSI does not support APE events. */ 909 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 910 return; 911 912 /* Wait up to 1ms for APE to service previous event. */ 913 for (i = 10; i > 0; i--) { 914 if (bge_ape_lock(sc, BGE_APE_LOCK_MEM) != 0) 915 break; 916 apedata = APE_READ_4(sc, BGE_APE_EVENT_STATUS); 917 if ((apedata & BGE_APE_EVENT_STATUS_EVENT_PENDING) == 0) { 918 APE_WRITE_4(sc, BGE_APE_EVENT_STATUS, event | 919 BGE_APE_EVENT_STATUS_EVENT_PENDING); 920 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 921 APE_WRITE_4(sc, BGE_APE_EVENT, BGE_APE_EVENT_1); 922 break; 923 } 924 bge_ape_unlock(sc, BGE_APE_LOCK_MEM); 925 DELAY(100); 926 } 927 if (i == 0) 928 device_printf(sc->bge_dev, "APE event 0x%08x send timed out\n", 929 event); 930 } 931 932 static void 933 bge_ape_driver_state_change(struct bge_softc *sc, int kind) 934 { 935 uint32_t apedata, event; 936 937 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) == 0) 938 return; 939 940 switch (kind) { 941 case BGE_RESET_START: 942 /* If this is the first load, clear the load counter. */ 943 apedata = APE_READ_4(sc, BGE_APE_HOST_SEG_SIG); 944 if (apedata != BGE_APE_HOST_SEG_SIG_MAGIC) 945 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, 0); 946 else { 947 apedata = APE_READ_4(sc, BGE_APE_HOST_INIT_COUNT); 948 APE_WRITE_4(sc, BGE_APE_HOST_INIT_COUNT, ++apedata); 949 } 950 APE_WRITE_4(sc, BGE_APE_HOST_SEG_SIG, 951 BGE_APE_HOST_SEG_SIG_MAGIC); 952 APE_WRITE_4(sc, BGE_APE_HOST_SEG_LEN, 953 BGE_APE_HOST_SEG_LEN_MAGIC); 954 955 /* Add some version info if bge(4) supports it. */ 956 APE_WRITE_4(sc, BGE_APE_HOST_DRIVER_ID, 957 BGE_APE_HOST_DRIVER_ID_MAGIC(1, 0)); 958 APE_WRITE_4(sc, BGE_APE_HOST_BEHAVIOR, 959 BGE_APE_HOST_BEHAV_NO_PHYLOCK); 960 APE_WRITE_4(sc, BGE_APE_HOST_HEARTBEAT_INT_MS, 961 BGE_APE_HOST_HEARTBEAT_INT_DISABLE); 962 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 963 BGE_APE_HOST_DRVR_STATE_START); 964 event = BGE_APE_EVENT_STATUS_STATE_START; 965 break; 966 case BGE_RESET_SHUTDOWN: 967 APE_WRITE_4(sc, BGE_APE_HOST_DRVR_STATE, 968 BGE_APE_HOST_DRVR_STATE_UNLOAD); 969 event = BGE_APE_EVENT_STATUS_STATE_UNLOAD; 970 break; 971 case BGE_RESET_SUSPEND: 972 event = BGE_APE_EVENT_STATUS_STATE_SUSPEND; 973 break; 974 default: 975 return; 976 } 977 978 bge_ape_send_event(sc, event | BGE_APE_EVENT_STATUS_DRIVER_EVNT | 979 BGE_APE_EVENT_STATUS_STATE_CHNGE); 980 } 981 982 /* 983 * Map a single buffer address. 984 */ 985 986 static void 987 bge_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 988 { 989 struct bge_dmamap_arg *ctx; 990 991 if (error) 992 return; 993 994 KASSERT(nseg == 1, ("%s: %d segments returned!", __func__, nseg)); 995 996 ctx = arg; 997 ctx->bge_busaddr = segs->ds_addr; 998 } 999 1000 static uint8_t 1001 bge_nvram_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1002 { 1003 uint32_t access, byte = 0; 1004 int i; 1005 1006 /* Lock. */ 1007 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 1008 for (i = 0; i < 8000; i++) { 1009 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & BGE_NVRAMSWARB_GNT1) 1010 break; 1011 DELAY(20); 1012 } 1013 if (i == 8000) 1014 return (1); 1015 1016 /* Enable access. */ 1017 access = CSR_READ_4(sc, BGE_NVRAM_ACCESS); 1018 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access | BGE_NVRAMACC_ENABLE); 1019 1020 CSR_WRITE_4(sc, BGE_NVRAM_ADDR, addr & 0xfffffffc); 1021 CSR_WRITE_4(sc, BGE_NVRAM_CMD, BGE_NVRAM_READCMD); 1022 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 1023 DELAY(10); 1024 if (CSR_READ_4(sc, BGE_NVRAM_CMD) & BGE_NVRAMCMD_DONE) { 1025 DELAY(10); 1026 break; 1027 } 1028 } 1029 1030 if (i == BGE_TIMEOUT * 10) { 1031 if_printf(sc->bge_ifp, "nvram read timed out\n"); 1032 return (1); 1033 } 1034 1035 /* Get result. */ 1036 byte = CSR_READ_4(sc, BGE_NVRAM_RDDATA); 1037 1038 *dest = (bswap32(byte) >> ((addr % 4) * 8)) & 0xFF; 1039 1040 /* Disable access. */ 1041 CSR_WRITE_4(sc, BGE_NVRAM_ACCESS, access); 1042 1043 /* Unlock. */ 1044 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_CLR1); 1045 CSR_READ_4(sc, BGE_NVRAM_SWARB); 1046 1047 return (0); 1048 } 1049 1050 /* 1051 * Read a sequence of bytes from NVRAM. 1052 */ 1053 static int 1054 bge_read_nvram(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1055 { 1056 int err = 0, i; 1057 uint8_t byte = 0; 1058 1059 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1060 return (1); 1061 1062 for (i = 0; i < cnt; i++) { 1063 err = bge_nvram_getbyte(sc, off + i, &byte); 1064 if (err) 1065 break; 1066 *(dest + i) = byte; 1067 } 1068 1069 return (err ? 1 : 0); 1070 } 1071 1072 /* 1073 * Read a byte of data stored in the EEPROM at address 'addr.' The 1074 * BCM570x supports both the traditional bitbang interface and an 1075 * auto access interface for reading the EEPROM. We use the auto 1076 * access method. 1077 */ 1078 static uint8_t 1079 bge_eeprom_getbyte(struct bge_softc *sc, int addr, uint8_t *dest) 1080 { 1081 int i; 1082 uint32_t byte = 0; 1083 1084 /* 1085 * Enable use of auto EEPROM access so we can avoid 1086 * having to use the bitbang method. 1087 */ 1088 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 1089 1090 /* Reset the EEPROM, load the clock period. */ 1091 CSR_WRITE_4(sc, BGE_EE_ADDR, 1092 BGE_EEADDR_RESET | BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 1093 DELAY(20); 1094 1095 /* Issue the read EEPROM command. */ 1096 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 1097 1098 /* Wait for completion */ 1099 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 1100 DELAY(10); 1101 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 1102 break; 1103 } 1104 1105 if (i == BGE_TIMEOUT * 10) { 1106 device_printf(sc->bge_dev, "EEPROM read timed out\n"); 1107 return (1); 1108 } 1109 1110 /* Get result. */ 1111 byte = CSR_READ_4(sc, BGE_EE_DATA); 1112 1113 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 1114 1115 return (0); 1116 } 1117 1118 /* 1119 * Read a sequence of bytes from the EEPROM. 1120 */ 1121 static int 1122 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, int off, int cnt) 1123 { 1124 int i, error = 0; 1125 uint8_t byte = 0; 1126 1127 for (i = 0; i < cnt; i++) { 1128 error = bge_eeprom_getbyte(sc, off + i, &byte); 1129 if (error) 1130 break; 1131 *(dest + i) = byte; 1132 } 1133 1134 return (error ? 1 : 0); 1135 } 1136 1137 static int 1138 bge_miibus_readreg(device_t dev, int phy, int reg) 1139 { 1140 struct bge_softc *sc; 1141 uint32_t val; 1142 int i; 1143 1144 sc = device_get_softc(dev); 1145 1146 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1147 return (0); 1148 1149 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1150 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1151 CSR_WRITE_4(sc, BGE_MI_MODE, 1152 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1153 DELAY(80); 1154 } 1155 1156 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ | BGE_MICOMM_BUSY | 1157 BGE_MIPHY(phy) | BGE_MIREG(reg)); 1158 1159 /* Poll for the PHY register access to complete. */ 1160 for (i = 0; i < BGE_TIMEOUT; i++) { 1161 DELAY(10); 1162 val = CSR_READ_4(sc, BGE_MI_COMM); 1163 if ((val & BGE_MICOMM_BUSY) == 0) { 1164 DELAY(5); 1165 val = CSR_READ_4(sc, BGE_MI_COMM); 1166 break; 1167 } 1168 } 1169 1170 if (i == BGE_TIMEOUT) { 1171 device_printf(sc->bge_dev, 1172 "PHY read timed out (phy %d, reg %d, val 0x%08x)\n", 1173 phy, reg, val); 1174 val = 0; 1175 } 1176 1177 /* Restore the autopoll bit if necessary. */ 1178 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1179 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1180 DELAY(80); 1181 } 1182 1183 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1184 1185 if (val & BGE_MICOMM_READFAIL) 1186 return (0); 1187 1188 return (val & 0xFFFF); 1189 } 1190 1191 static int 1192 bge_miibus_writereg(device_t dev, int phy, int reg, int val) 1193 { 1194 struct bge_softc *sc; 1195 int i; 1196 1197 sc = device_get_softc(dev); 1198 1199 if (sc->bge_asicrev == BGE_ASICREV_BCM5906 && 1200 (reg == BRGPHY_MII_1000CTL || reg == BRGPHY_MII_AUXCTL)) 1201 return (0); 1202 1203 if (bge_ape_lock(sc, sc->bge_phy_ape_lock) != 0) 1204 return (0); 1205 1206 /* Clear the autopoll bit if set, otherwise may trigger PCI errors. */ 1207 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1208 CSR_WRITE_4(sc, BGE_MI_MODE, 1209 sc->bge_mi_mode & ~BGE_MIMODE_AUTOPOLL); 1210 DELAY(80); 1211 } 1212 1213 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE | BGE_MICOMM_BUSY | 1214 BGE_MIPHY(phy) | BGE_MIREG(reg) | val); 1215 1216 for (i = 0; i < BGE_TIMEOUT; i++) { 1217 DELAY(10); 1218 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) { 1219 DELAY(5); 1220 CSR_READ_4(sc, BGE_MI_COMM); /* dummy read */ 1221 break; 1222 } 1223 } 1224 1225 /* Restore the autopoll bit if necessary. */ 1226 if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 1227 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 1228 DELAY(80); 1229 } 1230 1231 bge_ape_unlock(sc, sc->bge_phy_ape_lock); 1232 1233 if (i == BGE_TIMEOUT) 1234 device_printf(sc->bge_dev, 1235 "PHY write timed out (phy %d, reg %d, val 0x%04x)\n", 1236 phy, reg, val); 1237 1238 return (0); 1239 } 1240 1241 static void 1242 bge_miibus_statchg(device_t dev) 1243 { 1244 struct bge_softc *sc; 1245 struct mii_data *mii; 1246 uint32_t mac_mode, rx_mode, tx_mode; 1247 1248 sc = device_get_softc(dev); 1249 if ((sc->bge_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1250 return; 1251 mii = device_get_softc(sc->bge_miibus); 1252 1253 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1254 (IFM_ACTIVE | IFM_AVALID)) { 1255 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1256 case IFM_10_T: 1257 case IFM_100_TX: 1258 sc->bge_link = 1; 1259 break; 1260 case IFM_1000_T: 1261 case IFM_1000_SX: 1262 case IFM_2500_SX: 1263 if (sc->bge_asicrev != BGE_ASICREV_BCM5906) 1264 sc->bge_link = 1; 1265 else 1266 sc->bge_link = 0; 1267 break; 1268 default: 1269 sc->bge_link = 0; 1270 break; 1271 } 1272 } else 1273 sc->bge_link = 0; 1274 if (sc->bge_link == 0) 1275 return; 1276 1277 /* 1278 * APE firmware touches these registers to keep the MAC 1279 * connected to the outside world. Try to keep the 1280 * accesses atomic. 1281 */ 1282 1283 /* Set the port mode (MII/GMII) to match the link speed. */ 1284 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & 1285 ~(BGE_MACMODE_PORTMODE | BGE_MACMODE_HALF_DUPLEX); 1286 tx_mode = CSR_READ_4(sc, BGE_TX_MODE); 1287 rx_mode = CSR_READ_4(sc, BGE_RX_MODE); 1288 1289 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 1290 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 1291 mac_mode |= BGE_PORTMODE_GMII; 1292 else 1293 mac_mode |= BGE_PORTMODE_MII; 1294 1295 /* Set MAC flow control behavior to match link flow control settings. */ 1296 tx_mode &= ~BGE_TXMODE_FLOWCTL_ENABLE; 1297 rx_mode &= ~BGE_RXMODE_FLOWCTL_ENABLE; 1298 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1299 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1300 tx_mode |= BGE_TXMODE_FLOWCTL_ENABLE; 1301 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1302 rx_mode |= BGE_RXMODE_FLOWCTL_ENABLE; 1303 } else 1304 mac_mode |= BGE_MACMODE_HALF_DUPLEX; 1305 1306 CSR_WRITE_4(sc, BGE_MAC_MODE, mac_mode); 1307 DELAY(40); 1308 CSR_WRITE_4(sc, BGE_TX_MODE, tx_mode); 1309 CSR_WRITE_4(sc, BGE_RX_MODE, rx_mode); 1310 } 1311 1312 /* 1313 * Intialize a standard receive ring descriptor. 1314 */ 1315 static int 1316 bge_newbuf_std(struct bge_softc *sc, int i) 1317 { 1318 struct mbuf *m; 1319 struct bge_rx_bd *r; 1320 bus_dma_segment_t segs[1]; 1321 bus_dmamap_t map; 1322 int error, nsegs; 1323 1324 if (sc->bge_flags & BGE_FLAG_JUMBO_STD && 1325 (sc->bge_ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + 1326 ETHER_VLAN_ENCAP_LEN > (MCLBYTES - ETHER_ALIGN))) { 1327 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1328 if (m == NULL) 1329 return (ENOBUFS); 1330 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1331 } else { 1332 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1333 if (m == NULL) 1334 return (ENOBUFS); 1335 m->m_len = m->m_pkthdr.len = MCLBYTES; 1336 } 1337 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1338 m_adj(m, ETHER_ALIGN); 1339 1340 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_rx_mtag, 1341 sc->bge_cdata.bge_rx_std_sparemap, m, segs, &nsegs, 0); 1342 if (error != 0) { 1343 m_freem(m); 1344 return (error); 1345 } 1346 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1347 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1348 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_POSTREAD); 1349 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1350 sc->bge_cdata.bge_rx_std_dmamap[i]); 1351 } 1352 map = sc->bge_cdata.bge_rx_std_dmamap[i]; 1353 sc->bge_cdata.bge_rx_std_dmamap[i] = sc->bge_cdata.bge_rx_std_sparemap; 1354 sc->bge_cdata.bge_rx_std_sparemap = map; 1355 sc->bge_cdata.bge_rx_std_chain[i] = m; 1356 sc->bge_cdata.bge_rx_std_seglen[i] = segs[0].ds_len; 1357 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 1358 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1359 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1360 r->bge_flags = BGE_RXBDFLAG_END; 1361 r->bge_len = segs[0].ds_len; 1362 r->bge_idx = i; 1363 1364 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1365 sc->bge_cdata.bge_rx_std_dmamap[i], BUS_DMASYNC_PREREAD); 1366 1367 return (0); 1368 } 1369 1370 /* 1371 * Initialize a jumbo receive ring descriptor. This allocates 1372 * a jumbo buffer from the pool managed internally by the driver. 1373 */ 1374 static int 1375 bge_newbuf_jumbo(struct bge_softc *sc, int i) 1376 { 1377 bus_dma_segment_t segs[BGE_NSEG_JUMBO]; 1378 bus_dmamap_t map; 1379 struct bge_extrx_bd *r; 1380 struct mbuf *m; 1381 int error, nsegs; 1382 1383 MGETHDR(m, M_NOWAIT, MT_DATA); 1384 if (m == NULL) 1385 return (ENOBUFS); 1386 1387 m_cljget(m, M_NOWAIT, MJUM9BYTES); 1388 if (!(m->m_flags & M_EXT)) { 1389 m_freem(m); 1390 return (ENOBUFS); 1391 } 1392 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1393 if ((sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) == 0) 1394 m_adj(m, ETHER_ALIGN); 1395 1396 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_mtag_jumbo, 1397 sc->bge_cdata.bge_rx_jumbo_sparemap, m, segs, &nsegs, 0); 1398 if (error != 0) { 1399 m_freem(m); 1400 return (error); 1401 } 1402 1403 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1404 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1405 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_POSTREAD); 1406 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1407 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1408 } 1409 map = sc->bge_cdata.bge_rx_jumbo_dmamap[i]; 1410 sc->bge_cdata.bge_rx_jumbo_dmamap[i] = 1411 sc->bge_cdata.bge_rx_jumbo_sparemap; 1412 sc->bge_cdata.bge_rx_jumbo_sparemap = map; 1413 sc->bge_cdata.bge_rx_jumbo_chain[i] = m; 1414 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = 0; 1415 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = 0; 1416 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = 0; 1417 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = 0; 1418 1419 /* 1420 * Fill in the extended RX buffer descriptor. 1421 */ 1422 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 1423 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 1424 r->bge_idx = i; 1425 r->bge_len3 = r->bge_len2 = r->bge_len1 = 0; 1426 switch (nsegs) { 1427 case 4: 1428 r->bge_addr3.bge_addr_lo = BGE_ADDR_LO(segs[3].ds_addr); 1429 r->bge_addr3.bge_addr_hi = BGE_ADDR_HI(segs[3].ds_addr); 1430 r->bge_len3 = segs[3].ds_len; 1431 sc->bge_cdata.bge_rx_jumbo_seglen[i][3] = segs[3].ds_len; 1432 case 3: 1433 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr); 1434 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr); 1435 r->bge_len2 = segs[2].ds_len; 1436 sc->bge_cdata.bge_rx_jumbo_seglen[i][2] = segs[2].ds_len; 1437 case 2: 1438 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr); 1439 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr); 1440 r->bge_len1 = segs[1].ds_len; 1441 sc->bge_cdata.bge_rx_jumbo_seglen[i][1] = segs[1].ds_len; 1442 case 1: 1443 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr); 1444 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr); 1445 r->bge_len0 = segs[0].ds_len; 1446 sc->bge_cdata.bge_rx_jumbo_seglen[i][0] = segs[0].ds_len; 1447 break; 1448 default: 1449 panic("%s: %d segments\n", __func__, nsegs); 1450 } 1451 1452 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1453 sc->bge_cdata.bge_rx_jumbo_dmamap[i], BUS_DMASYNC_PREREAD); 1454 1455 return (0); 1456 } 1457 1458 static int 1459 bge_init_rx_ring_std(struct bge_softc *sc) 1460 { 1461 int error, i; 1462 1463 bzero(sc->bge_ldata.bge_rx_std_ring, BGE_STD_RX_RING_SZ); 1464 sc->bge_std = 0; 1465 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1466 if ((error = bge_newbuf_std(sc, i)) != 0) 1467 return (error); 1468 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1469 } 1470 1471 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 1472 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 1473 1474 sc->bge_std = 0; 1475 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, BGE_STD_RX_RING_CNT - 1); 1476 1477 return (0); 1478 } 1479 1480 static void 1481 bge_free_rx_ring_std(struct bge_softc *sc) 1482 { 1483 int i; 1484 1485 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 1486 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 1487 bus_dmamap_sync(sc->bge_cdata.bge_rx_mtag, 1488 sc->bge_cdata.bge_rx_std_dmamap[i], 1489 BUS_DMASYNC_POSTREAD); 1490 bus_dmamap_unload(sc->bge_cdata.bge_rx_mtag, 1491 sc->bge_cdata.bge_rx_std_dmamap[i]); 1492 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 1493 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 1494 } 1495 bzero((char *)&sc->bge_ldata.bge_rx_std_ring[i], 1496 sizeof(struct bge_rx_bd)); 1497 } 1498 } 1499 1500 static int 1501 bge_init_rx_ring_jumbo(struct bge_softc *sc) 1502 { 1503 struct bge_rcb *rcb; 1504 int error, i; 1505 1506 bzero(sc->bge_ldata.bge_rx_jumbo_ring, BGE_JUMBO_RX_RING_SZ); 1507 sc->bge_jumbo = 0; 1508 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1509 if ((error = bge_newbuf_jumbo(sc, i)) != 0) 1510 return (error); 1511 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1512 } 1513 1514 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 1515 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 1516 1517 sc->bge_jumbo = 0; 1518 1519 /* Enable the jumbo receive producer ring. */ 1520 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 1521 rcb->bge_maxlen_flags = 1522 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_USE_EXT_RX_BD); 1523 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1524 1525 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, BGE_JUMBO_RX_RING_CNT - 1); 1526 1527 return (0); 1528 } 1529 1530 static void 1531 bge_free_rx_ring_jumbo(struct bge_softc *sc) 1532 { 1533 int i; 1534 1535 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 1536 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 1537 bus_dmamap_sync(sc->bge_cdata.bge_mtag_jumbo, 1538 sc->bge_cdata.bge_rx_jumbo_dmamap[i], 1539 BUS_DMASYNC_POSTREAD); 1540 bus_dmamap_unload(sc->bge_cdata.bge_mtag_jumbo, 1541 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 1542 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 1543 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 1544 } 1545 bzero((char *)&sc->bge_ldata.bge_rx_jumbo_ring[i], 1546 sizeof(struct bge_extrx_bd)); 1547 } 1548 } 1549 1550 static void 1551 bge_free_tx_ring(struct bge_softc *sc) 1552 { 1553 int i; 1554 1555 if (sc->bge_ldata.bge_tx_ring == NULL) 1556 return; 1557 1558 for (i = 0; i < BGE_TX_RING_CNT; i++) { 1559 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 1560 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 1561 sc->bge_cdata.bge_tx_dmamap[i], 1562 BUS_DMASYNC_POSTWRITE); 1563 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 1564 sc->bge_cdata.bge_tx_dmamap[i]); 1565 m_freem(sc->bge_cdata.bge_tx_chain[i]); 1566 sc->bge_cdata.bge_tx_chain[i] = NULL; 1567 } 1568 bzero((char *)&sc->bge_ldata.bge_tx_ring[i], 1569 sizeof(struct bge_tx_bd)); 1570 } 1571 } 1572 1573 static int 1574 bge_init_tx_ring(struct bge_softc *sc) 1575 { 1576 sc->bge_txcnt = 0; 1577 sc->bge_tx_saved_considx = 0; 1578 1579 bzero(sc->bge_ldata.bge_tx_ring, BGE_TX_RING_SZ); 1580 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 1581 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1582 1583 /* Initialize transmit producer index for host-memory send ring. */ 1584 sc->bge_tx_prodidx = 0; 1585 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1586 1587 /* 5700 b2 errata */ 1588 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1589 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, sc->bge_tx_prodidx); 1590 1591 /* NIC-memory send ring not used; initialize to zero. */ 1592 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1593 /* 5700 b2 errata */ 1594 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 1595 bge_writembx(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 1596 1597 return (0); 1598 } 1599 1600 static void 1601 bge_setpromisc(struct bge_softc *sc) 1602 { 1603 struct ifnet *ifp; 1604 1605 BGE_LOCK_ASSERT(sc); 1606 1607 ifp = sc->bge_ifp; 1608 1609 /* Enable or disable promiscuous mode as needed. */ 1610 if (ifp->if_flags & IFF_PROMISC) 1611 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1612 else 1613 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 1614 } 1615 1616 static void 1617 bge_setmulti(struct bge_softc *sc) 1618 { 1619 struct ifnet *ifp; 1620 struct ifmultiaddr *ifma; 1621 uint32_t hashes[4] = { 0, 0, 0, 0 }; 1622 int h, i; 1623 1624 BGE_LOCK_ASSERT(sc); 1625 1626 ifp = sc->bge_ifp; 1627 1628 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 1629 for (i = 0; i < 4; i++) 1630 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 1631 return; 1632 } 1633 1634 /* First, zot all the existing filters. */ 1635 for (i = 0; i < 4; i++) 1636 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 1637 1638 /* Now program new ones. */ 1639 if_maddr_rlock(ifp); 1640 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1641 if (ifma->ifma_addr->sa_family != AF_LINK) 1642 continue; 1643 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 1644 ifma->ifma_addr), ETHER_ADDR_LEN) & 0x7F; 1645 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 1646 } 1647 if_maddr_runlock(ifp); 1648 1649 for (i = 0; i < 4; i++) 1650 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 1651 } 1652 1653 static void 1654 bge_setvlan(struct bge_softc *sc) 1655 { 1656 struct ifnet *ifp; 1657 1658 BGE_LOCK_ASSERT(sc); 1659 1660 ifp = sc->bge_ifp; 1661 1662 /* Enable or disable VLAN tag stripping as needed. */ 1663 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) 1664 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1665 else 1666 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_KEEP_VLAN_DIAG); 1667 } 1668 1669 static void 1670 bge_sig_pre_reset(struct bge_softc *sc, int type) 1671 { 1672 1673 /* 1674 * Some chips don't like this so only do this if ASF is enabled 1675 */ 1676 if (sc->bge_asf_mode) 1677 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 1678 1679 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1680 switch (type) { 1681 case BGE_RESET_START: 1682 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1683 BGE_FW_DRV_STATE_START); 1684 break; 1685 case BGE_RESET_SHUTDOWN: 1686 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1687 BGE_FW_DRV_STATE_UNLOAD); 1688 break; 1689 case BGE_RESET_SUSPEND: 1690 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1691 BGE_FW_DRV_STATE_SUSPEND); 1692 break; 1693 } 1694 } 1695 1696 if (type == BGE_RESET_START || type == BGE_RESET_SUSPEND) 1697 bge_ape_driver_state_change(sc, type); 1698 } 1699 1700 static void 1701 bge_sig_post_reset(struct bge_softc *sc, int type) 1702 { 1703 1704 if (sc->bge_asf_mode & ASF_NEW_HANDSHAKE) { 1705 switch (type) { 1706 case BGE_RESET_START: 1707 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1708 BGE_FW_DRV_STATE_START_DONE); 1709 /* START DONE */ 1710 break; 1711 case BGE_RESET_SHUTDOWN: 1712 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1713 BGE_FW_DRV_STATE_UNLOAD_DONE); 1714 break; 1715 } 1716 } 1717 if (type == BGE_RESET_SHUTDOWN) 1718 bge_ape_driver_state_change(sc, type); 1719 } 1720 1721 static void 1722 bge_sig_legacy(struct bge_softc *sc, int type) 1723 { 1724 1725 if (sc->bge_asf_mode) { 1726 switch (type) { 1727 case BGE_RESET_START: 1728 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1729 BGE_FW_DRV_STATE_START); 1730 break; 1731 case BGE_RESET_SHUTDOWN: 1732 bge_writemem_ind(sc, BGE_SRAM_FW_DRV_STATE_MB, 1733 BGE_FW_DRV_STATE_UNLOAD); 1734 break; 1735 } 1736 } 1737 } 1738 1739 static void 1740 bge_stop_fw(struct bge_softc *sc) 1741 { 1742 int i; 1743 1744 if (sc->bge_asf_mode) { 1745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, BGE_FW_CMD_PAUSE); 1746 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 1747 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | BGE_RX_CPU_DRV_EVENT); 1748 1749 for (i = 0; i < 100; i++ ) { 1750 if (!(CSR_READ_4(sc, BGE_RX_CPU_EVENT) & 1751 BGE_RX_CPU_DRV_EVENT)) 1752 break; 1753 DELAY(10); 1754 } 1755 } 1756 } 1757 1758 static uint32_t 1759 bge_dma_swap_options(struct bge_softc *sc) 1760 { 1761 uint32_t dma_options; 1762 1763 dma_options = BGE_MODECTL_WORDSWAP_NONFRAME | 1764 BGE_MODECTL_BYTESWAP_DATA | BGE_MODECTL_WORDSWAP_DATA; 1765 #if BYTE_ORDER == BIG_ENDIAN 1766 dma_options |= BGE_MODECTL_BYTESWAP_NONFRAME; 1767 #endif 1768 return (dma_options); 1769 } 1770 1771 /* 1772 * Do endian, PCI and DMA initialization. 1773 */ 1774 static int 1775 bge_chipinit(struct bge_softc *sc) 1776 { 1777 uint32_t dma_rw_ctl, misc_ctl, mode_ctl; 1778 uint16_t val; 1779 int i; 1780 1781 /* Set endianness before we access any non-PCI registers. */ 1782 misc_ctl = BGE_INIT; 1783 if (sc->bge_flags & BGE_FLAG_TAGGED_STATUS) 1784 misc_ctl |= BGE_PCIMISCCTL_TAGGED_STATUS; 1785 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, misc_ctl, 4); 1786 1787 /* 1788 * Clear the MAC statistics block in the NIC's 1789 * internal memory. 1790 */ 1791 for (i = BGE_STATS_BLOCK; 1792 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t)) 1793 BGE_MEMWIN_WRITE(sc, i, 0); 1794 1795 for (i = BGE_STATUS_BLOCK; 1796 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t)) 1797 BGE_MEMWIN_WRITE(sc, i, 0); 1798 1799 if (sc->bge_chiprev == BGE_CHIPREV_5704_BX) { 1800 /* 1801 * Fix data corruption caused by non-qword write with WB. 1802 * Fix master abort in PCI mode. 1803 * Fix PCI latency timer. 1804 */ 1805 val = pci_read_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, 2); 1806 val |= (1 << 10) | (1 << 12) | (1 << 13); 1807 pci_write_config(sc->bge_dev, BGE_PCI_MSI_DATA + 2, val, 2); 1808 } 1809 1810 if (sc->bge_asicrev == BGE_ASICREV_BCM57765 || 1811 sc->bge_asicrev == BGE_ASICREV_BCM57766) { 1812 /* 1813 * For the 57766 and non Ax versions of 57765, bootcode 1814 * needs to setup the PCIE Fast Training Sequence (FTS) 1815 * value to prevent transmit hangs. 1816 */ 1817 if (sc->bge_chiprev != BGE_CHIPREV_57765_AX) { 1818 CSR_WRITE_4(sc, BGE_CPMU_PADRNG_CTL, 1819 CSR_READ_4(sc, BGE_CPMU_PADRNG_CTL) | 1820 BGE_CPMU_PADRNG_CTL_RDIV2); 1821 } 1822 } 1823 1824 /* 1825 * Set up the PCI DMA control register. 1826 */ 1827 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) | 1828 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7); 1829 if (sc->bge_flags & BGE_FLAG_PCIE) { 1830 if (sc->bge_mps >= 256) 1831 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1832 else 1833 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1834 } else if (sc->bge_flags & BGE_FLAG_PCIX) { 1835 if (BGE_IS_5714_FAMILY(sc)) { 1836 /* 256 bytes for read and write. */ 1837 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) | 1838 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2); 1839 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ? 1840 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL : 1841 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL; 1842 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 1843 /* 1844 * In the BCM5703, the DMA read watermark should 1845 * be set to less than or equal to the maximum 1846 * memory read byte count of the PCI-X command 1847 * register. 1848 */ 1849 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(4) | 1850 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1851 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1852 /* 1536 bytes for read, 384 bytes for write. */ 1853 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1854 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3); 1855 } else { 1856 /* 384 bytes for read and write. */ 1857 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(3) | 1858 BGE_PCIDMARWCTL_WR_WAT_SHIFT(3) | 1859 0x0F; 1860 } 1861 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1862 sc->bge_asicrev == BGE_ASICREV_BCM5704) { 1863 uint32_t tmp; 1864 1865 /* Set ONE_DMA_AT_ONCE for hardware workaround. */ 1866 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 1867 if (tmp == 6 || tmp == 7) 1868 dma_rw_ctl |= 1869 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL; 1870 1871 /* Set PCI-X DMA write workaround. */ 1872 dma_rw_ctl |= BGE_PCIDMARWCTL_ASRT_ALL_BE; 1873 } 1874 } else { 1875 /* Conventional PCI bus: 256 bytes for read and write. */ 1876 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(7) | 1877 BGE_PCIDMARWCTL_WR_WAT_SHIFT(7); 1878 1879 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 && 1880 sc->bge_asicrev != BGE_ASICREV_BCM5750) 1881 dma_rw_ctl |= 0x0F; 1882 } 1883 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 1884 sc->bge_asicrev == BGE_ASICREV_BCM5701) 1885 dma_rw_ctl |= BGE_PCIDMARWCTL_USE_MRM | 1886 BGE_PCIDMARWCTL_ASRT_ALL_BE; 1887 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 || 1888 sc->bge_asicrev == BGE_ASICREV_BCM5704) 1889 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA; 1890 if (BGE_IS_5717_PLUS(sc)) { 1891 dma_rw_ctl &= ~BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT; 1892 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 1893 dma_rw_ctl &= ~BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK; 1894 /* 1895 * Enable HW workaround for controllers that misinterpret 1896 * a status tag update and leave interrupts permanently 1897 * disabled. 1898 */ 1899 if (!BGE_IS_57765_PLUS(sc) && 1900 sc->bge_asicrev != BGE_ASICREV_BCM5717 && 1901 sc->bge_asicrev != BGE_ASICREV_BCM5762) 1902 dma_rw_ctl |= BGE_PCIDMARWCTL_TAGGED_STATUS_WA; 1903 } 1904 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4); 1905 1906 /* 1907 * Set up general mode register. 1908 */ 1909 mode_ctl = bge_dma_swap_options(sc); 1910 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 1911 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 1912 /* Retain Host-2-BMC settings written by APE firmware. */ 1913 mode_ctl |= CSR_READ_4(sc, BGE_MODE_CTL) & 1914 (BGE_MODECTL_BYTESWAP_B2HRX_DATA | 1915 BGE_MODECTL_WORDSWAP_B2HRX_DATA | 1916 BGE_MODECTL_B2HRX_ENABLE | BGE_MODECTL_HTX2B_ENABLE); 1917 } 1918 mode_ctl |= BGE_MODECTL_MAC_ATTN_INTR | BGE_MODECTL_HOST_SEND_BDS | 1919 BGE_MODECTL_TX_NO_PHDR_CSUM; 1920 1921 /* 1922 * BCM5701 B5 have a bug causing data corruption when using 1923 * 64-bit DMA reads, which can be terminated early and then 1924 * completed later as 32-bit accesses, in combination with 1925 * certain bridges. 1926 */ 1927 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 1928 sc->bge_chipid == BGE_CHIPID_BCM5701_B5) 1929 mode_ctl |= BGE_MODECTL_FORCE_PCI32; 1930 1931 /* 1932 * Tell the firmware the driver is running 1933 */ 1934 if (sc->bge_asf_mode & ASF_STACKUP) 1935 mode_ctl |= BGE_MODECTL_STACKUP; 1936 1937 CSR_WRITE_4(sc, BGE_MODE_CTL, mode_ctl); 1938 1939 /* 1940 * Disable memory write invalidate. Apparently it is not supported 1941 * properly by these devices. Also ensure that INTx isn't disabled, 1942 * as these chips need it even when using MSI. 1943 */ 1944 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1945 PCIM_CMD_INTxDIS | PCIM_CMD_MWIEN, 4); 1946 1947 /* Set the timer prescaler (always 66 MHz). */ 1948 CSR_WRITE_4(sc, BGE_MISC_CFG, BGE_32BITTIME_66MHZ); 1949 1950 /* XXX: The Linux tg3 driver does this at the start of brgphy_reset. */ 1951 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 1952 DELAY(40); /* XXX */ 1953 1954 /* Put PHY into ready state */ 1955 BGE_CLRBIT(sc, BGE_MISC_CFG, BGE_MISCCFG_EPHY_IDDQ); 1956 CSR_READ_4(sc, BGE_MISC_CFG); /* Flush */ 1957 DELAY(40); 1958 } 1959 1960 return (0); 1961 } 1962 1963 static int 1964 bge_blockinit(struct bge_softc *sc) 1965 { 1966 struct bge_rcb *rcb; 1967 bus_size_t vrcb; 1968 bge_hostaddr taddr; 1969 uint32_t dmactl, rdmareg, val; 1970 int i, limit; 1971 1972 /* 1973 * Initialize the memory window pointer register so that 1974 * we can access the first 32K of internal NIC RAM. This will 1975 * allow us to set up the TX send ring RCBs and the RX return 1976 * ring RCBs, plus other things which live in NIC memory. 1977 */ 1978 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1979 1980 /* Note: the BCM5704 has a smaller mbuf space than other chips. */ 1981 1982 if (!(BGE_IS_5705_PLUS(sc))) { 1983 /* Configure mbuf memory pool */ 1984 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1985 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) 1986 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000); 1987 else 1988 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1989 1990 /* Configure DMA resource pool */ 1991 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, 1992 BGE_DMA_DESCRIPTORS); 1993 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1994 } 1995 1996 /* Configure mbuf pool watermarks */ 1997 if (BGE_IS_5717_PLUS(sc)) { 1998 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 1999 if (sc->bge_ifp->if_mtu > ETHERMTU) { 2000 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x7e); 2001 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xea); 2002 } else { 2003 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x2a); 2004 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0xa0); 2005 } 2006 } else if (!BGE_IS_5705_PLUS(sc)) { 2007 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 2008 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 2009 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2010 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2011 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2012 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x04); 2013 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x10); 2014 } else { 2015 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0); 2016 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10); 2017 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 2018 } 2019 2020 /* Configure DMA resource watermarks */ 2021 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 2022 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 2023 2024 /* Enable buffer manager */ 2025 val = BGE_BMANMODE_ENABLE | BGE_BMANMODE_LOMBUF_ATTN; 2026 /* 2027 * Change the arbitration algorithm of TXMBUF read request to 2028 * round-robin instead of priority based for BCM5719. When 2029 * TXFIFO is almost empty, RDMA will hold its request until 2030 * TXFIFO is not almost empty. 2031 */ 2032 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2033 val |= BGE_BMANMODE_NO_TX_UNDERRUN; 2034 CSR_WRITE_4(sc, BGE_BMAN_MODE, val); 2035 2036 /* Poll for buffer manager start indication */ 2037 for (i = 0; i < BGE_TIMEOUT; i++) { 2038 DELAY(10); 2039 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 2040 break; 2041 } 2042 2043 if (i == BGE_TIMEOUT) { 2044 device_printf(sc->bge_dev, "buffer manager failed to start\n"); 2045 return (ENXIO); 2046 } 2047 2048 /* Enable flow-through queues */ 2049 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2050 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2051 2052 /* Wait until queue initialization is complete */ 2053 for (i = 0; i < BGE_TIMEOUT; i++) { 2054 DELAY(10); 2055 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 2056 break; 2057 } 2058 2059 if (i == BGE_TIMEOUT) { 2060 device_printf(sc->bge_dev, "flow-through queue init failed\n"); 2061 return (ENXIO); 2062 } 2063 2064 /* 2065 * Summary of rings supported by the controller: 2066 * 2067 * Standard Receive Producer Ring 2068 * - This ring is used to feed receive buffers for "standard" 2069 * sized frames (typically 1536 bytes) to the controller. 2070 * 2071 * Jumbo Receive Producer Ring 2072 * - This ring is used to feed receive buffers for jumbo sized 2073 * frames (i.e. anything bigger than the "standard" frames) 2074 * to the controller. 2075 * 2076 * Mini Receive Producer Ring 2077 * - This ring is used to feed receive buffers for "mini" 2078 * sized frames to the controller. 2079 * - This feature required external memory for the controller 2080 * but was never used in a production system. Should always 2081 * be disabled. 2082 * 2083 * Receive Return Ring 2084 * - After the controller has placed an incoming frame into a 2085 * receive buffer that buffer is moved into a receive return 2086 * ring. The driver is then responsible to passing the 2087 * buffer up to the stack. Many versions of the controller 2088 * support multiple RR rings. 2089 * 2090 * Send Ring 2091 * - This ring is used for outgoing frames. Many versions of 2092 * the controller support multiple send rings. 2093 */ 2094 2095 /* Initialize the standard receive producer ring control block. */ 2096 rcb = &sc->bge_ldata.bge_info.bge_std_rx_rcb; 2097 rcb->bge_hostaddr.bge_addr_lo = 2098 BGE_ADDR_LO(sc->bge_ldata.bge_rx_std_ring_paddr); 2099 rcb->bge_hostaddr.bge_addr_hi = 2100 BGE_ADDR_HI(sc->bge_ldata.bge_rx_std_ring_paddr); 2101 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 2102 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREREAD); 2103 if (BGE_IS_5717_PLUS(sc)) { 2104 /* 2105 * Bits 31-16: Programmable ring size (2048, 1024, 512, .., 32) 2106 * Bits 15-2 : Maximum RX frame size 2107 * Bit 1 : 1 = Ring Disabled, 0 = Ring ENabled 2108 * Bit 0 : Reserved 2109 */ 2110 rcb->bge_maxlen_flags = 2111 BGE_RCB_MAXLEN_FLAGS(512, BGE_MAX_FRAMELEN << 2); 2112 } else if (BGE_IS_5705_PLUS(sc)) { 2113 /* 2114 * Bits 31-16: Programmable ring size (512, 256, 128, 64, 32) 2115 * Bits 15-2 : Reserved (should be 0) 2116 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2117 * Bit 0 : Reserved 2118 */ 2119 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0); 2120 } else { 2121 /* 2122 * Ring size is always XXX entries 2123 * Bits 31-16: Maximum RX frame size 2124 * Bits 15-2 : Reserved (should be 0) 2125 * Bit 1 : 1 = Ring Disabled, 0 = Ring Enabled 2126 * Bit 0 : Reserved 2127 */ 2128 rcb->bge_maxlen_flags = 2129 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 2130 } 2131 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2132 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2133 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2134 rcb->bge_nicaddr = BGE_STD_RX_RINGS_5717; 2135 else 2136 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 2137 /* Write the standard receive producer ring control block. */ 2138 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 2139 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 2140 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 2141 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 2142 2143 /* Reset the standard receive producer ring producer index. */ 2144 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, 0); 2145 2146 /* 2147 * Initialize the jumbo RX producer ring control 2148 * block. We set the 'ring disabled' bit in the 2149 * flags field until we're actually ready to start 2150 * using this ring (i.e. once we set the MTU 2151 * high enough to require it). 2152 */ 2153 if (BGE_IS_JUMBO_CAPABLE(sc)) { 2154 rcb = &sc->bge_ldata.bge_info.bge_jumbo_rx_rcb; 2155 /* Get the jumbo receive producer ring RCB parameters. */ 2156 rcb->bge_hostaddr.bge_addr_lo = 2157 BGE_ADDR_LO(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2158 rcb->bge_hostaddr.bge_addr_hi = 2159 BGE_ADDR_HI(sc->bge_ldata.bge_rx_jumbo_ring_paddr); 2160 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2161 sc->bge_cdata.bge_rx_jumbo_ring_map, 2162 BUS_DMASYNC_PREREAD); 2163 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 2164 BGE_RCB_FLAG_USE_EXT_RX_BD | BGE_RCB_FLAG_RING_DISABLED); 2165 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2166 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2167 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2168 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS_5717; 2169 else 2170 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 2171 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 2172 rcb->bge_hostaddr.bge_addr_hi); 2173 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 2174 rcb->bge_hostaddr.bge_addr_lo); 2175 /* Program the jumbo receive producer ring RCB parameters. */ 2176 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, 2177 rcb->bge_maxlen_flags); 2178 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 2179 /* Reset the jumbo receive producer ring producer index. */ 2180 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 2181 } 2182 2183 /* Disable the mini receive producer ring RCB. */ 2184 if (BGE_IS_5700_FAMILY(sc)) { 2185 rcb = &sc->bge_ldata.bge_info.bge_mini_rx_rcb; 2186 rcb->bge_maxlen_flags = 2187 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 2188 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, 2189 rcb->bge_maxlen_flags); 2190 /* Reset the mini receive producer ring producer index. */ 2191 bge_writembx(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 2192 } 2193 2194 /* Choose de-pipeline mode for BCM5906 A0, A1 and A2. */ 2195 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 2196 if (sc->bge_chipid == BGE_CHIPID_BCM5906_A0 || 2197 sc->bge_chipid == BGE_CHIPID_BCM5906_A1 || 2198 sc->bge_chipid == BGE_CHIPID_BCM5906_A2) 2199 CSR_WRITE_4(sc, BGE_ISO_PKT_TX, 2200 (CSR_READ_4(sc, BGE_ISO_PKT_TX) & ~3) | 2); 2201 } 2202 /* 2203 * The BD ring replenish thresholds control how often the 2204 * hardware fetches new BD's from the producer rings in host 2205 * memory. Setting the value too low on a busy system can 2206 * starve the hardware and recue the throughpout. 2207 * 2208 * Set the BD ring replentish thresholds. The recommended 2209 * values are 1/8th the number of descriptors allocated to 2210 * each ring. 2211 * XXX The 5754 requires a lower threshold, so it might be a 2212 * requirement of all 575x family chips. The Linux driver sets 2213 * the lower threshold for all 5705 family chips as well, but there 2214 * are reports that it might not need to be so strict. 2215 * 2216 * XXX Linux does some extra fiddling here for the 5906 parts as 2217 * well. 2218 */ 2219 if (BGE_IS_5705_PLUS(sc)) 2220 val = 8; 2221 else 2222 val = BGE_STD_RX_RING_CNT / 8; 2223 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, val); 2224 if (BGE_IS_JUMBO_CAPABLE(sc)) 2225 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, 2226 BGE_JUMBO_RX_RING_CNT/8); 2227 if (BGE_IS_5717_PLUS(sc)) { 2228 CSR_WRITE_4(sc, BGE_STD_REPLENISH_LWM, 32); 2229 CSR_WRITE_4(sc, BGE_JMB_REPLENISH_LWM, 16); 2230 } 2231 2232 /* 2233 * Disable all send rings by setting the 'ring disabled' bit 2234 * in the flags field of all the TX send ring control blocks, 2235 * located in NIC memory. 2236 */ 2237 if (!BGE_IS_5705_PLUS(sc)) 2238 /* 5700 to 5704 had 16 send rings. */ 2239 limit = BGE_TX_RINGS_EXTSSRAM_MAX; 2240 else if (BGE_IS_57765_PLUS(sc) || 2241 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2242 limit = 2; 2243 else if (BGE_IS_5717_PLUS(sc)) 2244 limit = 4; 2245 else 2246 limit = 1; 2247 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2248 for (i = 0; i < limit; i++) { 2249 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2250 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED)); 2251 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2252 vrcb += sizeof(struct bge_rcb); 2253 } 2254 2255 /* Configure send ring RCB 0 (we use only the first ring) */ 2256 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB; 2257 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr); 2258 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2259 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2260 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2261 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2262 sc->bge_asicrev == BGE_ASICREV_BCM5720) 2263 RCB_WRITE_4(sc, vrcb, bge_nicaddr, BGE_SEND_RING_5717); 2264 else 2265 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 2266 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT)); 2267 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2268 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0)); 2269 2270 /* 2271 * Disable all receive return rings by setting the 2272 * 'ring diabled' bit in the flags field of all the receive 2273 * return ring control blocks, located in NIC memory. 2274 */ 2275 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 2276 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 2277 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2278 /* Should be 17, use 16 until we get an SRAM map. */ 2279 limit = 16; 2280 } else if (!BGE_IS_5705_PLUS(sc)) 2281 limit = BGE_RX_RINGS_MAX; 2282 else if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 2283 sc->bge_asicrev == BGE_ASICREV_BCM5762 || 2284 BGE_IS_57765_PLUS(sc)) 2285 limit = 4; 2286 else 2287 limit = 1; 2288 /* Disable all receive return rings. */ 2289 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2290 for (i = 0; i < limit; i++) { 2291 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0); 2292 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0); 2293 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2294 BGE_RCB_FLAG_RING_DISABLED); 2295 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2296 bge_writembx(sc, BGE_MBX_RX_CONS0_LO + 2297 (i * (sizeof(uint64_t))), 0); 2298 vrcb += sizeof(struct bge_rcb); 2299 } 2300 2301 /* 2302 * Set up receive return ring 0. Note that the NIC address 2303 * for RX return rings is 0x0. The return rings live entirely 2304 * within the host, so the nicaddr field in the RCB isn't used. 2305 */ 2306 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB; 2307 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr); 2308 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi); 2309 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo); 2310 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0); 2311 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags, 2312 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0)); 2313 2314 /* Set random backoff seed for TX */ 2315 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 2316 (IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] + 2317 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] + 2318 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5]) & 2319 BGE_TX_BACKOFF_SEED_MASK); 2320 2321 /* Set inter-packet gap */ 2322 val = 0x2620; 2323 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2324 sc->bge_asicrev == BGE_ASICREV_BCM5762) 2325 val |= CSR_READ_4(sc, BGE_TX_LENGTHS) & 2326 (BGE_TXLEN_JMB_FRM_LEN_MSK | BGE_TXLEN_CNT_DN_VAL_MSK); 2327 CSR_WRITE_4(sc, BGE_TX_LENGTHS, val); 2328 2329 /* 2330 * Specify which ring to use for packets that don't match 2331 * any RX rules. 2332 */ 2333 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 2334 2335 /* 2336 * Configure number of RX lists. One interrupt distribution 2337 * list, sixteen active lists, one bad frames class. 2338 */ 2339 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 2340 2341 /* Inialize RX list placement stats mask. */ 2342 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 2343 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 2344 2345 /* Disable host coalescing until we get it set up */ 2346 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 2347 2348 /* Poll to make sure it's shut down. */ 2349 for (i = 0; i < BGE_TIMEOUT; i++) { 2350 DELAY(10); 2351 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 2352 break; 2353 } 2354 2355 if (i == BGE_TIMEOUT) { 2356 device_printf(sc->bge_dev, 2357 "host coalescing engine failed to idle\n"); 2358 return (ENXIO); 2359 } 2360 2361 /* Set up host coalescing defaults */ 2362 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 2363 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 2364 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 2365 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 2366 if (!(BGE_IS_5705_PLUS(sc))) { 2367 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 2368 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 2369 } 2370 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 1); 2371 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 1); 2372 2373 /* Set up address of statistics block */ 2374 if (!(BGE_IS_5705_PLUS(sc))) { 2375 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 2376 BGE_ADDR_HI(sc->bge_ldata.bge_stats_paddr)); 2377 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 2378 BGE_ADDR_LO(sc->bge_ldata.bge_stats_paddr)); 2379 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 2380 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 2381 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 2382 } 2383 2384 /* Set up address of status block */ 2385 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 2386 BGE_ADDR_HI(sc->bge_ldata.bge_status_block_paddr)); 2387 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 2388 BGE_ADDR_LO(sc->bge_ldata.bge_status_block_paddr)); 2389 2390 /* Set up status block size. */ 2391 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2392 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) { 2393 val = BGE_STATBLKSZ_FULL; 2394 bzero(sc->bge_ldata.bge_status_block, BGE_STATUS_BLK_SZ); 2395 } else { 2396 val = BGE_STATBLKSZ_32BYTE; 2397 bzero(sc->bge_ldata.bge_status_block, 32); 2398 } 2399 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 2400 sc->bge_cdata.bge_status_map, 2401 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2402 2403 /* Turn on host coalescing state machine */ 2404 CSR_WRITE_4(sc, BGE_HCC_MODE, val | BGE_HCCMODE_ENABLE); 2405 2406 /* Turn on RX BD completion state machine and enable attentions */ 2407 CSR_WRITE_4(sc, BGE_RBDC_MODE, 2408 BGE_RBDCMODE_ENABLE | BGE_RBDCMODE_ATTN); 2409 2410 /* Turn on RX list placement state machine */ 2411 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2412 2413 /* Turn on RX list selector state machine. */ 2414 if (!(BGE_IS_5705_PLUS(sc))) 2415 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2416 2417 /* Turn on DMA, clear stats. */ 2418 val = BGE_MACMODE_TXDMA_ENB | BGE_MACMODE_RXDMA_ENB | 2419 BGE_MACMODE_RX_STATS_CLEAR | BGE_MACMODE_TX_STATS_CLEAR | 2420 BGE_MACMODE_RX_STATS_ENB | BGE_MACMODE_TX_STATS_ENB | 2421 BGE_MACMODE_FRMHDR_DMA_ENB; 2422 2423 if (sc->bge_flags & BGE_FLAG_TBI) 2424 val |= BGE_PORTMODE_TBI; 2425 else if (sc->bge_flags & BGE_FLAG_MII_SERDES) 2426 val |= BGE_PORTMODE_GMII; 2427 else 2428 val |= BGE_PORTMODE_MII; 2429 2430 /* Allow APE to send/receive frames. */ 2431 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 2432 val |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 2433 2434 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 2435 DELAY(40); 2436 2437 /* Set misc. local control, enable interrupts on attentions */ 2438 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 2439 2440 #ifdef notdef 2441 /* Assert GPIO pins for PHY reset */ 2442 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0 | 2443 BGE_MLC_MISCIO_OUT1 | BGE_MLC_MISCIO_OUT2); 2444 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0 | 2445 BGE_MLC_MISCIO_OUTEN1 | BGE_MLC_MISCIO_OUTEN2); 2446 #endif 2447 2448 /* Turn on DMA completion state machine */ 2449 if (!(BGE_IS_5705_PLUS(sc))) 2450 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2451 2452 val = BGE_WDMAMODE_ENABLE | BGE_WDMAMODE_ALL_ATTNS; 2453 2454 /* Enable host coalescing bug fix. */ 2455 if (BGE_IS_5755_PLUS(sc)) 2456 val |= BGE_WDMAMODE_STATUS_TAG_FIX; 2457 2458 /* Request larger DMA burst size to get better performance. */ 2459 if (sc->bge_asicrev == BGE_ASICREV_BCM5785) 2460 val |= BGE_WDMAMODE_BURST_ALL_DATA; 2461 2462 /* Turn on write DMA state machine */ 2463 CSR_WRITE_4(sc, BGE_WDMA_MODE, val); 2464 DELAY(40); 2465 2466 /* Turn on read DMA state machine */ 2467 val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS; 2468 2469 if (sc->bge_asicrev == BGE_ASICREV_BCM5717) 2470 val |= BGE_RDMAMODE_MULT_DMA_RD_DIS; 2471 2472 if (sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2473 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2474 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2475 val |= BGE_RDMAMODE_BD_SBD_CRPT_ATTN | 2476 BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN | 2477 BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN; 2478 if (sc->bge_flags & BGE_FLAG_PCIE) 2479 val |= BGE_RDMAMODE_FIFO_LONG_BURST; 2480 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 2481 val |= BGE_RDMAMODE_TSO4_ENABLE; 2482 if (sc->bge_flags & BGE_FLAG_TSO3 || 2483 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2484 sc->bge_asicrev == BGE_ASICREV_BCM57780) 2485 val |= BGE_RDMAMODE_TSO6_ENABLE; 2486 } 2487 2488 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 2489 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2490 val |= CSR_READ_4(sc, BGE_RDMA_MODE) & 2491 BGE_RDMAMODE_H2BNC_VLAN_DET; 2492 /* 2493 * Allow multiple outstanding read requests from 2494 * non-LSO read DMA engine. 2495 */ 2496 val &= ~BGE_RDMAMODE_MULT_DMA_RD_DIS; 2497 } 2498 2499 if (sc->bge_asicrev == BGE_ASICREV_BCM5761 || 2500 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 2501 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 2502 sc->bge_asicrev == BGE_ASICREV_BCM57780 || 2503 BGE_IS_5717_PLUS(sc) || BGE_IS_57765_PLUS(sc)) { 2504 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 2505 rdmareg = BGE_RDMA_RSRVCTRL_REG2; 2506 else 2507 rdmareg = BGE_RDMA_RSRVCTRL; 2508 dmactl = CSR_READ_4(sc, rdmareg); 2509 /* 2510 * Adjust tx margin to prevent TX data corruption and 2511 * fix internal FIFO overflow. 2512 */ 2513 if (sc->bge_chipid == BGE_CHIPID_BCM5719_A0 || 2514 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2515 dmactl &= ~(BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK | 2516 BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK | 2517 BGE_RDMA_RSRVCTRL_TXMRGN_MASK); 2518 dmactl |= BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K | 2519 BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K | 2520 BGE_RDMA_RSRVCTRL_TXMRGN_320B; 2521 } 2522 /* 2523 * Enable fix for read DMA FIFO overruns. 2524 * The fix is to limit the number of RX BDs 2525 * the hardware would fetch at a fime. 2526 */ 2527 CSR_WRITE_4(sc, rdmareg, dmactl | 2528 BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 2529 } 2530 2531 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) { 2532 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2533 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2534 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2535 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2536 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5720) { 2537 /* 2538 * Allow 4KB burst length reads for non-LSO frames. 2539 * Enable 512B burst length reads for buffer descriptors. 2540 */ 2541 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, 2542 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL) | 2543 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 | 2544 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2545 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5762) { 2546 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2, 2547 CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL_REG2) | 2548 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K | 2549 BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K); 2550 } 2551 2552 CSR_WRITE_4(sc, BGE_RDMA_MODE, val); 2553 DELAY(40); 2554 2555 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 2556 for (i = 0; i < BGE_NUM_RDMA_CHANNELS / 2; i++) { 2557 val = CSR_READ_4(sc, BGE_RDMA_LENGTH + i * 4); 2558 if ((val & 0xFFFF) > BGE_FRAMELEN) 2559 break; 2560 if (((val >> 16) & 0xFFFF) > BGE_FRAMELEN) 2561 break; 2562 } 2563 if (i != BGE_NUM_RDMA_CHANNELS / 2) { 2564 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 2565 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 2566 val |= BGE_RDMA_TX_LENGTH_WA_5719; 2567 else 2568 val |= BGE_RDMA_TX_LENGTH_WA_5720; 2569 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 2570 } 2571 } 2572 2573 /* Turn on RX data completion state machine */ 2574 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2575 2576 /* Turn on RX BD initiator state machine */ 2577 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2578 2579 /* Turn on RX data and RX BD initiator state machine */ 2580 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 2581 2582 /* Turn on Mbuf cluster free state machine */ 2583 if (!(BGE_IS_5705_PLUS(sc))) 2584 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2585 2586 /* Turn on send BD completion state machine */ 2587 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2588 2589 /* Turn on send data completion state machine */ 2590 val = BGE_SDCMODE_ENABLE; 2591 if (sc->bge_asicrev == BGE_ASICREV_BCM5761) 2592 val |= BGE_SDCMODE_CDELAY; 2593 CSR_WRITE_4(sc, BGE_SDC_MODE, val); 2594 2595 /* Turn on send data initiator state machine */ 2596 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) 2597 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE | 2598 BGE_SDIMODE_HW_LSO_PRE_DMA); 2599 else 2600 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2601 2602 /* Turn on send BD initiator state machine */ 2603 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2604 2605 /* Turn on send BD selector state machine */ 2606 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2607 2608 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 2609 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 2610 BGE_SDISTATSCTL_ENABLE | BGE_SDISTATSCTL_FASTER); 2611 2612 /* ack/clear link change events */ 2613 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2614 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2615 BGE_MACSTAT_LINK_CHANGED); 2616 CSR_WRITE_4(sc, BGE_MI_STS, 0); 2617 2618 /* 2619 * Enable attention when the link has changed state for 2620 * devices that use auto polling. 2621 */ 2622 if (sc->bge_flags & BGE_FLAG_TBI) { 2623 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 2624 } else { 2625 if (sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) { 2626 CSR_WRITE_4(sc, BGE_MI_MODE, sc->bge_mi_mode); 2627 DELAY(80); 2628 } 2629 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2630 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) 2631 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2632 BGE_EVTENB_MI_INTERRUPT); 2633 } 2634 2635 /* 2636 * Clear any pending link state attention. 2637 * Otherwise some link state change events may be lost until attention 2638 * is cleared by bge_intr() -> bge_link_upd() sequence. 2639 * It's not necessary on newer BCM chips - perhaps enabling link 2640 * state change attentions implies clearing pending attention. 2641 */ 2642 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 2643 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 2644 BGE_MACSTAT_LINK_CHANGED); 2645 2646 /* Enable link state change attentions. */ 2647 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 2648 2649 return (0); 2650 } 2651 2652 static const struct bge_revision * 2653 bge_lookup_rev(uint32_t chipid) 2654 { 2655 const struct bge_revision *br; 2656 2657 for (br = bge_revisions; br->br_name != NULL; br++) { 2658 if (br->br_chipid == chipid) 2659 return (br); 2660 } 2661 2662 for (br = bge_majorrevs; br->br_name != NULL; br++) { 2663 if (br->br_chipid == BGE_ASICREV(chipid)) 2664 return (br); 2665 } 2666 2667 return (NULL); 2668 } 2669 2670 static const struct bge_vendor * 2671 bge_lookup_vendor(uint16_t vid) 2672 { 2673 const struct bge_vendor *v; 2674 2675 for (v = bge_vendors; v->v_name != NULL; v++) 2676 if (v->v_id == vid) 2677 return (v); 2678 2679 return (NULL); 2680 } 2681 2682 static uint32_t 2683 bge_chipid(device_t dev) 2684 { 2685 uint32_t id; 2686 2687 id = pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 2688 BGE_PCIMISCCTL_ASICREV_SHIFT; 2689 if (BGE_ASICREV(id) == BGE_ASICREV_USE_PRODID_REG) { 2690 /* 2691 * Find the ASCI revision. Different chips use different 2692 * registers. 2693 */ 2694 switch (pci_get_device(dev)) { 2695 case BCOM_DEVICEID_BCM5717: 2696 case BCOM_DEVICEID_BCM5718: 2697 case BCOM_DEVICEID_BCM5719: 2698 case BCOM_DEVICEID_BCM5720: 2699 case BCOM_DEVICEID_BCM5725: 2700 case BCOM_DEVICEID_BCM5727: 2701 case BCOM_DEVICEID_BCM5762: 2702 case BCOM_DEVICEID_BCM57764: 2703 case BCOM_DEVICEID_BCM57767: 2704 case BCOM_DEVICEID_BCM57787: 2705 id = pci_read_config(dev, 2706 BGE_PCI_GEN2_PRODID_ASICREV, 4); 2707 break; 2708 case BCOM_DEVICEID_BCM57761: 2709 case BCOM_DEVICEID_BCM57762: 2710 case BCOM_DEVICEID_BCM57765: 2711 case BCOM_DEVICEID_BCM57766: 2712 case BCOM_DEVICEID_BCM57781: 2713 case BCOM_DEVICEID_BCM57782: 2714 case BCOM_DEVICEID_BCM57785: 2715 case BCOM_DEVICEID_BCM57786: 2716 case BCOM_DEVICEID_BCM57791: 2717 case BCOM_DEVICEID_BCM57795: 2718 id = pci_read_config(dev, 2719 BGE_PCI_GEN15_PRODID_ASICREV, 4); 2720 break; 2721 default: 2722 id = pci_read_config(dev, BGE_PCI_PRODID_ASICREV, 4); 2723 } 2724 } 2725 return (id); 2726 } 2727 2728 /* 2729 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 2730 * against our list and return its name if we find a match. 2731 * 2732 * Note that since the Broadcom controller contains VPD support, we 2733 * try to get the device name string from the controller itself instead 2734 * of the compiled-in string. It guarantees we'll always announce the 2735 * right product name. We fall back to the compiled-in string when 2736 * VPD is unavailable or corrupt. 2737 */ 2738 static int 2739 bge_probe(device_t dev) 2740 { 2741 char buf[96]; 2742 char model[64]; 2743 const struct bge_revision *br; 2744 const char *pname; 2745 struct bge_softc *sc; 2746 const struct bge_type *t = bge_devs; 2747 const struct bge_vendor *v; 2748 uint32_t id; 2749 uint16_t did, vid; 2750 2751 sc = device_get_softc(dev); 2752 sc->bge_dev = dev; 2753 vid = pci_get_vendor(dev); 2754 did = pci_get_device(dev); 2755 while(t->bge_vid != 0) { 2756 if ((vid == t->bge_vid) && (did == t->bge_did)) { 2757 id = bge_chipid(dev); 2758 br = bge_lookup_rev(id); 2759 if (bge_has_eaddr(sc) && 2760 pci_get_vpd_ident(dev, &pname) == 0) 2761 snprintf(model, sizeof(model), "%s", pname); 2762 else { 2763 v = bge_lookup_vendor(vid); 2764 snprintf(model, sizeof(model), "%s %s", 2765 v != NULL ? v->v_name : "Unknown", 2766 br != NULL ? br->br_name : 2767 "NetXtreme/NetLink Ethernet Controller"); 2768 } 2769 snprintf(buf, sizeof(buf), "%s, %sASIC rev. %#08x", 2770 model, br != NULL ? "" : "unknown ", id); 2771 device_set_desc_copy(dev, buf); 2772 return (BUS_PROBE_DEFAULT); 2773 } 2774 t++; 2775 } 2776 2777 return (ENXIO); 2778 } 2779 2780 static void 2781 bge_dma_free(struct bge_softc *sc) 2782 { 2783 int i; 2784 2785 /* Destroy DMA maps for RX buffers. */ 2786 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 2787 if (sc->bge_cdata.bge_rx_std_dmamap[i]) 2788 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2789 sc->bge_cdata.bge_rx_std_dmamap[i]); 2790 } 2791 if (sc->bge_cdata.bge_rx_std_sparemap) 2792 bus_dmamap_destroy(sc->bge_cdata.bge_rx_mtag, 2793 sc->bge_cdata.bge_rx_std_sparemap); 2794 2795 /* Destroy DMA maps for jumbo RX buffers. */ 2796 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 2797 if (sc->bge_cdata.bge_rx_jumbo_dmamap[i]) 2798 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2799 sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 2800 } 2801 if (sc->bge_cdata.bge_rx_jumbo_sparemap) 2802 bus_dmamap_destroy(sc->bge_cdata.bge_mtag_jumbo, 2803 sc->bge_cdata.bge_rx_jumbo_sparemap); 2804 2805 /* Destroy DMA maps for TX buffers. */ 2806 for (i = 0; i < BGE_TX_RING_CNT; i++) { 2807 if (sc->bge_cdata.bge_tx_dmamap[i]) 2808 bus_dmamap_destroy(sc->bge_cdata.bge_tx_mtag, 2809 sc->bge_cdata.bge_tx_dmamap[i]); 2810 } 2811 2812 if (sc->bge_cdata.bge_rx_mtag) 2813 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_mtag); 2814 if (sc->bge_cdata.bge_mtag_jumbo) 2815 bus_dma_tag_destroy(sc->bge_cdata.bge_mtag_jumbo); 2816 if (sc->bge_cdata.bge_tx_mtag) 2817 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_mtag); 2818 2819 /* Destroy standard RX ring. */ 2820 if (sc->bge_ldata.bge_rx_std_ring_paddr) 2821 bus_dmamap_unload(sc->bge_cdata.bge_rx_std_ring_tag, 2822 sc->bge_cdata.bge_rx_std_ring_map); 2823 if (sc->bge_ldata.bge_rx_std_ring) 2824 bus_dmamem_free(sc->bge_cdata.bge_rx_std_ring_tag, 2825 sc->bge_ldata.bge_rx_std_ring, 2826 sc->bge_cdata.bge_rx_std_ring_map); 2827 2828 if (sc->bge_cdata.bge_rx_std_ring_tag) 2829 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_std_ring_tag); 2830 2831 /* Destroy jumbo RX ring. */ 2832 if (sc->bge_ldata.bge_rx_jumbo_ring_paddr) 2833 bus_dmamap_unload(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2834 sc->bge_cdata.bge_rx_jumbo_ring_map); 2835 2836 if (sc->bge_ldata.bge_rx_jumbo_ring) 2837 bus_dmamem_free(sc->bge_cdata.bge_rx_jumbo_ring_tag, 2838 sc->bge_ldata.bge_rx_jumbo_ring, 2839 sc->bge_cdata.bge_rx_jumbo_ring_map); 2840 2841 if (sc->bge_cdata.bge_rx_jumbo_ring_tag) 2842 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_jumbo_ring_tag); 2843 2844 /* Destroy RX return ring. */ 2845 if (sc->bge_ldata.bge_rx_return_ring_paddr) 2846 bus_dmamap_unload(sc->bge_cdata.bge_rx_return_ring_tag, 2847 sc->bge_cdata.bge_rx_return_ring_map); 2848 2849 if (sc->bge_ldata.bge_rx_return_ring) 2850 bus_dmamem_free(sc->bge_cdata.bge_rx_return_ring_tag, 2851 sc->bge_ldata.bge_rx_return_ring, 2852 sc->bge_cdata.bge_rx_return_ring_map); 2853 2854 if (sc->bge_cdata.bge_rx_return_ring_tag) 2855 bus_dma_tag_destroy(sc->bge_cdata.bge_rx_return_ring_tag); 2856 2857 /* Destroy TX ring. */ 2858 if (sc->bge_ldata.bge_tx_ring_paddr) 2859 bus_dmamap_unload(sc->bge_cdata.bge_tx_ring_tag, 2860 sc->bge_cdata.bge_tx_ring_map); 2861 2862 if (sc->bge_ldata.bge_tx_ring) 2863 bus_dmamem_free(sc->bge_cdata.bge_tx_ring_tag, 2864 sc->bge_ldata.bge_tx_ring, 2865 sc->bge_cdata.bge_tx_ring_map); 2866 2867 if (sc->bge_cdata.bge_tx_ring_tag) 2868 bus_dma_tag_destroy(sc->bge_cdata.bge_tx_ring_tag); 2869 2870 /* Destroy status block. */ 2871 if (sc->bge_ldata.bge_status_block_paddr) 2872 bus_dmamap_unload(sc->bge_cdata.bge_status_tag, 2873 sc->bge_cdata.bge_status_map); 2874 2875 if (sc->bge_ldata.bge_status_block) 2876 bus_dmamem_free(sc->bge_cdata.bge_status_tag, 2877 sc->bge_ldata.bge_status_block, 2878 sc->bge_cdata.bge_status_map); 2879 2880 if (sc->bge_cdata.bge_status_tag) 2881 bus_dma_tag_destroy(sc->bge_cdata.bge_status_tag); 2882 2883 /* Destroy statistics block. */ 2884 if (sc->bge_ldata.bge_stats_paddr) 2885 bus_dmamap_unload(sc->bge_cdata.bge_stats_tag, 2886 sc->bge_cdata.bge_stats_map); 2887 2888 if (sc->bge_ldata.bge_stats) 2889 bus_dmamem_free(sc->bge_cdata.bge_stats_tag, 2890 sc->bge_ldata.bge_stats, 2891 sc->bge_cdata.bge_stats_map); 2892 2893 if (sc->bge_cdata.bge_stats_tag) 2894 bus_dma_tag_destroy(sc->bge_cdata.bge_stats_tag); 2895 2896 if (sc->bge_cdata.bge_buffer_tag) 2897 bus_dma_tag_destroy(sc->bge_cdata.bge_buffer_tag); 2898 2899 /* Destroy the parent tag. */ 2900 if (sc->bge_cdata.bge_parent_tag) 2901 bus_dma_tag_destroy(sc->bge_cdata.bge_parent_tag); 2902 } 2903 2904 static int 2905 bge_dma_ring_alloc(struct bge_softc *sc, bus_size_t alignment, 2906 bus_size_t maxsize, bus_dma_tag_t *tag, uint8_t **ring, bus_dmamap_t *map, 2907 bus_addr_t *paddr, const char *msg) 2908 { 2909 struct bge_dmamap_arg ctx; 2910 int error; 2911 2912 error = bus_dma_tag_create(sc->bge_cdata.bge_parent_tag, 2913 alignment, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 2914 NULL, maxsize, 1, maxsize, 0, NULL, NULL, tag); 2915 if (error != 0) { 2916 device_printf(sc->bge_dev, 2917 "could not create %s dma tag\n", msg); 2918 return (ENOMEM); 2919 } 2920 /* Allocate DMA'able memory for ring. */ 2921 error = bus_dmamem_alloc(*tag, (void **)ring, 2922 BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, map); 2923 if (error != 0) { 2924 device_printf(sc->bge_dev, 2925 "could not allocate DMA'able memory for %s\n", msg); 2926 return (ENOMEM); 2927 } 2928 /* Load the address of the ring. */ 2929 ctx.bge_busaddr = 0; 2930 error = bus_dmamap_load(*tag, *map, *ring, maxsize, bge_dma_map_addr, 2931 &ctx, BUS_DMA_NOWAIT); 2932 if (error != 0) { 2933 device_printf(sc->bge_dev, 2934 "could not load DMA'able memory for %s\n", msg); 2935 return (ENOMEM); 2936 } 2937 *paddr = ctx.bge_busaddr; 2938 return (0); 2939 } 2940 2941 static int 2942 bge_dma_alloc(struct bge_softc *sc) 2943 { 2944 bus_addr_t lowaddr; 2945 bus_size_t rxmaxsegsz, sbsz, txsegsz, txmaxsegsz; 2946 int i, error; 2947 2948 lowaddr = BUS_SPACE_MAXADDR; 2949 if ((sc->bge_flags & BGE_FLAG_40BIT_BUG) != 0) 2950 lowaddr = BGE_DMA_MAXADDR; 2951 /* 2952 * Allocate the parent bus DMA tag appropriate for PCI. 2953 */ 2954 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 2955 1, 0, lowaddr, BUS_SPACE_MAXADDR, NULL, 2956 NULL, BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 2957 0, NULL, NULL, &sc->bge_cdata.bge_parent_tag); 2958 if (error != 0) { 2959 device_printf(sc->bge_dev, 2960 "could not allocate parent dma tag\n"); 2961 return (ENOMEM); 2962 } 2963 2964 /* Create tag for standard RX ring. */ 2965 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STD_RX_RING_SZ, 2966 &sc->bge_cdata.bge_rx_std_ring_tag, 2967 (uint8_t **)&sc->bge_ldata.bge_rx_std_ring, 2968 &sc->bge_cdata.bge_rx_std_ring_map, 2969 &sc->bge_ldata.bge_rx_std_ring_paddr, "RX ring"); 2970 if (error) 2971 return (error); 2972 2973 /* Create tag for RX return ring. */ 2974 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_RX_RTN_RING_SZ(sc), 2975 &sc->bge_cdata.bge_rx_return_ring_tag, 2976 (uint8_t **)&sc->bge_ldata.bge_rx_return_ring, 2977 &sc->bge_cdata.bge_rx_return_ring_map, 2978 &sc->bge_ldata.bge_rx_return_ring_paddr, "RX return ring"); 2979 if (error) 2980 return (error); 2981 2982 /* Create tag for TX ring. */ 2983 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_TX_RING_SZ, 2984 &sc->bge_cdata.bge_tx_ring_tag, 2985 (uint8_t **)&sc->bge_ldata.bge_tx_ring, 2986 &sc->bge_cdata.bge_tx_ring_map, 2987 &sc->bge_ldata.bge_tx_ring_paddr, "TX ring"); 2988 if (error) 2989 return (error); 2990 2991 /* 2992 * Create tag for status block. 2993 * Because we only use single Tx/Rx/Rx return ring, use 2994 * minimum status block size except BCM5700 AX/BX which 2995 * seems to want to see full status block size regardless 2996 * of configured number of ring. 2997 */ 2998 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 2999 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 3000 sbsz = BGE_STATUS_BLK_SZ; 3001 else 3002 sbsz = 32; 3003 error = bge_dma_ring_alloc(sc, PAGE_SIZE, sbsz, 3004 &sc->bge_cdata.bge_status_tag, 3005 (uint8_t **)&sc->bge_ldata.bge_status_block, 3006 &sc->bge_cdata.bge_status_map, 3007 &sc->bge_ldata.bge_status_block_paddr, "status block"); 3008 if (error) 3009 return (error); 3010 3011 /* Create tag for statistics block. */ 3012 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_STATS_SZ, 3013 &sc->bge_cdata.bge_stats_tag, 3014 (uint8_t **)&sc->bge_ldata.bge_stats, 3015 &sc->bge_cdata.bge_stats_map, 3016 &sc->bge_ldata.bge_stats_paddr, "statistics block"); 3017 if (error) 3018 return (error); 3019 3020 /* Create tag for jumbo RX ring. */ 3021 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3022 error = bge_dma_ring_alloc(sc, PAGE_SIZE, BGE_JUMBO_RX_RING_SZ, 3023 &sc->bge_cdata.bge_rx_jumbo_ring_tag, 3024 (uint8_t **)&sc->bge_ldata.bge_rx_jumbo_ring, 3025 &sc->bge_cdata.bge_rx_jumbo_ring_map, 3026 &sc->bge_ldata.bge_rx_jumbo_ring_paddr, "jumbo RX ring"); 3027 if (error) 3028 return (error); 3029 } 3030 3031 /* Create parent tag for buffers. */ 3032 if ((sc->bge_flags & BGE_FLAG_4G_BNDRY_BUG) != 0) { 3033 /* 3034 * XXX 3035 * watchdog timeout issue was observed on BCM5704 which 3036 * lives behind PCI-X bridge(e.g AMD 8131 PCI-X bridge). 3037 * Both limiting DMA address space to 32bits and flushing 3038 * mailbox write seem to address the issue. 3039 */ 3040 if (sc->bge_pcixcap != 0) 3041 lowaddr = BUS_SPACE_MAXADDR_32BIT; 3042 } 3043 error = bus_dma_tag_create(bus_get_dma_tag(sc->bge_dev), 1, 0, lowaddr, 3044 BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE_32BIT, 0, 3045 BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL, 3046 &sc->bge_cdata.bge_buffer_tag); 3047 if (error != 0) { 3048 device_printf(sc->bge_dev, 3049 "could not allocate buffer dma tag\n"); 3050 return (ENOMEM); 3051 } 3052 /* Create tag for Tx mbufs. */ 3053 if (sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) { 3054 txsegsz = BGE_TSOSEG_SZ; 3055 txmaxsegsz = 65535 + sizeof(struct ether_vlan_header); 3056 } else { 3057 txsegsz = MCLBYTES; 3058 txmaxsegsz = MCLBYTES * BGE_NSEG_NEW; 3059 } 3060 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 3061 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 3062 txmaxsegsz, BGE_NSEG_NEW, txsegsz, 0, NULL, NULL, 3063 &sc->bge_cdata.bge_tx_mtag); 3064 3065 if (error) { 3066 device_printf(sc->bge_dev, "could not allocate TX dma tag\n"); 3067 return (ENOMEM); 3068 } 3069 3070 /* Create tag for Rx mbufs. */ 3071 if (sc->bge_flags & BGE_FLAG_JUMBO_STD) 3072 rxmaxsegsz = MJUM9BYTES; 3073 else 3074 rxmaxsegsz = MCLBYTES; 3075 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 1, 0, 3076 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, rxmaxsegsz, 1, 3077 rxmaxsegsz, 0, NULL, NULL, &sc->bge_cdata.bge_rx_mtag); 3078 3079 if (error) { 3080 device_printf(sc->bge_dev, "could not allocate RX dma tag\n"); 3081 return (ENOMEM); 3082 } 3083 3084 /* Create DMA maps for RX buffers. */ 3085 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3086 &sc->bge_cdata.bge_rx_std_sparemap); 3087 if (error) { 3088 device_printf(sc->bge_dev, 3089 "can't create spare DMA map for RX\n"); 3090 return (ENOMEM); 3091 } 3092 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 3093 error = bus_dmamap_create(sc->bge_cdata.bge_rx_mtag, 0, 3094 &sc->bge_cdata.bge_rx_std_dmamap[i]); 3095 if (error) { 3096 device_printf(sc->bge_dev, 3097 "can't create DMA map for RX\n"); 3098 return (ENOMEM); 3099 } 3100 } 3101 3102 /* Create DMA maps for TX buffers. */ 3103 for (i = 0; i < BGE_TX_RING_CNT; i++) { 3104 error = bus_dmamap_create(sc->bge_cdata.bge_tx_mtag, 0, 3105 &sc->bge_cdata.bge_tx_dmamap[i]); 3106 if (error) { 3107 device_printf(sc->bge_dev, 3108 "can't create DMA map for TX\n"); 3109 return (ENOMEM); 3110 } 3111 } 3112 3113 /* Create tags for jumbo RX buffers. */ 3114 if (BGE_IS_JUMBO_CAPABLE(sc)) { 3115 error = bus_dma_tag_create(sc->bge_cdata.bge_buffer_tag, 3116 1, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 3117 NULL, MJUM9BYTES, BGE_NSEG_JUMBO, PAGE_SIZE, 3118 0, NULL, NULL, &sc->bge_cdata.bge_mtag_jumbo); 3119 if (error) { 3120 device_printf(sc->bge_dev, 3121 "could not allocate jumbo dma tag\n"); 3122 return (ENOMEM); 3123 } 3124 /* Create DMA maps for jumbo RX buffers. */ 3125 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3126 0, &sc->bge_cdata.bge_rx_jumbo_sparemap); 3127 if (error) { 3128 device_printf(sc->bge_dev, 3129 "can't create spare DMA map for jumbo RX\n"); 3130 return (ENOMEM); 3131 } 3132 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 3133 error = bus_dmamap_create(sc->bge_cdata.bge_mtag_jumbo, 3134 0, &sc->bge_cdata.bge_rx_jumbo_dmamap[i]); 3135 if (error) { 3136 device_printf(sc->bge_dev, 3137 "can't create DMA map for jumbo RX\n"); 3138 return (ENOMEM); 3139 } 3140 } 3141 } 3142 3143 return (0); 3144 } 3145 3146 /* 3147 * Return true if this device has more than one port. 3148 */ 3149 static int 3150 bge_has_multiple_ports(struct bge_softc *sc) 3151 { 3152 device_t dev = sc->bge_dev; 3153 u_int b, d, f, fscan, s; 3154 3155 d = pci_get_domain(dev); 3156 b = pci_get_bus(dev); 3157 s = pci_get_slot(dev); 3158 f = pci_get_function(dev); 3159 for (fscan = 0; fscan <= PCI_FUNCMAX; fscan++) 3160 if (fscan != f && pci_find_dbsf(d, b, s, fscan) != NULL) 3161 return (1); 3162 return (0); 3163 } 3164 3165 /* 3166 * Return true if MSI can be used with this device. 3167 */ 3168 static int 3169 bge_can_use_msi(struct bge_softc *sc) 3170 { 3171 int can_use_msi = 0; 3172 3173 if (sc->bge_msi == 0) 3174 return (0); 3175 3176 /* Disable MSI for polling(4). */ 3177 #ifdef DEVICE_POLLING 3178 return (0); 3179 #endif 3180 switch (sc->bge_asicrev) { 3181 case BGE_ASICREV_BCM5714_A0: 3182 case BGE_ASICREV_BCM5714: 3183 /* 3184 * Apparently, MSI doesn't work when these chips are 3185 * configured in single-port mode. 3186 */ 3187 if (bge_has_multiple_ports(sc)) 3188 can_use_msi = 1; 3189 break; 3190 case BGE_ASICREV_BCM5750: 3191 if (sc->bge_chiprev != BGE_CHIPREV_5750_AX && 3192 sc->bge_chiprev != BGE_CHIPREV_5750_BX) 3193 can_use_msi = 1; 3194 break; 3195 default: 3196 if (BGE_IS_575X_PLUS(sc)) 3197 can_use_msi = 1; 3198 } 3199 return (can_use_msi); 3200 } 3201 3202 static int 3203 bge_mbox_reorder(struct bge_softc *sc) 3204 { 3205 /* Lists of PCI bridges that are known to reorder mailbox writes. */ 3206 static const struct mbox_reorder { 3207 const uint16_t vendor; 3208 const uint16_t device; 3209 const char *desc; 3210 } mbox_reorder_lists[] = { 3211 { 0x1022, 0x7450, "AMD-8131 PCI-X Bridge" }, 3212 }; 3213 devclass_t pci, pcib; 3214 device_t bus, dev; 3215 int i; 3216 3217 pci = devclass_find("pci"); 3218 pcib = devclass_find("pcib"); 3219 dev = sc->bge_dev; 3220 bus = device_get_parent(dev); 3221 for (;;) { 3222 dev = device_get_parent(bus); 3223 bus = device_get_parent(dev); 3224 if (device_get_devclass(dev) != pcib) 3225 break; 3226 for (i = 0; i < nitems(mbox_reorder_lists); i++) { 3227 if (pci_get_vendor(dev) == 3228 mbox_reorder_lists[i].vendor && 3229 pci_get_device(dev) == 3230 mbox_reorder_lists[i].device) { 3231 device_printf(sc->bge_dev, 3232 "enabling MBOX workaround for %s\n", 3233 mbox_reorder_lists[i].desc); 3234 return (1); 3235 } 3236 } 3237 if (device_get_devclass(bus) != pci) 3238 break; 3239 } 3240 return (0); 3241 } 3242 3243 static void 3244 bge_devinfo(struct bge_softc *sc) 3245 { 3246 uint32_t cfg, clk; 3247 3248 device_printf(sc->bge_dev, 3249 "CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; ", 3250 sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev); 3251 if (sc->bge_flags & BGE_FLAG_PCIE) 3252 printf("PCI-E\n"); 3253 else if (sc->bge_flags & BGE_FLAG_PCIX) { 3254 printf("PCI-X "); 3255 cfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3256 if (cfg == BGE_MISCCFG_BOARD_ID_5704CIOBE) 3257 clk = 133; 3258 else { 3259 clk = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1F; 3260 switch (clk) { 3261 case 0: 3262 clk = 33; 3263 break; 3264 case 2: 3265 clk = 50; 3266 break; 3267 case 4: 3268 clk = 66; 3269 break; 3270 case 6: 3271 clk = 100; 3272 break; 3273 case 7: 3274 clk = 133; 3275 break; 3276 } 3277 } 3278 printf("%u MHz\n", clk); 3279 } else { 3280 if (sc->bge_pcixcap != 0) 3281 printf("PCI on PCI-X "); 3282 else 3283 printf("PCI "); 3284 cfg = pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4); 3285 if (cfg & BGE_PCISTATE_PCI_BUSSPEED) 3286 clk = 66; 3287 else 3288 clk = 33; 3289 if (cfg & BGE_PCISTATE_32BIT_BUS) 3290 printf("%u MHz; 32bit\n", clk); 3291 else 3292 printf("%u MHz; 64bit\n", clk); 3293 } 3294 } 3295 3296 static int 3297 bge_attach(device_t dev) 3298 { 3299 struct ifnet *ifp; 3300 struct bge_softc *sc; 3301 uint32_t hwcfg = 0, misccfg, pcistate; 3302 u_char eaddr[ETHER_ADDR_LEN]; 3303 int capmask, error, reg, rid, trys; 3304 3305 sc = device_get_softc(dev); 3306 sc->bge_dev = dev; 3307 3308 BGE_LOCK_INIT(sc, device_get_nameunit(dev)); 3309 TASK_INIT(&sc->bge_intr_task, 0, bge_intr_task, sc); 3310 callout_init_mtx(&sc->bge_stat_ch, &sc->bge_mtx, 0); 3311 3312 pci_enable_busmaster(dev); 3313 3314 /* 3315 * Allocate control/status registers. 3316 */ 3317 rid = PCIR_BAR(0); 3318 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3319 RF_ACTIVE); 3320 3321 if (sc->bge_res == NULL) { 3322 device_printf (sc->bge_dev, "couldn't map BAR0 memory\n"); 3323 error = ENXIO; 3324 goto fail; 3325 } 3326 3327 /* Save various chip information. */ 3328 sc->bge_func_addr = pci_get_function(dev); 3329 sc->bge_chipid = bge_chipid(dev); 3330 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid); 3331 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid); 3332 3333 /* Set default PHY address. */ 3334 sc->bge_phy_addr = 1; 3335 /* 3336 * PHY address mapping for various devices. 3337 * 3338 * | F0 Cu | F0 Sr | F1 Cu | F1 Sr | 3339 * ---------+-------+-------+-------+-------+ 3340 * BCM57XX | 1 | X | X | X | 3341 * BCM5704 | 1 | X | 1 | X | 3342 * BCM5717 | 1 | 8 | 2 | 9 | 3343 * BCM5719 | 1 | 8 | 2 | 9 | 3344 * BCM5720 | 1 | 8 | 2 | 9 | 3345 * 3346 * | F2 Cu | F2 Sr | F3 Cu | F3 Sr | 3347 * ---------+-------+-------+-------+-------+ 3348 * BCM57XX | X | X | X | X | 3349 * BCM5704 | X | X | X | X | 3350 * BCM5717 | X | X | X | X | 3351 * BCM5719 | 3 | 10 | 4 | 11 | 3352 * BCM5720 | X | X | X | X | 3353 * 3354 * Other addresses may respond but they are not 3355 * IEEE compliant PHYs and should be ignored. 3356 */ 3357 if (sc->bge_asicrev == BGE_ASICREV_BCM5717 || 3358 sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3359 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3360 if (sc->bge_chipid != BGE_CHIPID_BCM5717_A0) { 3361 if (CSR_READ_4(sc, BGE_SGDIG_STS) & 3362 BGE_SGDIGSTS_IS_SERDES) 3363 sc->bge_phy_addr = sc->bge_func_addr + 8; 3364 else 3365 sc->bge_phy_addr = sc->bge_func_addr + 1; 3366 } else { 3367 if (CSR_READ_4(sc, BGE_CPMU_PHY_STRAP) & 3368 BGE_CPMU_PHY_STRAP_IS_SERDES) 3369 sc->bge_phy_addr = sc->bge_func_addr + 8; 3370 else 3371 sc->bge_phy_addr = sc->bge_func_addr + 1; 3372 } 3373 } 3374 3375 if (bge_has_eaddr(sc)) 3376 sc->bge_flags |= BGE_FLAG_EADDR; 3377 3378 /* Save chipset family. */ 3379 switch (sc->bge_asicrev) { 3380 case BGE_ASICREV_BCM5762: 3381 case BGE_ASICREV_BCM57765: 3382 case BGE_ASICREV_BCM57766: 3383 sc->bge_flags |= BGE_FLAG_57765_PLUS; 3384 /* FALLTHROUGH */ 3385 case BGE_ASICREV_BCM5717: 3386 case BGE_ASICREV_BCM5719: 3387 case BGE_ASICREV_BCM5720: 3388 sc->bge_flags |= BGE_FLAG_5717_PLUS | BGE_FLAG_5755_PLUS | 3389 BGE_FLAG_575X_PLUS | BGE_FLAG_5705_PLUS | BGE_FLAG_JUMBO | 3390 BGE_FLAG_JUMBO_FRAME; 3391 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3392 sc->bge_asicrev == BGE_ASICREV_BCM5720) { 3393 /* 3394 * Enable work around for DMA engine miscalculation 3395 * of TXMBUF available space. 3396 */ 3397 sc->bge_flags |= BGE_FLAG_RDMA_BUG; 3398 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3399 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3400 /* Jumbo frame on BCM5719 A0 does not work. */ 3401 sc->bge_flags &= ~BGE_FLAG_JUMBO; 3402 } 3403 } 3404 break; 3405 case BGE_ASICREV_BCM5755: 3406 case BGE_ASICREV_BCM5761: 3407 case BGE_ASICREV_BCM5784: 3408 case BGE_ASICREV_BCM5785: 3409 case BGE_ASICREV_BCM5787: 3410 case BGE_ASICREV_BCM57780: 3411 sc->bge_flags |= BGE_FLAG_5755_PLUS | BGE_FLAG_575X_PLUS | 3412 BGE_FLAG_5705_PLUS; 3413 break; 3414 case BGE_ASICREV_BCM5700: 3415 case BGE_ASICREV_BCM5701: 3416 case BGE_ASICREV_BCM5703: 3417 case BGE_ASICREV_BCM5704: 3418 sc->bge_flags |= BGE_FLAG_5700_FAMILY | BGE_FLAG_JUMBO; 3419 break; 3420 case BGE_ASICREV_BCM5714_A0: 3421 case BGE_ASICREV_BCM5780: 3422 case BGE_ASICREV_BCM5714: 3423 sc->bge_flags |= BGE_FLAG_5714_FAMILY | BGE_FLAG_JUMBO_STD; 3424 /* FALLTHROUGH */ 3425 case BGE_ASICREV_BCM5750: 3426 case BGE_ASICREV_BCM5752: 3427 case BGE_ASICREV_BCM5906: 3428 sc->bge_flags |= BGE_FLAG_575X_PLUS; 3429 /* FALLTHROUGH */ 3430 case BGE_ASICREV_BCM5705: 3431 sc->bge_flags |= BGE_FLAG_5705_PLUS; 3432 break; 3433 } 3434 3435 /* Identify chips with APE processor. */ 3436 switch (sc->bge_asicrev) { 3437 case BGE_ASICREV_BCM5717: 3438 case BGE_ASICREV_BCM5719: 3439 case BGE_ASICREV_BCM5720: 3440 case BGE_ASICREV_BCM5761: 3441 case BGE_ASICREV_BCM5762: 3442 sc->bge_flags |= BGE_FLAG_APE; 3443 break; 3444 } 3445 3446 /* Chips with APE need BAR2 access for APE registers/memory. */ 3447 if ((sc->bge_flags & BGE_FLAG_APE) != 0) { 3448 rid = PCIR_BAR(2); 3449 sc->bge_res2 = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 3450 RF_ACTIVE); 3451 if (sc->bge_res2 == NULL) { 3452 device_printf (sc->bge_dev, 3453 "couldn't map BAR2 memory\n"); 3454 error = ENXIO; 3455 goto fail; 3456 } 3457 3458 /* Enable APE register/memory access by host driver. */ 3459 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 3460 pcistate |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 3461 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 3462 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 3463 pci_write_config(dev, BGE_PCI_PCISTATE, pcistate, 4); 3464 3465 bge_ape_lock_init(sc); 3466 bge_ape_read_fw_ver(sc); 3467 } 3468 3469 /* Add SYSCTLs, requires the chipset family to be set. */ 3470 bge_add_sysctls(sc); 3471 3472 /* Identify the chips that use an CPMU. */ 3473 if (BGE_IS_5717_PLUS(sc) || 3474 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3475 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3476 sc->bge_asicrev == BGE_ASICREV_BCM5785 || 3477 sc->bge_asicrev == BGE_ASICREV_BCM57780) 3478 sc->bge_flags |= BGE_FLAG_CPMU_PRESENT; 3479 if ((sc->bge_flags & BGE_FLAG_CPMU_PRESENT) != 0) 3480 sc->bge_mi_mode = BGE_MIMODE_500KHZ_CONST; 3481 else 3482 sc->bge_mi_mode = BGE_MIMODE_BASE; 3483 /* Enable auto polling for BCM570[0-5]. */ 3484 if (BGE_IS_5700_FAMILY(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5705) 3485 sc->bge_mi_mode |= BGE_MIMODE_AUTOPOLL; 3486 3487 /* 3488 * All Broadcom controllers have 4GB boundary DMA bug. 3489 * Whenever an address crosses a multiple of the 4GB boundary 3490 * (including 4GB, 8Gb, 12Gb, etc.) and makes the transition 3491 * from 0xX_FFFF_FFFF to 0x(X+1)_0000_0000 an internal DMA 3492 * state machine will lockup and cause the device to hang. 3493 */ 3494 sc->bge_flags |= BGE_FLAG_4G_BNDRY_BUG; 3495 3496 /* BCM5755 or higher and BCM5906 have short DMA bug. */ 3497 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 3498 sc->bge_flags |= BGE_FLAG_SHORT_DMA_BUG; 3499 3500 /* 3501 * BCM5719 cannot handle DMA requests for DMA segments that 3502 * have larger than 4KB in size. However the maximum DMA 3503 * segment size created in DMA tag is 4KB for TSO, so we 3504 * wouldn't encounter the issue here. 3505 */ 3506 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 3507 sc->bge_flags |= BGE_FLAG_4K_RDMA_BUG; 3508 3509 misccfg = CSR_READ_4(sc, BGE_MISC_CFG) & BGE_MISCCFG_BOARD_ID_MASK; 3510 if (sc->bge_asicrev == BGE_ASICREV_BCM5705) { 3511 if (misccfg == BGE_MISCCFG_BOARD_ID_5788 || 3512 misccfg == BGE_MISCCFG_BOARD_ID_5788M) 3513 sc->bge_flags |= BGE_FLAG_5788; 3514 } 3515 3516 capmask = BMSR_DEFCAPMASK; 3517 if ((sc->bge_asicrev == BGE_ASICREV_BCM5703 && 3518 (misccfg == 0x4000 || misccfg == 0x8000)) || 3519 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3520 pci_get_vendor(dev) == BCOM_VENDORID && 3521 (pci_get_device(dev) == BCOM_DEVICEID_BCM5901 || 3522 pci_get_device(dev) == BCOM_DEVICEID_BCM5901A2 || 3523 pci_get_device(dev) == BCOM_DEVICEID_BCM5705F)) || 3524 (pci_get_vendor(dev) == BCOM_VENDORID && 3525 (pci_get_device(dev) == BCOM_DEVICEID_BCM5751F || 3526 pci_get_device(dev) == BCOM_DEVICEID_BCM5753F || 3527 pci_get_device(dev) == BCOM_DEVICEID_BCM5787F)) || 3528 pci_get_device(dev) == BCOM_DEVICEID_BCM57790 || 3529 pci_get_device(dev) == BCOM_DEVICEID_BCM57791 || 3530 pci_get_device(dev) == BCOM_DEVICEID_BCM57795 || 3531 sc->bge_asicrev == BGE_ASICREV_BCM5906) { 3532 /* These chips are 10/100 only. */ 3533 capmask &= ~BMSR_EXTSTAT; 3534 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3535 } 3536 3537 /* 3538 * Some controllers seem to require a special firmware to use 3539 * TSO. But the firmware is not available to FreeBSD and Linux 3540 * claims that the TSO performed by the firmware is slower than 3541 * hardware based TSO. Moreover the firmware based TSO has one 3542 * known bug which can't handle TSO if Ethernet header + IP/TCP 3543 * header is greater than 80 bytes. A workaround for the TSO 3544 * bug exist but it seems it's too expensive than not using 3545 * TSO at all. Some hardwares also have the TSO bug so limit 3546 * the TSO to the controllers that are not affected TSO issues 3547 * (e.g. 5755 or higher). 3548 */ 3549 if (BGE_IS_5717_PLUS(sc)) { 3550 /* BCM5717 requires different TSO configuration. */ 3551 sc->bge_flags |= BGE_FLAG_TSO3; 3552 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 && 3553 sc->bge_chipid == BGE_CHIPID_BCM5719_A0) { 3554 /* TSO on BCM5719 A0 does not work. */ 3555 sc->bge_flags &= ~BGE_FLAG_TSO3; 3556 } 3557 } else if (BGE_IS_5755_PLUS(sc)) { 3558 /* 3559 * BCM5754 and BCM5787 shares the same ASIC id so 3560 * explicit device id check is required. 3561 * Due to unknown reason TSO does not work on BCM5755M. 3562 */ 3563 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5754 && 3564 pci_get_device(dev) != BCOM_DEVICEID_BCM5754M && 3565 pci_get_device(dev) != BCOM_DEVICEID_BCM5755M) 3566 sc->bge_flags |= BGE_FLAG_TSO; 3567 } 3568 3569 /* 3570 * Check if this is a PCI-X or PCI Express device. 3571 */ 3572 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 3573 /* 3574 * Found a PCI Express capabilities register, this 3575 * must be a PCI Express device. 3576 */ 3577 sc->bge_flags |= BGE_FLAG_PCIE; 3578 sc->bge_expcap = reg; 3579 /* Extract supported maximum payload size. */ 3580 sc->bge_mps = pci_read_config(dev, sc->bge_expcap + 3581 PCIER_DEVICE_CAP, 2); 3582 sc->bge_mps = 128 << (sc->bge_mps & PCIEM_CAP_MAX_PAYLOAD); 3583 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 || 3584 sc->bge_asicrev == BGE_ASICREV_BCM5720) 3585 sc->bge_expmrq = 2048; 3586 else 3587 sc->bge_expmrq = 4096; 3588 pci_set_max_read_req(dev, sc->bge_expmrq); 3589 } else { 3590 /* 3591 * Check if the device is in PCI-X Mode. 3592 * (This bit is not valid on PCI Express controllers.) 3593 */ 3594 if (pci_find_cap(dev, PCIY_PCIX, ®) == 0) 3595 sc->bge_pcixcap = reg; 3596 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 3597 BGE_PCISTATE_PCI_BUSMODE) == 0) 3598 sc->bge_flags |= BGE_FLAG_PCIX; 3599 } 3600 3601 /* 3602 * The 40bit DMA bug applies to the 5714/5715 controllers and is 3603 * not actually a MAC controller bug but an issue with the embedded 3604 * PCIe to PCI-X bridge in the device. Use 40bit DMA workaround. 3605 */ 3606 if (BGE_IS_5714_FAMILY(sc) && (sc->bge_flags & BGE_FLAG_PCIX)) 3607 sc->bge_flags |= BGE_FLAG_40BIT_BUG; 3608 /* 3609 * Some PCI-X bridges are known to trigger write reordering to 3610 * the mailbox registers. Typical phenomena is watchdog timeouts 3611 * caused by out-of-order TX completions. Enable workaround for 3612 * PCI-X devices that live behind these bridges. 3613 * Note, PCI-X controllers can run in PCI mode so we can't use 3614 * BGE_FLAG_PCIX flag to detect PCI-X controllers. 3615 */ 3616 if (sc->bge_pcixcap != 0 && bge_mbox_reorder(sc) != 0) 3617 sc->bge_flags |= BGE_FLAG_MBOX_REORDER; 3618 /* 3619 * Allocate the interrupt, using MSI if possible. These devices 3620 * support 8 MSI messages, but only the first one is used in 3621 * normal operation. 3622 */ 3623 rid = 0; 3624 if (pci_find_cap(sc->bge_dev, PCIY_MSI, ®) == 0) { 3625 sc->bge_msicap = reg; 3626 reg = 1; 3627 if (bge_can_use_msi(sc) && pci_alloc_msi(dev, ®) == 0) { 3628 rid = 1; 3629 sc->bge_flags |= BGE_FLAG_MSI; 3630 } 3631 } 3632 3633 /* 3634 * All controllers except BCM5700 supports tagged status but 3635 * we use tagged status only for MSI case on BCM5717. Otherwise 3636 * MSI on BCM5717 does not work. 3637 */ 3638 #ifndef DEVICE_POLLING 3639 if (sc->bge_flags & BGE_FLAG_MSI && BGE_IS_5717_PLUS(sc)) 3640 sc->bge_flags |= BGE_FLAG_TAGGED_STATUS; 3641 #endif 3642 3643 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 3644 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 3645 3646 if (sc->bge_irq == NULL) { 3647 device_printf(sc->bge_dev, "couldn't map interrupt\n"); 3648 error = ENXIO; 3649 goto fail; 3650 } 3651 3652 bge_devinfo(sc); 3653 3654 sc->bge_asf_mode = 0; 3655 /* No ASF if APE present. */ 3656 if ((sc->bge_flags & BGE_FLAG_APE) == 0) { 3657 if (bge_allow_asf && (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == 3658 BGE_SRAM_DATA_SIG_MAGIC)) { 3659 if (bge_readmem_ind(sc, BGE_SRAM_DATA_CFG) & 3660 BGE_HWCFG_ASF) { 3661 sc->bge_asf_mode |= ASF_ENABLE; 3662 sc->bge_asf_mode |= ASF_STACKUP; 3663 if (BGE_IS_575X_PLUS(sc)) 3664 sc->bge_asf_mode |= ASF_NEW_HANDSHAKE; 3665 } 3666 } 3667 } 3668 3669 bge_stop_fw(sc); 3670 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 3671 if (bge_reset(sc)) { 3672 device_printf(sc->bge_dev, "chip reset failed\n"); 3673 error = ENXIO; 3674 goto fail; 3675 } 3676 3677 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 3678 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 3679 3680 if (bge_chipinit(sc)) { 3681 device_printf(sc->bge_dev, "chip initialization failed\n"); 3682 error = ENXIO; 3683 goto fail; 3684 } 3685 3686 error = bge_get_eaddr(sc, eaddr); 3687 if (error) { 3688 device_printf(sc->bge_dev, 3689 "failed to read station address\n"); 3690 error = ENXIO; 3691 goto fail; 3692 } 3693 3694 /* 5705 limits RX return ring to 512 entries. */ 3695 if (BGE_IS_5717_PLUS(sc)) 3696 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3697 else if (BGE_IS_5705_PLUS(sc)) 3698 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705; 3699 else 3700 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT; 3701 3702 if (bge_dma_alloc(sc)) { 3703 device_printf(sc->bge_dev, 3704 "failed to allocate DMA resources\n"); 3705 error = ENXIO; 3706 goto fail; 3707 } 3708 3709 /* Set default tuneable values. */ 3710 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 3711 sc->bge_rx_coal_ticks = 150; 3712 sc->bge_tx_coal_ticks = 150; 3713 sc->bge_rx_max_coal_bds = 10; 3714 sc->bge_tx_max_coal_bds = 10; 3715 3716 /* Initialize checksum features to use. */ 3717 sc->bge_csum_features = BGE_CSUM_FEATURES; 3718 if (sc->bge_forced_udpcsum != 0) 3719 sc->bge_csum_features |= CSUM_UDP; 3720 3721 /* Set up ifnet structure */ 3722 ifp = sc->bge_ifp = if_alloc(IFT_ETHER); 3723 if (ifp == NULL) { 3724 device_printf(sc->bge_dev, "failed to if_alloc()\n"); 3725 error = ENXIO; 3726 goto fail; 3727 } 3728 ifp->if_softc = sc; 3729 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 3730 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 3731 ifp->if_ioctl = bge_ioctl; 3732 ifp->if_start = bge_start; 3733 ifp->if_init = bge_init; 3734 ifp->if_snd.ifq_drv_maxlen = BGE_TX_RING_CNT - 1; 3735 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 3736 IFQ_SET_READY(&ifp->if_snd); 3737 ifp->if_hwassist = sc->bge_csum_features; 3738 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | 3739 IFCAP_VLAN_MTU; 3740 if ((sc->bge_flags & (BGE_FLAG_TSO | BGE_FLAG_TSO3)) != 0) { 3741 ifp->if_hwassist |= CSUM_TSO; 3742 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_VLAN_HWTSO; 3743 } 3744 #ifdef IFCAP_VLAN_HWCSUM 3745 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 3746 #endif 3747 ifp->if_capenable = ifp->if_capabilities; 3748 #ifdef DEVICE_POLLING 3749 ifp->if_capabilities |= IFCAP_POLLING; 3750 #endif 3751 3752 /* 3753 * 5700 B0 chips do not support checksumming correctly due 3754 * to hardware bugs. 3755 */ 3756 if (sc->bge_chipid == BGE_CHIPID_BCM5700_B0) { 3757 ifp->if_capabilities &= ~IFCAP_HWCSUM; 3758 ifp->if_capenable &= ~IFCAP_HWCSUM; 3759 ifp->if_hwassist = 0; 3760 } 3761 3762 /* 3763 * Figure out what sort of media we have by checking the 3764 * hardware config word in the first 32k of NIC internal memory, 3765 * or fall back to examining the EEPROM if necessary. 3766 * Note: on some BCM5700 cards, this value appears to be unset. 3767 * If that's the case, we have to rely on identifying the NIC 3768 * by its PCI subsystem ID, as we do below for the SysKonnect 3769 * SK-9D41. 3770 */ 3771 if (bge_readmem_ind(sc, BGE_SRAM_DATA_SIG) == BGE_SRAM_DATA_SIG_MAGIC) 3772 hwcfg = bge_readmem_ind(sc, BGE_SRAM_DATA_CFG); 3773 else if ((sc->bge_flags & BGE_FLAG_EADDR) && 3774 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 3775 if (bge_read_eeprom(sc, (caddr_t)&hwcfg, BGE_EE_HWCFG_OFFSET, 3776 sizeof(hwcfg))) { 3777 device_printf(sc->bge_dev, "failed to read EEPROM\n"); 3778 error = ENXIO; 3779 goto fail; 3780 } 3781 hwcfg = ntohl(hwcfg); 3782 } 3783 3784 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 3785 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == 3786 SK_SUBSYSID_9D41 || (hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) { 3787 if (BGE_IS_5705_PLUS(sc)) { 3788 sc->bge_flags |= BGE_FLAG_MII_SERDES; 3789 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3790 } else 3791 sc->bge_flags |= BGE_FLAG_TBI; 3792 } 3793 3794 /* Set various PHY bug flags. */ 3795 if (sc->bge_chipid == BGE_CHIPID_BCM5701_A0 || 3796 sc->bge_chipid == BGE_CHIPID_BCM5701_B0) 3797 sc->bge_phy_flags |= BGE_PHY_CRC_BUG; 3798 if (sc->bge_chiprev == BGE_CHIPREV_5703_AX || 3799 sc->bge_chiprev == BGE_CHIPREV_5704_AX) 3800 sc->bge_phy_flags |= BGE_PHY_ADC_BUG; 3801 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0) 3802 sc->bge_phy_flags |= BGE_PHY_5704_A0_BUG; 3803 if (pci_get_subvendor(dev) == DELL_VENDORID) 3804 sc->bge_phy_flags |= BGE_PHY_NO_3LED; 3805 if ((BGE_IS_5705_PLUS(sc)) && 3806 sc->bge_asicrev != BGE_ASICREV_BCM5906 && 3807 sc->bge_asicrev != BGE_ASICREV_BCM5785 && 3808 sc->bge_asicrev != BGE_ASICREV_BCM57780 && 3809 !BGE_IS_5717_PLUS(sc)) { 3810 if (sc->bge_asicrev == BGE_ASICREV_BCM5755 || 3811 sc->bge_asicrev == BGE_ASICREV_BCM5761 || 3812 sc->bge_asicrev == BGE_ASICREV_BCM5784 || 3813 sc->bge_asicrev == BGE_ASICREV_BCM5787) { 3814 if (pci_get_device(dev) != BCOM_DEVICEID_BCM5722 && 3815 pci_get_device(dev) != BCOM_DEVICEID_BCM5756) 3816 sc->bge_phy_flags |= BGE_PHY_JITTER_BUG; 3817 if (pci_get_device(dev) == BCOM_DEVICEID_BCM5755M) 3818 sc->bge_phy_flags |= BGE_PHY_ADJUST_TRIM; 3819 } else 3820 sc->bge_phy_flags |= BGE_PHY_BER_BUG; 3821 } 3822 3823 /* 3824 * Don't enable Ethernet@WireSpeed for the 5700 or the 3825 * 5705 A0 and A1 chips. 3826 */ 3827 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 3828 (sc->bge_asicrev == BGE_ASICREV_BCM5705 && 3829 (sc->bge_chipid != BGE_CHIPID_BCM5705_A0 && 3830 sc->bge_chipid != BGE_CHIPID_BCM5705_A1))) 3831 sc->bge_phy_flags |= BGE_PHY_NO_WIRESPEED; 3832 3833 if (sc->bge_flags & BGE_FLAG_TBI) { 3834 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, bge_ifmedia_upd, 3835 bge_ifmedia_sts); 3836 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX, 0, NULL); 3837 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_1000_SX | IFM_FDX, 3838 0, NULL); 3839 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 3840 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER | IFM_AUTO); 3841 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media; 3842 } else { 3843 /* 3844 * Do transceiver setup and tell the firmware the 3845 * driver is down so we can try to get access the 3846 * probe if ASF is running. Retry a couple of times 3847 * if we get a conflict with the ASF firmware accessing 3848 * the PHY. 3849 */ 3850 trys = 0; 3851 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3852 again: 3853 bge_asf_driver_up(sc); 3854 3855 error = mii_attach(dev, &sc->bge_miibus, ifp, bge_ifmedia_upd, 3856 bge_ifmedia_sts, capmask, sc->bge_phy_addr, MII_OFFSET_ANY, 3857 MIIF_DOPAUSE); 3858 if (error != 0) { 3859 if (trys++ < 4) { 3860 device_printf(sc->bge_dev, "Try again\n"); 3861 bge_miibus_writereg(sc->bge_dev, 3862 sc->bge_phy_addr, MII_BMCR, BMCR_RESET); 3863 goto again; 3864 } 3865 device_printf(sc->bge_dev, "attaching PHYs failed\n"); 3866 goto fail; 3867 } 3868 3869 /* 3870 * Now tell the firmware we are going up after probing the PHY 3871 */ 3872 if (sc->bge_asf_mode & ASF_STACKUP) 3873 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 3874 } 3875 3876 /* 3877 * When using the BCM5701 in PCI-X mode, data corruption has 3878 * been observed in the first few bytes of some received packets. 3879 * Aligning the packet buffer in memory eliminates the corruption. 3880 * Unfortunately, this misaligns the packet payloads. On platforms 3881 * which do not support unaligned accesses, we will realign the 3882 * payloads by copying the received packets. 3883 */ 3884 if (sc->bge_asicrev == BGE_ASICREV_BCM5701 && 3885 sc->bge_flags & BGE_FLAG_PCIX) 3886 sc->bge_flags |= BGE_FLAG_RX_ALIGNBUG; 3887 3888 /* 3889 * Call MI attach routine. 3890 */ 3891 ether_ifattach(ifp, eaddr); 3892 3893 /* Tell upper layer we support long frames. */ 3894 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 3895 3896 /* 3897 * Hookup IRQ last. 3898 */ 3899 if (BGE_IS_5755_PLUS(sc) && sc->bge_flags & BGE_FLAG_MSI) { 3900 /* Take advantage of single-shot MSI. */ 3901 CSR_WRITE_4(sc, BGE_MSI_MODE, CSR_READ_4(sc, BGE_MSI_MODE) & 3902 ~BGE_MSIMODE_ONE_SHOT_DISABLE); 3903 sc->bge_tq = taskqueue_create_fast("bge_taskq", M_WAITOK, 3904 taskqueue_thread_enqueue, &sc->bge_tq); 3905 if (sc->bge_tq == NULL) { 3906 device_printf(dev, "could not create taskqueue.\n"); 3907 ether_ifdetach(ifp); 3908 error = ENOMEM; 3909 goto fail; 3910 } 3911 error = taskqueue_start_threads(&sc->bge_tq, 1, PI_NET, 3912 "%s taskq", device_get_nameunit(sc->bge_dev)); 3913 if (error != 0) { 3914 device_printf(dev, "could not start threads.\n"); 3915 ether_ifdetach(ifp); 3916 goto fail; 3917 } 3918 error = bus_setup_intr(dev, sc->bge_irq, 3919 INTR_TYPE_NET | INTR_MPSAFE, bge_msi_intr, NULL, sc, 3920 &sc->bge_intrhand); 3921 } else 3922 error = bus_setup_intr(dev, sc->bge_irq, 3923 INTR_TYPE_NET | INTR_MPSAFE, NULL, bge_intr, sc, 3924 &sc->bge_intrhand); 3925 3926 if (error) { 3927 ether_ifdetach(ifp); 3928 device_printf(sc->bge_dev, "couldn't set up irq\n"); 3929 } 3930 3931 fail: 3932 if (error) 3933 bge_detach(dev); 3934 return (error); 3935 } 3936 3937 static int 3938 bge_detach(device_t dev) 3939 { 3940 struct bge_softc *sc; 3941 struct ifnet *ifp; 3942 3943 sc = device_get_softc(dev); 3944 ifp = sc->bge_ifp; 3945 3946 #ifdef DEVICE_POLLING 3947 if (ifp->if_capenable & IFCAP_POLLING) 3948 ether_poll_deregister(ifp); 3949 #endif 3950 3951 if (device_is_attached(dev)) { 3952 ether_ifdetach(ifp); 3953 BGE_LOCK(sc); 3954 bge_stop(sc); 3955 BGE_UNLOCK(sc); 3956 callout_drain(&sc->bge_stat_ch); 3957 } 3958 3959 if (sc->bge_tq) 3960 taskqueue_drain(sc->bge_tq, &sc->bge_intr_task); 3961 3962 if (sc->bge_flags & BGE_FLAG_TBI) 3963 ifmedia_removeall(&sc->bge_ifmedia); 3964 else if (sc->bge_miibus != NULL) { 3965 bus_generic_detach(dev); 3966 device_delete_child(dev, sc->bge_miibus); 3967 } 3968 3969 bge_release_resources(sc); 3970 3971 return (0); 3972 } 3973 3974 static void 3975 bge_release_resources(struct bge_softc *sc) 3976 { 3977 device_t dev; 3978 3979 dev = sc->bge_dev; 3980 3981 if (sc->bge_tq != NULL) 3982 taskqueue_free(sc->bge_tq); 3983 3984 if (sc->bge_intrhand != NULL) 3985 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 3986 3987 if (sc->bge_irq != NULL) { 3988 bus_release_resource(dev, SYS_RES_IRQ, 3989 rman_get_rid(sc->bge_irq), sc->bge_irq); 3990 pci_release_msi(dev); 3991 } 3992 3993 if (sc->bge_res != NULL) 3994 bus_release_resource(dev, SYS_RES_MEMORY, 3995 rman_get_rid(sc->bge_res), sc->bge_res); 3996 3997 if (sc->bge_res2 != NULL) 3998 bus_release_resource(dev, SYS_RES_MEMORY, 3999 rman_get_rid(sc->bge_res2), sc->bge_res2); 4000 4001 if (sc->bge_ifp != NULL) 4002 if_free(sc->bge_ifp); 4003 4004 bge_dma_free(sc); 4005 4006 if (mtx_initialized(&sc->bge_mtx)) /* XXX */ 4007 BGE_LOCK_DESTROY(sc); 4008 } 4009 4010 static int 4011 bge_reset(struct bge_softc *sc) 4012 { 4013 device_t dev; 4014 uint32_t cachesize, command, mac_mode, mac_mode_mask, reset, val; 4015 void (*write_op)(struct bge_softc *, int, int); 4016 uint16_t devctl; 4017 int i; 4018 4019 dev = sc->bge_dev; 4020 4021 mac_mode_mask = BGE_MACMODE_HALF_DUPLEX | BGE_MACMODE_PORTMODE; 4022 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4023 mac_mode_mask |= BGE_MACMODE_APE_RX_EN | BGE_MACMODE_APE_TX_EN; 4024 mac_mode = CSR_READ_4(sc, BGE_MAC_MODE) & mac_mode_mask; 4025 4026 if (BGE_IS_575X_PLUS(sc) && !BGE_IS_5714_FAMILY(sc) && 4027 (sc->bge_asicrev != BGE_ASICREV_BCM5906)) { 4028 if (sc->bge_flags & BGE_FLAG_PCIE) 4029 write_op = bge_writemem_direct; 4030 else 4031 write_op = bge_writemem_ind; 4032 } else 4033 write_op = bge_writereg_ind; 4034 4035 if (sc->bge_asicrev != BGE_ASICREV_BCM5700 && 4036 sc->bge_asicrev != BGE_ASICREV_BCM5701) { 4037 CSR_WRITE_4(sc, BGE_NVRAM_SWARB, BGE_NVRAMSWARB_SET1); 4038 for (i = 0; i < 8000; i++) { 4039 if (CSR_READ_4(sc, BGE_NVRAM_SWARB) & 4040 BGE_NVRAMSWARB_GNT1) 4041 break; 4042 DELAY(20); 4043 } 4044 if (i == 8000) { 4045 if (bootverbose) 4046 device_printf(dev, "NVRAM lock timedout!\n"); 4047 } 4048 } 4049 /* Take APE lock when performing reset. */ 4050 bge_ape_lock(sc, BGE_APE_LOCK_GRC); 4051 4052 /* Save some important PCI state. */ 4053 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 4054 command = pci_read_config(dev, BGE_PCI_CMD, 4); 4055 4056 pci_write_config(dev, BGE_PCI_MISC_CTL, 4057 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4058 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4059 4060 /* Disable fastboot on controllers that support it. */ 4061 if (sc->bge_asicrev == BGE_ASICREV_BCM5752 || 4062 BGE_IS_5755_PLUS(sc)) { 4063 if (bootverbose) 4064 device_printf(dev, "Disabling fastboot\n"); 4065 CSR_WRITE_4(sc, BGE_FASTBOOT_PC, 0x0); 4066 } 4067 4068 /* 4069 * Write the magic number to SRAM at offset 0xB50. 4070 * When firmware finishes its initialization it will 4071 * write ~BGE_SRAM_FW_MB_MAGIC to the same location. 4072 */ 4073 bge_writemem_ind(sc, BGE_SRAM_FW_MB, BGE_SRAM_FW_MB_MAGIC); 4074 4075 reset = BGE_MISCCFG_RESET_CORE_CLOCKS | BGE_32BITTIME_66MHZ; 4076 4077 /* XXX: Broadcom Linux driver. */ 4078 if (sc->bge_flags & BGE_FLAG_PCIE) { 4079 if (sc->bge_asicrev != BGE_ASICREV_BCM5785 && 4080 (sc->bge_flags & BGE_FLAG_5717_PLUS) == 0) { 4081 if (CSR_READ_4(sc, 0x7E2C) == 0x60) /* PCIE 1.0 */ 4082 CSR_WRITE_4(sc, 0x7E2C, 0x20); 4083 } 4084 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) { 4085 /* Prevent PCIE link training during global reset */ 4086 CSR_WRITE_4(sc, BGE_MISC_CFG, 1 << 29); 4087 reset |= 1 << 29; 4088 } 4089 } 4090 4091 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4092 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4093 CSR_WRITE_4(sc, BGE_VCPU_STATUS, 4094 val | BGE_VCPU_STATUS_DRV_RESET); 4095 val = CSR_READ_4(sc, BGE_VCPU_EXT_CTRL); 4096 CSR_WRITE_4(sc, BGE_VCPU_EXT_CTRL, 4097 val & ~BGE_VCPU_EXT_CTRL_HALT_CPU); 4098 } 4099 4100 /* 4101 * Set GPHY Power Down Override to leave GPHY 4102 * powered up in D0 uninitialized. 4103 */ 4104 if (BGE_IS_5705_PLUS(sc) && 4105 (sc->bge_flags & BGE_FLAG_CPMU_PRESENT) == 0) 4106 reset |= BGE_MISCCFG_GPHY_PD_OVERRIDE; 4107 4108 /* Issue global reset */ 4109 write_op(sc, BGE_MISC_CFG, reset); 4110 4111 if (sc->bge_flags & BGE_FLAG_PCIE) 4112 DELAY(100 * 1000); 4113 else 4114 DELAY(1000); 4115 4116 /* XXX: Broadcom Linux driver. */ 4117 if (sc->bge_flags & BGE_FLAG_PCIE) { 4118 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) { 4119 DELAY(500000); /* wait for link training to complete */ 4120 val = pci_read_config(dev, 0xC4, 4); 4121 pci_write_config(dev, 0xC4, val | (1 << 15), 4); 4122 } 4123 devctl = pci_read_config(dev, 4124 sc->bge_expcap + PCIER_DEVICE_CTL, 2); 4125 /* Clear enable no snoop and disable relaxed ordering. */ 4126 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE | 4127 PCIEM_CTL_NOSNOOP_ENABLE); 4128 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL, 4129 devctl, 2); 4130 pci_set_max_read_req(dev, sc->bge_expmrq); 4131 /* Clear error status. */ 4132 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA, 4133 PCIEM_STA_CORRECTABLE_ERROR | 4134 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR | 4135 PCIEM_STA_UNSUPPORTED_REQ, 2); 4136 } 4137 4138 /* Reset some of the PCI state that got zapped by reset. */ 4139 pci_write_config(dev, BGE_PCI_MISC_CTL, 4140 BGE_PCIMISCCTL_INDIRECT_ACCESS | BGE_PCIMISCCTL_MASK_PCI_INTR | 4141 BGE_HIF_SWAP_OPTIONS | BGE_PCIMISCCTL_PCISTATE_RW, 4); 4142 val = BGE_PCISTATE_ROM_ENABLE | BGE_PCISTATE_ROM_RETRY_ENABLE; 4143 if (sc->bge_chipid == BGE_CHIPID_BCM5704_A0 && 4144 (sc->bge_flags & BGE_FLAG_PCIX) != 0) 4145 val |= BGE_PCISTATE_RETRY_SAME_DMA; 4146 if ((sc->bge_mfw_flags & BGE_MFW_ON_APE) != 0) 4147 val |= BGE_PCISTATE_ALLOW_APE_CTLSPC_WR | 4148 BGE_PCISTATE_ALLOW_APE_SHMEM_WR | 4149 BGE_PCISTATE_ALLOW_APE_PSPACE_WR; 4150 pci_write_config(dev, BGE_PCI_PCISTATE, val, 4); 4151 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 4152 pci_write_config(dev, BGE_PCI_CMD, command, 4); 4153 /* 4154 * Disable PCI-X relaxed ordering to ensure status block update 4155 * comes first then packet buffer DMA. Otherwise driver may 4156 * read stale status block. 4157 */ 4158 if (sc->bge_flags & BGE_FLAG_PCIX) { 4159 devctl = pci_read_config(dev, 4160 sc->bge_pcixcap + PCIXR_COMMAND, 2); 4161 devctl &= ~PCIXM_COMMAND_ERO; 4162 if (sc->bge_asicrev == BGE_ASICREV_BCM5703) { 4163 devctl &= ~PCIXM_COMMAND_MAX_READ; 4164 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4165 } else if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 4166 devctl &= ~(PCIXM_COMMAND_MAX_SPLITS | 4167 PCIXM_COMMAND_MAX_READ); 4168 devctl |= PCIXM_COMMAND_MAX_READ_2048; 4169 } 4170 pci_write_config(dev, sc->bge_pcixcap + PCIXR_COMMAND, 4171 devctl, 2); 4172 } 4173 /* Re-enable MSI, if necessary, and enable the memory arbiter. */ 4174 if (BGE_IS_5714_FAMILY(sc)) { 4175 /* This chip disables MSI on reset. */ 4176 if (sc->bge_flags & BGE_FLAG_MSI) { 4177 val = pci_read_config(dev, 4178 sc->bge_msicap + PCIR_MSI_CTRL, 2); 4179 pci_write_config(dev, 4180 sc->bge_msicap + PCIR_MSI_CTRL, 4181 val | PCIM_MSICTRL_MSI_ENABLE, 2); 4182 val = CSR_READ_4(sc, BGE_MSI_MODE); 4183 CSR_WRITE_4(sc, BGE_MSI_MODE, 4184 val | BGE_MSIMODE_ENABLE); 4185 } 4186 val = CSR_READ_4(sc, BGE_MARB_MODE); 4187 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE | val); 4188 } else 4189 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 4190 4191 /* Fix up byte swapping. */ 4192 CSR_WRITE_4(sc, BGE_MODE_CTL, bge_dma_swap_options(sc)); 4193 4194 val = CSR_READ_4(sc, BGE_MAC_MODE); 4195 val = (val & ~mac_mode_mask) | mac_mode; 4196 CSR_WRITE_4(sc, BGE_MAC_MODE, val); 4197 DELAY(40); 4198 4199 bge_ape_unlock(sc, BGE_APE_LOCK_GRC); 4200 4201 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) { 4202 for (i = 0; i < BGE_TIMEOUT; i++) { 4203 val = CSR_READ_4(sc, BGE_VCPU_STATUS); 4204 if (val & BGE_VCPU_STATUS_INIT_DONE) 4205 break; 4206 DELAY(100); 4207 } 4208 if (i == BGE_TIMEOUT) { 4209 device_printf(dev, "reset timed out\n"); 4210 return (1); 4211 } 4212 } else { 4213 /* 4214 * Poll until we see the 1's complement of the magic number. 4215 * This indicates that the firmware initialization is complete. 4216 * We expect this to fail if no chip containing the Ethernet 4217 * address is fitted though. 4218 */ 4219 for (i = 0; i < BGE_TIMEOUT; i++) { 4220 DELAY(10); 4221 val = bge_readmem_ind(sc, BGE_SRAM_FW_MB); 4222 if (val == ~BGE_SRAM_FW_MB_MAGIC) 4223 break; 4224 } 4225 4226 if ((sc->bge_flags & BGE_FLAG_EADDR) && i == BGE_TIMEOUT) 4227 device_printf(dev, 4228 "firmware handshake timed out, found 0x%08x\n", 4229 val); 4230 /* BCM57765 A0 needs additional time before accessing. */ 4231 if (sc->bge_chipid == BGE_CHIPID_BCM57765_A0) 4232 DELAY(10 * 1000); /* XXX */ 4233 } 4234 4235 /* 4236 * The 5704 in TBI mode apparently needs some special 4237 * adjustment to insure the SERDES drive level is set 4238 * to 1.2V. 4239 */ 4240 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && 4241 sc->bge_flags & BGE_FLAG_TBI) { 4242 val = CSR_READ_4(sc, BGE_SERDES_CFG); 4243 val = (val & ~0xFFF) | 0x880; 4244 CSR_WRITE_4(sc, BGE_SERDES_CFG, val); 4245 } 4246 4247 /* XXX: Broadcom Linux driver. */ 4248 if (sc->bge_flags & BGE_FLAG_PCIE && 4249 !BGE_IS_5717_PLUS(sc) && 4250 sc->bge_chipid != BGE_CHIPID_BCM5750_A0 && 4251 sc->bge_asicrev != BGE_ASICREV_BCM5785) { 4252 /* Enable Data FIFO protection. */ 4253 val = CSR_READ_4(sc, 0x7C00); 4254 CSR_WRITE_4(sc, 0x7C00, val | (1 << 25)); 4255 } 4256 4257 if (sc->bge_asicrev == BGE_ASICREV_BCM5720) 4258 BGE_CLRBIT(sc, BGE_CPMU_CLCK_ORIDE, 4259 CPMU_CLCK_ORIDE_MAC_ORIDE_EN); 4260 4261 return (0); 4262 } 4263 4264 static __inline void 4265 bge_rxreuse_std(struct bge_softc *sc, int i) 4266 { 4267 struct bge_rx_bd *r; 4268 4269 r = &sc->bge_ldata.bge_rx_std_ring[sc->bge_std]; 4270 r->bge_flags = BGE_RXBDFLAG_END; 4271 r->bge_len = sc->bge_cdata.bge_rx_std_seglen[i]; 4272 r->bge_idx = i; 4273 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4274 } 4275 4276 static __inline void 4277 bge_rxreuse_jumbo(struct bge_softc *sc, int i) 4278 { 4279 struct bge_extrx_bd *r; 4280 4281 r = &sc->bge_ldata.bge_rx_jumbo_ring[sc->bge_jumbo]; 4282 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING | BGE_RXBDFLAG_END; 4283 r->bge_len0 = sc->bge_cdata.bge_rx_jumbo_seglen[i][0]; 4284 r->bge_len1 = sc->bge_cdata.bge_rx_jumbo_seglen[i][1]; 4285 r->bge_len2 = sc->bge_cdata.bge_rx_jumbo_seglen[i][2]; 4286 r->bge_len3 = sc->bge_cdata.bge_rx_jumbo_seglen[i][3]; 4287 r->bge_idx = i; 4288 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4289 } 4290 4291 /* 4292 * Frame reception handling. This is called if there's a frame 4293 * on the receive return list. 4294 * 4295 * Note: we have to be able to handle two possibilities here: 4296 * 1) the frame is from the jumbo receive ring 4297 * 2) the frame is from the standard receive ring 4298 */ 4299 4300 static int 4301 bge_rxeof(struct bge_softc *sc, uint16_t rx_prod, int holdlck) 4302 { 4303 struct ifnet *ifp; 4304 int rx_npkts = 0, stdcnt = 0, jumbocnt = 0; 4305 uint16_t rx_cons; 4306 4307 rx_cons = sc->bge_rx_saved_considx; 4308 4309 /* Nothing to do. */ 4310 if (rx_cons == rx_prod) 4311 return (rx_npkts); 4312 4313 ifp = sc->bge_ifp; 4314 4315 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4316 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_POSTREAD); 4317 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4318 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_POSTWRITE); 4319 if (BGE_IS_JUMBO_CAPABLE(sc) && 4320 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 4321 (MCLBYTES - ETHER_ALIGN)) 4322 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4323 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_POSTWRITE); 4324 4325 while (rx_cons != rx_prod) { 4326 struct bge_rx_bd *cur_rx; 4327 uint32_t rxidx; 4328 struct mbuf *m = NULL; 4329 uint16_t vlan_tag = 0; 4330 int have_tag = 0; 4331 4332 #ifdef DEVICE_POLLING 4333 if (ifp->if_capenable & IFCAP_POLLING) { 4334 if (sc->rxcycles <= 0) 4335 break; 4336 sc->rxcycles--; 4337 } 4338 #endif 4339 4340 cur_rx = &sc->bge_ldata.bge_rx_return_ring[rx_cons]; 4341 4342 rxidx = cur_rx->bge_idx; 4343 BGE_INC(rx_cons, sc->bge_return_ring_cnt); 4344 4345 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING && 4346 cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 4347 have_tag = 1; 4348 vlan_tag = cur_rx->bge_vlan_tag; 4349 } 4350 4351 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 4352 jumbocnt++; 4353 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 4354 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4355 bge_rxreuse_jumbo(sc, rxidx); 4356 continue; 4357 } 4358 if (bge_newbuf_jumbo(sc, rxidx) != 0) { 4359 bge_rxreuse_jumbo(sc, rxidx); 4360 ifp->if_iqdrops++; 4361 continue; 4362 } 4363 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 4364 } else { 4365 stdcnt++; 4366 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 4367 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 4368 bge_rxreuse_std(sc, rxidx); 4369 continue; 4370 } 4371 if (bge_newbuf_std(sc, rxidx) != 0) { 4372 bge_rxreuse_std(sc, rxidx); 4373 ifp->if_iqdrops++; 4374 continue; 4375 } 4376 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 4377 } 4378 4379 ifp->if_ipackets++; 4380 #ifndef __NO_STRICT_ALIGNMENT 4381 /* 4382 * For architectures with strict alignment we must make sure 4383 * the payload is aligned. 4384 */ 4385 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) { 4386 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 4387 cur_rx->bge_len); 4388 m->m_data += ETHER_ALIGN; 4389 } 4390 #endif 4391 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN; 4392 m->m_pkthdr.rcvif = ifp; 4393 4394 if (ifp->if_capenable & IFCAP_RXCSUM) 4395 bge_rxcsum(sc, cur_rx, m); 4396 4397 /* 4398 * If we received a packet with a vlan tag, 4399 * attach that information to the packet. 4400 */ 4401 if (have_tag) { 4402 m->m_pkthdr.ether_vtag = vlan_tag; 4403 m->m_flags |= M_VLANTAG; 4404 } 4405 4406 if (holdlck != 0) { 4407 BGE_UNLOCK(sc); 4408 (*ifp->if_input)(ifp, m); 4409 BGE_LOCK(sc); 4410 } else 4411 (*ifp->if_input)(ifp, m); 4412 rx_npkts++; 4413 4414 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 4415 return (rx_npkts); 4416 } 4417 4418 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag, 4419 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREREAD); 4420 if (stdcnt > 0) 4421 bus_dmamap_sync(sc->bge_cdata.bge_rx_std_ring_tag, 4422 sc->bge_cdata.bge_rx_std_ring_map, BUS_DMASYNC_PREWRITE); 4423 4424 if (jumbocnt > 0) 4425 bus_dmamap_sync(sc->bge_cdata.bge_rx_jumbo_ring_tag, 4426 sc->bge_cdata.bge_rx_jumbo_ring_map, BUS_DMASYNC_PREWRITE); 4427 4428 sc->bge_rx_saved_considx = rx_cons; 4429 bge_writembx(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 4430 if (stdcnt) 4431 bge_writembx(sc, BGE_MBX_RX_STD_PROD_LO, (sc->bge_std + 4432 BGE_STD_RX_RING_CNT - 1) % BGE_STD_RX_RING_CNT); 4433 if (jumbocnt) 4434 bge_writembx(sc, BGE_MBX_RX_JUMBO_PROD_LO, (sc->bge_jumbo + 4435 BGE_JUMBO_RX_RING_CNT - 1) % BGE_JUMBO_RX_RING_CNT); 4436 #ifdef notyet 4437 /* 4438 * This register wraps very quickly under heavy packet drops. 4439 * If you need correct statistics, you can enable this check. 4440 */ 4441 if (BGE_IS_5705_PLUS(sc)) 4442 ifp->if_ierrors += CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4443 #endif 4444 return (rx_npkts); 4445 } 4446 4447 static void 4448 bge_rxcsum(struct bge_softc *sc, struct bge_rx_bd *cur_rx, struct mbuf *m) 4449 { 4450 4451 if (BGE_IS_5717_PLUS(sc)) { 4452 if ((cur_rx->bge_flags & BGE_RXBDFLAG_IPV6) == 0) { 4453 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4454 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4455 if ((cur_rx->bge_error_flag & 4456 BGE_RXERRFLAG_IP_CSUM_NOK) == 0) 4457 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4458 } 4459 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 4460 m->m_pkthdr.csum_data = 4461 cur_rx->bge_tcp_udp_csum; 4462 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4463 CSUM_PSEUDO_HDR; 4464 } 4465 } 4466 } else { 4467 if (cur_rx->bge_flags & BGE_RXBDFLAG_IP_CSUM) { 4468 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 4469 if ((cur_rx->bge_ip_csum ^ 0xFFFF) == 0) 4470 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 4471 } 4472 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM && 4473 m->m_pkthdr.len >= ETHER_MIN_NOPAD) { 4474 m->m_pkthdr.csum_data = 4475 cur_rx->bge_tcp_udp_csum; 4476 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 4477 CSUM_PSEUDO_HDR; 4478 } 4479 } 4480 } 4481 4482 static void 4483 bge_txeof(struct bge_softc *sc, uint16_t tx_cons) 4484 { 4485 struct bge_tx_bd *cur_tx; 4486 struct ifnet *ifp; 4487 4488 BGE_LOCK_ASSERT(sc); 4489 4490 /* Nothing to do. */ 4491 if (sc->bge_tx_saved_considx == tx_cons) 4492 return; 4493 4494 ifp = sc->bge_ifp; 4495 4496 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 4497 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_POSTWRITE); 4498 /* 4499 * Go through our tx ring and free mbufs for those 4500 * frames that have been sent. 4501 */ 4502 while (sc->bge_tx_saved_considx != tx_cons) { 4503 uint32_t idx; 4504 4505 idx = sc->bge_tx_saved_considx; 4506 cur_tx = &sc->bge_ldata.bge_tx_ring[idx]; 4507 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 4508 ifp->if_opackets++; 4509 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 4510 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, 4511 sc->bge_cdata.bge_tx_dmamap[idx], 4512 BUS_DMASYNC_POSTWRITE); 4513 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, 4514 sc->bge_cdata.bge_tx_dmamap[idx]); 4515 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 4516 sc->bge_cdata.bge_tx_chain[idx] = NULL; 4517 } 4518 sc->bge_txcnt--; 4519 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 4520 } 4521 4522 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4523 if (sc->bge_txcnt == 0) 4524 sc->bge_timer = 0; 4525 } 4526 4527 #ifdef DEVICE_POLLING 4528 static int 4529 bge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 4530 { 4531 struct bge_softc *sc = ifp->if_softc; 4532 uint16_t rx_prod, tx_cons; 4533 uint32_t statusword; 4534 int rx_npkts = 0; 4535 4536 BGE_LOCK(sc); 4537 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4538 BGE_UNLOCK(sc); 4539 return (rx_npkts); 4540 } 4541 4542 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4543 sc->bge_cdata.bge_status_map, 4544 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4545 /* Fetch updates from the status block. */ 4546 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4547 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4548 4549 statusword = sc->bge_ldata.bge_status_block->bge_status; 4550 /* Clear the status so the next pass only sees the changes. */ 4551 sc->bge_ldata.bge_status_block->bge_status = 0; 4552 4553 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4554 sc->bge_cdata.bge_status_map, 4555 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4556 4557 /* Note link event. It will be processed by POLL_AND_CHECK_STATUS. */ 4558 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) 4559 sc->bge_link_evt++; 4560 4561 if (cmd == POLL_AND_CHECK_STATUS) 4562 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4563 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4564 sc->bge_link_evt || (sc->bge_flags & BGE_FLAG_TBI)) 4565 bge_link_upd(sc); 4566 4567 sc->rxcycles = count; 4568 rx_npkts = bge_rxeof(sc, rx_prod, 1); 4569 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 4570 BGE_UNLOCK(sc); 4571 return (rx_npkts); 4572 } 4573 bge_txeof(sc, tx_cons); 4574 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4575 bge_start_locked(ifp); 4576 4577 BGE_UNLOCK(sc); 4578 return (rx_npkts); 4579 } 4580 #endif /* DEVICE_POLLING */ 4581 4582 static int 4583 bge_msi_intr(void *arg) 4584 { 4585 struct bge_softc *sc; 4586 4587 sc = (struct bge_softc *)arg; 4588 /* 4589 * This interrupt is not shared and controller already 4590 * disabled further interrupt. 4591 */ 4592 taskqueue_enqueue(sc->bge_tq, &sc->bge_intr_task); 4593 return (FILTER_HANDLED); 4594 } 4595 4596 static void 4597 bge_intr_task(void *arg, int pending) 4598 { 4599 struct bge_softc *sc; 4600 struct ifnet *ifp; 4601 uint32_t status, status_tag; 4602 uint16_t rx_prod, tx_cons; 4603 4604 sc = (struct bge_softc *)arg; 4605 ifp = sc->bge_ifp; 4606 4607 BGE_LOCK(sc); 4608 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4609 BGE_UNLOCK(sc); 4610 return; 4611 } 4612 4613 /* Get updated status block. */ 4614 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4615 sc->bge_cdata.bge_status_map, 4616 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4617 4618 /* Save producer/consumer indices. */ 4619 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4620 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4621 status = sc->bge_ldata.bge_status_block->bge_status; 4622 status_tag = sc->bge_ldata.bge_status_block->bge_status_tag << 24; 4623 /* Dirty the status flag. */ 4624 sc->bge_ldata.bge_status_block->bge_status = 0; 4625 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4626 sc->bge_cdata.bge_status_map, 4627 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4628 if ((sc->bge_flags & BGE_FLAG_TAGGED_STATUS) == 0) 4629 status_tag = 0; 4630 4631 if ((status & BGE_STATFLAG_LINKSTATE_CHANGED) != 0) 4632 bge_link_upd(sc); 4633 4634 /* Let controller work. */ 4635 bge_writembx(sc, BGE_MBX_IRQ0_LO, status_tag); 4636 4637 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4638 sc->bge_rx_saved_considx != rx_prod) { 4639 /* Check RX return ring producer/consumer. */ 4640 BGE_UNLOCK(sc); 4641 bge_rxeof(sc, rx_prod, 0); 4642 BGE_LOCK(sc); 4643 } 4644 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4645 /* Check TX ring producer/consumer. */ 4646 bge_txeof(sc, tx_cons); 4647 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4648 bge_start_locked(ifp); 4649 } 4650 BGE_UNLOCK(sc); 4651 } 4652 4653 static void 4654 bge_intr(void *xsc) 4655 { 4656 struct bge_softc *sc; 4657 struct ifnet *ifp; 4658 uint32_t statusword; 4659 uint16_t rx_prod, tx_cons; 4660 4661 sc = xsc; 4662 4663 BGE_LOCK(sc); 4664 4665 ifp = sc->bge_ifp; 4666 4667 #ifdef DEVICE_POLLING 4668 if (ifp->if_capenable & IFCAP_POLLING) { 4669 BGE_UNLOCK(sc); 4670 return; 4671 } 4672 #endif 4673 4674 /* 4675 * Ack the interrupt by writing something to BGE_MBX_IRQ0_LO. Don't 4676 * disable interrupts by writing nonzero like we used to, since with 4677 * our current organization this just gives complications and 4678 * pessimizations for re-enabling interrupts. We used to have races 4679 * instead of the necessary complications. Disabling interrupts 4680 * would just reduce the chance of a status update while we are 4681 * running (by switching to the interrupt-mode coalescence 4682 * parameters), but this chance is already very low so it is more 4683 * efficient to get another interrupt than prevent it. 4684 * 4685 * We do the ack first to ensure another interrupt if there is a 4686 * status update after the ack. We don't check for the status 4687 * changing later because it is more efficient to get another 4688 * interrupt than prevent it, not quite as above (not checking is 4689 * a smaller optimization than not toggling the interrupt enable, 4690 * since checking doesn't involve PCI accesses and toggling require 4691 * the status check). So toggling would probably be a pessimization 4692 * even with MSI. It would only be needed for using a task queue. 4693 */ 4694 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 4695 4696 /* 4697 * Do the mandatory PCI flush as well as get the link status. 4698 */ 4699 statusword = CSR_READ_4(sc, BGE_MAC_STS) & BGE_MACSTAT_LINK_CHANGED; 4700 4701 /* Make sure the descriptor ring indexes are coherent. */ 4702 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4703 sc->bge_cdata.bge_status_map, 4704 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 4705 rx_prod = sc->bge_ldata.bge_status_block->bge_idx[0].bge_rx_prod_idx; 4706 tx_cons = sc->bge_ldata.bge_status_block->bge_idx[0].bge_tx_cons_idx; 4707 sc->bge_ldata.bge_status_block->bge_status = 0; 4708 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 4709 sc->bge_cdata.bge_status_map, 4710 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4711 4712 if ((sc->bge_asicrev == BGE_ASICREV_BCM5700 && 4713 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) || 4714 statusword || sc->bge_link_evt) 4715 bge_link_upd(sc); 4716 4717 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4718 /* Check RX return ring producer/consumer. */ 4719 bge_rxeof(sc, rx_prod, 1); 4720 } 4721 4722 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4723 /* Check TX ring producer/consumer. */ 4724 bge_txeof(sc, tx_cons); 4725 } 4726 4727 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 4728 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 4729 bge_start_locked(ifp); 4730 4731 BGE_UNLOCK(sc); 4732 } 4733 4734 static void 4735 bge_asf_driver_up(struct bge_softc *sc) 4736 { 4737 if (sc->bge_asf_mode & ASF_STACKUP) { 4738 /* Send ASF heartbeat aprox. every 2s */ 4739 if (sc->bge_asf_count) 4740 sc->bge_asf_count --; 4741 else { 4742 sc->bge_asf_count = 2; 4743 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_MB, 4744 BGE_FW_CMD_DRV_ALIVE); 4745 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_LEN_MB, 4); 4746 bge_writemem_ind(sc, BGE_SRAM_FW_CMD_DATA_MB, 4747 BGE_FW_HB_TIMEOUT_SEC); 4748 CSR_WRITE_4(sc, BGE_RX_CPU_EVENT, 4749 CSR_READ_4(sc, BGE_RX_CPU_EVENT) | 4750 BGE_RX_CPU_DRV_EVENT); 4751 } 4752 } 4753 } 4754 4755 static void 4756 bge_tick(void *xsc) 4757 { 4758 struct bge_softc *sc = xsc; 4759 struct mii_data *mii = NULL; 4760 4761 BGE_LOCK_ASSERT(sc); 4762 4763 /* Synchronize with possible callout reset/stop. */ 4764 if (callout_pending(&sc->bge_stat_ch) || 4765 !callout_active(&sc->bge_stat_ch)) 4766 return; 4767 4768 if (BGE_IS_5705_PLUS(sc)) 4769 bge_stats_update_regs(sc); 4770 else 4771 bge_stats_update(sc); 4772 4773 /* XXX Add APE heartbeat check here? */ 4774 4775 if ((sc->bge_flags & BGE_FLAG_TBI) == 0) { 4776 mii = device_get_softc(sc->bge_miibus); 4777 /* 4778 * Do not touch PHY if we have link up. This could break 4779 * IPMI/ASF mode or produce extra input errors 4780 * (extra errors was reported for bcm5701 & bcm5704). 4781 */ 4782 if (!sc->bge_link) 4783 mii_tick(mii); 4784 } else { 4785 /* 4786 * Since in TBI mode auto-polling can't be used we should poll 4787 * link status manually. Here we register pending link event 4788 * and trigger interrupt. 4789 */ 4790 #ifdef DEVICE_POLLING 4791 /* In polling mode we poll link state in bge_poll(). */ 4792 if (!(sc->bge_ifp->if_capenable & IFCAP_POLLING)) 4793 #endif 4794 { 4795 sc->bge_link_evt++; 4796 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 4797 sc->bge_flags & BGE_FLAG_5788) 4798 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 4799 else 4800 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 4801 } 4802 } 4803 4804 bge_asf_driver_up(sc); 4805 bge_watchdog(sc); 4806 4807 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 4808 } 4809 4810 static void 4811 bge_stats_update_regs(struct bge_softc *sc) 4812 { 4813 struct ifnet *ifp; 4814 struct bge_mac_stats *stats; 4815 uint32_t val; 4816 4817 ifp = sc->bge_ifp; 4818 stats = &sc->bge_mac_stats; 4819 4820 stats->ifHCOutOctets += 4821 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4822 stats->etherStatsCollisions += 4823 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4824 stats->outXonSent += 4825 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4826 stats->outXoffSent += 4827 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4828 stats->dot3StatsInternalMacTransmitErrors += 4829 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4830 stats->dot3StatsSingleCollisionFrames += 4831 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4832 stats->dot3StatsMultipleCollisionFrames += 4833 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4834 stats->dot3StatsDeferredTransmissions += 4835 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4836 stats->dot3StatsExcessiveCollisions += 4837 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4838 stats->dot3StatsLateCollisions += 4839 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4840 stats->ifHCOutUcastPkts += 4841 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4842 stats->ifHCOutMulticastPkts += 4843 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4844 stats->ifHCOutBroadcastPkts += 4845 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4846 4847 stats->ifHCInOctets += 4848 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4849 stats->etherStatsFragments += 4850 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4851 stats->ifHCInUcastPkts += 4852 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4853 stats->ifHCInMulticastPkts += 4854 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4855 stats->ifHCInBroadcastPkts += 4856 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4857 stats->dot3StatsFCSErrors += 4858 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4859 stats->dot3StatsAlignmentErrors += 4860 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4861 stats->xonPauseFramesReceived += 4862 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4863 stats->xoffPauseFramesReceived += 4864 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4865 stats->macControlFramesReceived += 4866 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4867 stats->xoffStateEntered += 4868 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4869 stats->dot3StatsFramesTooLong += 4870 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4871 stats->etherStatsJabbers += 4872 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4873 stats->etherStatsUndersizePkts += 4874 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4875 4876 stats->FramesDroppedDueToFilters += 4877 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4878 stats->DmaWriteQueueFull += 4879 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4880 stats->DmaWriteHighPriQueueFull += 4881 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4882 stats->NoMoreRxBDs += 4883 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4884 /* 4885 * XXX 4886 * Unlike other controllers, BGE_RXLP_LOCSTAT_IFIN_DROPS 4887 * counter of BCM5717, BCM5718, BCM5719 A0 and BCM5720 A0 4888 * includes number of unwanted multicast frames. This comes 4889 * from silicon bug and known workaround to get rough(not 4890 * exact) counter is to enable interrupt on MBUF low water 4891 * attention. This can be accomplished by setting 4892 * BGE_HCCMODE_ATTN bit of BGE_HCC_MODE, 4893 * BGE_BMANMODE_LOMBUF_ATTN bit of BGE_BMAN_MODE and 4894 * BGE_MODECTL_FLOWCTL_ATTN_INTR bit of BGE_MODE_CTL. 4895 * However that change would generate more interrupts and 4896 * there are still possibilities of losing multiple frames 4897 * during BGE_MODECTL_FLOWCTL_ATTN_INTR interrupt handling. 4898 * Given that the workaround still would not get correct 4899 * counter I don't think it's worth to implement it. So 4900 * ignore reading the counter on controllers that have the 4901 * silicon bug. 4902 */ 4903 if (sc->bge_asicrev != BGE_ASICREV_BCM5717 && 4904 sc->bge_chipid != BGE_CHIPID_BCM5719_A0 && 4905 sc->bge_chipid != BGE_CHIPID_BCM5720_A0) 4906 stats->InputDiscards += 4907 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4908 stats->InputErrors += 4909 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4910 stats->RecvThresholdHit += 4911 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4912 4913 ifp->if_collisions = (u_long)stats->etherStatsCollisions; 4914 ifp->if_ierrors = (u_long)(stats->NoMoreRxBDs + stats->InputDiscards + 4915 stats->InputErrors); 4916 4917 if (sc->bge_flags & BGE_FLAG_RDMA_BUG) { 4918 /* 4919 * If controller transmitted more than BGE_NUM_RDMA_CHANNELS 4920 * frames, it's safe to disable workaround for DMA engine's 4921 * miscalculation of TXMBUF space. 4922 */ 4923 if (stats->ifHCOutUcastPkts + stats->ifHCOutMulticastPkts + 4924 stats->ifHCOutBroadcastPkts > BGE_NUM_RDMA_CHANNELS) { 4925 val = CSR_READ_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL); 4926 if (sc->bge_asicrev == BGE_ASICREV_BCM5719) 4927 val &= ~BGE_RDMA_TX_LENGTH_WA_5719; 4928 else 4929 val &= ~BGE_RDMA_TX_LENGTH_WA_5720; 4930 CSR_WRITE_4(sc, BGE_RDMA_LSO_CRPTEN_CTRL, val); 4931 sc->bge_flags &= ~BGE_FLAG_RDMA_BUG; 4932 } 4933 } 4934 } 4935 4936 static void 4937 bge_stats_clear_regs(struct bge_softc *sc) 4938 { 4939 4940 CSR_READ_4(sc, BGE_TX_MAC_STATS_OCTETS); 4941 CSR_READ_4(sc, BGE_TX_MAC_STATS_COLLS); 4942 CSR_READ_4(sc, BGE_TX_MAC_STATS_XON_SENT); 4943 CSR_READ_4(sc, BGE_TX_MAC_STATS_XOFF_SENT); 4944 CSR_READ_4(sc, BGE_TX_MAC_STATS_ERRORS); 4945 CSR_READ_4(sc, BGE_TX_MAC_STATS_SINGLE_COLL); 4946 CSR_READ_4(sc, BGE_TX_MAC_STATS_MULTI_COLL); 4947 CSR_READ_4(sc, BGE_TX_MAC_STATS_DEFERRED); 4948 CSR_READ_4(sc, BGE_TX_MAC_STATS_EXCESS_COLL); 4949 CSR_READ_4(sc, BGE_TX_MAC_STATS_LATE_COLL); 4950 CSR_READ_4(sc, BGE_TX_MAC_STATS_UCAST); 4951 CSR_READ_4(sc, BGE_TX_MAC_STATS_MCAST); 4952 CSR_READ_4(sc, BGE_TX_MAC_STATS_BCAST); 4953 4954 CSR_READ_4(sc, BGE_RX_MAC_STATS_OCTESTS); 4955 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAGMENTS); 4956 CSR_READ_4(sc, BGE_RX_MAC_STATS_UCAST); 4957 CSR_READ_4(sc, BGE_RX_MAC_STATS_MCAST); 4958 CSR_READ_4(sc, BGE_RX_MAC_STATS_BCAST); 4959 CSR_READ_4(sc, BGE_RX_MAC_STATS_FCS_ERRORS); 4960 CSR_READ_4(sc, BGE_RX_MAC_STATS_ALGIN_ERRORS); 4961 CSR_READ_4(sc, BGE_RX_MAC_STATS_XON_RCVD); 4962 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_RCVD); 4963 CSR_READ_4(sc, BGE_RX_MAC_STATS_CTRL_RCVD); 4964 CSR_READ_4(sc, BGE_RX_MAC_STATS_XOFF_ENTERED); 4965 CSR_READ_4(sc, BGE_RX_MAC_STATS_FRAME_TOO_LONG); 4966 CSR_READ_4(sc, BGE_RX_MAC_STATS_JABBERS); 4967 CSR_READ_4(sc, BGE_RX_MAC_STATS_UNDERSIZE); 4968 4969 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_FILTDROP); 4970 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_WRQ_FULL); 4971 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL); 4972 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_OUT_OF_BDS); 4973 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_DROPS); 4974 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_IFIN_ERRORS); 4975 CSR_READ_4(sc, BGE_RXLP_LOCSTAT_RXTHRESH_HIT); 4976 } 4977 4978 static void 4979 bge_stats_update(struct bge_softc *sc) 4980 { 4981 struct ifnet *ifp; 4982 bus_size_t stats; 4983 uint32_t cnt; /* current register value */ 4984 4985 ifp = sc->bge_ifp; 4986 4987 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK; 4988 4989 #define READ_STAT(sc, stats, stat) \ 4990 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat)) 4991 4992 cnt = READ_STAT(sc, stats, txstats.etherStatsCollisions.bge_addr_lo); 4993 ifp->if_collisions += (uint32_t)(cnt - sc->bge_tx_collisions); 4994 sc->bge_tx_collisions = cnt; 4995 4996 cnt = READ_STAT(sc, stats, nicNoMoreRxBDs.bge_addr_lo); 4997 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_nobds); 4998 sc->bge_rx_nobds = cnt; 4999 cnt = READ_STAT(sc, stats, ifInErrors.bge_addr_lo); 5000 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_inerrs); 5001 sc->bge_rx_inerrs = cnt; 5002 cnt = READ_STAT(sc, stats, ifInDiscards.bge_addr_lo); 5003 ifp->if_ierrors += (uint32_t)(cnt - sc->bge_rx_discards); 5004 sc->bge_rx_discards = cnt; 5005 5006 cnt = READ_STAT(sc, stats, txstats.ifOutDiscards.bge_addr_lo); 5007 ifp->if_oerrors += (uint32_t)(cnt - sc->bge_tx_discards); 5008 sc->bge_tx_discards = cnt; 5009 5010 #undef READ_STAT 5011 } 5012 5013 /* 5014 * Pad outbound frame to ETHER_MIN_NOPAD for an unusual reason. 5015 * The bge hardware will pad out Tx runts to ETHER_MIN_NOPAD, 5016 * but when such padded frames employ the bge IP/TCP checksum offload, 5017 * the hardware checksum assist gives incorrect results (possibly 5018 * from incorporating its own padding into the UDP/TCP checksum; who knows). 5019 * If we pad such runts with zeros, the onboard checksum comes out correct. 5020 */ 5021 static __inline int 5022 bge_cksum_pad(struct mbuf *m) 5023 { 5024 int padlen = ETHER_MIN_NOPAD - m->m_pkthdr.len; 5025 struct mbuf *last; 5026 5027 /* If there's only the packet-header and we can pad there, use it. */ 5028 if (m->m_pkthdr.len == m->m_len && M_WRITABLE(m) && 5029 M_TRAILINGSPACE(m) >= padlen) { 5030 last = m; 5031 } else { 5032 /* 5033 * Walk packet chain to find last mbuf. We will either 5034 * pad there, or append a new mbuf and pad it. 5035 */ 5036 for (last = m; last->m_next != NULL; last = last->m_next); 5037 if (!(M_WRITABLE(last) && M_TRAILINGSPACE(last) >= padlen)) { 5038 /* Allocate new empty mbuf, pad it. Compact later. */ 5039 struct mbuf *n; 5040 5041 MGET(n, M_NOWAIT, MT_DATA); 5042 if (n == NULL) 5043 return (ENOBUFS); 5044 n->m_len = 0; 5045 last->m_next = n; 5046 last = n; 5047 } 5048 } 5049 5050 /* Now zero the pad area, to avoid the bge cksum-assist bug. */ 5051 memset(mtod(last, caddr_t) + last->m_len, 0, padlen); 5052 last->m_len += padlen; 5053 m->m_pkthdr.len += padlen; 5054 5055 return (0); 5056 } 5057 5058 static struct mbuf * 5059 bge_check_short_dma(struct mbuf *m) 5060 { 5061 struct mbuf *n; 5062 int found; 5063 5064 /* 5065 * If device receive two back-to-back send BDs with less than 5066 * or equal to 8 total bytes then the device may hang. The two 5067 * back-to-back send BDs must in the same frame for this failure 5068 * to occur. Scan mbuf chains and see whether two back-to-back 5069 * send BDs are there. If this is the case, allocate new mbuf 5070 * and copy the frame to workaround the silicon bug. 5071 */ 5072 for (n = m, found = 0; n != NULL; n = n->m_next) { 5073 if (n->m_len < 8) { 5074 found++; 5075 if (found > 1) 5076 break; 5077 continue; 5078 } 5079 found = 0; 5080 } 5081 5082 if (found > 1) { 5083 n = m_defrag(m, M_NOWAIT); 5084 if (n == NULL) 5085 m_freem(m); 5086 } else 5087 n = m; 5088 return (n); 5089 } 5090 5091 static struct mbuf * 5092 bge_setup_tso(struct bge_softc *sc, struct mbuf *m, uint16_t *mss, 5093 uint16_t *flags) 5094 { 5095 struct ip *ip; 5096 struct tcphdr *tcp; 5097 struct mbuf *n; 5098 uint16_t hlen; 5099 uint32_t poff; 5100 5101 if (M_WRITABLE(m) == 0) { 5102 /* Get a writable copy. */ 5103 n = m_dup(m, M_NOWAIT); 5104 m_freem(m); 5105 if (n == NULL) 5106 return (NULL); 5107 m = n; 5108 } 5109 m = m_pullup(m, sizeof(struct ether_header) + sizeof(struct ip)); 5110 if (m == NULL) 5111 return (NULL); 5112 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5113 poff = sizeof(struct ether_header) + (ip->ip_hl << 2); 5114 m = m_pullup(m, poff + sizeof(struct tcphdr)); 5115 if (m == NULL) 5116 return (NULL); 5117 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5118 m = m_pullup(m, poff + (tcp->th_off << 2)); 5119 if (m == NULL) 5120 return (NULL); 5121 /* 5122 * It seems controller doesn't modify IP length and TCP pseudo 5123 * checksum. These checksum computed by upper stack should be 0. 5124 */ 5125 *mss = m->m_pkthdr.tso_segsz; 5126 ip = (struct ip *)(mtod(m, char *) + sizeof(struct ether_header)); 5127 ip->ip_sum = 0; 5128 ip->ip_len = htons(*mss + (ip->ip_hl << 2) + (tcp->th_off << 2)); 5129 /* Clear pseudo checksum computed by TCP stack. */ 5130 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 5131 tcp->th_sum = 0; 5132 /* 5133 * Broadcom controllers uses different descriptor format for 5134 * TSO depending on ASIC revision. Due to TSO-capable firmware 5135 * license issue and lower performance of firmware based TSO 5136 * we only support hardware based TSO. 5137 */ 5138 /* Calculate header length, incl. TCP/IP options, in 32 bit units. */ 5139 hlen = ((ip->ip_hl << 2) + (tcp->th_off << 2)) >> 2; 5140 if (sc->bge_flags & BGE_FLAG_TSO3) { 5141 /* 5142 * For BCM5717 and newer controllers, hardware based TSO 5143 * uses the 14 lower bits of the bge_mss field to store the 5144 * MSS and the upper 2 bits to store the lowest 2 bits of 5145 * the IP/TCP header length. The upper 6 bits of the header 5146 * length are stored in the bge_flags[14:10,4] field. Jumbo 5147 * frames are supported. 5148 */ 5149 *mss |= ((hlen & 0x3) << 14); 5150 *flags |= ((hlen & 0xF8) << 7) | ((hlen & 0x4) << 2); 5151 } else { 5152 /* 5153 * For BCM5755 and newer controllers, hardware based TSO uses 5154 * the lower 11 bits to store the MSS and the upper 5 bits to 5155 * store the IP/TCP header length. Jumbo frames are not 5156 * supported. 5157 */ 5158 *mss |= (hlen << 11); 5159 } 5160 return (m); 5161 } 5162 5163 /* 5164 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 5165 * pointers to descriptors. 5166 */ 5167 static int 5168 bge_encap(struct bge_softc *sc, struct mbuf **m_head, uint32_t *txidx) 5169 { 5170 bus_dma_segment_t segs[BGE_NSEG_NEW]; 5171 bus_dmamap_t map; 5172 struct bge_tx_bd *d; 5173 struct mbuf *m = *m_head; 5174 uint32_t idx = *txidx; 5175 uint16_t csum_flags, mss, vlan_tag; 5176 int nsegs, i, error; 5177 5178 csum_flags = 0; 5179 mss = 0; 5180 vlan_tag = 0; 5181 if ((sc->bge_flags & BGE_FLAG_SHORT_DMA_BUG) != 0 && 5182 m->m_next != NULL) { 5183 *m_head = bge_check_short_dma(m); 5184 if (*m_head == NULL) 5185 return (ENOBUFS); 5186 m = *m_head; 5187 } 5188 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5189 *m_head = m = bge_setup_tso(sc, m, &mss, &csum_flags); 5190 if (*m_head == NULL) 5191 return (ENOBUFS); 5192 csum_flags |= BGE_TXBDFLAG_CPU_PRE_DMA | 5193 BGE_TXBDFLAG_CPU_POST_DMA; 5194 } else if ((m->m_pkthdr.csum_flags & sc->bge_csum_features) != 0) { 5195 if (m->m_pkthdr.csum_flags & CSUM_IP) 5196 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 5197 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) { 5198 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 5199 if (m->m_pkthdr.len < ETHER_MIN_NOPAD && 5200 (error = bge_cksum_pad(m)) != 0) { 5201 m_freem(m); 5202 *m_head = NULL; 5203 return (error); 5204 } 5205 } 5206 } 5207 5208 if ((m->m_pkthdr.csum_flags & CSUM_TSO) == 0) { 5209 if (sc->bge_flags & BGE_FLAG_JUMBO_FRAME && 5210 m->m_pkthdr.len > ETHER_MAX_LEN) 5211 csum_flags |= BGE_TXBDFLAG_JUMBO_FRAME; 5212 if (sc->bge_forced_collapse > 0 && 5213 (sc->bge_flags & BGE_FLAG_PCIE) != 0 && m->m_next != NULL) { 5214 /* 5215 * Forcedly collapse mbuf chains to overcome hardware 5216 * limitation which only support a single outstanding 5217 * DMA read operation. 5218 */ 5219 if (sc->bge_forced_collapse == 1) 5220 m = m_defrag(m, M_NOWAIT); 5221 else 5222 m = m_collapse(m, M_NOWAIT, 5223 sc->bge_forced_collapse); 5224 if (m == NULL) 5225 m = *m_head; 5226 *m_head = m; 5227 } 5228 } 5229 5230 map = sc->bge_cdata.bge_tx_dmamap[idx]; 5231 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, m, segs, 5232 &nsegs, BUS_DMA_NOWAIT); 5233 if (error == EFBIG) { 5234 m = m_collapse(m, M_NOWAIT, BGE_NSEG_NEW); 5235 if (m == NULL) { 5236 m_freem(*m_head); 5237 *m_head = NULL; 5238 return (ENOBUFS); 5239 } 5240 *m_head = m; 5241 error = bus_dmamap_load_mbuf_sg(sc->bge_cdata.bge_tx_mtag, map, 5242 m, segs, &nsegs, BUS_DMA_NOWAIT); 5243 if (error) { 5244 m_freem(m); 5245 *m_head = NULL; 5246 return (error); 5247 } 5248 } else if (error != 0) 5249 return (error); 5250 5251 /* Check if we have enough free send BDs. */ 5252 if (sc->bge_txcnt + nsegs >= BGE_TX_RING_CNT) { 5253 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5254 return (ENOBUFS); 5255 } 5256 5257 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, BUS_DMASYNC_PREWRITE); 5258 5259 if (m->m_flags & M_VLANTAG) { 5260 csum_flags |= BGE_TXBDFLAG_VLAN_TAG; 5261 vlan_tag = m->m_pkthdr.ether_vtag; 5262 } 5263 5264 if (sc->bge_asicrev == BGE_ASICREV_BCM5762 && 5265 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 5266 /* 5267 * 5725 family of devices corrupts TSO packets when TSO DMA 5268 * buffers cross into regions which are within MSS bytes of 5269 * a 4GB boundary. If we encounter the condition, drop the 5270 * packet. 5271 */ 5272 for (i = 0; ; i++) { 5273 d = &sc->bge_ldata.bge_tx_ring[idx]; 5274 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5275 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5276 d->bge_len = segs[i].ds_len; 5277 if (d->bge_addr.bge_addr_lo + segs[i].ds_len + mss < 5278 d->bge_addr.bge_addr_lo) 5279 break; 5280 d->bge_flags = csum_flags; 5281 d->bge_vlan_tag = vlan_tag; 5282 d->bge_mss = mss; 5283 if (i == nsegs - 1) 5284 break; 5285 BGE_INC(idx, BGE_TX_RING_CNT); 5286 } 5287 if (i != nsegs - 1) { 5288 bus_dmamap_sync(sc->bge_cdata.bge_tx_mtag, map, 5289 BUS_DMASYNC_POSTWRITE); 5290 bus_dmamap_unload(sc->bge_cdata.bge_tx_mtag, map); 5291 m_freem(*m_head); 5292 *m_head = NULL; 5293 return (EIO); 5294 } 5295 } else { 5296 for (i = 0; ; i++) { 5297 d = &sc->bge_ldata.bge_tx_ring[idx]; 5298 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr); 5299 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr); 5300 d->bge_len = segs[i].ds_len; 5301 d->bge_flags = csum_flags; 5302 d->bge_vlan_tag = vlan_tag; 5303 d->bge_mss = mss; 5304 if (i == nsegs - 1) 5305 break; 5306 BGE_INC(idx, BGE_TX_RING_CNT); 5307 } 5308 } 5309 5310 /* Mark the last segment as end of packet... */ 5311 d->bge_flags |= BGE_TXBDFLAG_END; 5312 5313 /* 5314 * Insure that the map for this transmission 5315 * is placed at the array index of the last descriptor 5316 * in this chain. 5317 */ 5318 sc->bge_cdata.bge_tx_dmamap[*txidx] = sc->bge_cdata.bge_tx_dmamap[idx]; 5319 sc->bge_cdata.bge_tx_dmamap[idx] = map; 5320 sc->bge_cdata.bge_tx_chain[idx] = m; 5321 sc->bge_txcnt += nsegs; 5322 5323 BGE_INC(idx, BGE_TX_RING_CNT); 5324 *txidx = idx; 5325 5326 return (0); 5327 } 5328 5329 /* 5330 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5331 * to the mbuf data regions directly in the transmit descriptors. 5332 */ 5333 static void 5334 bge_start_locked(struct ifnet *ifp) 5335 { 5336 struct bge_softc *sc; 5337 struct mbuf *m_head; 5338 uint32_t prodidx; 5339 int count; 5340 5341 sc = ifp->if_softc; 5342 BGE_LOCK_ASSERT(sc); 5343 5344 if (!sc->bge_link || 5345 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 5346 IFF_DRV_RUNNING) 5347 return; 5348 5349 prodidx = sc->bge_tx_prodidx; 5350 5351 for (count = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd);) { 5352 if (sc->bge_txcnt > BGE_TX_RING_CNT - 16) { 5353 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5354 break; 5355 } 5356 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 5357 if (m_head == NULL) 5358 break; 5359 5360 /* 5361 * Pack the data into the transmit ring. If we 5362 * don't have room, set the OACTIVE flag and wait 5363 * for the NIC to drain the ring. 5364 */ 5365 if (bge_encap(sc, &m_head, &prodidx)) { 5366 if (m_head == NULL) 5367 break; 5368 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 5369 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5370 break; 5371 } 5372 ++count; 5373 5374 /* 5375 * If there's a BPF listener, bounce a copy of this frame 5376 * to him. 5377 */ 5378 #ifdef ETHER_BPF_MTAP 5379 ETHER_BPF_MTAP(ifp, m_head); 5380 #else 5381 BPF_MTAP(ifp, m_head); 5382 #endif 5383 } 5384 5385 if (count > 0) { 5386 bus_dmamap_sync(sc->bge_cdata.bge_tx_ring_tag, 5387 sc->bge_cdata.bge_tx_ring_map, BUS_DMASYNC_PREWRITE); 5388 /* Transmit. */ 5389 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5390 /* 5700 b2 errata */ 5391 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX) 5392 bge_writembx(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 5393 5394 sc->bge_tx_prodidx = prodidx; 5395 5396 /* 5397 * Set a timeout in case the chip goes out to lunch. 5398 */ 5399 sc->bge_timer = BGE_TX_TIMEOUT; 5400 } 5401 } 5402 5403 /* 5404 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 5405 * to the mbuf data regions directly in the transmit descriptors. 5406 */ 5407 static void 5408 bge_start(struct ifnet *ifp) 5409 { 5410 struct bge_softc *sc; 5411 5412 sc = ifp->if_softc; 5413 BGE_LOCK(sc); 5414 bge_start_locked(ifp); 5415 BGE_UNLOCK(sc); 5416 } 5417 5418 static void 5419 bge_init_locked(struct bge_softc *sc) 5420 { 5421 struct ifnet *ifp; 5422 uint16_t *m; 5423 uint32_t mode; 5424 5425 BGE_LOCK_ASSERT(sc); 5426 5427 ifp = sc->bge_ifp; 5428 5429 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 5430 return; 5431 5432 /* Cancel pending I/O and flush buffers. */ 5433 bge_stop(sc); 5434 5435 bge_stop_fw(sc); 5436 bge_sig_pre_reset(sc, BGE_RESET_START); 5437 bge_reset(sc); 5438 bge_sig_legacy(sc, BGE_RESET_START); 5439 bge_sig_post_reset(sc, BGE_RESET_START); 5440 5441 bge_chipinit(sc); 5442 5443 /* 5444 * Init the various state machines, ring 5445 * control blocks and firmware. 5446 */ 5447 if (bge_blockinit(sc)) { 5448 device_printf(sc->bge_dev, "initialization failure\n"); 5449 return; 5450 } 5451 5452 ifp = sc->bge_ifp; 5453 5454 /* Specify MTU. */ 5455 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 5456 ETHER_HDR_LEN + ETHER_CRC_LEN + 5457 (ifp->if_capenable & IFCAP_VLAN_MTU ? ETHER_VLAN_ENCAP_LEN : 0)); 5458 5459 /* Load our MAC address. */ 5460 m = (uint16_t *)IF_LLADDR(sc->bge_ifp); 5461 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 5462 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 5463 5464 /* Program promiscuous mode. */ 5465 bge_setpromisc(sc); 5466 5467 /* Program multicast filter. */ 5468 bge_setmulti(sc); 5469 5470 /* Program VLAN tag stripping. */ 5471 bge_setvlan(sc); 5472 5473 /* Override UDP checksum offloading. */ 5474 if (sc->bge_forced_udpcsum == 0) 5475 sc->bge_csum_features &= ~CSUM_UDP; 5476 else 5477 sc->bge_csum_features |= CSUM_UDP; 5478 if (ifp->if_capabilities & IFCAP_TXCSUM && 5479 ifp->if_capenable & IFCAP_TXCSUM) { 5480 ifp->if_hwassist &= ~(BGE_CSUM_FEATURES | CSUM_UDP); 5481 ifp->if_hwassist |= sc->bge_csum_features; 5482 } 5483 5484 /* Init RX ring. */ 5485 if (bge_init_rx_ring_std(sc) != 0) { 5486 device_printf(sc->bge_dev, "no memory for std Rx buffers.\n"); 5487 bge_stop(sc); 5488 return; 5489 } 5490 5491 /* 5492 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's 5493 * memory to insure that the chip has in fact read the first 5494 * entry of the ring. 5495 */ 5496 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) { 5497 uint32_t v, i; 5498 for (i = 0; i < 10; i++) { 5499 DELAY(20); 5500 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8); 5501 if (v == (MCLBYTES - ETHER_ALIGN)) 5502 break; 5503 } 5504 if (i == 10) 5505 device_printf (sc->bge_dev, 5506 "5705 A0 chip failed to load RX ring\n"); 5507 } 5508 5509 /* Init jumbo RX ring. */ 5510 if (BGE_IS_JUMBO_CAPABLE(sc) && 5511 ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN > 5512 (MCLBYTES - ETHER_ALIGN)) { 5513 if (bge_init_rx_ring_jumbo(sc) != 0) { 5514 device_printf(sc->bge_dev, 5515 "no memory for jumbo Rx buffers.\n"); 5516 bge_stop(sc); 5517 return; 5518 } 5519 } 5520 5521 /* Init our RX return ring index. */ 5522 sc->bge_rx_saved_considx = 0; 5523 5524 /* Init our RX/TX stat counters. */ 5525 sc->bge_rx_discards = sc->bge_tx_discards = sc->bge_tx_collisions = 0; 5526 5527 /* Init TX ring. */ 5528 bge_init_tx_ring(sc); 5529 5530 /* Enable TX MAC state machine lockup fix. */ 5531 mode = CSR_READ_4(sc, BGE_TX_MODE); 5532 if (BGE_IS_5755_PLUS(sc) || sc->bge_asicrev == BGE_ASICREV_BCM5906) 5533 mode |= BGE_TXMODE_MBUF_LOCKUP_FIX; 5534 if (sc->bge_asicrev == BGE_ASICREV_BCM5720 || 5535 sc->bge_asicrev == BGE_ASICREV_BCM5762) { 5536 mode &= ~(BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5537 mode |= CSR_READ_4(sc, BGE_TX_MODE) & 5538 (BGE_TXMODE_JMB_FRM_LEN | BGE_TXMODE_CNT_DN_MODE); 5539 } 5540 /* Turn on transmitter. */ 5541 CSR_WRITE_4(sc, BGE_TX_MODE, mode | BGE_TXMODE_ENABLE); 5542 DELAY(100); 5543 5544 /* Turn on receiver. */ 5545 mode = CSR_READ_4(sc, BGE_RX_MODE); 5546 if (BGE_IS_5755_PLUS(sc)) 5547 mode |= BGE_RXMODE_IPV6_ENABLE; 5548 if (sc->bge_asicrev == BGE_ASICREV_BCM5762) 5549 mode |= BGE_RXMODE_IPV4_FRAG_FIX; 5550 CSR_WRITE_4(sc,BGE_RX_MODE, mode | BGE_RXMODE_ENABLE); 5551 DELAY(10); 5552 5553 /* 5554 * Set the number of good frames to receive after RX MBUF 5555 * Low Watermark has been reached. After the RX MAC receives 5556 * this number of frames, it will drop subsequent incoming 5557 * frames until the MBUF High Watermark is reached. 5558 */ 5559 if (BGE_IS_57765_PLUS(sc)) 5560 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 1); 5561 else 5562 CSR_WRITE_4(sc, BGE_MAX_RX_FRAME_LOWAT, 2); 5563 5564 /* Clear MAC statistics. */ 5565 if (BGE_IS_5705_PLUS(sc)) 5566 bge_stats_clear_regs(sc); 5567 5568 /* Tell firmware we're alive. */ 5569 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 5570 5571 #ifdef DEVICE_POLLING 5572 /* Disable interrupts if we are polling. */ 5573 if (ifp->if_capenable & IFCAP_POLLING) { 5574 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5575 BGE_PCIMISCCTL_MASK_PCI_INTR); 5576 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5577 } else 5578 #endif 5579 5580 /* Enable host interrupts. */ 5581 { 5582 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 5583 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5584 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5585 } 5586 5587 ifp->if_drv_flags |= IFF_DRV_RUNNING; 5588 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 5589 5590 bge_ifmedia_upd_locked(ifp); 5591 5592 callout_reset(&sc->bge_stat_ch, hz, bge_tick, sc); 5593 } 5594 5595 static void 5596 bge_init(void *xsc) 5597 { 5598 struct bge_softc *sc = xsc; 5599 5600 BGE_LOCK(sc); 5601 bge_init_locked(sc); 5602 BGE_UNLOCK(sc); 5603 } 5604 5605 /* 5606 * Set media options. 5607 */ 5608 static int 5609 bge_ifmedia_upd(struct ifnet *ifp) 5610 { 5611 struct bge_softc *sc = ifp->if_softc; 5612 int res; 5613 5614 BGE_LOCK(sc); 5615 res = bge_ifmedia_upd_locked(ifp); 5616 BGE_UNLOCK(sc); 5617 5618 return (res); 5619 } 5620 5621 static int 5622 bge_ifmedia_upd_locked(struct ifnet *ifp) 5623 { 5624 struct bge_softc *sc = ifp->if_softc; 5625 struct mii_data *mii; 5626 struct mii_softc *miisc; 5627 struct ifmedia *ifm; 5628 5629 BGE_LOCK_ASSERT(sc); 5630 5631 ifm = &sc->bge_ifmedia; 5632 5633 /* If this is a 1000baseX NIC, enable the TBI port. */ 5634 if (sc->bge_flags & BGE_FLAG_TBI) { 5635 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 5636 return (EINVAL); 5637 switch(IFM_SUBTYPE(ifm->ifm_media)) { 5638 case IFM_AUTO: 5639 /* 5640 * The BCM5704 ASIC appears to have a special 5641 * mechanism for programming the autoneg 5642 * advertisement registers in TBI mode. 5643 */ 5644 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 5645 uint32_t sgdig; 5646 sgdig = CSR_READ_4(sc, BGE_SGDIG_STS); 5647 if (sgdig & BGE_SGDIGSTS_DONE) { 5648 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0); 5649 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG); 5650 sgdig |= BGE_SGDIGCFG_AUTO | 5651 BGE_SGDIGCFG_PAUSE_CAP | 5652 BGE_SGDIGCFG_ASYM_PAUSE; 5653 CSR_WRITE_4(sc, BGE_SGDIG_CFG, 5654 sgdig | BGE_SGDIGCFG_SEND); 5655 DELAY(5); 5656 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig); 5657 } 5658 } 5659 break; 5660 case IFM_1000_SX: 5661 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 5662 BGE_CLRBIT(sc, BGE_MAC_MODE, 5663 BGE_MACMODE_HALF_DUPLEX); 5664 } else { 5665 BGE_SETBIT(sc, BGE_MAC_MODE, 5666 BGE_MACMODE_HALF_DUPLEX); 5667 } 5668 DELAY(40); 5669 break; 5670 default: 5671 return (EINVAL); 5672 } 5673 return (0); 5674 } 5675 5676 sc->bge_link_evt++; 5677 mii = device_get_softc(sc->bge_miibus); 5678 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 5679 PHY_RESET(miisc); 5680 mii_mediachg(mii); 5681 5682 /* 5683 * Force an interrupt so that we will call bge_link_upd 5684 * if needed and clear any pending link state attention. 5685 * Without this we are not getting any further interrupts 5686 * for link state changes and thus will not UP the link and 5687 * not be able to send in bge_start_locked. The only 5688 * way to get things working was to receive a packet and 5689 * get an RX intr. 5690 * bge_tick should help for fiber cards and we might not 5691 * need to do this here if BGE_FLAG_TBI is set but as 5692 * we poll for fiber anyway it should not harm. 5693 */ 5694 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 || 5695 sc->bge_flags & BGE_FLAG_5788) 5696 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_SET); 5697 else 5698 BGE_SETBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_COAL_NOW); 5699 5700 return (0); 5701 } 5702 5703 /* 5704 * Report current media status. 5705 */ 5706 static void 5707 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 5708 { 5709 struct bge_softc *sc = ifp->if_softc; 5710 struct mii_data *mii; 5711 5712 BGE_LOCK(sc); 5713 5714 if ((ifp->if_flags & IFF_UP) == 0) { 5715 BGE_UNLOCK(sc); 5716 return; 5717 } 5718 if (sc->bge_flags & BGE_FLAG_TBI) { 5719 ifmr->ifm_status = IFM_AVALID; 5720 ifmr->ifm_active = IFM_ETHER; 5721 if (CSR_READ_4(sc, BGE_MAC_STS) & 5722 BGE_MACSTAT_TBI_PCS_SYNCHED) 5723 ifmr->ifm_status |= IFM_ACTIVE; 5724 else { 5725 ifmr->ifm_active |= IFM_NONE; 5726 BGE_UNLOCK(sc); 5727 return; 5728 } 5729 ifmr->ifm_active |= IFM_1000_SX; 5730 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 5731 ifmr->ifm_active |= IFM_HDX; 5732 else 5733 ifmr->ifm_active |= IFM_FDX; 5734 BGE_UNLOCK(sc); 5735 return; 5736 } 5737 5738 mii = device_get_softc(sc->bge_miibus); 5739 mii_pollstat(mii); 5740 ifmr->ifm_active = mii->mii_media_active; 5741 ifmr->ifm_status = mii->mii_media_status; 5742 5743 BGE_UNLOCK(sc); 5744 } 5745 5746 static int 5747 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 5748 { 5749 struct bge_softc *sc = ifp->if_softc; 5750 struct ifreq *ifr = (struct ifreq *) data; 5751 struct mii_data *mii; 5752 int flags, mask, error = 0; 5753 5754 switch (command) { 5755 case SIOCSIFMTU: 5756 if (BGE_IS_JUMBO_CAPABLE(sc) || 5757 (sc->bge_flags & BGE_FLAG_JUMBO_STD)) { 5758 if (ifr->ifr_mtu < ETHERMIN || 5759 ifr->ifr_mtu > BGE_JUMBO_MTU) { 5760 error = EINVAL; 5761 break; 5762 } 5763 } else if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU) { 5764 error = EINVAL; 5765 break; 5766 } 5767 BGE_LOCK(sc); 5768 if (ifp->if_mtu != ifr->ifr_mtu) { 5769 ifp->if_mtu = ifr->ifr_mtu; 5770 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5771 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5772 bge_init_locked(sc); 5773 } 5774 } 5775 BGE_UNLOCK(sc); 5776 break; 5777 case SIOCSIFFLAGS: 5778 BGE_LOCK(sc); 5779 if (ifp->if_flags & IFF_UP) { 5780 /* 5781 * If only the state of the PROMISC flag changed, 5782 * then just use the 'set promisc mode' command 5783 * instead of reinitializing the entire NIC. Doing 5784 * a full re-init means reloading the firmware and 5785 * waiting for it to start up, which may take a 5786 * second or two. Similarly for ALLMULTI. 5787 */ 5788 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5789 flags = ifp->if_flags ^ sc->bge_if_flags; 5790 if (flags & IFF_PROMISC) 5791 bge_setpromisc(sc); 5792 if (flags & IFF_ALLMULTI) 5793 bge_setmulti(sc); 5794 } else 5795 bge_init_locked(sc); 5796 } else { 5797 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5798 bge_stop(sc); 5799 } 5800 } 5801 sc->bge_if_flags = ifp->if_flags; 5802 BGE_UNLOCK(sc); 5803 error = 0; 5804 break; 5805 case SIOCADDMULTI: 5806 case SIOCDELMULTI: 5807 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 5808 BGE_LOCK(sc); 5809 bge_setmulti(sc); 5810 BGE_UNLOCK(sc); 5811 error = 0; 5812 } 5813 break; 5814 case SIOCSIFMEDIA: 5815 case SIOCGIFMEDIA: 5816 if (sc->bge_flags & BGE_FLAG_TBI) { 5817 error = ifmedia_ioctl(ifp, ifr, 5818 &sc->bge_ifmedia, command); 5819 } else { 5820 mii = device_get_softc(sc->bge_miibus); 5821 error = ifmedia_ioctl(ifp, ifr, 5822 &mii->mii_media, command); 5823 } 5824 break; 5825 case SIOCSIFCAP: 5826 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 5827 #ifdef DEVICE_POLLING 5828 if (mask & IFCAP_POLLING) { 5829 if (ifr->ifr_reqcap & IFCAP_POLLING) { 5830 error = ether_poll_register(bge_poll, ifp); 5831 if (error) 5832 return (error); 5833 BGE_LOCK(sc); 5834 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, 5835 BGE_PCIMISCCTL_MASK_PCI_INTR); 5836 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5837 ifp->if_capenable |= IFCAP_POLLING; 5838 BGE_UNLOCK(sc); 5839 } else { 5840 error = ether_poll_deregister(ifp); 5841 /* Enable interrupt even in error case */ 5842 BGE_LOCK(sc); 5843 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, 5844 BGE_PCIMISCCTL_MASK_PCI_INTR); 5845 bge_writembx(sc, BGE_MBX_IRQ0_LO, 0); 5846 ifp->if_capenable &= ~IFCAP_POLLING; 5847 BGE_UNLOCK(sc); 5848 } 5849 } 5850 #endif 5851 if ((mask & IFCAP_TXCSUM) != 0 && 5852 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 5853 ifp->if_capenable ^= IFCAP_TXCSUM; 5854 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 5855 ifp->if_hwassist |= sc->bge_csum_features; 5856 else 5857 ifp->if_hwassist &= ~sc->bge_csum_features; 5858 } 5859 5860 if ((mask & IFCAP_RXCSUM) != 0 && 5861 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 5862 ifp->if_capenable ^= IFCAP_RXCSUM; 5863 5864 if ((mask & IFCAP_TSO4) != 0 && 5865 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 5866 ifp->if_capenable ^= IFCAP_TSO4; 5867 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 5868 ifp->if_hwassist |= CSUM_TSO; 5869 else 5870 ifp->if_hwassist &= ~CSUM_TSO; 5871 } 5872 5873 if (mask & IFCAP_VLAN_MTU) { 5874 ifp->if_capenable ^= IFCAP_VLAN_MTU; 5875 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5876 bge_init(sc); 5877 } 5878 5879 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 5880 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 5881 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 5882 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 5883 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 5884 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 5885 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 5886 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 5887 BGE_LOCK(sc); 5888 bge_setvlan(sc); 5889 BGE_UNLOCK(sc); 5890 } 5891 #ifdef VLAN_CAPABILITIES 5892 VLAN_CAPABILITIES(ifp); 5893 #endif 5894 break; 5895 default: 5896 error = ether_ioctl(ifp, command, data); 5897 break; 5898 } 5899 5900 return (error); 5901 } 5902 5903 static void 5904 bge_watchdog(struct bge_softc *sc) 5905 { 5906 struct ifnet *ifp; 5907 uint32_t status; 5908 5909 BGE_LOCK_ASSERT(sc); 5910 5911 if (sc->bge_timer == 0 || --sc->bge_timer) 5912 return; 5913 5914 /* If pause frames are active then don't reset the hardware. */ 5915 if ((CSR_READ_4(sc, BGE_RX_MODE) & BGE_RXMODE_FLOWCTL_ENABLE) != 0) { 5916 status = CSR_READ_4(sc, BGE_RX_STS); 5917 if ((status & BGE_RXSTAT_REMOTE_XOFFED) != 0) { 5918 /* 5919 * If link partner has us in XOFF state then wait for 5920 * the condition to clear. 5921 */ 5922 CSR_WRITE_4(sc, BGE_RX_STS, status); 5923 sc->bge_timer = BGE_TX_TIMEOUT; 5924 return; 5925 } else if ((status & BGE_RXSTAT_RCVD_XOFF) != 0 && 5926 (status & BGE_RXSTAT_RCVD_XON) != 0) { 5927 /* 5928 * If link partner has us in XOFF state then wait for 5929 * the condition to clear. 5930 */ 5931 CSR_WRITE_4(sc, BGE_RX_STS, status); 5932 sc->bge_timer = BGE_TX_TIMEOUT; 5933 return; 5934 } 5935 /* 5936 * Any other condition is unexpected and the controller 5937 * should be reset. 5938 */ 5939 } 5940 5941 ifp = sc->bge_ifp; 5942 5943 if_printf(ifp, "watchdog timeout -- resetting\n"); 5944 5945 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 5946 bge_init_locked(sc); 5947 5948 ifp->if_oerrors++; 5949 } 5950 5951 static void 5952 bge_stop_block(struct bge_softc *sc, bus_size_t reg, uint32_t bit) 5953 { 5954 int i; 5955 5956 BGE_CLRBIT(sc, reg, bit); 5957 5958 for (i = 0; i < BGE_TIMEOUT; i++) { 5959 if ((CSR_READ_4(sc, reg) & bit) == 0) 5960 return; 5961 DELAY(100); 5962 } 5963 } 5964 5965 /* 5966 * Stop the adapter and free any mbufs allocated to the 5967 * RX and TX lists. 5968 */ 5969 static void 5970 bge_stop(struct bge_softc *sc) 5971 { 5972 struct ifnet *ifp; 5973 5974 BGE_LOCK_ASSERT(sc); 5975 5976 ifp = sc->bge_ifp; 5977 5978 callout_stop(&sc->bge_stat_ch); 5979 5980 /* Disable host interrupts. */ 5981 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 5982 bge_writembx(sc, BGE_MBX_IRQ0_LO, 1); 5983 5984 /* 5985 * Tell firmware we're shutting down. 5986 */ 5987 bge_stop_fw(sc); 5988 bge_sig_pre_reset(sc, BGE_RESET_SHUTDOWN); 5989 5990 /* 5991 * Disable all of the receiver blocks. 5992 */ 5993 bge_stop_block(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 5994 bge_stop_block(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 5995 bge_stop_block(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 5996 if (BGE_IS_5700_FAMILY(sc)) 5997 bge_stop_block(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 5998 bge_stop_block(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 5999 bge_stop_block(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 6000 bge_stop_block(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 6001 6002 /* 6003 * Disable all of the transmit blocks. 6004 */ 6005 bge_stop_block(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 6006 bge_stop_block(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 6007 bge_stop_block(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 6008 bge_stop_block(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 6009 bge_stop_block(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 6010 if (BGE_IS_5700_FAMILY(sc)) 6011 bge_stop_block(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 6012 bge_stop_block(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 6013 6014 /* 6015 * Shut down all of the memory managers and related 6016 * state machines. 6017 */ 6018 bge_stop_block(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 6019 bge_stop_block(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 6020 if (BGE_IS_5700_FAMILY(sc)) 6021 bge_stop_block(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 6022 6023 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 6024 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 6025 if (!(BGE_IS_5705_PLUS(sc))) { 6026 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 6027 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 6028 } 6029 /* Update MAC statistics. */ 6030 if (BGE_IS_5705_PLUS(sc)) 6031 bge_stats_update_regs(sc); 6032 6033 bge_reset(sc); 6034 bge_sig_legacy(sc, BGE_RESET_SHUTDOWN); 6035 bge_sig_post_reset(sc, BGE_RESET_SHUTDOWN); 6036 6037 /* 6038 * Keep the ASF firmware running if up. 6039 */ 6040 if (sc->bge_asf_mode & ASF_STACKUP) 6041 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6042 else 6043 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 6044 6045 /* Free the RX lists. */ 6046 bge_free_rx_ring_std(sc); 6047 6048 /* Free jumbo RX list. */ 6049 if (BGE_IS_JUMBO_CAPABLE(sc)) 6050 bge_free_rx_ring_jumbo(sc); 6051 6052 /* Free TX buffers. */ 6053 bge_free_tx_ring(sc); 6054 6055 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 6056 6057 /* Clear MAC's link state (PHY may still have link UP). */ 6058 if (bootverbose && sc->bge_link) 6059 if_printf(sc->bge_ifp, "link DOWN\n"); 6060 sc->bge_link = 0; 6061 6062 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 6063 } 6064 6065 /* 6066 * Stop all chip I/O so that the kernel's probe routines don't 6067 * get confused by errant DMAs when rebooting. 6068 */ 6069 static int 6070 bge_shutdown(device_t dev) 6071 { 6072 struct bge_softc *sc; 6073 6074 sc = device_get_softc(dev); 6075 BGE_LOCK(sc); 6076 bge_stop(sc); 6077 BGE_UNLOCK(sc); 6078 6079 return (0); 6080 } 6081 6082 static int 6083 bge_suspend(device_t dev) 6084 { 6085 struct bge_softc *sc; 6086 6087 sc = device_get_softc(dev); 6088 BGE_LOCK(sc); 6089 bge_stop(sc); 6090 BGE_UNLOCK(sc); 6091 6092 return (0); 6093 } 6094 6095 static int 6096 bge_resume(device_t dev) 6097 { 6098 struct bge_softc *sc; 6099 struct ifnet *ifp; 6100 6101 sc = device_get_softc(dev); 6102 BGE_LOCK(sc); 6103 ifp = sc->bge_ifp; 6104 if (ifp->if_flags & IFF_UP) { 6105 bge_init_locked(sc); 6106 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 6107 bge_start_locked(ifp); 6108 } 6109 BGE_UNLOCK(sc); 6110 6111 return (0); 6112 } 6113 6114 static void 6115 bge_link_upd(struct bge_softc *sc) 6116 { 6117 struct mii_data *mii; 6118 uint32_t link, status; 6119 6120 BGE_LOCK_ASSERT(sc); 6121 6122 /* Clear 'pending link event' flag. */ 6123 sc->bge_link_evt = 0; 6124 6125 /* 6126 * Process link state changes. 6127 * Grrr. The link status word in the status block does 6128 * not work correctly on the BCM5700 rev AX and BX chips, 6129 * according to all available information. Hence, we have 6130 * to enable MII interrupts in order to properly obtain 6131 * async link changes. Unfortunately, this also means that 6132 * we have to read the MAC status register to detect link 6133 * changes, thereby adding an additional register access to 6134 * the interrupt handler. 6135 * 6136 * XXX: perhaps link state detection procedure used for 6137 * BGE_CHIPID_BCM5700_B2 can be used for others BCM5700 revisions. 6138 */ 6139 6140 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6141 sc->bge_chipid != BGE_CHIPID_BCM5700_B2) { 6142 status = CSR_READ_4(sc, BGE_MAC_STS); 6143 if (status & BGE_MACSTAT_MI_INTERRUPT) { 6144 mii = device_get_softc(sc->bge_miibus); 6145 mii_pollstat(mii); 6146 if (!sc->bge_link && 6147 mii->mii_media_status & IFM_ACTIVE && 6148 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6149 sc->bge_link++; 6150 if (bootverbose) 6151 if_printf(sc->bge_ifp, "link UP\n"); 6152 } else if (sc->bge_link && 6153 (!(mii->mii_media_status & IFM_ACTIVE) || 6154 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6155 sc->bge_link = 0; 6156 if (bootverbose) 6157 if_printf(sc->bge_ifp, "link DOWN\n"); 6158 } 6159 6160 /* Clear the interrupt. */ 6161 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 6162 BGE_EVTENB_MI_INTERRUPT); 6163 bge_miibus_readreg(sc->bge_dev, sc->bge_phy_addr, 6164 BRGPHY_MII_ISR); 6165 bge_miibus_writereg(sc->bge_dev, sc->bge_phy_addr, 6166 BRGPHY_MII_IMR, BRGPHY_INTRS); 6167 } 6168 return; 6169 } 6170 6171 if (sc->bge_flags & BGE_FLAG_TBI) { 6172 status = CSR_READ_4(sc, BGE_MAC_STS); 6173 if (status & BGE_MACSTAT_TBI_PCS_SYNCHED) { 6174 if (!sc->bge_link) { 6175 sc->bge_link++; 6176 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) { 6177 BGE_CLRBIT(sc, BGE_MAC_MODE, 6178 BGE_MACMODE_TBI_SEND_CFGS); 6179 DELAY(40); 6180 } 6181 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 6182 if (bootverbose) 6183 if_printf(sc->bge_ifp, "link UP\n"); 6184 if_link_state_change(sc->bge_ifp, 6185 LINK_STATE_UP); 6186 } 6187 } else if (sc->bge_link) { 6188 sc->bge_link = 0; 6189 if (bootverbose) 6190 if_printf(sc->bge_ifp, "link DOWN\n"); 6191 if_link_state_change(sc->bge_ifp, LINK_STATE_DOWN); 6192 } 6193 } else if ((sc->bge_mi_mode & BGE_MIMODE_AUTOPOLL) != 0) { 6194 /* 6195 * Some broken BCM chips have BGE_STATFLAG_LINKSTATE_CHANGED bit 6196 * in status word always set. Workaround this bug by reading 6197 * PHY link status directly. 6198 */ 6199 link = (CSR_READ_4(sc, BGE_MI_STS) & BGE_MISTS_LINK) ? 1 : 0; 6200 6201 if (link != sc->bge_link || 6202 sc->bge_asicrev == BGE_ASICREV_BCM5700) { 6203 mii = device_get_softc(sc->bge_miibus); 6204 mii_pollstat(mii); 6205 if (!sc->bge_link && 6206 mii->mii_media_status & IFM_ACTIVE && 6207 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 6208 sc->bge_link++; 6209 if (bootverbose) 6210 if_printf(sc->bge_ifp, "link UP\n"); 6211 } else if (sc->bge_link && 6212 (!(mii->mii_media_status & IFM_ACTIVE) || 6213 IFM_SUBTYPE(mii->mii_media_active) == IFM_NONE)) { 6214 sc->bge_link = 0; 6215 if (bootverbose) 6216 if_printf(sc->bge_ifp, "link DOWN\n"); 6217 } 6218 } 6219 } else { 6220 /* 6221 * For controllers that call mii_tick, we have to poll 6222 * link status. 6223 */ 6224 mii = device_get_softc(sc->bge_miibus); 6225 mii_pollstat(mii); 6226 bge_miibus_statchg(sc->bge_dev); 6227 } 6228 6229 /* Disable MAC attention when link is up. */ 6230 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED | 6231 BGE_MACSTAT_CFG_CHANGED | BGE_MACSTAT_MI_COMPLETE | 6232 BGE_MACSTAT_LINK_CHANGED); 6233 } 6234 6235 static void 6236 bge_add_sysctls(struct bge_softc *sc) 6237 { 6238 struct sysctl_ctx_list *ctx; 6239 struct sysctl_oid_list *children; 6240 char tn[32]; 6241 int unit; 6242 6243 ctx = device_get_sysctl_ctx(sc->bge_dev); 6244 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bge_dev)); 6245 6246 #ifdef BGE_REGISTER_DEBUG 6247 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "debug_info", 6248 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_debug_info, "I", 6249 "Debug Information"); 6250 6251 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "reg_read", 6252 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_reg_read, "I", 6253 "MAC Register Read"); 6254 6255 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ape_read", 6256 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_ape_read, "I", 6257 "APE Register Read"); 6258 6259 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mem_read", 6260 CTLTYPE_INT | CTLFLAG_RW, sc, 0, bge_sysctl_mem_read, "I", 6261 "Memory Read"); 6262 6263 #endif 6264 6265 unit = device_get_unit(sc->bge_dev); 6266 /* 6267 * A common design characteristic for many Broadcom client controllers 6268 * is that they only support a single outstanding DMA read operation 6269 * on the PCIe bus. This means that it will take twice as long to fetch 6270 * a TX frame that is split into header and payload buffers as it does 6271 * to fetch a single, contiguous TX frame (2 reads vs. 1 read). For 6272 * these controllers, coalescing buffers to reduce the number of memory 6273 * reads is effective way to get maximum performance(about 940Mbps). 6274 * Without collapsing TX buffers the maximum TCP bulk transfer 6275 * performance is about 850Mbps. However forcing coalescing mbufs 6276 * consumes a lot of CPU cycles, so leave it off by default. 6277 */ 6278 sc->bge_forced_collapse = 0; 6279 snprintf(tn, sizeof(tn), "dev.bge.%d.forced_collapse", unit); 6280 TUNABLE_INT_FETCH(tn, &sc->bge_forced_collapse); 6281 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_collapse", 6282 CTLFLAG_RW, &sc->bge_forced_collapse, 0, 6283 "Number of fragmented TX buffers of a frame allowed before " 6284 "forced collapsing"); 6285 6286 sc->bge_msi = 1; 6287 snprintf(tn, sizeof(tn), "dev.bge.%d.msi", unit); 6288 TUNABLE_INT_FETCH(tn, &sc->bge_msi); 6289 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "msi", 6290 CTLFLAG_RD, &sc->bge_msi, 0, "Enable MSI"); 6291 6292 /* 6293 * It seems all Broadcom controllers have a bug that can generate UDP 6294 * datagrams with checksum value 0 when TX UDP checksum offloading is 6295 * enabled. Generating UDP checksum value 0 is RFC 768 violation. 6296 * Even though the probability of generating such UDP datagrams is 6297 * low, I don't want to see FreeBSD boxes to inject such datagrams 6298 * into network so disable UDP checksum offloading by default. Users 6299 * still override this behavior by setting a sysctl variable, 6300 * dev.bge.0.forced_udpcsum. 6301 */ 6302 sc->bge_forced_udpcsum = 0; 6303 snprintf(tn, sizeof(tn), "dev.bge.%d.bge_forced_udpcsum", unit); 6304 TUNABLE_INT_FETCH(tn, &sc->bge_forced_udpcsum); 6305 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "forced_udpcsum", 6306 CTLFLAG_RW, &sc->bge_forced_udpcsum, 0, 6307 "Enable UDP checksum offloading even if controller can " 6308 "generate UDP checksum value 0"); 6309 6310 if (BGE_IS_5705_PLUS(sc)) 6311 bge_add_sysctl_stats_regs(sc, ctx, children); 6312 else 6313 bge_add_sysctl_stats(sc, ctx, children); 6314 } 6315 6316 #define BGE_SYSCTL_STAT(sc, ctx, desc, parent, node, oid) \ 6317 SYSCTL_ADD_PROC(ctx, parent, OID_AUTO, oid, CTLTYPE_UINT|CTLFLAG_RD, \ 6318 sc, offsetof(struct bge_stats, node), bge_sysctl_stats, "IU", \ 6319 desc) 6320 6321 static void 6322 bge_add_sysctl_stats(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6323 struct sysctl_oid_list *parent) 6324 { 6325 struct sysctl_oid *tree; 6326 struct sysctl_oid_list *children, *schildren; 6327 6328 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6329 NULL, "BGE Statistics"); 6330 schildren = children = SYSCTL_CHILDREN(tree); 6331 BGE_SYSCTL_STAT(sc, ctx, "Frames Dropped Due To Filters", 6332 children, COSFramesDroppedDueToFilters, 6333 "FramesDroppedDueToFilters"); 6334 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write Queue Full", 6335 children, nicDmaWriteQueueFull, "DmaWriteQueueFull"); 6336 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Write High Priority Queue Full", 6337 children, nicDmaWriteHighPriQueueFull, "DmaWriteHighPriQueueFull"); 6338 BGE_SYSCTL_STAT(sc, ctx, "NIC No More RX Buffer Descriptors", 6339 children, nicNoMoreRxBDs, "NoMoreRxBDs"); 6340 BGE_SYSCTL_STAT(sc, ctx, "Discarded Input Frames", 6341 children, ifInDiscards, "InputDiscards"); 6342 BGE_SYSCTL_STAT(sc, ctx, "Input Errors", 6343 children, ifInErrors, "InputErrors"); 6344 BGE_SYSCTL_STAT(sc, ctx, "NIC Recv Threshold Hit", 6345 children, nicRecvThresholdHit, "RecvThresholdHit"); 6346 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read Queue Full", 6347 children, nicDmaReadQueueFull, "DmaReadQueueFull"); 6348 BGE_SYSCTL_STAT(sc, ctx, "NIC DMA Read High Priority Queue Full", 6349 children, nicDmaReadHighPriQueueFull, "DmaReadHighPriQueueFull"); 6350 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Data Complete Queue Full", 6351 children, nicSendDataCompQueueFull, "SendDataCompQueueFull"); 6352 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Set Send Producer Index", 6353 children, nicRingSetSendProdIndex, "RingSetSendProdIndex"); 6354 BGE_SYSCTL_STAT(sc, ctx, "NIC Ring Status Update", 6355 children, nicRingStatusUpdate, "RingStatusUpdate"); 6356 BGE_SYSCTL_STAT(sc, ctx, "NIC Interrupts", 6357 children, nicInterrupts, "Interrupts"); 6358 BGE_SYSCTL_STAT(sc, ctx, "NIC Avoided Interrupts", 6359 children, nicAvoidedInterrupts, "AvoidedInterrupts"); 6360 BGE_SYSCTL_STAT(sc, ctx, "NIC Send Threshold Hit", 6361 children, nicSendThresholdHit, "SendThresholdHit"); 6362 6363 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "rx", CTLFLAG_RD, 6364 NULL, "BGE RX Statistics"); 6365 children = SYSCTL_CHILDREN(tree); 6366 BGE_SYSCTL_STAT(sc, ctx, "Inbound Octets", 6367 children, rxstats.ifHCInOctets, "ifHCInOctets"); 6368 BGE_SYSCTL_STAT(sc, ctx, "Fragments", 6369 children, rxstats.etherStatsFragments, "Fragments"); 6370 BGE_SYSCTL_STAT(sc, ctx, "Inbound Unicast Packets", 6371 children, rxstats.ifHCInUcastPkts, "UnicastPkts"); 6372 BGE_SYSCTL_STAT(sc, ctx, "Inbound Multicast Packets", 6373 children, rxstats.ifHCInMulticastPkts, "MulticastPkts"); 6374 BGE_SYSCTL_STAT(sc, ctx, "FCS Errors", 6375 children, rxstats.dot3StatsFCSErrors, "FCSErrors"); 6376 BGE_SYSCTL_STAT(sc, ctx, "Alignment Errors", 6377 children, rxstats.dot3StatsAlignmentErrors, "AlignmentErrors"); 6378 BGE_SYSCTL_STAT(sc, ctx, "XON Pause Frames Received", 6379 children, rxstats.xonPauseFramesReceived, "xonPauseFramesReceived"); 6380 BGE_SYSCTL_STAT(sc, ctx, "XOFF Pause Frames Received", 6381 children, rxstats.xoffPauseFramesReceived, 6382 "xoffPauseFramesReceived"); 6383 BGE_SYSCTL_STAT(sc, ctx, "MAC Control Frames Received", 6384 children, rxstats.macControlFramesReceived, 6385 "ControlFramesReceived"); 6386 BGE_SYSCTL_STAT(sc, ctx, "XOFF State Entered", 6387 children, rxstats.xoffStateEntered, "xoffStateEntered"); 6388 BGE_SYSCTL_STAT(sc, ctx, "Frames Too Long", 6389 children, rxstats.dot3StatsFramesTooLong, "FramesTooLong"); 6390 BGE_SYSCTL_STAT(sc, ctx, "Jabbers", 6391 children, rxstats.etherStatsJabbers, "Jabbers"); 6392 BGE_SYSCTL_STAT(sc, ctx, "Undersized Packets", 6393 children, rxstats.etherStatsUndersizePkts, "UndersizePkts"); 6394 BGE_SYSCTL_STAT(sc, ctx, "Inbound Range Length Errors", 6395 children, rxstats.inRangeLengthError, "inRangeLengthError"); 6396 BGE_SYSCTL_STAT(sc, ctx, "Outbound Range Length Errors", 6397 children, rxstats.outRangeLengthError, "outRangeLengthError"); 6398 6399 tree = SYSCTL_ADD_NODE(ctx, schildren, OID_AUTO, "tx", CTLFLAG_RD, 6400 NULL, "BGE TX Statistics"); 6401 children = SYSCTL_CHILDREN(tree); 6402 BGE_SYSCTL_STAT(sc, ctx, "Outbound Octets", 6403 children, txstats.ifHCOutOctets, "ifHCOutOctets"); 6404 BGE_SYSCTL_STAT(sc, ctx, "TX Collisions", 6405 children, txstats.etherStatsCollisions, "Collisions"); 6406 BGE_SYSCTL_STAT(sc, ctx, "XON Sent", 6407 children, txstats.outXonSent, "XonSent"); 6408 BGE_SYSCTL_STAT(sc, ctx, "XOFF Sent", 6409 children, txstats.outXoffSent, "XoffSent"); 6410 BGE_SYSCTL_STAT(sc, ctx, "Flow Control Done", 6411 children, txstats.flowControlDone, "flowControlDone"); 6412 BGE_SYSCTL_STAT(sc, ctx, "Internal MAC TX errors", 6413 children, txstats.dot3StatsInternalMacTransmitErrors, 6414 "InternalMacTransmitErrors"); 6415 BGE_SYSCTL_STAT(sc, ctx, "Single Collision Frames", 6416 children, txstats.dot3StatsSingleCollisionFrames, 6417 "SingleCollisionFrames"); 6418 BGE_SYSCTL_STAT(sc, ctx, "Multiple Collision Frames", 6419 children, txstats.dot3StatsMultipleCollisionFrames, 6420 "MultipleCollisionFrames"); 6421 BGE_SYSCTL_STAT(sc, ctx, "Deferred Transmissions", 6422 children, txstats.dot3StatsDeferredTransmissions, 6423 "DeferredTransmissions"); 6424 BGE_SYSCTL_STAT(sc, ctx, "Excessive Collisions", 6425 children, txstats.dot3StatsExcessiveCollisions, 6426 "ExcessiveCollisions"); 6427 BGE_SYSCTL_STAT(sc, ctx, "Late Collisions", 6428 children, txstats.dot3StatsLateCollisions, 6429 "LateCollisions"); 6430 BGE_SYSCTL_STAT(sc, ctx, "Outbound Unicast Packets", 6431 children, txstats.ifHCOutUcastPkts, "UnicastPkts"); 6432 BGE_SYSCTL_STAT(sc, ctx, "Outbound Multicast Packets", 6433 children, txstats.ifHCOutMulticastPkts, "MulticastPkts"); 6434 BGE_SYSCTL_STAT(sc, ctx, "Outbound Broadcast Packets", 6435 children, txstats.ifHCOutBroadcastPkts, "BroadcastPkts"); 6436 BGE_SYSCTL_STAT(sc, ctx, "Carrier Sense Errors", 6437 children, txstats.dot3StatsCarrierSenseErrors, 6438 "CarrierSenseErrors"); 6439 BGE_SYSCTL_STAT(sc, ctx, "Outbound Discards", 6440 children, txstats.ifOutDiscards, "Discards"); 6441 BGE_SYSCTL_STAT(sc, ctx, "Outbound Errors", 6442 children, txstats.ifOutErrors, "Errors"); 6443 } 6444 6445 #undef BGE_SYSCTL_STAT 6446 6447 #define BGE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 6448 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 6449 6450 static void 6451 bge_add_sysctl_stats_regs(struct bge_softc *sc, struct sysctl_ctx_list *ctx, 6452 struct sysctl_oid_list *parent) 6453 { 6454 struct sysctl_oid *tree; 6455 struct sysctl_oid_list *child, *schild; 6456 struct bge_mac_stats *stats; 6457 6458 stats = &sc->bge_mac_stats; 6459 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "stats", CTLFLAG_RD, 6460 NULL, "BGE Statistics"); 6461 schild = child = SYSCTL_CHILDREN(tree); 6462 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesDroppedDueToFilters", 6463 &stats->FramesDroppedDueToFilters, "Frames Dropped Due to Filters"); 6464 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteQueueFull", 6465 &stats->DmaWriteQueueFull, "NIC DMA Write Queue Full"); 6466 BGE_SYSCTL_STAT_ADD64(ctx, child, "DmaWriteHighPriQueueFull", 6467 &stats->DmaWriteHighPriQueueFull, 6468 "NIC DMA Write High Priority Queue Full"); 6469 BGE_SYSCTL_STAT_ADD64(ctx, child, "NoMoreRxBDs", 6470 &stats->NoMoreRxBDs, "NIC No More RX Buffer Descriptors"); 6471 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputDiscards", 6472 &stats->InputDiscards, "Discarded Input Frames"); 6473 BGE_SYSCTL_STAT_ADD64(ctx, child, "InputErrors", 6474 &stats->InputErrors, "Input Errors"); 6475 BGE_SYSCTL_STAT_ADD64(ctx, child, "RecvThresholdHit", 6476 &stats->RecvThresholdHit, "NIC Recv Threshold Hit"); 6477 6478 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 6479 NULL, "BGE RX Statistics"); 6480 child = SYSCTL_CHILDREN(tree); 6481 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCInOctets", 6482 &stats->ifHCInOctets, "Inbound Octets"); 6483 BGE_SYSCTL_STAT_ADD64(ctx, child, "Fragments", 6484 &stats->etherStatsFragments, "Fragments"); 6485 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6486 &stats->ifHCInUcastPkts, "Inbound Unicast Packets"); 6487 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6488 &stats->ifHCInMulticastPkts, "Inbound Multicast Packets"); 6489 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6490 &stats->ifHCInBroadcastPkts, "Inbound Broadcast Packets"); 6491 BGE_SYSCTL_STAT_ADD64(ctx, child, "FCSErrors", 6492 &stats->dot3StatsFCSErrors, "FCS Errors"); 6493 BGE_SYSCTL_STAT_ADD64(ctx, child, "AlignmentErrors", 6494 &stats->dot3StatsAlignmentErrors, "Alignment Errors"); 6495 BGE_SYSCTL_STAT_ADD64(ctx, child, "xonPauseFramesReceived", 6496 &stats->xonPauseFramesReceived, "XON Pause Frames Received"); 6497 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffPauseFramesReceived", 6498 &stats->xoffPauseFramesReceived, "XOFF Pause Frames Received"); 6499 BGE_SYSCTL_STAT_ADD64(ctx, child, "ControlFramesReceived", 6500 &stats->macControlFramesReceived, "MAC Control Frames Received"); 6501 BGE_SYSCTL_STAT_ADD64(ctx, child, "xoffStateEntered", 6502 &stats->xoffStateEntered, "XOFF State Entered"); 6503 BGE_SYSCTL_STAT_ADD64(ctx, child, "FramesTooLong", 6504 &stats->dot3StatsFramesTooLong, "Frames Too Long"); 6505 BGE_SYSCTL_STAT_ADD64(ctx, child, "Jabbers", 6506 &stats->etherStatsJabbers, "Jabbers"); 6507 BGE_SYSCTL_STAT_ADD64(ctx, child, "UndersizePkts", 6508 &stats->etherStatsUndersizePkts, "Undersized Packets"); 6509 6510 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 6511 NULL, "BGE TX Statistics"); 6512 child = SYSCTL_CHILDREN(tree); 6513 BGE_SYSCTL_STAT_ADD64(ctx, child, "ifHCOutOctets", 6514 &stats->ifHCOutOctets, "Outbound Octets"); 6515 BGE_SYSCTL_STAT_ADD64(ctx, child, "Collisions", 6516 &stats->etherStatsCollisions, "TX Collisions"); 6517 BGE_SYSCTL_STAT_ADD64(ctx, child, "XonSent", 6518 &stats->outXonSent, "XON Sent"); 6519 BGE_SYSCTL_STAT_ADD64(ctx, child, "XoffSent", 6520 &stats->outXoffSent, "XOFF Sent"); 6521 BGE_SYSCTL_STAT_ADD64(ctx, child, "InternalMacTransmitErrors", 6522 &stats->dot3StatsInternalMacTransmitErrors, 6523 "Internal MAC TX Errors"); 6524 BGE_SYSCTL_STAT_ADD64(ctx, child, "SingleCollisionFrames", 6525 &stats->dot3StatsSingleCollisionFrames, "Single Collision Frames"); 6526 BGE_SYSCTL_STAT_ADD64(ctx, child, "MultipleCollisionFrames", 6527 &stats->dot3StatsMultipleCollisionFrames, 6528 "Multiple Collision Frames"); 6529 BGE_SYSCTL_STAT_ADD64(ctx, child, "DeferredTransmissions", 6530 &stats->dot3StatsDeferredTransmissions, "Deferred Transmissions"); 6531 BGE_SYSCTL_STAT_ADD64(ctx, child, "ExcessiveCollisions", 6532 &stats->dot3StatsExcessiveCollisions, "Excessive Collisions"); 6533 BGE_SYSCTL_STAT_ADD64(ctx, child, "LateCollisions", 6534 &stats->dot3StatsLateCollisions, "Late Collisions"); 6535 BGE_SYSCTL_STAT_ADD64(ctx, child, "UnicastPkts", 6536 &stats->ifHCOutUcastPkts, "Outbound Unicast Packets"); 6537 BGE_SYSCTL_STAT_ADD64(ctx, child, "MulticastPkts", 6538 &stats->ifHCOutMulticastPkts, "Outbound Multicast Packets"); 6539 BGE_SYSCTL_STAT_ADD64(ctx, child, "BroadcastPkts", 6540 &stats->ifHCOutBroadcastPkts, "Outbound Broadcast Packets"); 6541 } 6542 6543 #undef BGE_SYSCTL_STAT_ADD64 6544 6545 static int 6546 bge_sysctl_stats(SYSCTL_HANDLER_ARGS) 6547 { 6548 struct bge_softc *sc; 6549 uint32_t result; 6550 int offset; 6551 6552 sc = (struct bge_softc *)arg1; 6553 offset = arg2; 6554 result = CSR_READ_4(sc, BGE_MEMWIN_START + BGE_STATS_BLOCK + offset + 6555 offsetof(bge_hostaddr, bge_addr_lo)); 6556 return (sysctl_handle_int(oidp, &result, 0, req)); 6557 } 6558 6559 #ifdef BGE_REGISTER_DEBUG 6560 static int 6561 bge_sysctl_debug_info(SYSCTL_HANDLER_ARGS) 6562 { 6563 struct bge_softc *sc; 6564 uint16_t *sbdata; 6565 int error, result, sbsz; 6566 int i, j; 6567 6568 result = -1; 6569 error = sysctl_handle_int(oidp, &result, 0, req); 6570 if (error || (req->newptr == NULL)) 6571 return (error); 6572 6573 if (result == 1) { 6574 sc = (struct bge_softc *)arg1; 6575 6576 if (sc->bge_asicrev == BGE_ASICREV_BCM5700 && 6577 sc->bge_chipid != BGE_CHIPID_BCM5700_C0) 6578 sbsz = BGE_STATUS_BLK_SZ; 6579 else 6580 sbsz = 32; 6581 sbdata = (uint16_t *)sc->bge_ldata.bge_status_block; 6582 printf("Status Block:\n"); 6583 BGE_LOCK(sc); 6584 bus_dmamap_sync(sc->bge_cdata.bge_status_tag, 6585 sc->bge_cdata.bge_status_map, 6586 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 6587 for (i = 0x0; i < sbsz / sizeof(uint16_t); ) { 6588 printf("%06x:", i); 6589 for (j = 0; j < 8; j++) 6590 printf(" %04x", sbdata[i++]); 6591 printf("\n"); 6592 } 6593 6594 printf("Registers:\n"); 6595 for (i = 0x800; i < 0xA00; ) { 6596 printf("%06x:", i); 6597 for (j = 0; j < 8; j++) { 6598 printf(" %08x", CSR_READ_4(sc, i)); 6599 i += 4; 6600 } 6601 printf("\n"); 6602 } 6603 BGE_UNLOCK(sc); 6604 6605 printf("Hardware Flags:\n"); 6606 if (BGE_IS_5717_PLUS(sc)) 6607 printf(" - 5717 Plus\n"); 6608 if (BGE_IS_5755_PLUS(sc)) 6609 printf(" - 5755 Plus\n"); 6610 if (BGE_IS_575X_PLUS(sc)) 6611 printf(" - 575X Plus\n"); 6612 if (BGE_IS_5705_PLUS(sc)) 6613 printf(" - 5705 Plus\n"); 6614 if (BGE_IS_5714_FAMILY(sc)) 6615 printf(" - 5714 Family\n"); 6616 if (BGE_IS_5700_FAMILY(sc)) 6617 printf(" - 5700 Family\n"); 6618 if (sc->bge_flags & BGE_FLAG_JUMBO) 6619 printf(" - Supports Jumbo Frames\n"); 6620 if (sc->bge_flags & BGE_FLAG_PCIX) 6621 printf(" - PCI-X Bus\n"); 6622 if (sc->bge_flags & BGE_FLAG_PCIE) 6623 printf(" - PCI Express Bus\n"); 6624 if (sc->bge_phy_flags & BGE_PHY_NO_3LED) 6625 printf(" - No 3 LEDs\n"); 6626 if (sc->bge_flags & BGE_FLAG_RX_ALIGNBUG) 6627 printf(" - RX Alignment Bug\n"); 6628 } 6629 6630 return (error); 6631 } 6632 6633 static int 6634 bge_sysctl_reg_read(SYSCTL_HANDLER_ARGS) 6635 { 6636 struct bge_softc *sc; 6637 int error; 6638 uint16_t result; 6639 uint32_t val; 6640 6641 result = -1; 6642 error = sysctl_handle_int(oidp, &result, 0, req); 6643 if (error || (req->newptr == NULL)) 6644 return (error); 6645 6646 if (result < 0x8000) { 6647 sc = (struct bge_softc *)arg1; 6648 val = CSR_READ_4(sc, result); 6649 printf("reg 0x%06X = 0x%08X\n", result, val); 6650 } 6651 6652 return (error); 6653 } 6654 6655 static int 6656 bge_sysctl_ape_read(SYSCTL_HANDLER_ARGS) 6657 { 6658 struct bge_softc *sc; 6659 int error; 6660 uint16_t result; 6661 uint32_t val; 6662 6663 result = -1; 6664 error = sysctl_handle_int(oidp, &result, 0, req); 6665 if (error || (req->newptr == NULL)) 6666 return (error); 6667 6668 if (result < 0x8000) { 6669 sc = (struct bge_softc *)arg1; 6670 val = APE_READ_4(sc, result); 6671 printf("reg 0x%06X = 0x%08X\n", result, val); 6672 } 6673 6674 return (error); 6675 } 6676 6677 static int 6678 bge_sysctl_mem_read(SYSCTL_HANDLER_ARGS) 6679 { 6680 struct bge_softc *sc; 6681 int error; 6682 uint16_t result; 6683 uint32_t val; 6684 6685 result = -1; 6686 error = sysctl_handle_int(oidp, &result, 0, req); 6687 if (error || (req->newptr == NULL)) 6688 return (error); 6689 6690 if (result < 0x8000) { 6691 sc = (struct bge_softc *)arg1; 6692 val = bge_readmem_ind(sc, result); 6693 printf("mem 0x%06X = 0x%08X\n", result, val); 6694 } 6695 6696 return (error); 6697 } 6698 #endif 6699 6700 static int 6701 bge_get_eaddr_fw(struct bge_softc *sc, uint8_t ether_addr[]) 6702 { 6703 6704 if (sc->bge_flags & BGE_FLAG_EADDR) 6705 return (1); 6706 6707 #ifdef __sparc64__ 6708 OF_getetheraddr(sc->bge_dev, ether_addr); 6709 return (0); 6710 #endif 6711 return (1); 6712 } 6713 6714 static int 6715 bge_get_eaddr_mem(struct bge_softc *sc, uint8_t ether_addr[]) 6716 { 6717 uint32_t mac_addr; 6718 6719 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_HIGH_MB); 6720 if ((mac_addr >> 16) == 0x484b) { 6721 ether_addr[0] = (uint8_t)(mac_addr >> 8); 6722 ether_addr[1] = (uint8_t)mac_addr; 6723 mac_addr = bge_readmem_ind(sc, BGE_SRAM_MAC_ADDR_LOW_MB); 6724 ether_addr[2] = (uint8_t)(mac_addr >> 24); 6725 ether_addr[3] = (uint8_t)(mac_addr >> 16); 6726 ether_addr[4] = (uint8_t)(mac_addr >> 8); 6727 ether_addr[5] = (uint8_t)mac_addr; 6728 return (0); 6729 } 6730 return (1); 6731 } 6732 6733 static int 6734 bge_get_eaddr_nvram(struct bge_softc *sc, uint8_t ether_addr[]) 6735 { 6736 int mac_offset = BGE_EE_MAC_OFFSET; 6737 6738 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6739 mac_offset = BGE_EE_MAC_OFFSET_5906; 6740 6741 return (bge_read_nvram(sc, ether_addr, mac_offset + 2, 6742 ETHER_ADDR_LEN)); 6743 } 6744 6745 static int 6746 bge_get_eaddr_eeprom(struct bge_softc *sc, uint8_t ether_addr[]) 6747 { 6748 6749 if (sc->bge_asicrev == BGE_ASICREV_BCM5906) 6750 return (1); 6751 6752 return (bge_read_eeprom(sc, ether_addr, BGE_EE_MAC_OFFSET + 2, 6753 ETHER_ADDR_LEN)); 6754 } 6755 6756 static int 6757 bge_get_eaddr(struct bge_softc *sc, uint8_t eaddr[]) 6758 { 6759 static const bge_eaddr_fcn_t bge_eaddr_funcs[] = { 6760 /* NOTE: Order is critical */ 6761 bge_get_eaddr_fw, 6762 bge_get_eaddr_mem, 6763 bge_get_eaddr_nvram, 6764 bge_get_eaddr_eeprom, 6765 NULL 6766 }; 6767 const bge_eaddr_fcn_t *func; 6768 6769 for (func = bge_eaddr_funcs; *func != NULL; ++func) { 6770 if ((*func)(sc, eaddr) == 0) 6771 break; 6772 } 6773 return (*func == NULL ? ENXIO : 0); 6774 } 6775